Semiconductor devices and their manufacturing methods, memory systems

Abstract

This disclosure provides a semiconductor device and its manufacturing method, as well as a storage system. The semiconductor device includes a semiconductor structure; the semiconductor structure includes a semiconductor body extending along a first direction; and a capacitor structure; the capacitor structure is located on one side of the semiconductor body along the first direction; wherein the capacitor structure includes a first electrode layer, a first dielectric layer, a second dielectric layer, and a second electrode layer arranged sequentially; the first dielectric layer and the second dielectric layer are made of different materials.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a method for manufacturing the same, and a memory system. Background Technology

[0002] Semiconductor devices, such as Dynamic Random Access Memory (DRAM), are among the most important storage components in electronic systems. They typically employ a 1T1C structure, consisting of a transistor (T) and a capacitor (C), as a storage cell. This 1T1C structure allows DRAM to achieve high integration and low cost, giving it an irreplaceable position in computer storage devices. With the rapid development of semiconductor technology, DRAM is rapidly evolving towards higher density and higher quality. Summary of the Invention

[0003] According to one aspect of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a semiconductor structure; the semiconductor structure comprising: a semiconductor body extending along a first direction; and a capacitor structure; the capacitor structure being located on one side of the semiconductor body along the first direction; wherein the capacitor structure comprises a first electrode layer, a first dielectric layer, a second dielectric layer, and a second electrode layer arranged sequentially; the first dielectric layer and the second dielectric layer are made of different materials.

[0004] In some embodiments, the crystal phase of the second dielectric layer includes a ferroelectric phase and an antiferroelectric phase.

[0005] In some embodiments, the ferroelectric phase includes an orthorhombic phase; the antiferroelectric phase includes a monoclinic phase, a tetragonal phase, or a cubic phase.

[0006] In some embodiments, the material of the first dielectric layer includes niobium oxide; the material of the second dielectric layer includes one of hafnium oxide, zirconium oxide, aluminum oxide, and tantalum oxide.

[0007] In some embodiments, the thickness of the first dielectric layer is less than or equal to 1 angstrom; the thickness of the second dielectric layer is 1 to 10 nanometers.

[0008] In some embodiments, the capacitor structure further includes: an intermediate layer located between the first dielectric layer and the second dielectric layer; the intermediate layer includes a first element in the first dielectric layer and a second element in the second dielectric layer.

[0009] In some embodiments, the first element includes niobium; the second element includes one of hafnium, zirconium, aluminum, and tantalum.

[0010] In some embodiments, the second electrode layer includes: a first sub-electrode layer and a second sub-electrode layer located between the first sub-electrode layer and the second dielectric layer; wherein the material of the first sub-electrode layer is different from the material of the first electrode layer, and the material of the second sub-electrode layer is the same as the material of the first electrode layer.

[0011] In some embodiments, the semiconductor structure further includes a gate structure located on at least one side of the semiconductor body in a second direction; the second direction is perpendicular to the first direction.

[0012] According to another aspect of this disclosure, a storage system is provided, comprising: a semiconductor device as described in the above embodiments of this disclosure; and a memory controller connected to the semiconductor device and configured to control the semiconductor device.

[0013] According to another aspect of this disclosure, a method for manufacturing a semiconductor device is provided, the semiconductor device including a semiconductor structure; the method for forming the semiconductor structure includes: forming a semiconductor body extending along a first direction; forming a capacitor structure; the capacitor structure being located on one side of the semiconductor body along the first direction; wherein the capacitor structure includes a first electrode layer, a first dielectric layer, a second dielectric layer, and a second electrode layer arranged sequentially; the first dielectric layer and the second dielectric layer are made of different materials.

[0014] In some embodiments, forming the capacitor structure includes: forming alternating layers of sacrificial and support layers to form a stacked structure; forming a capacitor aperture penetrating the stacked structure; forming a first electrode layer on the sidewalls and bottom of the capacitor aperture; forming a filling structure in the capacitor aperture where the first electrode layer is formed; forming an opening in the support layer that exposes the sacrificial layer; removing the sacrificial layer based on the opening to expose the surface of the first electrode layer; forming a first dielectric layer on the surface of the first electrode layer; forming a second dielectric layer on the surface of the first dielectric layer; and forming a second electrode layer on the surface of the second dielectric layer to form the capacitor structure.

[0015] In some embodiments, forming the second dielectric layer on the surface of the first dielectric layer includes: forming an intermediate layer on the surface of the first dielectric layer; forming the second dielectric layer on the surface of the intermediate layer; wherein the intermediate layer includes a first element in the first dielectric layer and a second element in the second dielectric layer.

[0016] In some embodiments, the first dielectric layer and the second dielectric layer are formed using an atomic layer deposition process.

[0017] In some embodiments, forming the second electrode layer on the surface of the second dielectric layer includes: forming a second sub-electrode layer on the surface of the second dielectric layer; forming a first sub-electrode layer on the surface of the second sub-electrode layer to form the second electrode layer; wherein the material of the first sub-electrode layer is different from the material of the first electrode layer, and the material of the second sub-electrode layer is the same as the material of the first electrode layer.

[0018] In this embodiment of the present disclosure, the capacitor structure includes two dielectric layers of different materials. The formation method may include first forming a first dielectric layer and then forming a second dielectric layer on the surface of the first dielectric layer. In this way, after the formation of the first dielectric layer, the quasi-isomorphic phase boundary can be formed in the second dielectric layer through the induction effect or interface modification effect of the first dielectric layer, thereby obtaining a dielectric layer material with a dielectric constant much larger than that of the tetragonal phase (T phase), thereby improving the capacitance value of the capacitor structure. Attached Figure Description

[0019] Figure 1 A schematic diagram of the structure of a dynamic random access memory provided in an embodiment of this disclosure;

[0020] Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure;

[0021] Figure 3 A schematic diagram of a capacitor structure provided in an embodiment of this disclosure;

[0022] Figure 4 A schematic diagram of another capacitor structure provided in this disclosure embodiment;

[0023] Figure 5 This is a schematic diagram of a capacitor structure with an intermediate layer provided in an embodiment of the present disclosure;

[0024] Figure 6 This is a schematic diagram of a semiconductor structure manufacturing method provided in an embodiment of the present disclosure;

[0025] Figures 7 to 16 This is a schematic diagram of the manufacturing process of a semiconductor structure provided in an embodiment of the present disclosure.

[0026] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0027] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0028] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0029] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0030] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0032] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0033] The semiconductor devices disclosed herein are at least a portion of those to be used in subsequent processes to form the final device structure. Here, the final device may include memory, including but not limited to dynamic random access memory (DRAM). The following description uses DRAM as an example only. However, it should be noted that the following descriptions of DRAM in the embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0034] With the development of dynamic random access memory technology, the size of memory cells is getting smaller and smaller, and their array architecture has increased from 8F. 2 Go to 6F 2 Then go to 4F 2 Furthermore, based on the requirements of dynamic random access memory for ions and leakage current, the memory architecture has evolved from planar array transistors to recessed gate array transistors, then from recessed gate array transistors to buried channel array transistors, and finally from buried channel array transistors to vertical channel array transistors.

[0035] In some embodiments of this disclosure, whether planar transistors or buried transistors, the dynamic random access memory is composed of multiple memory cells. Each memory cell consists of a transistor and a capacitor controlled by the transistor. That is, the dynamic random access memory includes a (1T1C) architecture of one transistor and one capacitor. Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0036] The following is combined with Figure 1 One architecture of dynamic random access memory is described in detail. In the introduction... Figure 1 Before illustrating the semiconductor device, we first define the various directions that may be used in the following description. The extension direction of the semiconductor body is defined as the first direction (i.e., the Z-axis direction). In a plane perpendicular to the Z-axis direction, we define the intersecting second direction (i.e., the X-axis direction) and the third direction (i.e., the Y-axis direction). In some embodiments, the X-axis direction, the Y-axis direction, and the Z-axis direction can be mutually perpendicular.

[0037] refer to Figure 1 , Figure 1 This is a cross-sectional view of a three-dimensional (3D) dynamic random access memory 100 including vertical transistors provided in an embodiment of this disclosure; as shown... Figure 1 As shown, the dynamic random access memory 100 includes a first device 102 and a second device 104 stacked on top of the first device 102 along the Z-axis direction. The first device 102 and the second device 104 are connected through a bonding interface 106. The first device 102 and the second device 104 can be connected by a hybrid bonding method or the like. In some embodiments, the second device 104 can be bonded to the top of the first device 102 face-to-face at the bonding interface 106.

[0038] The first device 102 may include a first substrate 1010, a peripheral circuit 1012 located on one side of the first substrate 1010, and a first interconnect layer 1016 located on the side of the peripheral circuit 1012 away from the first substrate 1010. The first interconnect layer 1016 is used to transmit electrical signals of the peripheral circuit 1012. The peripheral circuit 1012 may include a plurality of transistors 1014. In some embodiments, trench isolation (such as shallow trench isolation, STI) and doped regions (such as the well, source, and drain of the transistor 1014) may also be formed on or in the first substrate 1010.

[0039] The first device 102 may further include a first bonding layer 1018 located at the bonding interface 106 and on the side of the first interconnect layer 1016 away from the peripheral circuit 1012. The first bonding layer 1018 may include a plurality of first bonding contacts 1019 and a dielectric material electrically isolating the first bonding contacts 1019. The first bonding contacts 1019 in the first bonding layer 1018 and the surrounding dielectric material can be used for mixed bonding. Conversely, the second device 104 may also include a second bonding layer 1020 located at the bonding interface 106 and on the side of the first bonding layer 1018 away from the first interconnect layer 1016. The second bonding layer 1020 may include a plurality of second bonding contacts 1021 and a dielectric material electrically isolating the second bonding contacts 1021. The second bonding contacts 1021 in the second bonding layer 1020 and the surrounding dielectric material can be used for mixed bonding. Here, the second bonding contact 1021 contacts the first bonding contact 1019 at the bonding interface 106.

[0040] In some embodiments, the peripheral circuitry 1012 may further include word lines (WL) and word line drivers / row decoders coupled to the second interconnect layer 1022 via second bonding contacts 1021 in the second bonding layer 1020, first bonding contacts 1019 in the first bonding layer 1018, and the first interconnect layer 1016. In other embodiments, the peripheral circuitry 1012 may further include bit lines 1023 (BL) and bit line drivers / column decoders coupled to the second interconnect layer 1022 via second bonding contacts 1021 in the second bonding layer 1020, first bonding contacts 1019 in the first bonding layer 1018, and the first interconnect layer 1016. Here, the second interconnect layer 1022 includes bit lines 1023 above the second bonding layer 1020, and the bit lines 1023 are used to transmit electrical signals.

[0041] In other embodiments, the stacked first device 102 and second device 104 may not be connected by bonding, but rather integrated on the same substrate (only the first substrate, no second substrate), and directly connected through one or more interconnect layers between the first device 102 and the second device 104. In this case, the first device 102 does not have a first bonding layer 1018 and a first bonding contact 1019; the second device 104 does not have a second bonding layer 1020 and a second bonding contact 1021; and the bonding interface 106 between the first device 102 and the second device 104 also does not exist.

[0042] refer to Figure 1 The second device 104 also includes a memory cell array 1024 located on the second interconnect layer 1022. The memory cell array 1024 may include a plurality of memory cells, a second substrate 1048 located on the memory cell array 1024, and a third interconnect layer 1050 located on the second substrate 1048. Figure 1 The cross section of the dynamic random access memory 100 can be cut along the bit line direction (X-axis direction), and a bit line 1023 in the second interconnect layer 1022 extending laterally in the X-axis direction can be coupled to a column of memory cells.

[0043] Here, each memory cell may include a vertical transistor 1026 and a capacitor structure 1028 coupled to the vertical transistor 1026; the vertical transistor 1026 includes a semiconductor body 1030 extending vertically (in the Z-axis direction) and a gate structure 1036 contacting one side of the semiconductor body 1030 in the bit line direction (X-axis direction); in other embodiments, the gate structure may also completely surround the semiconductor body, partially surround the semiconductor body, or be located on two opposite sides of the semiconductor body, etc., which will not be elaborated here. Here, the gate structure 1036 includes a gate electrode 1034 and a gate dielectric 1032 located between the gate electrode 1034 and the semiconductor body 1030 in the bit line direction (X-axis direction). In some embodiments, the gate dielectric 1032 is adjacent to one side of the semiconductor body 1030, and the gate electrode 1034 is adjacent to the gate dielectric 1032.

[0044] In some embodiments, the semiconductor body 1030 has two ends (an upper end and a lower end) in the vertical direction (Z-axis direction), and one end (such as...) Figure 1 The lower end of the semiconductor body 1030 extends in the vertical direction (Z-axis direction) beyond the gate dielectric 1032 into the interlayer dielectric (ILD) layer, while the other end of the semiconductor body 1030 (such as...) Figure 1 The upper end of the semiconductor body 1030 is flush with the corresponding end of the gate dielectric 1032. In other embodiments, the two ends (upper and lower) of the semiconductor body 1030 extend in the vertical direction (Z-axis direction) beyond the gate electrode 1034 into the ILD layer. In other words, the semiconductor body 1030 may have a larger vertical dimension than the vertical dimension (e.g., depth in the Z-axis direction) of the gate electrode 1034, and neither the upper nor lower end of the semiconductor body 1030 is flush with the corresponding end of the gate electrode 1034. This avoids short circuits between the bit line 1023 and the gate electrode 1034 or between the gate electrode 1034 and the capacitor structure 1028.

[0045] The vertical transistor 1026 may further include a source 1038 and a drain 1040 respectively disposed at two ends (upper end and lower end) of the semiconductor body 1030 in the vertical direction (Z-axis direction). (The positions of the source and drain can be interchanged; here and below, the upper end is the source 1038 and the lower end is the drain 1040 as an example.) In some embodiments, the source 1038 is coupled to the capacitor structure 1028, and the drain 1040 is coupled to the bit line 1023.

[0046] Since the gate electrode 1034 can be part of a word line or extend as a word line in the word line direction, the second device 104 of the dynamic random access memory 100 can also include multiple word lines, each extending in the word line direction (Y-axis direction). Here, each word line can be coupled to a row of memory cells.

[0047] Vertical transistor 1026 extends vertically through and contacts the word line, and its drain 1040 at its lower end contacts the bit line 1023. Therefore, due to the vertical arrangement of the vertical transistor 1026, the word line and bit line 1023 can be arranged in different planes in the vertical direction, which simplifies the wiring of the word line and bit line 1023. Here, the vertical transistor 1026 can be arranged in a mirror-symmetric manner to increase the density of memory cells in the bit line direction (X-axis direction). Two adjacent vertical transistors 1026 in the bit line direction are mirror-symmetric with respect to trench isolation 1060; that is, the second device 104 may include a plurality of trench isolations 1060, each trench isolation 1060 extending parallel to the word line in the word line direction (Y-axis direction) and disposed between the semiconductor bodies 1030 of two adjacent rows of vertical transistors 1026. In some embodiments, rows of vertical transistors 1026 separated by trench isolation 1060 are mirror-symmetric with respect to trench isolation 1060. It should be understood that the trench isolation 1060 may include air gaps, each air gap being laterally disposed between adjacent semiconductor bodies 1030. The second device 104 also includes a plurality of gate isolations 1062, each gate isolation 1062 extending parallel to the word line in the word line direction (Y-axis direction) and disposed between word lines of two adjacent rows of vertical transistors 1026. It should be understood that the dimensions of the gate isolations 1062 and word lines in the bit line direction (X-axis direction) may be the same as or different from the dimensions of the trench isolation 1060 in the bit line direction (X-axis direction); when their dimensions in the bit line direction (X-axis direction) are different, the spacing between the plurality of semiconductor bodies 1030 arranged along the bit line direction (X-axis direction) is different, that is, the plurality of semiconductor bodies 1030 arranged along the bit line direction (X-axis direction) are non-uniformly arranged.

[0048] like Figure 1 As shown, capacitor structure 1028 can be a vertical capacitor. In some embodiments, a conductive structure 1064 is formed between the vertical transistor 1026 (further, for example, source 1038) and capacitor structure 1028 to reduce contact resistance.

[0049] like Figure 1As shown, the second device 104 may further include capacitive contacts 1047 that contact the common plate of the capacitor structure 1028 for coupling the capacitor structure 1028 to the peripheral circuit 1012 or directly to ground. In some embodiments, the ILD layer forming the capacitor structure 1028 has the same dielectric material, such as silicon oxide, as the two ILD layers into which the semiconductor body 1030 extends. The construction of the capacitor structure 1028 may include any suitable structure and construction, such as a planar capacitor, a stacked capacitor, a multi-fin capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-planar capacitor.

[0050] like Figure 1 As shown, the vertical transistor 1026 extends vertically through and contacts the word line. The drain 1040 at its lower end contacts the bit line 1023, and the source 1038 at its upper end contacts the capacitor structure 1028. That is, due to the vertical arrangement of the vertical transistor 1026, the bit line 1023 and the capacitor structure 1028 can be arranged in different planes in the vertical direction and coupled vertically to opposite ends of the vertical transistor 1026 of the memory cell. In some embodiments, the bit line 1023 and the capacitor structure 1028 are arranged on opposite sides of the vertical transistor 1026 in the vertical direction. Compared to conventional memory cells where the bit line and capacitor structure are arranged on the same side of a planar transistor, this simplifies the wiring of the bit line 1023 and reduces the coupling capacitance between the bit line 1023 and the capacitor structure 1028.

[0051] In some embodiments, the vertical transistor 1026 is vertically disposed between the capacitor structure 1028 and the bonding interface 106. That is, the vertical transistor 1026 can be arranged closer to the peripheral circuitry 1012 / bonding interface 106 of the first device 102 than the capacitor structure 1028. Since the bit line 1023 and the capacitor structure 1028 are coupled to opposite ends of the vertical transistor 1026, the bit line 1023 (as part of the second interconnect layer 1022) is vertically disposed between the vertical transistor 1026 and the bonding interface 106 to reduce interconnect wiring distance and complexity.

[0052] In some embodiments, the second device 104 further includes a second substrate 1048 disposed above the memory cell array 1024, and a third interconnect layer 1050 with pads disposed above the memory cell array 1024. The third interconnect layer 1050 with pads may include interconnects in one or more ILD layers, such as contact pads 1054.

[0053] In some embodiments, the second device 104 further includes one or more contacts 1052 extending through pads to lead out the third interconnect layer 1050 and the second substrate 1048, so as to lead out the third interconnect layer 1050 through the pads and couple to the memory cell and the second interconnect layer 1022. Thus, the peripheral circuitry 1012 can be coupled to the memory cell through the first interconnect layer 1016 and the second interconnect layer 1022, as well as the second bonding layer 1020 and the first bonding layer 1018, and the peripheral circuitry 1012 and the memory cell array 1024 can be led out through the contacts 1052 and the pads to the third interconnect layer 1050 and coupled to external circuitry.

[0054] With the development of semiconductor technology, the demand for storage capacity in memory is increasing, and the demand for storage density of the capacitor structure constituting the memory device is also constantly increasing. Here, the capacitor structure may include a first electrode layer, a dielectric layer covering the surface of the first electrode layer, and a second electrode layer covering the surface of the dielectric layer; the first electrode layer serves as the lower electrode of the capacitor structure; the dielectric layer serves as the dielectric of the capacitor structure; and the second electrode layer serves as the upper electrode of the capacitor structure. In practical applications, the capacitance can be increased by increasing the surface area of ​​the first electrode layer, the dielectric layer, and the second electrode layer; the capacitance can also be increased by decreasing the distance between the first electrode layer and the second electrode layer; or the capacitance can be increased by doping the dielectric layer to increase its dielectric constant.

[0055] However, as memory integration becomes increasingly sophisticated and overall size shrinks, the size and surface area of ​​capacitor structures are constantly decreasing. Therefore, increasing the storage capacity of capacitor structures has become an urgent problem to be solved.

[0056] In view of the above, based on one or more of the above problems, this disclosure provides a semiconductor device, the semiconductor device comprising: a semiconductor structure; the semiconductor structure comprising: a semiconductor body extending along a first direction; and a capacitor structure; the capacitor structure being located on one side of the semiconductor body along the first direction; wherein the capacitor structure comprises a first electrode layer, a first dielectric layer, a second dielectric layer, and a second electrode layer arranged sequentially; the first dielectric layer and the second dielectric layer are made of different materials.

[0057] Thus, by incorporating two dielectric layers of different materials into the capacitor structure, the overall dielectric constant of the dielectric layers can be increased, thereby enhancing the capacitance or capacity of the capacitor structure. Specific methods may include: first forming a first dielectric layer, and then forming a second dielectric layer on the surface of the first dielectric layer; wherein, after forming the first dielectric layer, the inductive effect or interface modification effect of the first dielectric layer can be used to create quasi-isomorphic phase boundaries in the second dielectric layer, thereby obtaining a dielectric layer material with a dielectric constant far greater than that of a tetragonal phase (T-phase), thus increasing the capacitance or capacity of the capacitor structure.

[0058] The specific structure of the semiconductor device described above will be described in detail below with reference to the accompanying drawings. In the following description, the first direction is the Z-axis direction, and the second direction intersects with the third direction and is perpendicular to the first direction. For example, the second direction is the X-axis direction, and the third direction is the Y-axis direction; the X-axis, Y-axis, and Z-axis directions can be mutually perpendicular.

[0059] refer to Figure 2 , Figure 2 A schematic cross-sectional view of another semiconductor device 200 in the XZ plane is shown. The semiconductor device 200 includes a semiconductor structure 210; the semiconductor structure 210 includes a semiconductor body 211 extending along the Z-axis direction; and a capacitor structure 212; the capacitor structure 212 is located on one side of the semiconductor body 211 along the Z-axis direction; wherein, in conjunction with reference to... Figure 2 ,refer to Figure 3 and Figure 4 The capacitor structure 212 includes a first electrode layer 301, a first dielectric layer 302, a second dielectric layer 303, and a second electrode layer 304 arranged in sequence; the first dielectric layer 302 and the second dielectric layer 303 are made of different materials.

[0060] The first electrode layer 301 serves as the lower electrode of the capacitor structure 212. The first dielectric layer 302 and the second dielectric layer 303 serve as the dielectric of the capacitor structure 212. The second electrode layer 304 serves as the upper electrode of the capacitor structure 212. Both the first electrode layer 301 and the second electrode layer 304 are made of conductive materials. Here, the conductive material can be one of the following: doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride (TiN), tantalum nitride, etc.), metallic materials (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). The thickness of the first electrode layer 301 and the second electrode layer 304 can be selected according to implementation requirements. The method for forming the first electrode layer 301 and the second electrode layer 304 includes a deposition process, which includes, but is not limited to, chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0061] In some embodiments, the second electrode layer may include two sub-electrode layers, such as a first sub-electrode layer and a second sub-electrode layer: the second sub-electrode layer is located between the first sub-electrode layer and the second dielectric layer; wherein the material of the first sub-electrode layer is different from the material of the first electrode layer, and the material of the second sub-electrode layer is the same as the material of the first electrode layer. For example, when the material of the first electrode layer is titanium nitride, the material of the first sub-electrode layer is tungsten (W); the material of the second sub-electrode layer is titanium nitride. Here, the first and second sub-electrode layers are used as the upper electrode of the capacitor structure. In addition, the first sub-electrode layer also improves the carrier mobility, enhances the conductivity and stability of the device, prevents metal diffusion into the second sub-electrode layer, enhances mechanical properties, and improves the reliability of the capacitor structure.

[0062] In other embodiments, the second electrode layer may further include three sub-electrode layers, such as a third sub-electrode layer, a fourth sub-electrode layer, and a fifth sub-electrode layer; the fourth sub-electrode layer is located between the third and fifth sub-electrode layers, and the fifth sub-electrode layer is located between the fourth sub-electrode layer and the second dielectric layer. Here, the materials of the third and fourth sub-electrode layers are different from the material of the first electrode layer, while the material of the fifth sub-electrode layer is the same as the material of the first electrode layer. For example, when the material of the first electrode layer is titanium nitride, the material of the fifth sub-electrode layer is titanium nitride (TiN), the material of the fourth sub-electrode layer is silicon germanium (SiGe), and the material of the third sub-electrode layer is tungsten (W). The third, fourth, and fifth sub-electrode layers together serve as the upper electrode plate. The methods for forming the third, fourth, and fifth sub-electrode layers can all include CVD, LPCVD, PECVD, PVD, ALD, etc.

[0063] Continue to refer to Figure 2 , Figure 3 and Figure 4 The first dielectric layer 302 and the second dielectric layer 303 are made of different materials. The first dielectric layer 302 is made of niobium oxide (Nb₂O₅). The second dielectric layer is made of one of hafnium oxide (HfO₂), zirconium oxide (ZrO₂), aluminum oxide (Al₂O₃), and tantalum oxide (TaO₂). The thickness of the first dielectric layer 302 is less than or equal to 1 angstrom. The thickness of the second dielectric layer 303 ranges from 1 nm to 10 nm. Methods for forming the first dielectric layer 302 include, but are not limited to, ALD; methods for forming the second dielectric layer 303 include, but are not limited to, CVD, LPCVD, PECVD, PVD, ALD, etc.

[0064] In this embodiment, the crystal phase of the second dielectric layer includes a ferroelectric phase and an antiferroelectric phase. In other words, the second dielectric layer has quasi-isomorphic phase boundaries, which can improve the dielectric constant of the second dielectric layer.

[0065] In some embodiments, the ferroelectric phase includes an orthorhombic phase (O phase); the antiferroelectric phase includes a monoclinic phase (M phase), a tetragonal phase (T phase), or a cubic phase (C phase). For example, the second dielectric layer contains both an orthorhombic and a monoclinic phase. Alternatively, the second dielectric layer contains both an orthorhombic and a tetragonal phase. Alternatively, the second dielectric layer contains both an orthorhombic and a cubic phase. In other embodiments, the second dielectric layer may also contain multiple other coexisting crystalline phases, such as the coexistence of orthorhombic, monoclinic, and tetragonal phases.

[0066] It should be noted that dielectric materials formed under common fabrication processes and parameters typically only possess an antiferroelectric phase. In this embodiment, the second dielectric layer contains both an antiferroelectric phase and a ferroelectric phase. The boundary between the antiferroelectric phase and the ferroelectric phase is a quasi-isomorphic phase boundary. In other words, the dielectric constant of the second dielectric layer in this disclosure is greater than that of dielectric materials with a single crystalline phase, thereby increasing the capacitance value of the capacitor structure described in this disclosure.

[0067] refer to Figure 3 and Figure 4 , Figure 3 and Figure 4 This is a schematic cross-sectional view of two different shaped capacitor structures on the XZ plane. The shapes of each layer in these two capacitor structures differ, but other aspects such as the formation method and materials are the same.

[0068] Figure 3 The semiconductor structure shown also includes a first support layer 305, a second support layer 306, a third support layer 307, and a protective layer 310. The first support layer 305, second support layer 306, and third support layer 307 serve a supporting function during the formation of the capacitor structure 212. The first support layer 305 includes, but is not limited to, silicon boron nitride (SiBN), and the materials of the second support layer 306 and third support layer 307 include, but are not limited to, silicon carbon nitride (SiCN). The protective layer 310 protects the third support layer 307 from damage during the formation of the capacitor structure 212. The material of the protective layer 310 includes, but is not limited to, silicon nitride (SiN). The methods for forming the first support layer 305, second support layer 306, third support layer 307, and protective layer 310 can include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD.

[0069] refer to Figure 3The semiconductor structure also includes a filler structure 311 located in the first electrode layer 301, which increases the surface area of ​​the first electrode layer and provides support. The filler structure 311 can be made of a conductive or non-conductive material. When the filler structure 311 is made of a conductive material, it can also serve as the lower electrode of the capacitor structure 212 together with the first electrode layer. For example, the filler structure 311 may be made of polysilicon, and methods for forming the filler structure 311 include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD.

[0070] Figure 4 The capacitor structure shown is cup-shaped (CUP), i.e., a CUP capacitor. In this capacitor structure 212, the cross-sectional shape of the first electrode layer 301, the first dielectric layer 302, the second dielectric layer 303, and the second electrode layer 304 in the XZ plane is cup-shaped or U-shaped. Furthermore, Figure 4 The capacitor structure shown also includes a filler layer 308 located in the second electrode layer 304. The material of the filler layer 308 includes, but is not limited to, polycrystalline silicon. The filler layer 308 can be used to provide support and improve the electrical performance of the capacitor structure.

[0071] In some embodiments, reference Figure 5 , Figure 5 for Figure 3 or Figure 4 A partially enlarged schematic diagram of the capacitor structure. The capacitor structure 212 further includes an intermediate layer 312, located between the first dielectric layer 302 and the second dielectric layer 303; the intermediate layer 312 includes a first element from the first dielectric layer 302 and a second element from the second dielectric layer 303.

[0072] In some embodiments, the first element includes niobium (Nb); the second element includes one of hafnium (Hf), zirconium (Zr), aluminum (Al), and tantalum (Ta).

[0073] In practice, after the formation of the first dielectric layer and in the initial stage of forming the second dielectric layer, an intermediate layer 312 can be formed based on the combination of a first element on the surface of the first dielectric layer and a second element used to form the second dielectric layer. Methods for forming the intermediate layer 312 include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD.

[0074] Return to reference Figure 2 The semiconductor body 211 is made of materials including, but not limited to, silicon (Si). Methods for forming the semiconductor body 211 include, but are not limited to, etching, ion implantation, and other processes. Here, the semiconductor body includes a channel region and source and drain electrodes located on opposite sides of the channel region in the Z-axis direction.

[0075] In some embodiments, the semiconductor structure further includes a gate structure; the gate structure is located on at least one side of the semiconductor body in the X-axis direction. For example, continuing to refer to... Figure 2 The gate structure 213 is located on one side of the semiconductor body 211 in the X-axis direction. Here, the gate structure 213 includes a gate electrode 2131 and a gate dielectric 2132 located between the gate electrode 2131 and the semiconductor body 211 in the X-axis direction. In some embodiments, the gate dielectric 2132 is adjacent to one side of the semiconductor body 211, and the gate electrode 2131 is adjacent to the gate dielectric 2132.

[0076] In some embodiments, reference Figure 2 The semiconductor structure 210 also includes a contact structure 214, which is located between the semiconductor body 211 and the capacitor structure 212. The contact structure 214 is used to reduce contact resistance. The material of the contact structure 214 includes titanium nitride, tungsten, etc. The methods for forming the contact structure 214 include, but are not limited to, CVD, LPCVD, PECVD, PVD, ALD, etc.

[0077] Based on the above-described semiconductor device, this disclosure also provides a method for manufacturing a semiconductor device. The semiconductor device includes a semiconductor structure, as shown in the reference... Figure 6 , Figure 6 This is a schematic flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure; the method includes:

[0078] Step S601: Form a semiconductor body extending along a first direction.

[0079] Step S602: Form a capacitor structure; the capacitor structure is located on one side of the semiconductor body along the first direction; wherein, the capacitor structure includes a first electrode layer, a first dielectric layer, a second dielectric layer and a second electrode layer arranged in sequence; the materials of the first dielectric layer and the second dielectric layer are different.

[0080] It should be understood that Figure 6 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 6 The steps shown can be adjusted in order according to actual needs. It should be noted that a semiconductor device may include one or more semiconductor structures; here and in the following text, we will use the example of a semiconductor device including multiple semiconductor structures.

[0081] It should be understood that the semiconductor structure is formed differently depending on the relative position of the gate structure and the semiconductor body. In this embodiment, the example is taken where the gate structure is located on one side of the semiconductor body in the X-axis direction, and the gate structures of two adjacent semiconductor structures are arranged face-to-face. However, it should be understood that the following description of the relative position of the gate structure and the semiconductor body is for illustrative purposes only and is not intended to limit the scope of this disclosure.

[0082] The formation process of the semiconductor structure is described in detail below with reference to the accompanying drawings.

[0083] In some embodiments, step S601 is performed to form a semiconductor body.

[0084] The method may specifically include: referencing Figure 7 A semiconductor layer 700 is provided, in which a plurality of first grooves extending along the X-axis and spaced apart along the Y-axis are formed, and an insulating material 701 is formed in the first grooves; and a plurality of second grooves 702 and a plurality of third grooves 703 extending along the Y-axis and alternately spaced along the X-axis are formed. The plurality of first grooves (or insulating material 701), the plurality of second grooves 702, and the plurality of third grooves 703 divide a portion of the semiconductor layer 700 into a plurality of semiconductor pillars 704 arranged in an array (e.g., ...). Figure 7 (As shown in the dashed box). The constituent materials of semiconductor layer 700 include, but are not limited to, silicon (Si).

[0085] In some embodiments, the first groove, the second groove 702, and the third groove 703 can be formed by a photolithography process (here and hereinafter understood as photolithography-etching (LE)). The order in which the first groove, the second groove 702, and the third groove 703 are formed can be selected and set according to the actual situation. The methods for forming the insulating material 701 include, but are not limited to, CVD, LPCVD, PECVD, PVD, ALD, etc.

[0086] Here, the dimensions of the second groove 702 along the X-axis can be the same as or different from those of the third groove 703 along the X-axis. Considering that the structures formed in the second groove 702 and the third groove 703 in subsequent processes are different, and that the area of ​​the semiconductor layer can be effectively utilized, the dimension of the third groove 703 along the X-axis is set to be larger than that of the second groove 702 along the X-axis.

[0087] In some embodiments, in conjunction with reference Figure 7 and Figure 8A trench isolation 705 is formed in the second groove 702. The trench isolation 705 can be used to reduce the coupling capacitance between two adjacent semiconductor devices. The constituent materials of the trench isolation 705 include, but are not limited to, silicon oxide. The methods for forming the trench isolation 705 include, but are not limited to, CVD, LPCVD, PECVD, PVD, ALD, etc.

[0088] A gate structure 706 is formed in the third recess 703, covering the sidewalls of the third recess 703. The gate structure includes a gate electrode 7061 and a gate dielectric 7062 located between the gate electrode 7061 and the semiconductor pillar 704 in the X-axis direction; the constituent material of the gate dielectric 7062 includes, but is not limited to, silicon oxide, and the constituent material of the gate electrode 7061 includes, but is not limited to, a metal (such as tungsten W). The methods for forming the gate dielectric 7062 and the gate electrode 7061 include, but are not limited to, CVD, LPCVD, PECVD, PVD, ALD, etc.

[0089] A gate isolation 707 is formed in the third recess in which the gate structure 706 is formed. The gate isolation 707 is used to isolate the two gate structures 706 that are arranged face to face. The material of the gate isolation 707 includes silicon oxide, and the methods for forming the gate isolation 707 include, but are not limited to, CVD, LPCVD, PECVD, PVD, ALD, etc.

[0090] In some embodiments, continue to refer to Figure 8 The method further includes: doping the opposite ends of the semiconductor pillar along the Z-axis direction, such as by ion implantation, to form a source 708 and a drain 709. The positions of the source 708 and the drain 709 can be interchanged. The region between the source 708 and the drain 709 is the channel region 710. The channel region 710, the source 708, and the drain 709 together constitute the semiconductor body 711.

[0091] Step S602: Forming a capacitor structure. It should be noted that the shape of the capacitor structure can include various forms, such as... Figure 3 and Figure 4 The two examples shown are formed using the same method, but the order in which the layers are formed differs. The following examples use... Figure 3 The capacitor structure shown is used as an example for illustration.

[0092] refer to Figure 9The process involves forming alternating layers of sacrificial and support layers to form a stacked structure, and forming a protective layer on the stacked structure. Exemplarily, the support layers include a first support layer 901, a second support layer 903, and a third support layer 905, and the sacrificial layers include a first sacrificial layer 902 and a second sacrificial layer 904. The material of the first support layer 901 includes silicon boron nitride (SiBN), and the materials of the second support layers 903 and the third support layer 905 include silicon carbon nitride (SiCN). The material of the first sacrificial layer 902 includes borosilicate glass (BPSG). The material of the second sacrificial layer 904 includes tetraethyl orthosilicate (TEOS). The material of the protective layer 906 includes silicon nitride (SiN). Methods for forming the first support layer 901, the first sacrificial layer 902, the second support layer 903, the second sacrificial layer 904, the third support layer 905, and the protective layer 906 include, but are not limited to, deposition processes, including but not limited to CVD, LPCVD, PECVD, PVD, ALD, etc.

[0093] Continue to refer to Figure 9 A capacitor via 907 is formed, penetrating the stacked structure along the Z-axis. Here, the capacitor via 907 also penetrates the protective layer 906. The number of capacitor vias can be determined based on the number of semiconductor substrates. Methods for forming the capacitor via 907 include, but are not limited to, etching.

[0094] refer to Figure 10 An electrode material layer 908 is formed on the sidewalls and bottom surface of the capacitor hole 907 and on the surface of the protective layer 906. The material of the electrode material layer 908 can be one of the following: doped semiconductor material (e.g., doped silicon, doped germanium, etc.), conductive metal nitride (e.g., titanium nitride (TiN), tantalum nitride, etc.), metallic material (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.), and metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0095] refer to Figure 11 The electrode material layer is etched back to remove the electrode material layer located on the surface of the protective layer 906, so as to form the first electrode layer 909 in the capacitor hole 907.

[0096] refer to Figure 12 A filling material layer 910 is formed in the capacitor hole where the first electrode layer 909 is formed and on the surface of the protective layer 906. The material of the filling material layer 910 includes polysilicon. The method for forming the filling material layer 910 includes, but is not limited to, deposition processes, including, but not limited to, CVD, LPCVD, PECVD, PVD, ALD, etc.

[0097] refer to Figure 13The filler material layer on the surface of the protective layer 906 is removed to form a filler structure 911 in the capacitor hole. The removal process includes, but is not limited to, chemical mechanical polishing (CMP).

[0098] Continue to refer to Figure 13 An opening 912 is formed in a support layer (such as a second support layer and a third support layer), exposing a sacrificial layer (such as a first sacrificial layer and a second sacrificial layer). The sacrificial layer (such as the first sacrificial layer and the second sacrificial layer) is removed based on the opening 912 to form a capacitor gap 913. The capacitor gap 913 exposes the surface of the first electrode layer 909. The removal process includes, but is not limited to, wet etching.

[0099] refer to Figure 14 A first dielectric layer 914 is formed on the surface of the first electrode layer 909 using the capacitor gap 913. The material of the first dielectric layer 914 includes niobium oxide (Nb2O5), and the method for forming the first dielectric layer 914 includes, but is not limited to, ALD. It should be noted that the first dielectric layer 914 is also located on the surface of the support layer exposed by the capacitor gap 913, the sidewall of the protective layer 906 exposed by the opening 912, and the surface of the protective layer 906.

[0100] refer to Figure 15 A second dielectric layer 915 is formed on the surface of the first dielectric layer 914 using a capacitor gap 913. The material of the second dielectric layer 915 includes one of hafnium oxide, zirconium oxide, aluminum oxide, and tantalum oxide. The formation of the second dielectric layer 915 includes, but is not limited to, deposition processes, including but not limited to CVD, LPCVD, PECVD, PVD, ALD, etc.

[0101] It should be noted that here, the first dielectric layer 914 plays an inductive or interface modification role, so that antiferroelectric and ferroelectric phases are formed in the second dielectric layer 915, that is, there are quasi-isomorphic phase boundaries in the second dielectric layer 915, thereby obtaining a dielectric layer material with a dielectric constant much larger than that of the tetragonal phase (T phase), thus improving the capacitance value or capacitance of the capacitor structure.

[0102] In some embodiments, the ferroelectric phase includes an orthorhombic phase (O phase); the antiferroelectric phase includes a monoclinic phase (M phase), a tetragonal phase (T phase), or a cubic phase (C phase). For example, the second dielectric layer contains both an orthorhombic and a monoclinic phase. Alternatively, the second dielectric layer contains both an orthorhombic and a tetragonal phase. Alternatively, the second dielectric layer contains both an orthorhombic and a cubic phase. In other embodiments, the second dielectric layer may also contain multiple other coexisting crystalline phases, such as the coexistence of orthorhombic, monoclinic, and tetragonal phases.

[0103] In some embodiments, the thickness of the first dielectric layer 302 is less than or equal to 1 angstrom. The thickness of the second dielectric layer 303 ranges from 1 nm to 10 nm.

[0104] In some embodiments, the method further includes: forming an intermediate layer on the surface of a first dielectric layer; forming a second dielectric layer on the surface of the intermediate layer; wherein the intermediate layer includes a first element in the first dielectric layer and a second element in the second dielectric layer. In other words, before forming the second dielectric layer, based on the current process conditions and parameters, the second element in the reaction source used to form the second dielectric layer first reacts with the first element on the surface of the first dielectric layer to generate an intermediate layer located on the surface of the first dielectric layer; as the reaction occurs, the second dielectric layer is then formed on the surface of the intermediate layer. Similarly, the intermediate layer can also serve an inductive or interface-modifying function to enable the formation of antiferroelectric and ferroelectric phases in the second dielectric layer, thereby increasing the capacitance or capacitance value of the capacitor structure.

[0105] In some embodiments, the first element includes niobium (Nb); the second element includes one of hafnium (Hf), zirconium (Zr), aluminum (Al), and tantalum (Ta).

[0106] refer to Figure 16 A second electrode layer 916 is formed on the surface of the second dielectric layer 915 using a capacitor gap to form a capacitor structure 917. The material of the second electrode layer 916 can be one of the following: doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride (TiN), tantalum nitride, etc.), metallic materials (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). Methods for forming the second electrode layer 916 include, but are not limited to, deposition processes, including but not limited to CVD, LPCVD, PECVD, PVD, ALD, etc.

[0107] In some embodiments, the second electrode layer may include two sub-electrode layers, such as a first sub-electrode layer and a second sub-electrode layer. Based on this, a method for forming the second electrode layer may include: forming the second sub-electrode layer on the surface of the second dielectric layer; and forming the first sub-electrode layer on the surface of the second sub-electrode layer to form the second electrode layer; the methods for forming the first and second sub-electrode layers may include CVD, LPCVD, PECVD, PVD, ALD, etc.

[0108] In this capacitor structure, the material of the first sub-electrode layer is different from that of the first electrode layer, while the material of the second sub-electrode layer is the same as that of the first electrode layer. For example, when the material of the first electrode layer is titanium nitride (TiN), the material of the first sub-electrode layer is tungsten (W); and the material of the second sub-electrode layer is titanium nitride (TiN). The first electrode layer serves as the lower electrode of the capacitor structure, and the first and second sub-electrode layers serve as the upper electrode of the capacitor structure. Furthermore, the first sub-electrode layer improves the carrier mobility of the upper electrode, enhances the conductivity and stability of the device, prevents metal diffusion in the second sub-electrode layer, strengthens mechanical properties, and improves the reliability of the capacitor structure.

[0109] In other embodiments, the second electrode layer may further include three sub-electrode layers, such as a third sub-electrode layer, a fourth sub-electrode layer, and a fifth sub-electrode layer; the fourth sub-electrode layer is located between the third and fifth sub-electrode layers, and the fifth sub-electrode layer is located between the fourth sub-electrode layer and the second dielectric layer. Based on this, a method for forming the second electrode layer may include: forming a fifth sub-electrode layer on the surface of the second dielectric layer, forming a fourth sub-electrode layer on the surface of the fifth sub-electrode layer, and forming a third sub-electrode layer on the surface of the fourth sub-electrode layer, thereby forming the second electrode layer.

[0110] Here, the materials of the third and fourth sub-electrode layers are different from the material of the first electrode layer, while the material of the fifth sub-electrode layer is the same as that of the first electrode layer. For example, when the material of the first electrode layer is titanium nitride, the material of the fifth sub-electrode layer is titanium nitride (TiN), the material of the fourth sub-electrode layer is silicon-germanium (SiGe), and the material of the third sub-electrode layer is tungsten (W). The third, fourth, and fifth sub-electrode layers together serve as the upper electrode of the capacitor structure. The methods for forming the third, fourth, and fifth sub-electrode layers can all include CVD, LPCVD, PECVD, PVD, ALD, etc.

[0111] In some embodiments, the capacitor structure can also take on various shapes, such as a cup-shaped capacitor (CUP), a cylindrical capacitor (CYL), and a pillar-shaped capacitor (PIL). The shape of the capacitor structure can be selected and set according to actual needs, and this disclosure does not limit it.

[0112] In some embodiments, reference Figure 16 The method further includes forming a contact structure 918 between the semiconductor substrate and the capacitor structure 917, wherein the contact structure 918 is used to reduce contact resistance. Materials for the contact structure include titanium nitride, tungsten, etc. Methods for forming the contact structure include, but are not limited to, CVD, LPCVD, PECVD, PVD, ALD, etc.

[0113] According to one aspect of this disclosure, a storage system is provided, comprising: a semiconductor device as described in the above embodiments of this disclosure; and a memory controller connected to the semiconductor device and configured to control the semiconductor device.

[0114] This disclosure provides specific embodiments, but its scope of protection is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: a semiconductor structure; The semiconductor structure includes: a semiconductor body extending along a first direction; and a capacitor structure located on one side of the semiconductor body along the first direction; The capacitor structure includes a first electrode layer, a first dielectric layer, a second dielectric layer, and a second electrode layer arranged in sequence; the first dielectric layer and the second dielectric layer are made of different materials.

2. The semiconductor device according to claim 1, characterized in that, The crystal phases of the second dielectric layer include a ferroelectric phase and an antiferroelectric phase.

3. The semiconductor device according to claim 2, characterized in that, The ferroelectric phase includes: orthorhombic phase; the antiferroelectric phase includes: monoclinic phase, tetragonal phase or cubic phase.

4. The semiconductor device according to claim 1, characterized in that, The material of the first dielectric layer includes niobium oxide; the material of the second dielectric layer includes one of hafnium oxide, zirconium oxide, aluminum oxide and tantalum oxide.

5. The semiconductor device according to claim 4, characterized in that, The thickness of the first dielectric layer is less than or equal to 1 angstrom; the thickness of the second dielectric layer is 1 to 10 nanometers.

6. The semiconductor device according to claim 1, characterized in that, The capacitor structure also includes: An intermediate layer is located between the first dielectric layer and the second dielectric layer; the intermediate layer includes a first element in the first dielectric layer and a second element in the second dielectric layer.

7. The semiconductor device according to claim 6, characterized in that, The first element includes niobium; the second element includes one of hafnium, zirconium, aluminum, and tantalum.

8. The semiconductor device according to claim 1, characterized in that, The second electrode layer includes: The first sub-electrode layer, and the second sub-electrode layer located between the first sub-electrode layer and the second dielectric layer; The material of the first sub-electrode layer is different from that of the first electrode layer, while the material of the second sub-electrode layer is the same as that of the first electrode layer.

9. The semiconductor device according to claim 1, characterized in that, The semiconductor structure also includes: A gate structure is located on at least one side of the semiconductor body in a second direction; the second direction is perpendicular to the first direction.

10. A storage system, characterized in that, include: The semiconductor device as described in any one of claims 1-9; And a memory controller, connected to the semiconductor device and used to control the semiconductor device.

11. A method for manufacturing a semiconductor device, characterized in that, The semiconductor device includes a semiconductor structure; The method of forming the semiconductor structure includes: A semiconductor body extending along the first direction is formed; A capacitor structure is formed; the capacitor structure is located on one side of the semiconductor body along the first direction; The capacitor structure includes a first electrode layer, a first dielectric layer, a second dielectric layer, and a second electrode layer arranged in sequence; the first dielectric layer and the second dielectric layer are made of different materials.

12. The manufacturing method according to claim 11, characterized in that, The formation of the capacitor structure includes: Alternating layers of sacrificial and supporting layers are formed to create a layered structure; Forming a capacitor hole that penetrates the stacked structure; The first electrode layer is formed on the sidewall and bottom of the capacitor hole; A filling structure is formed in the capacitor hole where the first electrode layer is formed; An opening is formed in the support layer, the opening exposing the sacrificial layer, and the sacrificial layer is removed based on the opening to expose the surface of the first electrode layer; The first dielectric layer is formed on the surface of the first electrode layer; The second dielectric layer is formed on the surface of the first dielectric layer; The second electrode layer is formed on the surface of the second dielectric layer to form the capacitor structure.

13. The manufacturing method according to claim 12, characterized in that, The step of forming the second dielectric layer on the surface of the first dielectric layer includes: An intermediate layer is formed on the surface of the first dielectric layer; The second dielectric layer is formed on the surface of the intermediate layer; The intermediate layer includes a first element in the first dielectric layer and a second element in the second dielectric layer.

14. The manufacturing method according to claim 13, characterized in that, The first dielectric layer and the second dielectric layer are formed using atomic layer deposition (ALD) technology.

15. The manufacturing method according to claim 13, characterized in that, The step of forming the second electrode layer on the surface of the second dielectric layer includes: A second sub-electrode layer is formed on the surface of the second dielectric layer; A first sub-electrode layer is formed on the surface of the second sub-electrode layer to form the second electrode layer; The material of the first sub-electrode layer is different from that of the first electrode layer, while the material of the second sub-electrode layer is the same as that of the first electrode layer.

Images