Semiconductor memory devices

Abstract

Examples of semiconductor memory devices include: a substrate; a bit line extending on the substrate in a first direction; a first back gate line extending in a second direction; a first semiconductor pattern connected to the bit line on the first back gate line and extending in a third direction; a word line extending on the first semiconductor pattern in a second direction; a second semiconductor pattern connected to the bit line on the word line and extending in a third direction; and a second back gate line extending on the second semiconductor pattern in a second direction.

Description

Cross-reference of related applications

[0001] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2025-0019115, filed on February 14, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a semiconductor memory device with improved integration density. Background Technology

[0003] To meet consumer demand for superior performance and low cost, it may be necessary to increase the integration density of semiconductor memory devices. Since the integration density of semiconductor memory devices can determine product cost, achieving higher integration density is particularly important.

[0004] For two-dimensional (2D) or planar semiconductor memory devices, integration density depends primarily on the area occupied by a single memory cell and is therefore significantly affected by the level of fine patterning technology. However, the integration density of 2D semiconductor memory devices can be limited by the use of expensive equipment to achieve finer patterns. Summary of the Invention

[0005] The purpose of this disclosure is to provide a semiconductor memory device comprising multiple memory cells.

[0006] The purpose of this disclosure is not limited to the above-described purposes, and other purposes not expressly stated will be clearly understood by those skilled in the art based on the following description.

[0007] According to one aspect of this disclosure, a semiconductor memory device includes: a substrate; a bit line extending on the substrate in a first direction; a first back gate line extending in a second direction; a first semiconductor pattern connected to the bit line on the first back gate line and extending in a third direction; a word line extending on the first semiconductor pattern in a second direction; a second semiconductor pattern connected to the bit line on the word line and extending in a third direction; and a second back gate line extending on the second semiconductor pattern in a second direction.

[0008] According to the above and other embodiments of the present invention, a semiconductor memory device includes: a substrate; a first back gate line and a second back gate line alternately arranged and spaced apart along a first direction on the substrate; word lines respectively located between adjacent first back gate lines and second back gate lines in the first direction; bit lines extending along the first direction on the substrate; first semiconductor patterns connected to the bit lines, and each first semiconductor pattern located between adjacent first back gate lines and word lines in the first direction; a memory node connected to the first semiconductor patterns; and second semiconductor patterns connected to the bit lines, and each second semiconductor pattern located between adjacent word lines and second back gate lines in the first direction.

[0009] According to the above and other embodiments of the present invention, a semiconductor memory device includes: a substrate; first back gate lines and second back gate lines alternately arranged and spaced apart along a first direction and extending along a second direction on the substrate; word lines extending in the second direction, with each word line located between adjacent first back gate lines and second back gate lines in the first direction; bit lines extending in the first direction and spaced apart in the second direction on the substrate; first semiconductor patterns connected to corresponding bit lines, each first semiconductor pattern located between adjacent first back gate lines and word lines in the first direction and extending upward in a third direction; and second semiconductor patterns connected to corresponding bit lines, each second semiconductor pattern located between adjacent word lines and second back gate lines in the first direction and extending upward in a third direction, wherein the first direction, the second direction, and the third direction intersect each other, and one of the first direction, the second direction, and the third direction is perpendicular to the upper surface of the substrate.

[0010] It should be noted that the effects of this disclosure are not limited to those described above, and other effects of this disclosure will become clear from the following description. Attached Figure Description

[0011] The above and other aspects and features of this disclosure will become clearer from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which: Figure 1 This is an exemplary circuit diagram of a semiconductor memory device according to some embodiments; Figure 2A and Figure 2B It is used for explanation Figure 1 A diagram illustrating write operations to memory cells; Figure 3A and Figure 3B It is used for explanation Figure 1 A diagram illustrating the read operation of a memory cell in the memory; Figure 4 This is an exemplary perspective view of a semiconductor memory device according to some embodiments; Figure 5 This is an exemplary perspective view of a semiconductor memory device according to some embodiments; Figure 6 yes Figure 5 An exemplary cross-sectional view of a semiconductor memory device; Figure 7 This is an exemplary perspective view of a semiconductor memory device according to some embodiments; Figure 8 This is an exemplary perspective view of a semiconductor memory device according to some embodiments; Figure 9 This is an exemplary perspective view of a semiconductor memory device according to some embodiments; Figure 10 yes Figure 9 An exemplary cross-sectional view of a semiconductor memory device; Figure 11 This is an exemplary perspective view of a semiconductor memory device according to some embodiments; Figure 12 and Figure 13 This is an exemplary perspective view of a semiconductor memory device according to some embodiments; Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A and Figure 27A It is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments; Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 26B and Figure 27B They are along Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A and Figure 27A A cross-sectional view taken from line A-A'; Figure 28A It is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments; Figure 28B It is along Figure 28A A cross-sectional view taken from line A-A'; Figure 29A , Figure 30A and Figure 31A It is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments; Figure 29B , Figure 30B and Figure 31B They are along Figure 29A , Figure 30A and Figure 31A A cross-sectional view taken by line A-A'; and Figure 32 It is a diagram used to illustrate the operation of a semiconductor memory device according to some embodiments. Detailed Implementation

[0012] Figure 1 This is an exemplary circuit diagram of a semiconductor memory device according to some embodiments.

[0013] Reference Figure 1 According to some embodiments, a semiconductor memory device may include a plurality of memory cells MC. The memory cells MC may be arranged in a two-dimensional (2D) or three-dimensional (3D) manner.

[0014] Multiple bit lines BL can extend along a first direction DR1 and can be arranged along a second direction DR2. Multiple word lines WL can extend along the second direction DR2 and can be spaced apart along the first direction DR1. A memory cell MC can be located between a word line WL and a bit line BL.

[0015] A first back gate line BG1 or a second back gate line BG2 may be located between two adjacent word lines WL. The first back gate line BG1 and the second back gate line BG2 may be arranged alternately along the first direction DR1. Two adjacent word lines WL may share a first back gate line BG1 or a second back gate line BG2. Two memory cells MC connected to the same bit line BL and adjacent to each other in the first direction DR1 may share a first back gate line BG1 or a second back gate line BG2.

[0016] Each memory cell MC may include a write transistor WTR and a read transistor RTR. The read transistor RTR and write transistor WTR of a memory cell MC may share a word line WL and a bit line BL. Here, the write transistor WTR and the read transistor RTR can be transistors of different conductivity types. For example, the write transistor WTR can be an n-type metal-oxide-semiconductor (NMOS) transistor, and the read transistor RTR can be a p-type metal-oxide-semiconductor (PMOS) transistor.

[0017] The write transistor WTR can be connected between the memory node SN and the bit line BL. The gate terminal of the write transistor WTR can be connected to the word line WL, the first source / drain terminal of the write transistor WTR can be connected to the memory node SN, and the second source / drain terminal of the write transistor WTR can be connected to the bit line BL.

[0018] The read transistor RTR can be connected between ground and bit line BL. The gate terminal of the read transistor RTR can be connected to word line WL, the first source / drain terminal of the read transistor RTR can be connected to bit line BL, and the second source / drain terminal of the read transistor RTR can be connected to ground.

[0019] A first back gate line BG1 or a second back gate line BG2 may be provided for the write transistor WTR or the read transistor RTR. Specifically, a first back gate line BG1 may be provided for the write transistor WTR, and a second back gate line BG2 may be provided for the read transistor RTR.

[0020] In a semiconductor memory device according to some embodiments, by adjusting the voltage applied to the first back gate line BG1 (e.g., a negative voltage) and the voltage applied to the second back gate line BG2 (e.g., a positive voltage), the cutoff current flowing through the write transistor WTR and the read transistor RTR in a standby state when the semiconductor memory device according to some embodiments is not performing a read or write operation can be reduced. Furthermore, in the standby state of the semiconductor memory device according to some embodiments, the cutoff current flowing through the write transistor WTR may not change according to the state of the memory node SN (whether it is logic high or logic low). Therefore, power consumption in the semiconductor memory device caused by changes in the cutoff current of the write transistor WTR according to the state of the memory node SN can be prevented or reduced. Furthermore, the semiconductor memory device according to some embodiments can maintain a stable standby state.

[0021] Semiconductor memory devices that include memory cells (MC) can also be referred to as dual-transistor zero-capacitor (2T-OC) memory devices. According to some embodiments, semiconductor memory devices may not include a separate capacitor for charge storage. Therefore, the area required to form the capacitor can be reduced, enabling higher integration and lower manufacturing costs for the semiconductor memory device.

[0022] Figure 2A and Figure 2B It is used for explanation Figure 1 A diagram illustrating the write operation of a memory cell.

[0023] Reference Figure 1 and Figure 2A A logic high voltage can be applied to the bit line BL. When a logic high voltage is applied to the word line WL, the write transistor WTR is turned on, and the read transistor RTR is turned off. Therefore, an electrical signal (or charge) from the bit line BL can be transferred (or charged) to the memory node SN, causing the memory node SN to become logic high. In this state, the data value 1 can be written to the memory cell MC.

[0024] Reference Figure 1 and Figure 2B A logic low voltage can be applied to the bit line BL. When a logic high voltage is applied to the word line WL, the write transistor WTR is turned on, and the read transistor RTR is turned off. Therefore, the memory node SN can be made logic low, and the data value 0 can be written to the memory cell MC.

[0025] Figure 3A and Figure 3B It is used for explanation Figure 1 A diagram illustrating the read operation of a memory cell.

[0026] Reference Figure 1 and Figure 3A The memory node SN can be in a logic high state. When a logic low voltage is applied to the word line WL, the read transistor RTR is turned on, and the write transistor WTR is turned off. Therefore, the electrical signal stored in the memory node SN can be read by the current flowing in the bit line BL. A logic high voltage can be applied to the bit line BL, and the data value 1 stored in the memory cell MC can be read. The memory node SN can remain in its logic high state even after a read operation. That is, the memory cell MC retains the data even after a read operation.

[0027] Reference Figure 1 and Figure 3BThe memory node SN can be in a logic low state. When a logic low voltage is applied to the word line WL, the read transistor RTR is turned on, and the write transistor WTR is turned off. Therefore, the electrical signal stored in the memory node SN can be read by the current flowing in the bit line BL. A logic low voltage can be applied to the bit line BL, and the data value 0 stored in the memory cell MC can be read. The memory node SN can remain in its logic low state even after a read operation. That is, the memory cell MC retains the data even after a read operation.

[0028] Figure 4 This is an exemplary perspective view of a semiconductor memory device according to some embodiments.

[0029] Reference Figure 4 According to some embodiments, a semiconductor memory device may include a substrate 100 and a stacked structure ST.

[0030] In one example, substrate 100 may be a silicon substrate, or may include other materials such as silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. In another example, substrate 100 may include a ceramic substrate, a quartz substrate, or a glass substrate. In yet another example, substrate 100 may include a flexible plastic substrate such as polyimide, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polymethyl methacrylate (PMMA), polycarbonate (PC), polyethersulfone (PES), or polyester.

[0031] The stacked structure ST may be located on the substrate 100. The surface on which the stacked structure ST is located may be referred to as the upper surface of the substrate 100. The stacked structure ST may include a plurality of memory cells MC arranged along the second direction DR2. The stacked structure ST may include bit lines BL, a first semiconductor pattern SP1, a second semiconductor pattern SP2, word lines WL, a first back gate line BG1, and a second back gate line BG2.

[0032] Bit lines BL may be located on substrate 100. Bit lines BL may extend in a first direction DR1. Bit lines BL may be spaced apart in a second direction DR2.

[0033] Bit lines BL may include conductive materials. For example, bit lines BL may include at least one of doped semiconductor materials, conductive metal nitrides, conductive metal silicon nitrides, metal carbonitrides, conductive metal silicides, conductive metal oxides, 2D materials, and metals. Bit lines BL are shown as a single layer, but are not limited thereto.

[0034] In semiconductor memory devices according to some embodiments, the 2D material can be a metallic material and / or a semiconductor material. The 2D material may include 2D allotropes or 2D compounds, and may include, for example, graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), tungsten disulfide (WS2), or combinations thereof, but this disclosure is not limited thereto. That is, the above-described 2D materials are merely exemplary, and the 2D materials that may be included in semiconductor memory devices according to some embodiments are not particularly limited.

[0035] A first semiconductor pattern SP1 may be located on a substrate 100. The first semiconductor pattern SP1 may extend along a third direction DR3. At the same height from the substrate 100, the first semiconductor pattern SP1 may be spaced apart along a second direction DR2.

[0036] Each of the first semiconductor patterns SP1 may include a first source / drain region, a second source / drain region, and a channel region between the first source / drain region and the second source / drain region. The first source / drain region and the second source / drain region may be located at opposite ends of the respective first semiconductor pattern SP1 on a third-direction DR3. The first source / drain region, the channel region, and the second source / drain region of the first semiconductor pattern SP1 may be used as... Figure 1 The first source / drain terminal, channel region, and second source / drain terminal of the write transistor WTR are included. The first source / drain region and the second source / drain region of the first semiconductor pattern SP1 may include n-type impurities, such as arsenic (As) or phosphorus (P).

[0037] The first semiconductor pattern SP1 can be electrically connected to the corresponding memory node SN. The memory node SN can be located on the first source / drain region of the first semiconductor pattern SP1. The first semiconductor pattern SP1 can be in contact with the memory node SN.

[0038] For example, the memory node SN may include the same material as the second semiconductor pattern SP2. In another example, the memory node SN may include a conductive material. The memory node SN may include at least one of the following: doped semiconductor material, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, and metal. The memory node SN is illustrated as a single layer, but is not limited thereto.

[0039] The second source / drain region of the first semiconductor pattern SP1 can be electrically connected to the corresponding bit line BL. The second source / drain region of the first semiconductor pattern SP1 can be in contact with the bit line BL.

[0040] For example, the first semiconductor pattern SP1 may include a semiconductor material. The first semiconductor pattern SP1 may include at least one of silicon, silicon germanium, and polycrystalline silicon, but is not limited thereto. In some embodiments, the first semiconductor pattern SP1 may include epitaxial silicon.

[0041] Each of the first semiconductor patterns SP1 may comprise an oxide semiconductor material. The first semiconductor pattern SP1 may include, for example, a metal oxide. In one example, each of the first semiconductor patterns SP1 may comprise an amorphous metal oxide film. In another example, each of the first semiconductor patterns SP1 may comprise a polycrystalline metal oxide film. In yet another example, each of the first semiconductor patterns SP1 may comprise a combination of an amorphous metal oxide film and a polycrystalline metal oxide film. In still another example, each of the first semiconductor patterns SP1 may comprise a c-axis aligned crystallization (CAAC) metal oxide film.

[0042] For example, the first semiconductor pattern SP1 may each include indium oxide, tin oxide, zinc oxide, In-Zn-based oxide, Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide, In-Ga-Zn-based oxide, In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, and In-Nd-Zn-based oxide. One of the following oxides: In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, and In-Hf-Al-Zn-based oxide, but not limited thereto.

[0043] Here, the term "In-Ga-Zn based oxide" refers to an oxide having In, Ga, and Zn as its main components, and does not indicate the ratio of In, Ga, and Zn. That is, in the case of, for example, In-Ga-Zn based oxide, the first semiconductor pattern SP1 may include indium gallium zinc oxide (IGZO, In x Ga y Zn zIGZO containing equal proportions of In, Ga, and Zn (In:Ga:Zn = 1:1:1) can be classified as In-Ga-Zn based oxides. Compared to IGZO (In:Ga:Zn = 1:1:1), Ga-rich IGZO can have a higher Ga content and a lower In content. Ga-rich IGZO can also be classified as In-Ga-Zn based oxides. Furthermore, compared to IGZO (In:Ga:Zn = 1:1:1), In-rich IGZO can have a higher indium content and a lower gallium content. In-rich IGZO can also be classified as In-Ga-Zn based oxides.

[0044] The above description has been provided using IGZO as an example, but this disclosure is not limited thereto. The above description still applies if the first semiconductor pattern SP1 comprises a ternary or higher metal oxide. Furthermore, when the first semiconductor pattern SP1 comprises an In-Ga-Zn based oxide, the first semiconductor pattern SP1 may also include doped metal elements in addition to In, Ga, and Zn.

[0045] The second semiconductor pattern SP2 may be located on the substrate 100. The second semiconductor pattern SP2 may extend along a third direction DR3. At the same height from the substrate 100, the second semiconductor pattern SP2 may be spaced apart along the second direction DR2.

[0046] The second semiconductor pattern SP2 may be located below the first semiconductor pattern SP1. The first semiconductor pattern SP1 may overlap with the second semiconductor pattern SP2 in the first direction DR1. The memory node SN may overlap with the second semiconductor pattern SP2 in the first direction DR1.

[0047] The second semiconductor pattern SP2 may each include a first source / drain region, a second source / drain region, and a channel region between the first source / drain region and the second source / drain region. The first source / drain region and the second source / drain region may be located at opposite ends of the respective second semiconductor pattern SP2 on a third-direction DR3. The first source / drain region, the channel region, and the second source / drain region of the second semiconductor pattern SP2 may be used as... Figure 1 The read transistor RTR in the second semiconductor pattern SP2 includes a first source / drain terminal, a channel region, and a second source / drain terminal. The first source / drain region and the second source / drain region of the second semiconductor pattern SP2 may include p-type impurities, such as boron (B) or aluminum (Al). The first semiconductor pattern SP1 may include impurities of a first conductivity type (e.g., n-type impurities), and the second semiconductor pattern SP2 may include impurities of a second conductivity type different from the first conductivity type (e.g., p-type impurities).

[0048] The first source / drain region of the second semiconductor pattern SP2 can be electrically connected to the corresponding bit line BL. The first source / drain region of the second semiconductor pattern SP2 can be in contact with the corresponding bit line BL. The second source / drain region of the second semiconductor pattern SP2 can be electrically connected to a ground line or a power line.

[0049] The second semiconductor pattern SP2 may include, for example, a semiconductor material or an oxide semiconductor material. The description of the semiconductor material and oxide semiconductor material included in the second semiconductor pattern SP2 may be substantially the same as the description of the semiconductor material and oxide semiconductor material included in the first semiconductor pattern SP1. In some embodiments, the second semiconductor pattern SP2 may include epitaxial silicon.

[0050] The word line WL may be located on the substrate 100. The word line WL may be located between a first semiconductor pattern SP1 and a second semiconductor pattern SP2 adjacent to the first semiconductor pattern SP1 in the first direction DR1. The word line WL may overlap with the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in the first direction DR1. The first semiconductor pattern SP1 and the second semiconductor pattern SP2 adjacent to the first semiconductor pattern SP1 in the first direction DR1 may share the word line WL.

[0051] The word line WL may extend in the second direction DR2. The word line WL may overlap with a first semiconductor pattern SP1 spaced apart in the second direction DR2 and a second semiconductor pattern SP2 adjacent to the first semiconductor pattern SP1 in the first direction DR1 and spaced apart in the second direction DR2. The first semiconductor pattern SP1 spaced apart in the second direction DR2 and the second semiconductor pattern SP2 adjacent to the first semiconductor pattern SP1 in the first direction DR1 and spaced apart in the second direction DR2 may share the word line WL.

[0052] The first back gate line BG1 may be located on the substrate 100. The first back gate line BG1 may be located on the first semiconductor pattern SP1. The first semiconductor pattern SP1 may be located between the word line WL and the first back gate line BG1 adjacent to the word line WL in the first direction DR1. The first back gate line BG1 may overlap with the first semiconductor pattern SP1 in the first direction DR1.

[0053] The first back gate line BG1 may extend in the second direction DR2. The first back gate line BG1 may overlap with a first semiconductor pattern SP1 spaced apart in the second direction DR2. The first semiconductor pattern SP1 spaced apart in the second direction DR2 may share the first back gate line BG1. The first back gate line BG1 may overlap with a word line WL in the first direction DR1.

[0054] The second back gate line BG2 may be located on the substrate 100. The second back gate line BG2 may be located below the second semiconductor pattern SP2. The second semiconductor pattern SP2 may be located between the word line WL and the second back gate line BG2 adjacent to the word line WL in the first direction DR1. The second back gate line BG2 may overlap with the second semiconductor pattern SP2 in the first direction DR1.

[0055] The second back gate line BG2 may extend in the second direction DR2. The second back gate line BG2 may overlap with a second semiconductor pattern SP2 spaced apart in the second direction DR2. The second semiconductor pattern SP2 spaced apart in the second direction DR2 may share the second back gate line BG2. The second back gate line BG2 may overlap with a word line WL in the first direction DR1. The second back gate line BG2 may overlap with a first back gate line BG1 in the first direction DR1.

[0056] The word line WL, the first back gate line BG1, and the second back gate line BG2 may each comprise a conductive material. For example, the word line WL, the first back gate line BG1, and the second back gate line BG2 may each comprise at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a 2D material, and a metal. The word line WL, the first back gate line BG1, and the second back gate line BG2 are shown as a single layer, but are not limited thereto.

[0057] The first direction DR1 can be perpendicular to the second direction DR2 and the third direction DR3. The second direction DR2 can intersect with the third direction DR3.

[0058] In some embodiments, the first direction DR1 may be perpendicular to the upper surface of the substrate 100, and the second direction DR2 and the third direction DR3 may be parallel to the upper surface of the substrate 100. That is, the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may extend along the third direction DR3 parallel to the upper surface of the substrate 100. The bit line BL may extend along the first direction DR1 perpendicular to the upper surface of the substrate 100, and the word line WL, the first back gate line BG1, and the second back gate line BG2 may extend along the second direction DR2 parallel to the upper surface of the substrate 100.

[0059] Figure 5 This is an exemplary perspective view of a semiconductor memory device according to some embodiments. Figure 6 yes Figure 5 An exemplary cross-sectional view of a semiconductor memory device is shown. For convenience, the following description will focus on the reference. Figures 1 to 4 The differences in the described implementation methods.

[0060] Reference Figure 5 and Figure 6In a semiconductor memory device according to some embodiments, a stacked structure ST may include a plurality of memory cells MC arranged along a first direction DR1 and a second direction DR2. The stacked structure ST may include a bit line BL, a first semiconductor pattern SP1, a second semiconductor pattern SP2, a word line WL, a first back gate line BG1, and a second back gate line BG2.

[0061] The second back gate line BG2 and the first back gate line BG1 may be alternately spaced apart along the first direction DR1. Each word line WL may be located between adjacent first back gate lines BG1 and second back gate lines BG2 along the first direction DR1. Each second semiconductor pattern SP2 may be located between adjacent word lines WL and second back gate lines BG2 along the first direction DR1. Each first semiconductor pattern SP1 and each memory node SN may be located between adjacent word lines WL and first back gate lines BG1 along the first direction DR1.

[0062] An adjacent second semiconductor pattern SP2 on the first direction DR1 may overlap with and share the second back gate line BG2 located therebetween on the first direction DR1. An adjacent first semiconductor pattern SP1 on the first direction DR1 may overlap with and share the first back gate line BG1 located therebetween on the first direction DR1. An adjacent first semiconductor pattern SP1 on the first direction DR1 may share the first back gate line BG1 located therebetween.

[0063] The stacked structure ST may also include a protective insulating layer 105, a first insulating layer 110, a second insulating layer 120, a third insulating layer 130, a fourth insulating layer 140, a fifth insulating layer 150, a sixth insulating layer 160, and a seventh insulating layer 170.

[0064] A protective insulating layer 105 may be located on the substrate 100. A second back gate line BG2 may be located within a first insulating layer 110. The first insulating layer 110 may be located between the bit line BL and the second back gate line BG2. A second insulating layer 120 may be located between the second semiconductor pattern SP2 and the first insulating layer 110, and between the second back gate line BG2 adjacent to the first insulating layer 110 in the first direction DR1. A word line WL may be located within a fourth insulating layer 140. The fourth insulating layer 140 may be located between the bit line BL and the word line WL. A third insulating layer 130 may be located between the second semiconductor pattern SP2 and the fourth insulating layer 140, and between the word lines WL adjacent to the fourth insulating layer 140 in the first direction DR1. A fifth insulating layer 150 may be located within the fourth insulating layer 140, and between the word line WL adjacent to the fourth insulating layer 140 in the first direction DR1 and the memory node SN. A first back gate line BG1 may be located within a seventh insulating layer 170. The seventh insulating layer 170 may be located between the bit line BL and the first back gate line BG1. The sixth insulating layer 160 may be located between the first semiconductor pattern SP1, the memory node SN adjacent to the first semiconductor pattern SP1 along the first direction DR1, the first back gate line BG1, and the seventh insulating layer 170.

[0065] In the first direction, two adjacent memory cells MC of DR1 can be symmetrical about their shared first back gate line BG1 or second back gate line BG2.

[0066] For example, two adjacent memory cells MC on the first direction DR1 may share a first back gate line BG1 and a seventh insulating layer 170. In this example, below the shared first back gate line BG1 and the seventh insulating layer 170, the first insulating layer 110 and the second back gate line BG2, the second insulating layer 120, the second semiconductor pattern SP2, the third insulating layer 130, the word line WL and the fourth insulating layer 140, the fifth insulating layer 150, the first semiconductor pattern SP1 and the memory node SN, and the sixth insulating layer 160 may be stacked sequentially along the first direction DR1, and above the shared first back gate line BG1 and the seventh insulating layer 170, the sixth insulating layer 160, the first semiconductor pattern SP1 and the memory node SN, the fifth insulating layer 150, the word line WL and the fourth insulating layer 140, the third insulating layer 130, the second semiconductor pattern SP2, the second insulating layer 120, the second back gate line BG2 and the first insulating layer 110 may be stacked sequentially along the first direction DR1. For example, two adjacent memory cells MC on the first direction DR1 may share a second back gate line BG2 and a first insulating layer 110. In this example, below the shared second back gate line BG2 and the first insulating layer 110, the first back gate line BG1 and the seventh insulating layer 170, the sixth insulating layer 160, the first semiconductor pattern SP1 and the memory node SN, the fifth insulating layer 150, the word line WL and the fourth insulating layer 140, the third insulating layer 130, the second semiconductor pattern SP2 and the second insulating layer 120 may be stacked sequentially, and above the shared second back gate line BG2 and the first insulating layer 110, the second insulating layer 120, the second semiconductor pattern SP2, the third insulating layer 130, the word line WL and the fourth insulating layer 140, the fifth insulating layer 150, the first semiconductor pattern SP1 and the memory node SN, the sixth insulating layer 160, the first back gate line BG1 and the seventh insulating layer 170 may be stacked sequentially along the first direction DR1.

[0067] Protective insulating layer 105, first insulating layer 110, second insulating layer 120, third insulating layer 130, fourth insulating layer 140, fifth insulating layer 150, sixth insulating layer 160, and seventh insulating layer 170 may each comprise an insulating material. For example, protective insulating layer 105, first insulating layer 110, second insulating layer 120, third insulating layer 130, fourth insulating layer 140, fifth insulating layer 150, sixth insulating layer 160, and seventh insulating layer 170 may each comprise silicon oxide, silicon oxynitride, a high-k insulating material having a higher dielectric constant than silicon oxide, or a combination thereof. The high-k insulating material may comprise metal oxides or metal oxynitrides. For example, the high-k insulating material may comprise at least one of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, aluminum oxide, and lanthanum oxide, but is not limited thereto.

[0068] Although not shown, insulating layers may be located between adjacent bit lines BL on the second direction DR2, between adjacent protective insulating layers 105 on the second direction DR2, between adjacent first insulating layers 110 on the second direction DR2, between adjacent second insulating layers 120 on the second direction DR2, between adjacent first semiconductor patterns SP1 on the second direction DR2, between adjacent third insulating layers 130 on the second direction DR2, between adjacent fourth insulating layers 140 on the second direction DR2, between adjacent fifth insulating layers 150 on the second direction DR2, between the second semiconductor pattern SP2 and the memory node SN adjacent to the second semiconductor pattern SP2 on the second direction DR2, between adjacent sixth insulating layers 160 on the second direction DR2, and between adjacent seventh insulating layers 170 on the second direction DR2. Furthermore, the second semiconductor pattern SP2 may protrude beyond the memory node SN on the third direction DR3.

[0069] Figure 7 This is an exemplary perspective view of a semiconductor memory device according to some embodiments. For convenience, the following description will focus on the reference... Figure 5 and Figure 6 The differences in the described implementation methods.

[0070] Reference Figure 7 In a semiconductor memory device according to some embodiments, the stacked structure ST may be spaced apart on the third-direction DR3.

[0071] For example, a stacked structure ST may include a first stacked structure ST1 and a second stacked structure ST2 adjacent to the first stacked structure ST1 on a third direction DR3. The first stacked structure ST1 and the second stacked structure ST2 may be arranged alternately on the third direction DR3. A pair of first stacked structures ST1 and second stacked structures ST2 adjacent on the third direction DR3 may be symmetrical about an imaginary extension line extending between them along a first direction DR1. For example, in a pair of first stacked structures ST1 and second stacked structures ST2 adjacent along the third direction DR3, bit lines BL in the first stacked structure ST1 and bit lines BL in the second stacked structure ST2 may be arranged in opposite directions, and the first stacked structures ST1 and the second stacked structures ST2 may be symmetrical about an imaginary extension line (e.g., an axis) extending between the bit lines BL of the first stacked structure ST1 and the bit lines BL of the second stacked structure ST2 along the first direction DR1.

[0072] Figure 8 This is an exemplary perspective view of a semiconductor memory device according to some embodiments. For convenience, the following description will focus on the reference... Figures 1 to 4 The differences in the described implementation methods.

[0073] Reference Figure 8In a semiconductor memory device according to some embodiments, the stacked structure ST may further include a first shielding gate line SG1 and a second shielding gate line SG2.

[0074] The first shielding gate line SG1 may be located on the memory node SN. The first shielding gate line SG1 may be spaced apart from the first back gate line BG1 on the third direction DR3. The first shielding gate line SG1 may overlap with the memory node SN on the first direction DR1.

[0075] A first shielding gate line SG1 may extend along a second direction DR2. The first shielding gate line SG1 may overlap with memory nodes SN that are spaced apart along the second direction DR2 and adjacent along the first direction DR1. The memory nodes SN spaced apart along the second direction DR2 may share the first shielding gate line SG1. The first shielding gate line SG1 may maintain or enhance the electric field effect on the memory nodes SN. Therefore, the hold time of the semiconductor memory device according to some embodiments may be increased. The voltage applied to the first shielding gate line SG1 may be adjusted according to the characteristics of the memory cell MC.

[0076] The second shielding gate line SG2 may be located below the second semiconductor pattern SP2. The second shielding gate line SG2 may be spaced apart from the second back gate line BG2 on the third direction DR3. The second shielding gate line SG2 may overlap with the second semiconductor pattern SP2 on the first direction DR1.

[0077] The second shielding gate line SG2 may extend along the second direction DR2. The second shielding gate line SG2 may overlap with a second semiconductor pattern SP2 spaced apart along the second direction DR2. The second semiconductor patterns SP2 spaced apart along the second direction DR2 may share the second shielding gate line SG2. The second shielding gate line SG2 may increase the current flowing through the read transistor RTR. Therefore, the read operation margin of the semiconductor memory device according to some embodiments may be increased. The voltage applied to the second shielding gate line SG2 may be adjusted according to the characteristics of the memory cell MC.

[0078] The first shielding gate line SG1 and the second shielding gate line SG2 may each comprise a conductive material. For example, the first shielding gate line SG1 and the second shielding gate line SG2 may each comprise at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a 2D material, and a metal. The first shielding gate line SG1 and the second shielding gate line SG2 are shown as a single layer, but are not limited thereto.

[0079] Figure 9 This is an exemplary perspective view of a semiconductor memory device according to some embodiments. Figure 10 yes Figure 9An exemplary cross-sectional view of a semiconductor memory device is shown. For convenience, the following description will focus on the reference. Figure 8 The differences in the described implementation methods.

[0080] Reference Figure 9 and Figure 10 In a semiconductor memory device according to some embodiments, a stacked structure ST may include a plurality of memory cells MC arranged along a first direction DR1 and a second direction DR2. The stacked structure ST may include a bit line BL, a first semiconductor pattern SP1, a second semiconductor pattern SP2, a word line WL, a first back gate line BG1, a first shield gate line SG1, a second back gate line BG2, and a second shield gate line SG2.

[0081] Each of the first shielding gate lines SG1 may be located between two adjacent memory nodes SN on the first direction DR1. Each of the second shielding gate lines SG2 may be located between two adjacent second semiconductor patterns SP2 on the first direction DR1.

[0082] Adjacent memory nodes SN on the first direction DR1 may overlap with and share the first shielded gate line SG1 located between them on the first direction DR1. The first shielded gate line SG1 may be located within the seventh insulating layer 170. The seventh insulating layer 170 may be located between the first back gate line BG1 and the first shielded gate line SG1. A sixth insulating layer 160 may be located between the first shielded gate line SG1 and the memory node SN adjacent to the first shielded gate line SG1 on the first direction DR1.

[0083] An adjacent second semiconductor pattern SP2 on the first direction DR1 may overlap with and share the second shielding gate line SG2 located therebetween on the first direction DR1. The second shielding gate line SG2 may be located within the first insulating layer 110. The first insulating layer 110 may be located between the second back gate line BG2 and the second shielding gate line SG2. The second insulating layer 120 may be located between the second shielding gate line SG2 and the second semiconductor pattern SP2 adjacent to the second shielding gate line SG2 on the first direction DR1.

[0084] Two memory cells MC connected to the same bit line BL and adjacent in the first direction DR1 may share a first back gate line BG1 and a first shield gate line SG1, or a second back gate line BG2 and a second shield gate line SG2. Two adjacent memory cells MC in the first direction DR1 may be symmetrical about their shared first back gate line BG1 and first shield gate line SG1, or their shared second back gate line BG2 and second shield gate line SG2.

[0085] Figure 11This is an exemplary perspective view of a semiconductor memory device according to some embodiments. For convenience, the following description will focus on the reference... Figure 9 and Figure 10 The differences in the described implementation methods.

[0086] Reference Figure 11 In a semiconductor memory device according to some embodiments, the stacked structure ST may be spaced apart on the third-direction DR3.

[0087] For example, a stacked structure ST may include a first stacked structure ST1 and a second stacked structure ST2 adjacent to the first stacked structure ST1 on a third direction DR3. The first stacked structure ST1 and the second stacked structure ST2 may be arranged sequentially on the third direction DR3. A pair of first stacked structures ST1 and second stacked structures ST2 adjacent on the third direction DR3 may be symmetrical about an imaginary extension line extending between them along a first direction DR1. For example, in a pair of first stacked structures ST1 and second stacked structures ST2 adjacent along the third direction DR3, bit lines BL in the first stacked structure ST1 and bit lines BL in the second stacked structure ST2 may be arranged in opposite directions, and the first stacked structures ST1 and second stacked structures ST2 may be symmetrical about an imaginary extension line extending between the bit lines BL of the first stacked structure ST1 and the bit lines BL of the second stacked structure ST2 along the first direction DR1.

[0088] Figure 12 and Figure 13 This is an exemplary perspective view of a semiconductor memory device according to some embodiments. For convenience, the following description will focus on the reference... Figures 1 to 4 The differences in the described implementation methods.

[0089] Reference Figure 12 and Figure 13 In a semiconductor memory device according to some embodiments, a first direction DR1 and a second direction DR2 may be parallel to the upper surface of the substrate 100, and a third direction DR3 may be perpendicular to the upper surface of the substrate 100. That is, a first semiconductor pattern SP1 and a second semiconductor pattern SP2 may extend along the third direction DR3 perpendicular to the upper surface of the substrate 100. The bit line BL may extend along the first direction DR1 parallel to the upper surface of the substrate 100, and the word line WL, the first back gate line BG1, and the second back gate line BG2 may extend along the second direction DR2 parallel to the upper surface of the substrate 100.

[0090] Unlike the diagram shown, the stacked structure ST may include multiple memory cells MC arranged on a first direction DR1 and a second direction DR2. Two memory cells MC connected to the same bit line BL and adjacent on the first direction DR1 may share a first back gate line BG1 or a second back gate line BG2. Adjacent second semiconductor patterns SP2 on the first direction DR1 may share a second back gate line BG2 located therebetween. Adjacent first semiconductor patterns SP1 on the first direction DR1 may share a first back gate line BG1 located therebetween. Adjacent memory cells MC on the first direction DR1 may be symmetrical about their shared first back gate line BG1 or second back gate line BG2.

[0091] Reference Figure 13 In a semiconductor memory device according to some embodiments, each memory cell MC may further include a first shielding gate line SG1 and a second shielding gate line SG2. The first shielding gate line SG1 and the second shielding gate line SG2 may extend in a second direction DR2 parallel to the upper surface of the substrate 100.

[0092] Unlike what is shown, in some embodiments, the stacked structure ST may include a plurality of memory cells MC arranged on a first direction DR1 and a second direction DR2. Two memory cells MC connected to the same bit line BL and adjacent on the first direction DR1 may share a first back gate line BG1 and a first shield gate line SG1, or a second back gate line BG2 and a second shield gate line SG2. Two adjacent second semiconductor patterns SP2 on the first direction DR1 may share a second back gate line BG2 and a second shield gate line SG2 located therebetween. Two adjacent first semiconductor patterns SP1 on the first direction DR1 may share a first back gate line BG1 and a first shield gate line SG1 located therebetween. Two memory cells MC adjacent on the first direction DR1 may be symmetrical about their shared first back gate line BG1 or second back gate line BG2. Specifically, two memory cells MC adjacent on the first direction DR1 may be symmetrical about their shared first back gate line BG1 and first shield gate line SG1 or their shared second back gate line BG2 and second shield gate line SG2.

[0093] Figures 14A to 27A This is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments. Figures 14B to 27B They are along Figures 14A to 27A The cross-sectional view taken by line A-A'. For convenience, the following description will focus on the reference. Figures 1 to 6 The differences in the described implementation methods.

[0094] Reference Figure 14A and Figure 14BA protective insulating layer 105 can be formed on the substrate 100. The protective insulating layer 105 can cover the upper surface of the substrate 100.

[0095] Subsequently, a second back gate line BG2 can be formed on the protective insulating layer 105. The second back gate line BG2 can extend in the second direction DR2.

[0096] For example, a mask pattern including an opening exposing a portion of the upper surface of the protective insulating layer 105 can be formed on the protective insulating layer 105. An initial gate line can be formed on the mask pattern and the opening, and the mask pattern and the initial gate line on the mask pattern can be removed to form a second back gate line BG2. In another example, an initial gate line can be formed on the protective insulating layer 105, and then the initial gate line can be patterned to form the second back gate line BG2.

[0097] Reference Figure 15A and Figure 15B A first insulating layer 110 may be formed on the protective insulating layer 105. The first insulating layer 110 may surround the second back gate line BG2. The upper surface of the second back gate line BG2 may be exposed through the first insulating layer 110.

[0098] Subsequently, a second insulating layer 120 may be formed on the first insulating layer 110 and the second back gate line BG2.

[0099] Reference Figure 16A and Figure 16B A first mask pattern MP1, including a first opening OP1, can be formed on the second insulating layer 120. The first opening OP1 can expose a portion of the upper surface of the second insulating layer 120. The first openings OP1 can be spaced apart in the second direction DR2.

[0100] Reference Figure 17A and Figure 17B The first trench T1 can be formed using the first mask pattern MP1 as an etching mask. Etching can be performed through the first opening OP1 of the first mask pattern MP1. Figure 16A and Figure 16B The first trench T1 is formed by a protective insulating layer 105, a first insulating layer 110, and a second insulating layer 120. The first trench T1 may expose at least some portions of the substrate 100. The first trench T1 may be spaced apart from the second back gate line BG2 on a third direction DR3. The first trench T1 may also be spaced apart on a second direction DR2.

[0101] Reference Figure 18A and Figure 18B It can remove ( Figure 17A and Figure 17B The first mask pattern MP1 in the middle.

[0102] Subsequently, a second semiconductor film 25 can be formed. The second semiconductor film 25 can be formed by an epitaxial growth process using the substrate 100 as a seed layer. The second semiconductor film 25 can be an epitaxial silicon film. Therefore, there may be no boundary between the substrate 100 and the second semiconductor film 25, and the second semiconductor film 25 can fill the first trench T1. The second semiconductor film 25 can cover the second insulating layer 120.

[0103] Reference Figure 19A and Figure 19B A planarization process can be performed on the second semiconductor film 25. For example, a chemical mechanical polishing (CMP) process can be performed on the second semiconductor film 25.

[0104] Subsequently, the second semiconductor film 25 on the second insulating layer 120 can be patterned to form a second semiconductor pattern SP2. The second semiconductor pattern SP2 can extend on the third direction DR3 and can be spaced apart on the second direction DR2. A doping process can also be performed to form a second semiconductor pattern SP2, each including a channel region and a first source / drain region and a second source / drain region.

[0105] Reference Figure 20A and Figure 20B A third insulating layer 130 can be formed on the second semiconductor pattern SP2. The third insulating layer 130 can fill the space between the second semiconductor patterns SP2. The third insulating layer 130 can cover the second semiconductor pattern SP2 and the second insulating layer 120.

[0106] Subsequently, word lines WL can be formed on the third insulating layer 130. Word lines WL can extend in the second direction DR2. Word lines WL can overlap with the second semiconductor pattern SP2 in the first direction DR1.

[0107] For example, a mask pattern including an opening exposing a portion of the upper surface of the third insulating layer 130 may be formed on the third insulating layer 130. Initial gate lines may be formed on the mask pattern and the opening, and the mask pattern and the initial gate lines on the mask pattern may be removed to form a word line WL. In another example, initial gate lines may be formed on the third insulating layer 130 and then patterned to form a word line WL.

[0108] Reference Figure 21A and Figure 21B A fourth insulating layer 140 may be formed on the third insulating layer 130. The fourth insulating layer 140 may surround the word line WL. The upper surface of the word line WL may be exposed through the fourth insulating layer 140.

[0109] Subsequently, a fifth insulating layer 150 may be formed on the fourth insulating layer 140 and the word line WL.

[0110] Reference Figure 22A and Figure 22B A second mask pattern MP2, including a second opening OP2, can be formed on the fifth insulating layer 150. The second opening OP2 can expose a portion of the upper surface of the fifth insulating layer 150. The second opening OP2 can overlap with the second semiconductor film 25 in the first direction DR1. The second openings OP2 can be spaced apart in the second direction DR2.

[0111] Reference Figure 23A and Figure 23B The second mask pattern MP2 can be used as an etching mask to form the second trench T2. This can be achieved by passing through (…). Figure 22A and Figure 22B The second opening OP2 of the second mask pattern MP2 is etched with the third insulating layer 130, the fourth insulating layer 140, and the fifth insulating layer 150 to form the second trench T2. The second trench T2 may expose at least some portions of the second semiconductor film 25. The second trench T2 may be spaced apart from the word line WL on the third direction DR3. The second trench T2 may also be spaced apart on the second direction DR2.

[0112] Reference Figure 24A and Figure 24B It can remove ( Figure 23A and Figure 23B The second mask pattern MP2.

[0113] Subsequently, a first semiconductor film 15 can be formed. The first semiconductor film 15 can be formed by an epitaxial growth process using a second semiconductor film 25 as a seed layer. The first semiconductor film 15 can be an epitaxial silicon film. Therefore, there may be no boundary between the first semiconductor film 15 and the second semiconductor film 25. The first semiconductor film 15 can fill the second trench T2. The first semiconductor film 15 can cover a fifth insulating layer 150.

[0114] Then, a planarization process can be performed on the first semiconductor film 15, for example, a CMP process can be performed on the first semiconductor film 15.

[0115] Subsequently, the first semiconductor film 15 on the fifth insulating layer 150 can be patterned to form a first semiconductor pattern SP1. The first semiconductor pattern SP1 can extend on the third direction DR3 and can be spaced apart on the second direction DR2. A doping process can also be performed to form a first semiconductor pattern SP1, each including a channel region and a first source / drain region and a second source / drain region. The first semiconductor pattern SP1 can overlap with the word line WL on the first direction DR1. A memory node SN can be formed at the end of the corresponding first semiconductor pattern SP1 on the third direction DR3. The memory node SN can contact the end of the corresponding first semiconductor pattern SP1. The memory nodes SN can be spaced apart on the second direction DR2.

[0116] Reference Figure 25A and Figure 25B A sixth insulating layer 160 may be formed on the first semiconductor pattern SP1 and the memory node SN. The sixth insulating layer 160 may fill the space between the first semiconductor patterns SP1 and between the memory nodes SN. The sixth insulating layer 160 may cover the first semiconductor pattern SP1 and the memory node SN.

[0117] Subsequently, a first back gate line BG1 can be formed on the sixth insulating layer 160. The first back gate line BG1 can extend in the second direction DR2. The first back gate line BG1 can overlap with the first semiconductor pattern SP1 in the first direction DR1.

[0118] For example, a mask pattern including an opening exposing a portion of the upper surface of the sixth insulating layer 160 can be formed on the sixth insulating layer 160. An initial gate line can be formed on the mask pattern and the opening, and the mask pattern and the initial gate line on the mask pattern can be removed to form a first back gate line BG1. In another example, an initial gate line can be formed on the sixth insulating layer 160 and then patterned to form the first back gate line BG1.

[0119] Reference Figure 26A and Figure 26B A seventh insulating layer 170 may be formed on the sixth insulating layer 160. The seventh insulating layer 170 may surround the first back gate line BG1. The upper surface of the first back gate line BG1 may be exposed through the seventh insulating layer 170.

[0120] Subsequently, another sixth insulating layer 160 may be formed on the seventh insulating layer 170 and the first back gate line BG1.

[0121] Subsequently, a third mask pattern MP3, including a third opening OP3, can be formed on the uppermost sixth insulating layer 160 relative to the upper surface of the substrate 100. The third opening OP3 can expose a portion of the upper surface of the uppermost sixth insulating layer 160 relative to the upper surface of the substrate 100. The third opening OP3 can overlap with the first semiconductor film 15 in the first direction DR1. The third opening OP3 can be spaced apart in the second direction DR2.

[0122] Reference Figure 26A , Figure 26B , Figure 27A and Figure 27BA third trench can be formed by etching through the third opening OP3 of the third mask pattern MP3 to sequentially stack the sixth insulating layer 160, the seventh insulating layer 170, and the sixth insulating layer 160 on the first semiconductor pattern SP1 and the memory node SN. The third trench can expose at least some portions of the first semiconductor film 15 and can be spaced apart from the first back gate line BG1 on the third direction DR3. The third trench can also be spaced apart on the second direction DR2. The third mask pattern MP3 can be removed, and using the first semiconductor film 15 as a seed layer, the first semiconductor film 15 filling the third trench and covering the uppermost sixth insulating layer 160 relative to the upper surface of the substrate 100 can be formed via an epitaxial growth process. These formed first semiconductor films 15 are then patterned to form the first semiconductor pattern SP1. The memory node SN can be formed at the end of the corresponding first semiconductor pattern SP1 on the third direction DR3.

[0123] After that, use Figures 14A to 26B The manufacturing process shown can also form a first insulating layer 110, a second insulating layer 120, a third insulating layer 130, a fourth insulating layer 140, a fifth insulating layer 150, a sixth insulating layer 160, a seventh insulating layer 170, a first back gate line BG1, a word line WL, a second back gate line BG2, a first semiconductor film 15, a second semiconductor film 25, a first semiconductor pattern SP1, and a second semiconductor pattern SP2, thereby forming an initial stacked structure pST.

[0124] The initial stacked structure pST is symmetrical about the second back gate line BG2 and the first insulating layer 110 in the first direction DR1, and also symmetrical about the first back gate line BG1 and the seventh insulating layer 170. The first insulating layer 110 and the second back gate line BG2, the second insulating layer 120, the second semiconductor pattern SP2, the third insulating layer 130, the fourth insulating layer 140 and the word line WL, the fifth insulating layer 150, the first semiconductor pattern SP1 and the memory node SN, and the sixth insulating layer 160 located below the first back gate line BG1 and the seventh insulating layer 170 in the first direction DR1 are arranged symmetrically with the sixth insulating layer 160, the first semiconductor pattern SP1 and the memory node SN, the fifth insulating layer 150, the fourth insulating layer 140 and the word line WL, the third insulating layer 130, the second semiconductor pattern SP2, the second insulating layer 120, the first insulating layer 110 and the second back gate line BG2 located above the first back gate line BG1 and the seventh insulating layer 170 in the first direction DR1. The fifth insulating layer 150 can each fill the space between the first semiconductor pattern SP1 and the memory node SN located below it along the first direction DR1. The sixth insulating layer 160 can each fill the space between the first semiconductor pattern SP1 and the memory node SN located below it along the first direction DR1. The second insulating layer 120 can each fill the space between the second semiconductor patterns SP2 located below it along the first direction DR1. The third insulating layer 130 can each fill the space between the second semiconductor patterns SP2 located below it along the first direction DR1.

[0125] The first semiconductor film 15 and the second semiconductor film 25 may be stacked in the first direction DR1. Therefore, a sacrificial film 5 may be formed, each comprising the first semiconductor film 15 and the second semiconductor film 25 stacked in the first direction DR1. The sacrificial films 5 may be spaced apart in the second direction DR2 and may extend in the first direction DR1.

[0126] Subsequently, refer to Figure 27A , Figure 27B , Figure 5 and Figure 6Bit lines BL can be formed in the space where the sacrificial film 5 has been removed. Bit lines BL can extend in a first direction DR1 and can be spaced apart in a second direction DR2. A first insulating layer 110, a second insulating layer 120, a third insulating layer 130, a fourth insulating layer 140, a fifth insulating layer 150, a sixth insulating layer 160, and a seventh insulating layer 170 can be located between adjacent bit lines BL in the second direction DR2. Memory cells MC can be formed on a first side of the bit lines BL in the third direction DR3. Furthermore, insulating layers can be formed on a second side of the bit lines BL in the third direction DR3 where no memory cells MC are formed. Here, the second side can be opposite the first side in the third direction DR3. That is, the first semiconductor pattern SP1 and the second semiconductor pattern SP2 on the second side of the bit lines BL in the third direction DR3 can be removed. Therefore, a stacked structure ST, each comprising a plurality of memory cells MC, can be formed. Figure 5 and Figure 6 It could be that some parts were omitted. Figure 27A and Figure 27B The diagram shows the bit line BL on the second side of the third direction DR3.

[0127] Figure 28A This is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments. Figure 28B It is along Figure 28A The cross-sectional view taken by line A-A'. For convenience, the following description will focus on the reference. Figures 14A to 27B The differences in the described implementation methods.

[0128] Reference Figure 28A and Figure 28B Multiple initial stacked structures pST can be formed simultaneously.

[0129] For example, a first initial stacked structure pST1 and a second initial stacked structure pST2 ​​adjacent to each other on a third-direction DR3 can be formed simultaneously. Each of the following components of the first initial stacked structure pST1—a protective insulating layer 105, a first back gate line BG1 and a second back gate line BG2, a word line WL, a first insulating layer 110, a second insulating layer 120, a third insulating layer 130, a fourth insulating layer 140, a fifth insulating layer 150, a sixth insulating layer 160, and a seventh insulating layer 170, a first semiconductor film 15 and a second semiconductor film 25, a first semiconductor pattern SP1 and a memory node SN, and a second semiconductor pattern SP2—can be formed simultaneously with a corresponding component of the second initial stacked structure pST2. For example, in… Figure 14A and Figure 14B In this process, a second back gate line BG2 spaced apart from the third-direction DR3 can be formed on the protective insulating layer 105 to form each of the first initial stacked structure pST1 and the second initial stacked structure pST2.

[0130] The first initial stacked structure pST1 may include a first sacrificial film 51, each sacrificial film 51 including a first semiconductor film 15 and a second semiconductor film 25 stacked on a first direction DR1. Similarly, the second initial stacked structure pST2 ​​may include a second sacrificial film 52, each second sacrificial film 52 including a first semiconductor film 15 and a second semiconductor film 25 stacked on a first direction DR1. The first semiconductor films 15 may be spaced apart on a second direction DR2, and the second sacrificial films 52 may also be spaced apart on a second direction DR2. The first sacrificial film 51 may be opposite the second sacrificial film 52 on a third direction DR3. The first initial stacked structure pST1 and the second initial stacked structure pST2 ​​may be symmetrical on a third direction DR3 about an imaginary extension line extending along the first direction DR1 between the first sacrificial films 51 and 52. For example, the first back gate line BG1 and the second back gate line BG2, the first semiconductor pattern SP1, the memory node SN, and the word line WL of the first initial stacked structure pST1 may be symmetrical on a third direction DR3 about corresponding components of the second initial stacked structure pST2.

[0131] Reference Figure 28A , Figure 28B and Figure 7 Bit lines BL can be formed in the spaces where the first sacrificial film 51 and the second sacrificial film 52 have been removed. An insulating layer extending in the first direction DR1 can be formed between the bit lines BL of the first initial stacked structure pST1 and the second initial stacked structure pST2. That is, the first semiconductor pattern SP1 and the second semiconductor pattern SP2 located between the bit lines BL of the first initial stacked structure pST1 and the second initial stacked structure pST2 ​​can be removed. Therefore, a first stacked structure ST1 and a second stacked structure ST2 including sets of bit lines BL in opposite directions can be formed simultaneously, as shown in the example. Figure 7 As shown. Unlike the example shown, a first initial stacking structure pST1 and a second initial stacking structure pST2, alternately arranged on a third-direction DR3, can be formed simultaneously, as shown below. Figure 28A and 28B As shown, this results in the simultaneous formation of a first stacked structure ST1 and a second stacked structure ST2 alternately arranged on the third-direction DR3, as follows: Figure 7 As shown.

[0132] Figures 29A to 31A This is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments. Figures 29B to 31B They are along Figures 29A to 31A The cross-sectional view taken by line A-A'. For convenience, the following description will focus on the reference. Figures 1 to 28B The differences in the described implementation methods.

[0133] Reference Figure 29A and Figure 29B A second back gate line BG2 and a second shield gate line SG2 may be formed on the protective insulating layer 105, spaced apart on the third direction DR3. The second back gate line BG2 and the second shield gate line SG2 may extend on the second direction DR2.

[0134] For example, a mask pattern comprising two openings exposing portions of the upper surface of the protective insulating layer 105 can be formed on the protective insulating layer 105. Initial gate lines can be formed on the mask pattern and the two openings, and the mask pattern and the initial gate lines on the mask pattern can be removed to form a second back gate line BG2 and a second shield gate line SG2. In another example, initial gate lines can be formed on the protective insulating layer 105 and then patterned to form the second back gate line BG2 and the second shield gate line SG2.

[0135] Reference Figure 30A and Figure 30B A first insulating layer 110 can be formed around the second back gate line BG2 and the second shield gate line SG2. Subsequently, a second insulating layer 120 can be formed on the first insulating layer 110, the second back gate line BG2, and the second shield gate line SG2.

[0136] After that, use Figures 16A to 25B The manufacturing process shown can form a second semiconductor pattern SP2, a second semiconductor film 25, a third insulating layer 130, a word line WL, a fourth insulating layer 140, a fifth insulating layer 150, a first semiconductor pattern SP1, a memory node SN, and a sixth insulating layer 160.

[0137] Subsequently, a first back gate line BG1 and a first shield gate line SG1 can be formed on the sixth insulating layer 160, spaced apart on the third direction DR3. The first back gate line BG1 and the first shield gate line SG1 can extend on the second direction DR2.

[0138] For example, a mask pattern including two openings exposing portions of the upper surface of the sixth insulating layer 160 can be formed on the sixth insulating layer 160. Initial gate lines can be formed on the mask pattern and the two openings, and the mask pattern and the initial gate lines on the mask pattern can be removed to form a first back gate line BG1 and a first shield gate line SG1. In another example, initial gate lines can be formed on the sixth insulating layer 160 and then patterned to form the first back gate line BG1 and the first shield gate line SG1.

[0139] Reference Figure 31A and Figure 31B A seventh insulating layer 170 can be formed around the first back gate line BG1 and the first shield gate line SG1.

[0140] After that, use Figures 29A to 31B The manufacturing process shown can further form a first insulating layer 110, a second insulating layer 120, a third insulating layer 130, a fourth insulating layer 140, a fifth insulating layer 150, a sixth insulating layer 160, a seventh insulating layer 170, a second shielding gate line SG2, a first semiconductor film 15, a second semiconductor film 25, a first semiconductor pattern SP1, and a second semiconductor pattern SP2, thereby forming an initial stacked structure pST. The initial stacked structure pST is symmetrical about the second back gate line BG2 and the first insulating layer 110 in the first direction DR1, and about the first back gate line BG1 and the seventh insulating layer 170.

[0141] Reference Figure 31A , Figure 31B , Figure 9 and Figure 10 Bit lines BL can be formed in the spaces where sacrificial film 5 has been removed. An insulating layer extending on third-direction DR3 can be formed on the second side of the bit lines BL where no memory cells MC are formed. Thus, a stacked structure ST, each comprising multiple memory cells MC, can be formed. Figure 9 and Figure 10 It could be omitted. Figure 31A and Figure 31B The diagram shows the bit line BL on the second side of the third direction DR3.

[0142] Figure 32 It is a diagram used to illustrate the operation of a semiconductor memory device according to some embodiments.

[0143] Reference Figure 32 Semiconductor memory devices according to some embodiments can be configured to selectively perform multiplication and accumulation (MAC) operations based on an operating mode. Semiconductor memory devices according to some embodiments may correspond to reference... Figures 1 to 13 The description refers to any one of its corresponding components.

[0144] For example, a semiconductor memory device according to some embodiments may operate as an in-memory processing (PIM) device in a first operating mode, or as a memory for a host device in a second operating mode. A semiconductor memory device according to some embodiments may operate in either the first or second operating mode in response to a mode selection signal from the host device.

[0145] In a first operating mode, the semiconductor memory device, according to some embodiments, can perform MAC operations. In a second operating mode, the semiconductor memory device can operate in a manner similar to that of a conventionally used volatile memory device. In the second operating mode, the semiconductor memory device, according to some embodiments, can operate as the main memory of a host device.

[0146] A first operating mode may be as follows. For example, a semiconductor memory device according to some embodiments may include a first memory cell MC1 connected to bit line BL and a first word line WL1, a second memory cell MC2 connected to bit line BL and a second word line WL2, and a sense amplifier SA connected to bit line BL. The sense amplifier SA can sense the voltage level of bit line BL, which varies according to the on / off state of the first word line WL1 and the second word line WL2 and the data values ​​stored in the first memory node SN1 and the second memory node SN2, and the sense amplifier SA can perform a weighted sum operation. The sense amplifier SA can generate output data Y, which is a weighted sum of input data X based on the on / off state of the first word line WL1 and the second word line WL2 and the weights W of the data values ​​stored in the first memory node SN1 and the second memory node SN2. If the first word line WL1 and the second word line WL2 are on, the input data X can be 1, and if the first word line WL1 and the second word line WL2 are off, the input data X can be 0. The off-state of the first word line WL1 and the second word line WL2 corresponds to the state when a logic high voltage is applied to the first word line WL1 and the second word line WL2, thereby turning off the read transistor RTR. The on-state of the first word line WL1 and the second word line WL2 corresponds to the state when a logic low voltage is applied to the word lines WL1 and WL2, thereby turning on the read transistor RTR. If the data value stored in the first memory node SN1 and the second memory node SN2 is 0, the weight W can be 0; and if the data value stored in the memory nodes SN1 and SN2 is 1, the weight W can be 1.

[0147] According to some embodiments, a semiconductor memory device can perform read operations on a first memory cell MC1 and a second memory cell MC2 to perform continuous MAC operations. For example, according to some embodiments, a semiconductor memory device can continuously perform read operations on the first memory cell MC1, perform read operations on the second memory cell MC2, and then perform read operations on both the first memory cell MC1 and the second memory cell MC2 to perform continuous MAC operations.

[0148] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to these embodiments and can be made in various other forms. Those skilled in the art will understand that the technical scope or essential features of the present disclosure can be modified and implemented in other specific forms without departing from the spirit of the invention. Therefore, the above embodiments should be understood as illustrative in all respects and not restrictive.

[0149] While this disclosure includes numerous specific implementation details, these should not be construed as limiting the scope of the claims. Certain features described in the context of individual embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations, one or more features from a combination may be removed from the combination in some cases, and combinations may be for sub-combinations or variations thereof.

Claims

1. A semiconductor memory device, comprising: Substrate; Bit lines that extend along a first direction on the substrate; A first back gate line extends in the second direction; A first semiconductor pattern is connected to the bit line, the first semiconductor pattern extending upward on a third side and located on the first back gate line; Word lines that extend along the second direction on the first semiconductor pattern; A second semiconductor pattern is connected to the bit line, the second semiconductor pattern extending upward on the third party and located on the word line; as well as The second back gate line extends along the second direction on the second semiconductor pattern.

2. The semiconductor memory device of claim 1, wherein, The word line overlaps with the first back gate line and the second back gate line in the first direction.

3. The semiconductor memory device as claimed in claim 1, wherein, The first direction is perpendicular to the upper surface of the substrate, and The second direction and the third direction are parallel to the upper surface of the substrate.

4. The semiconductor memory device of claim 1, wherein, The third direction is perpendicular to the upper surface of the substrate, and The first direction and the second direction are parallel to the upper surface of the substrate.

5. The semiconductor memory device of claim 1, wherein, The bit line, the first back gate line, the first semiconductor pattern, the word line, the second semiconductor pattern, and the second back gate line form a stacked structure. The stacking structure includes a first stacking structure and a second stacking structure that are adjacent to each other on the third side, and The first stacked structure and the second stacked structure are symmetrical about an axis extending along the first direction between the first stacked structure and the second stacked structure.

6. The semiconductor memory device of claim 1, wherein, The bit lines are spaced apart in the second direction. The first semiconductor pattern is spaced apart in the second direction, connected to corresponding bit lines, and overlaps with the first back gate line and the word line in the first direction. The second semiconductor pattern is spaced apart in the second direction, connected to the corresponding bit line, and overlaps with the word line and the second back gate line in the first direction.

7. The semiconductor memory device of claim 1, comprising: A storage node connected to the first semiconductor pattern; A first shielding gate line is spaced apart from the first back gate line along the third direction on the memory node; as well as The second shielding gate line is spaced apart from the second back gate line along the third direction on the second semiconductor pattern.

8. The semiconductor memory device of claim 7, wherein, The first shielding gate line overlaps with the memory node in the first direction, and The second shielding gate line overlaps with the second semiconductor pattern in the first direction.

9. The semiconductor memory device of claim 7, wherein, The first shielding gate line and the second shielding gate line overlap in the first direction.

10. The semiconductor memory device of claim 7, wherein, The first shielding gate line and the second shielding gate line extend in the second direction. The bit lines are spaced apart in the second direction. The first semiconductor pattern is spaced apart in the second direction and connected to corresponding bit lines. The second semiconductor pattern is spaced apart in the second direction, connected to corresponding bit lines, and overlaps with the first shielding gate line in the first direction. The storage nodes are spaced apart in the second direction, connected to a corresponding first semiconductor pattern, and overlap with the second shielding gate line in the first direction.

11. The semiconductor memory device of claim 1, wherein, The first semiconductor pattern and the second semiconductor pattern comprise epitaxial silicon.

12. The semiconductor memory device of claim 1, wherein, The first semiconductor pattern includes impurities of a first conductivity type, and The second semiconductor pattern includes impurities of a second conductivity type that are different from the first conductivity type.

13. A semiconductor memory device, comprising: Substrate; A first back gate line and a second back gate line are alternately arranged along a first direction on the substrate, the first back gate line and the second back gate line being spaced apart. Word lines, each word line being located between adjacent corresponding first back gate lines and second back gate lines in the first direction; Bit lines that extend on the substrate along the first direction; A first semiconductor pattern is connected to the bit line, each of the first semiconductor patterns being located between a corresponding first back gate line in the first direction and a corresponding word line in the word line. A storage node connected to the first semiconductor pattern; as well as A second semiconductor pattern is connected to the bit line, each of the second semiconductor patterns being located between a corresponding word line in the adjacent word lines in the first direction and a corresponding second back gate line in the second back gate line.

14. The semiconductor memory device of claim 13, wherein, The first back gate line, the second back gate line, and the word line extend in a second direction. The first semiconductor pattern and the second semiconductor pattern extend upward in a third direction. The first direction is perpendicular to the upper surface of the substrate, and The second direction and the third direction are parallel to the upper surface of the substrate.

15. The semiconductor memory device of claim 13, wherein, The first back gate line, the second back gate line, and the word line extend in a second direction. The first semiconductor pattern and the second semiconductor pattern extend upward in a third direction. The third direction is perpendicular to the upper surface of the substrate, and The first direction and the second direction are parallel to the upper surface of the substrate.

16. The semiconductor memory device of claim 13, comprising: A first shielding gate line is spaced apart from a corresponding first back gate line in a third direction, and the first shielding gate line overlaps with the memory node in the first direction. as well as The second shielding gate line is spaced apart from the corresponding second back gate line in the third direction, and the second shielding gate line overlaps with the second semiconductor pattern in the first direction.

17. The semiconductor memory device of claim 13, wherein, The bit line, the first back gate line, the first semiconductor pattern, the word line, the second semiconductor pattern, and the second back gate line form a stacked structure. The stacking structure includes a first stacking structure and a second stacking structure that are adjacent to each other, and The first stacked structure and the second stacked structure are symmetrical about an axis extending along the first direction between the first stacked structure and the second stacked structure.

18. The semiconductor memory device of claim 13, wherein, The first back gate line, the second back gate line, and the word line overlap in the first direction.

19. A semiconductor memory device, comprising: Substrate; A first back gate line and a second back gate line are alternately arranged on the substrate along a first direction, the first back gate line and the second back gate line being spaced apart, and the first back gate line and the second back gate line extending along a second direction; Word lines extending in the second direction, each of the word lines being located between a corresponding first back gate line among the first back gate lines adjacent in the first direction and a corresponding second back gate line among the second back gate lines; Bit lines that extend on the substrate in the first direction and are spaced apart in the second direction; A first semiconductor pattern is connected to a corresponding bit line, each of the first semiconductor patterns being located between a corresponding first back gate line in the first direction and a corresponding word line in the word line, and the first semiconductor pattern extending upward in the third direction. as well as A second semiconductor pattern is connected to a corresponding bit line, each of the second semiconductor patterns being located between a corresponding word line among the adjacent word lines in the first direction and a corresponding second back gate line among the second back gate lines, and the second semiconductor pattern extending upward in the third direction. Wherein, the first direction, the second direction, and the third direction intersect each other, and Wherein, one of the first direction, the second direction, and the third direction is perpendicular to the upper surface of the substrate.

20. The semiconductor memory device of claim 19, wherein, The first semiconductor pattern and the second semiconductor pattern comprise epitaxial silicon.

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