Semiconductor memory device and manufacturing method thereof

Abstract

A semiconductor memory device includes: memory cells arranged three-dimensionally on a substrate, each memory cell including a first transistor comprising a first channel layer and a second transistor comprising a second channel layer located above and below the first channel layer; a bit line connected to one end of the first channel layer and extending in a vertical direction; a ground electrode connected to the other end of the first channel layer and extending in a vertical direction; a memory node located above and below the first channel layer while in contact with a first surface of the second channel layer, the second channel layer and the memory node surrounding the first channel layer between the bit line and the ground electrode; and a word line surrounding the memory node and the second channel layer between the bit line and the ground electrode.

Description

Cross-references to related applications

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2025-0018092, filed on February 12, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to semiconductor memory devices and methods for manufacturing the same. Specifically, this disclosure relates to semiconductor memory devices including a gate-all-around (GAA) structure and methods for manufacturing the same. Background Technology

[0003] Due to advancements in electronic technology, the miniaturization of semiconductor memory devices has progressed rapidly. Consequently, there is a need for further miniaturization of memory cells, and limitations may exist in maintaining high integration and reliability within existing memory cells. Therefore, research has been conducted to develop semiconductor memory devices with structures that facilitate both miniaturization and high integration of memory cells. Summary of the Invention

[0004] This disclosure provides a semiconductor memory device that can be easily and highly integrated.

[0005] This disclosure also provides a method for manufacturing a semiconductor memory device that can be easily and highly integrated.

[0006] The technical concept of this disclosure aims to solve problems that are not limited to those mentioned above, and those skilled in the art can clearly understand other problems from the following description.

[0007] According to one aspect of this disclosure, a semiconductor memory device is provided, comprising: a plurality of memory cells arranged three-dimensionally on a substrate in a first horizontal direction, a second horizontal direction, and a vertical direction, wherein the second horizontal direction is orthogonal to the first horizontal direction and the vertical direction is perpendicular to the first and second horizontal directions; each of the plurality of memory cells includes a first transistor comprising a first channel layer and a second transistor comprising a second channel layer located above and below the first channel layer; a bit line connected to one end of the first channel layer and extending in a vertical direction; a ground electrode connected to the other end of the first channel layer and extending in a vertical direction; a memory node located above and below the first channel layer while contacting a first surface of the second channel layer, wherein the second channel layer and the memory node surround the first channel layer between the bit line and the ground electrode; and a word line surrounding the memory node and the second channel layer between the bit line and the ground electrode.

[0008] According to another aspect of this disclosure, a semiconductor memory device is provided, comprising: a first channel layer extending on a substrate in a second horizontal direction and spaced apart in a first horizontal direction perpendicular to the second horizontal direction, the first channel layer having a first surface and a second surface opposite to the first surface in the second horizontal direction; a second channel layer located above and below the first channel layer, the second channel layer having a first surface and a second surface opposite to the first surface in the second horizontal direction; a memory node disposed above and below the first channel layer while contacting the first surface of the second channel layer and formed inwardly relative to the first surface of the first channel layer in the second horizontal direction; a bit line contacting one end of each of the first channel layer and the second channel layer in a vertical direction, the vertical direction being perpendicular to the first and second horizontal directions; a ground electrode contacting the other end of the first channel layer in a vertical direction; and a word line located between the bit line and the ground electrode above the second channel layer and the memory node, wherein the second channel layer and the memory node surround the first channel layer, and the word line surrounds the second channel layer and the memory node.

[0009] According to another aspect of this disclosure, a semiconductor memory device is provided, comprising: a first channel layer extending on a substrate in a second horizontal direction and spaced apart in a first horizontal direction perpendicular to the second horizontal direction, the first channel layer having a first surface and a second surface opposite to the first surface in the second horizontal direction; a second channel layer located above and below the first channel layer, the second channel layer having a first surface and a second surface opposite to the first surface in the second horizontal direction; and a memory node disposed above and below the first channel layer while contacting the first surface of the second channel layer and opposite to the first surface of the first channel layer in the second horizontal direction. Formed inwards; a bit line that vertically contacts one end of each of the first and second channel layers, the vertical direction being perpendicular to the first and second horizontal directions; a ground electrode that vertically contacts the other end of the first channel layer; a word line located above the second channel layer between the bit line and the ground electrode, the second channel layer and the memory node surrounding the first channel layer, and the word line surrounding the second channel layer and not overlapping the memory node in the vertical direction; a first gate insulating layer located between the first channel layer and the memory node and between the first channel layer and the second channel layer; and a second gate insulating layer located between the second channel layer and the word line and between the memory node and the word line.

[0010] According to another aspect of this disclosure, a method for manufacturing a semiconductor memory device is provided, the method comprising: forming a first channel layer extending in a second horizontal direction on a substrate and spaced apart in a first horizontal direction perpendicular to the second horizontal direction, the first channel layer having a first surface and a second surface opposite to the first surface in the second horizontal direction; forming a first gate insulating layer surrounding the first channel layer; forming a second channel layer on the first gate insulating layer located above and below the first channel layer, the second channel layer having a first surface and a second surface opposite to the first surface in the second horizontal direction; forming a memory node contacting the first surface of the second channel layer and spaced apart above and below the first channel layer in the second horizontal direction. A second gate insulating layer is formed inwardly relative to a first surface of a first channel layer in a horizontal direction; a second gate insulating layer is formed around a second channel layer and a memory node; word lines extending in a first horizontal direction are formed on the second gate insulating layer located above and below the second channel layer and the memory node; bit lines are formed, which contact one end of each of the first channel layer and the second channel layer in a vertical direction, the vertical direction being perpendicular to the first and second horizontal directions; and a ground electrode is formed, which contacts the other end of the first channel layer in a vertical direction, wherein, in the first horizontal direction, the second channel layer and the memory node are formed such that the second channel layer and the memory node surround the first channel layer, and word lines are formed such that the word lines surround the second channel layer.

[0011] In some embodiments, the first channel layer comprises crystalline silicon. The second channel layer may comprise at least one of oxide semiconductors, polycrystalline silicon, 2D material semiconductors, and combinations thereof.

[0012] In some implementations, word lines may be formed to surround both the second channel layer and the memory node. A second surface of the second channel layer may be formed opposite to the first surface so that the second surface of the second channel layer contacts the bit lines.

[0013] In some embodiments, a first gate insulating layer may be formed between the first channel layer and the memory node, and between the first channel layer and the second channel layer. A second gate insulating layer may be formed between the second channel layer and the word line, and between the memory node and the word line.

[0014] In some embodiments, a work function adjustment layer in contact with the word line may also be formed on a second channel layer on one side of the word line. A bit line-side channel doped region in contact with the bit line may also be formed at one end of the first channel layer. A ground-side channel doped region in contact with the ground electrode may also be formed at the other end of the first channel layer. A silicide layer in contact with the bit line or ground electrode may also be formed at one or the other end of the first channel layer. Attached Figure Description

[0015] The embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is an equivalent circuit diagram showing a cell array of a semiconductor memory device according to some embodiments; Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G and Figure 2H This is a diagram illustrating a semiconductor memory device according to some embodiments; Figure 3 This is a layout diagram illustrating a semiconductor memory device according to some embodiments; Figure 4A and Figure 4B This is a cross-sectional view showing a semiconductor memory device according to an embodiment; Figure 5A , Figure 5B and Figure 5C This is a cross-sectional view showing a semiconductor memory device according to an embodiment; Figure 6A , Figure 6B and Figure 6C This is a cross-sectional view showing a semiconductor memory device according to an embodiment; Figure 7A and Figure 7B This is a cross-sectional view showing a semiconductor memory device according to an embodiment; and Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 12E , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 13E, Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 14E , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 15E , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 16E , Figure 16F , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 17E , Figure 17F , Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 18E , Figure 18F , Figure 19A , Figure 19B , Figure 19C , Figure 19D , Figure 19E and Figure 19F This is a diagram illustrating a method for manufacturing a semiconductor memory device according to some embodiments. Detailed Implementation

[0016] In the following description, embodiments of the present disclosure are illustrated with reference to the accompanying drawings. Embodiments of the present disclosure may be implemented by a single embodiment, or by a combination of more than one embodiment. Therefore, the technical concept of the present disclosure should not be interpreted solely by one of the embodiments.

[0017] In this document, unless the context clearly indicates otherwise, singular forms of parts may include plural forms. The accompanying drawings are exaggerated to describe this disclosure more clearly.

[0018] In this document, the terms “first,” “second,” etc., are used to describe various elements or components; however, it should be understood that these elements or components are not limited by these terms. These terms are used only to distinguish one element or component from another. Therefore, the first element or first component mentioned below may also be a second element or second component within the technical concept of this disclosure.

[0019] Figure 1 This is an equivalent circuit diagram showing the cell array of a semiconductor memory device EX according to some embodiments.

[0020] In the example, the semiconductor memory device EX may include multiple unit cells UC. Each unit cell UC may include a pair of transistors, for example, a first transistor TR1 and a second transistor TR2. In some embodiments, each of the first transistor TR1 and the second transistor TR2 may include a field-effect transistor (FET). In the example, the first transistor may be a PMOS transistor, and the second transistor may be an NMOS transistor.

[0021] Each unit cell UC included in the semiconductor memory device EX can operate as a DRAM memory cell performing write operations for storing information and read operations for reading information. The unit cell UC can store information in the memory node SN instead of in a capacitor. The semiconductor memory device EX including multiple unit cells UC can be referred to as a DRAM memory device with a floating gate. The semiconductor memory device EX including multiple unit cells UC can operate as a non-volatile semiconductor memory device.

[0022] The word line WL can be electrically connected to the gate electrode of each of the first transistor TR1 and the second transistor TR2 included in the multiple unit cells UC. One end of the channel layer of the first transistor TR1 can be electrically coupled to the bit line BL, and the other end of the channel layer can be electrically coupled to the ground electrode GL. The ground electrode GL can be biased as needed.

[0023] One end of the channel layer of the second transistor TR2 can be electrically coupled to the storage node SN, and the other end of the channel layer can be electrically coupled to the bit line BL. The second transistor TR2 can store charge in the storage node SN.

[0024] The threshold voltage of the first transistor TR1, which serves as the floating gate, can be changed based on the amount of charge stored in the storage node SN. The storage node SN can be the floating gate of the first transistor TR1. Based on the threshold voltage of the first transistor TR1, determined by the amount of charge stored in the storage node SN, the information stored in the unit cell UC can be read as "0" or "1".

[0025] For example, the second transistor TR2 of a unit cell UC can be selected by a word line WL and a bit line BL, and the charge can be stored in the channel layer below the storage node SN. Furthermore, the first transistor TR1 of a unit cell UC can be selected by a word line WL and a bit line BL.

[0026] Information stored in a unit cell UC can be read based on the threshold voltage of the first transistor TR1, determined by the amount of charge stored in the channel layer beneath the memory node SN. The first transistor TR1 can be referred to as the read transistor, and the second transistor TR2 can be referred to as the write transistor. The unit cell UC can be named a 2T memory cell.

[0027] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G and Figure 2H This is a diagram illustrating a semiconductor memory device EX1 according to some embodiments.

[0028] Specifically, Figure 2A This is a layout diagram of the semiconductor memory device EX1. Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F and Figure 2G They are along Figure 2A The cross-sectional views taken from lines B–B', C–C', D–D', E–E', F–F', and G–G'. Figure 2H yes Figure 2B A magnified cross-sectional view of a portion of the image.

[0029] Reference Figure 2A The semiconductor memory device EX1 may include a molded pattern MPA, a molded cover layer 108, a bit line 154, and a ground electrode 156 in this layout. The bit line 154 may correspond to... Figure 1 The bit line BL, and the ground electrode 156 can correspond to Figure 1 The ground electrode GL. A bias voltage can be applied to the ground electrode 156 as needed.

[0030] The molded pattern MPA can be spaced apart in a first horizontal direction (X direction) and a second horizontal direction (Y direction). The molded pattern MPA can be configured as a second molding layer 116. A molding cover layer 108 can be placed between the molded pattern MPA. In the manufacturing process, a first capping insulating layer 138 can be placed on the molding cover layer 108 and the molded pattern MPA.

[0031] In this configuration, bit lines 154 are arranged in a second trench T2 within the molded cover layer 108. Bit lines 154 extend in a second horizontal direction (Y direction) and are spaced apart from each other in a first horizontal direction (X direction). Ground electrodes 156 can be arranged to extend in the first horizontal direction (X direction) outside the molded cover layer 108.

[0032] In the manufacturing process, the first gate insulating layer 126, the first capping insulating layer 138, and the second gate insulating layer 140 can be disposed on one sidewall of the second trench T2. The second trench T2 can be filled with a fifth embedded insulating layer 152.

[0033] Reference Figure 2B and Figure 2H The semiconductor memory device EX1 may include, for example, Figure 2B The unit cell UC shown is shown. Figure 2B The unit UC can include Figure 1 The unit UC. Figure 2H It can be Figure 2B Enlarged cross-sectional view of the unit cell UC.

[0034] The unit cell UC can be insulated in the vertical direction (Z direction) by a fifth embedded insulating layer 152 according to the manufacturing process. The fifth embedded insulating layer 152 can be formed inside the third groove T3 according to the manufacturing process. The third groove T3 can be a recessed groove extending inward from one side of the molded cover layer 108.

[0035] The unit cell UC of the semiconductor memory device EX1 can be a memory cell. Multiple memory cells can be configured, and the multiple memory cells can be arranged three-dimensionally on the substrate 100 in a first horizontal direction (X direction), a second horizontal direction (Y direction), and a vertical direction (Z direction). The second horizontal direction (Y direction) is orthogonal to the first horizontal direction (X direction), and the vertical direction (Z direction) is perpendicular to the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0036] The memory cell may include a first channel layer 104, a memory node 134, a second channel layer 136, a first gate insulating layer 126, a second gate insulating layer 140, a bit line 154, a ground electrode 156, and a word line 148. The first channel layer 104 may extend on the substrate 100 in a second horizontal direction (Y direction) and be spaced apart in a first horizontal direction perpendicular to the second horizontal direction (Y direction). The first channel layer 104 may have a first surface 104S1 in the second horizontal direction (Y direction) and a second surface 104S2 opposite to the first surface 104S1.

[0037] The second channel layer 136 may be located above the first channel layer 104. The second channel layer 136 may have a first surface 136S1 in the second horizontal direction (Y direction) and a second surface 136S2 opposite to the first surface 136S1.

[0038] Storage node 134 can be positioned above and below first channel layer 104 while simultaneously contacting the first surface 136S1 of second channel layer 136. Storage node 134 can be formed inwardly relative to the first surface 104S1 of first channel layer 104 in the second horizontal direction (Y direction). First channel layer 104 can protrude relative to one side of storage node 134 in the second horizontal direction (Y direction).

[0039] Bit line 154 can extend in a vertical direction (Z direction) perpendicular to the first horizontal direction (X direction) and the second horizontal direction (Y direction). In the manufacturing process, bit line 154 can be placed inside the second trench T2. In the manufacturing process, the first gate insulating layer 126 and the first capping insulating layer 138 can be retained on the molded cover layer 108. The fifth buried insulating layer 152 can be retained below the second trench T2.

[0040] Bit line 154 may contact one end of the first channel layer 104 and the second channel layer 136 in the vertical direction (Z direction). Bit line 154 may contact the second surface 104S2 of the first channel layer 104 and the second surface 136S2 of the second channel layer 136 in the vertical direction (Z direction).

[0041] Ground electrode 156 may extend in the vertical direction (Z direction). Ground electrode 156 may contact the other end of the first channel layer 104 in the vertical direction (Z direction). Ground electrode 156 may contact the first surface 104S1 of the first channel layer 104 in the vertical direction (Z direction). In the manufacturing process, a second buried insulating layer 122 and a third liner layer 120 may be retained below ground electrode 156. A bias voltage may be applied to ground electrode 156 as needed.

[0042] Word line 148 may be located above and below the second channel layer 136 and memory node 134 between bit line 154 and ground electrode 156. Word line 148 may extend in a first horizontal direction (X direction) to surround at least a portion of each of the second channel layer 136 and memory node 134. As shown in the following... Figure 2D As shown, word lines 148 can also be placed between adjacent unit cells and above and below the second channel layer 136 and storage node 134.

[0043] The first gate insulating layer 126 may be located between the first channel layer 104 and the memory node 134, and between the first channel layer 104 and the second channel layer 136. The second gate insulating layer 140 may be located between the second channel layer 136 and the word line 148, and between the memory node 134 and the word line 148.

[0044] The first channel layer 104, the first gate insulating layer 126, the second gate insulating layer 140, and the word line 148 can constitute Figure 1 The first transistor TR1. The second channel layer 136, the first gate insulating layer 126, the second gate insulating layer 140, and the word line 148 can constitute Figure 1 The second transistor TR2.

[0045] Between the bit line 154 and the word line 148, a second cover insulating pattern 150 may be arranged in the second horizontal direction (Y direction) according to the manufacturing process. Between the ground electrode 156 and the word line 148, a fourth lining pattern 132 and a fifth lining pattern 146 may be formed in the second horizontal direction (Y direction) according to the manufacturing process.

[0046] Reference Figure 2C The semiconductor memory device EX1 may include a second trench T2 and a fourth trench T4 recessed inward from one surface of the molded cover layer 108 according to a manufacturing process. A first gate insulating layer 126 and a first capping insulating layer 138 may be disposed on the molded cover layer 108 according to a manufacturing process.

[0047] The semiconductor memory device EX1 may include a second buried insulating layer 122, a second gate insulating layer 140, a first gate insulating layer 126, a fifth liner pattern 146, a word line 148, a second capping insulating pattern 150, and a fifth buried insulating layer 152.

[0048] Word lines 148 can be positioned vertically spaced apart within the fourth trench T4. A fifth liner pattern 146, a second gate insulating layer 140, a fourth liner pattern 132, and a first gate insulating layer 126 can be located on one sidewall of the word line 148. A second capping insulating pattern 150 can be located on the other sidewall of the word line 148. In the manufacturing process, memory nodes 134 and the second channel layer 136 can be formed above and below the second trench T2 and the fourth trench T4, respectively.

[0049] Reference Figure 2D The semiconductor memory device EX1 may include a third trench T3 and a fourth trench T4. In the manufacturing process, a first gate insulating layer 126 and a first capping insulating layer 138 are formed on a molded capping layer 108.

[0050] Word lines 148 are formed within the third trench T3 and the fourth trench T4. Word lines 148 extend in a first horizontal direction (X direction) and connect to each other in a vertical direction (Z direction). Word lines 148 can be arranged around the first trench layer (…). Figure 2B The shape of 104 in the middle is formed.

[0051] The second sealing insulation pattern 150 is arranged between the letter lines 148 in the first horizontal direction (X direction). The fifth embedded insulation layer 152 is formed between the letter lines 148 in the vertical direction (Z direction).

[0052] In the manufacturing process, an uneven structure can be formed on the substrate 100. The first gate insulating layer 126, the second channel layer 136, and the second gate insulating layer 140 can be formed on the substrate 100 having the uneven structure.

[0053] Reference Figure 2E The semiconductor memory device EX1 may include a third trench T3 and a fourth trench T4. In the manufacturing process, a first gate insulating layer 126 and a first capping insulating layer 138 are formed on a molded capping layer 108.

[0054] The first trench layer 104 can be located within the third trench T3 and the fourth trench T4. The ground electrode 156 can be positioned to contact the first trench layer 104.

[0055] Reference Figure 2F The first gate insulating layer 126 can be formed to surround the first channel layer 104 in the vertical direction (Z direction). The second channel layer 136 can be formed to surround the first gate insulating layer 126. The second gate insulating layer 140 can be formed to surround the second channel layer 136. The word line 148 can be formed to surround the second gate insulating layer 140. The fifth buried insulating layer 152 can be formed above and below the word line 148.

[0056] Reference Figure 2G The first gate insulating layer 126 can be formed to surround the first channel layer 104 in the vertical direction (Z direction). The memory node 134 can be formed to surround the first gate insulating layer 126. The second gate insulating layer 140 can be formed to surround the memory node 134. The word line 148 can be formed to surround the second gate insulating layer 140. The fifth buried insulating layer 152 can be formed above and below the word line 148.

[0057] In the semiconductor memory device EX1 of this disclosure, configured as described above, the second channel layer 136 and the memory node 134 are formed around the first channel layer 104 in a first horizontal direction (X direction), and the word line 148 is configured around the second channel layer 136. The semiconductor memory device EX1 configured in this way is advantageous for high integration and can also improve electrical characteristics.

[0058] Figure 3 This is a layout diagram showing a semiconductor memory device EX2 according to some embodiments.

[0059] In detail, except that the ground electrode 156-1 is separated, the semiconductor memory device EX2 can be connected with... Figure 2A The semiconductor memory device EX1 is the same. Figure 3 In, with Figure 2A In the accompanying drawings, the same reference numerals denote the same components. Figure 3 In the text, references to the above are briefly given or omitted. Figure 2A The given description is the same as the given description.

[0060] The semiconductor memory device EX2 may include a molded pattern MPA, a molded cover layer 108, a bit line 154, and a ground electrode 156-1. The molded pattern MPA may be spaced apart from each other in a first horizontal direction (X direction) and a second horizontal direction (Y direction).

[0061] The molded pattern MPA can be configured as a second molding layer 116. A molding cover layer 108 can be placed between the molded pattern MPA. In the manufacturing process, a first capping insulation layer 138 can be placed on the molding cover layer 108 and the molded pattern MPA.

[0062] In the layout, bit lines 154 are arranged within the second groove T2 inside the molded cover layer 108. Bit lines 154 extend in the second horizontal direction (Y direction) and are spaced apart from each other in the first horizontal direction (X direction).

[0063] The ground electrode 156-1 can be separated and placed outside the molded cover layer 108 in the second horizontal direction (Y direction). The ground electrode 156-1 can be arranged separately from the bit line 154.

[0064] Figure 4A and Figure 4B This is a cross-sectional view showing semiconductor memory devices EX3a and EX3b according to embodiments.

[0065] In detail, in addition to the semiconductor memory device EX3a also including a work function adjustment layer 158 on one side of the word line 148-1, Figure 4A The semiconductor memory device EX3a can be used with Figure 2H The semiconductor memory device EX1 is the same, except that word line 148-2 does not overlap with memory node 134 in the vertical direction (Z direction). Figure 4B The semiconductor memory device EX3b can be used with Figure 2H It is the same as the semiconductor memory device EX1.

[0066] exist Figure 4A and Figure 4B In, with Figure 2H In the accompanying drawings, the same reference numerals denote the same components. Figure 4A and Figure 4B In the text, references to the above are briefly given or omitted. Figure 2H The given description is the same as the given description.

[0067] The semiconductor memory device EX3a may include a first channel layer 104, a memory node 134, a second channel layer 136, a first gate insulating layer 126, a second gate insulating layer 140, a bit line 154, a ground electrode 156, and a word line 148-1.

[0068] Furthermore, the semiconductor memory device EX3a may include a work function adjustment layer 158 on one side of the word line 148-1. The word line 148-1 may be configured as a main metal layer. The work function adjustment layer 158 may be formed as a metal layer. The work function adjustment layer 158 may include doped polysilicon, lanthanum oxide, titanium nitride, etc.

[0069] Therefore, the semiconductor memory device EX3a can easily control the voltage applied to the first channel layer 104 by using word line 148-1 and work function adjustment layer 158.

[0070] The semiconductor memory device EX3b may include a first channel layer 104, a memory node 134, a second channel layer 136, a first gate insulating layer 126, a second gate insulating layer 140, a bit line 154, a ground electrode 156, and a word line 148-2. The word line 148-2 may not overlap with the memory node 134 in the vertical direction (Z direction). Therefore, the semiconductor memory device EX3b can easily adjust the voltage applied to the first channel layer 104 using the word line 148-2.

[0071] Figures 5A to 5C This is a cross-sectional view showing semiconductor memory devices EX4a, EX4b and EX4c according to embodiments.

[0072] In detail, in addition to the semiconductor memory devices EX4a, EX4b, and EX4c also including ground-side channel doped regions 160, 160-1, and 160-2, respectively, Figure 5A , Figure 5B and Figure 5C The semiconductor memory devices EX4a, EX4b and EX4c can be used with Figure 2H and Figure 4B The semiconductor memory devices EX1 and EX3b are the same.

[0073] exist Figure 5A , Figure 5B and Figure 5C In, with Figure 2H and Figure 4B In the accompanying drawings, the same reference numerals denote the same components. Figure 5A , Figure 5B and Figure 5C In the text, references to the above are briefly given or omitted. Figure 2H and Figure 4B The given description is the same as the given description.

[0074] Semiconductor memory devices EX4a, EX4b and EX4c may each include a first channel layer 104, a memory node 134, a second channel layer 136, a first gate insulating layer 126, a second gate insulating layer 140, a bit line 154, a ground electrode 156 and a word line 148-2.

[0075] Furthermore, the semiconductor memory devices EX4a, EX4b, and EX4c may also include ground-side channel doped regions 160, 160-1, and 160-1 on one side of the first channel layer 104, respectively. The ground-side channel doped regions 160, 160-1, and 160-1 may correspond to the depth of the doped impurity regions in the first channel layer 104 in the direction of the ground electrode 156. The ground-side channel doped regions 160, 160-1, and 160-1 may be source and drain regions in contact with the ground electrode 156.

[0076] The ground-side channel doped region 160 of semiconductor memory device EX4a can be aligned with one end of memory node 134 in the vertical direction (Z direction). The ground-side channel doped region 160-1 of semiconductor memory device EX4b can not overlap with memory node 134 in the vertical direction (Z direction).

[0077] The ground-side channel doped region 160-2 of the semiconductor memory device EX4c can overlap with the memory node 134 in the vertical direction (Z direction). In this way, the semiconductor memory devices EX4a, EX4b and EX4c can have various configurations of the ground-side channel doped regions 160, 160-1 and 160-2.

[0078] Figure 6A , Figure 6B and Figure 6C This is a cross-sectional view showing semiconductor memory devices EX5a, EX5b and EX5c according to embodiments.

[0079] In detail, in addition to the semiconductor memory devices EX5a, EX5b, and EX5c also including bit-line side channel doped regions 162, 162-1, and 162-2, Figure 6A , Figure 6B and Figure 6C The semiconductor memory devices EX5a, EX5b and EX5c can be used with Figure 2H and Figure 4B The semiconductor memory devices EX1 and EX3b are the same.

[0080] exist Figure 6A , Figure 6B and Figure 6C In, with Figure 2H and Figure 4B In the accompanying drawings, the same reference numerals denote the same components. Figure 6A , Figure 6B and Figure 6C In the text, references to the above are briefly given or omitted. Figure 2H and Figure 4B The given description is the same as the given description.

[0081] Semiconductor memory devices EX5a, EX5b and EX5c may include a first channel layer 104, a memory node 134, a second channel layer 136, a first gate insulating layer 126, a second gate insulating layer 140, a bit line 154, a ground electrode 156 and a word line 148-2.

[0082] Furthermore, semiconductor memory devices EX5a, EX5b, and EX5c may also include bit-line-side channel doped regions 162, 162-1, and 162-2 on one side of the first channel layer 104, respectively. The bit-line-side channel doped regions 162, 162-1, and 162-2 may correspond to the depth of the doped impurity region in the first channel layer 104 in the direction of the bit line 154. The bit-line-side channel doped regions 162, 162-1, and 162-2 may be the source and drain regions contacting the bit line 154.

[0083] The bit-line side channel doped region 162 of semiconductor memory device EX5a can be aligned with one end of word line 148-2 in the vertical direction (Z direction). The bit-line side channel doped region 162-1 of semiconductor memory device EX5b can overlap with word line 148-2 in the vertical direction (Z direction).

[0084] The bit-line side channel doped region 162-2 of the semiconductor memory device EX5c may not overlap with the word line 148-2 in the vertical direction (Z direction). In this way, the semiconductor memory devices EX5a, EX5b and EX5c may have various configurations of the bit-line side channel doped regions 162, 162-1 and 162-2.

[0085] Figure 7A and Figure 7B This is a cross-sectional view showing semiconductor memory devices EX6a and EX6b according to embodiments.

[0086] In detail, in addition to semiconductor memory devices EX6a and EX6b also including silicide layers 164 and 164-1 respectively, Figure 7A and Figure 7B The semiconductor memory devices EX6a and EX6b can be used with Figure 2H and Figure 4BThe semiconductor memory devices EX1 and EX3b are the same.

[0087] exist Figure 7A and Figure 7B In, with Figure 2H and Figure 4B In the accompanying drawings, the same or similar reference numerals denote the same or similar components. Figure 7A and Figure 7B In the text, briefly describe or omit the related terms. Figure 2H and Figure 4B The same content as in [the previous text].

[0088] Semiconductor memory devices EX6a and EX6b may include a first channel layer 104, a memory node 134, a second channel layer 136, a first gate insulating layer 126, a second gate insulating layer 140, a bit line 154, a ground electrode 156, and a word line 148-2.

[0089] Furthermore, the semiconductor memory devices EX6a and EX6b may also include silicide layers 164 and 164-1 on one side and the other side of the first channel layer 104. The silicide layers 164 and 164-1 may be formed to reduce the contact resistance with the bit line 154 and the ground electrode 156.

[0090] The silicide layer 164 of the semiconductor memory device EX6a can be formed on both the side of the first channel layer 104 that is in contact with the bit line 154 and the ground electrode 156 and the other side.

[0091] In some embodiments, the silicide layer 164 of the semiconductor memory device EX6a may be formed on the first channel layer 104 to contact only one of the bit line 154 and the ground electrode 156. The silicide layer 164 may be formed in a square shape on one side and the other side of the first channel layer 104.

[0092] The silicide layer 164-1 of the semiconductor memory device EX6b can be formed on both one side and the other side of the first channel layer 104 to contact the bit line 154 and the ground electrode 156.

[0093] In some embodiments, the silicide layer 164-1 of the semiconductor memory device EX6b may be formed on the first channel layer 104 to contact only one of the bit line 154 and the ground electrode 156. The silicide layer 164-1 may be formed in a C-shape on one side and the other side of the first channel layer 104. In this way, the semiconductor memory devices EX6a and EX6b may have various configurations of the silicide layers 164 and 164-1.

[0094] The following describes the manufacturing process. Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G and Figure 2H Method for developing a semiconductor memory device EX1.

[0095] Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 12E , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 13E , Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 14E , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 15E , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 16E , Figure 16F , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 17E , Figure 17F , Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 18E , Figure 18F , Figure 19A , Figure 19B , Figure 19C , Figure 19D , Figure 19E and Figure 19F This is a diagram illustrating a method for manufacturing a semiconductor memory device according to some embodiments.

[0096] In detail, Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 12E , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 13E , Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 14E , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 15E , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 16E , Figure 16F , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 17E , Figure 17F , Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 18E , Figure 18F , Figure 19A , Figure 19B , Figure 19C , Figure 19D , Figure 19E and Figure 19F It shows the manufacturing process. Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F and Figure 2G A diagram illustrating a method for using the semiconductor memory device EX1. Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 12E , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 13E , Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 14E , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 15E , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 16E , Figure 16F , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 17E , Figure 17F , Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 18E , Figure 18F , Figure 19A , Figure 19B , Figure 19C , Figure 19D , Figure 19E and Figure 19F In the text, references to the above are briefly given or omitted. Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F and Figure 2G The given description is the same as the given description.

[0097] Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A ,and Figure 19A This is a layout diagram of intermediate operations in the manufacturing process of semiconductor memory devices. Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B and Figure 19B They are along Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A and Figure 19A The cross-sectional view taken by line B–B'. Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C and Figure 19C They are along Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18Aand Figure 19A A cross-sectional view taken from line C–C'.

[0098] Figure 9D , Figure 10D , Figure 11D , Figure 12D , Figure 13D , Figure 14D , Figure 15D , Figure 16D , Figure 17D , Figure 18D and Figure 19D They are along Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A and Figure 19A The cross-sectional view taken by line D–D'. Figure 9E , Figure 10E , Figure 11E , Figure 12E , Figure 13E , Figure 14E , Figure 15E , Figure 16E , Figure 17E , Figure 18E and Figure 19E They are along Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A and Figure 19A The cross-sectional view taken by line E–E'. Figure 16F , Figure 17F , Figure 18F and Figure 19F They are Figure 16B , Figure 17B , Figure 18B and Figure 19B An enlarged cross-sectional view of the part.

[0099] Figure 8A , Figure 8B , Figure 8C , Figure 8D and Figure 8EThis includes forming a memory stack layer MST on a substrate 100, the memory stack layer MST including a first channel layer 104, a molded pattern MPA, and a molded cover material layer 108r.

[0100] Specifically, a memory stack layer (MST) including a sacrificial semiconductor layer 102 and a first channel layer 104 is formed on the substrate 100. In some embodiments, the first channel layer 104 may comprise crystalline silicon. In some embodiments, the sacrificial semiconductor layer 102 may comprise silicon-germanium material.

[0101] A first trench T1 is formed within the memory stack layer MST, and a first molding layer 106 for forming a molding pattern MPA is formed within the first trench T1. A molding cover material layer 108r is formed on the first molding layer 106 and the memory stack layer MST. In some embodiments, the first molding layer 106 may include silicon oxide. In some embodiments, the molding cover material layer 108r may include silicon nitride.

[0102] Reference Figure 8A In the layout, a molded pattern MPA is formed inside the molded cover material layer 108r. The molded pattern MPA is spaced apart in a first horizontal direction (X direction) and a second horizontal direction (Y direction).

[0103] Reference Figure 8B A memory stack layer MST and a molding cover material layer 108r are formed on a substrate 100. The memory stack layer MST includes a sacrificial semiconductor layer 102 and a first channel layer 104 sequentially formed on the substrate 100. A first molding layer 106 constituting a molding pattern MPA and a molding cover material layer 108r are formed on the uppermost sacrificial semiconductor layer 102 constituting the memory stack layer MST.

[0104] Reference Figure 8C A first trench T1 is formed in a memory stack layer MST, which includes a sacrificial semiconductor layer 102 and a first channel layer 104. A first molding layer 106 for forming a molding pattern MPA is formed in the first trench T1. A molding cover material layer 108r is formed on the first molding layer 106 and the memory stack layer MST.

[0105] Reference Figure 8D and Figure 8E A first trench T1 is formed on substrate 100 in a memory stack layer MST including a sacrificial semiconductor layer 102 and a first channel layer 104. Figure 8D and Figure 8E The width of the first groove T1 shown is less than Figure 8CThe width of the first trench T1 is shown. A first molding layer 106 for forming the molding pattern MPA is formed within the first trench T1. A molding cover material layer 108r is formed on the first molding layer 106 and the memory stack layer MST.

[0106] Figure 9A , Figure 9B , Figure 9C , Figure 9D and Figure 9E The formation of the second trench T2, the third trench T3, and the molded cover layer 108 are shown.

[0107] In detail, by making the molding cover material layer ( Figure 8B The 108r layer is patterned to form a molded cover layer 108. The memory stack layer MST, including the sacrificial semiconductor layer 102 and the first channel layer 104, is patterned to form a second trench T2. The sacrificial semiconductor layer 102 is etched in the second horizontal direction (Y direction) to form a third trench T3.

[0108] Reference Figure 9A This allows the molded cover material layer in the layout to be covered. Figure 8A The 108r) is patterned to form a second groove T2. The second groove T2 extends in a first horizontal direction (X direction). The second groove T2 can be formed between the molded patterns MPA in the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0109] Reference Figure 9B On the memory stack layer MST, a molded overlay material layer is formed. Figure 8B The 108r) is patterned to form a molded cover layer 108. A first molded layer 106 may be formed below the molded cover layer 108. The memory stack layer MST, including the sacrificial semiconductor layer 102 and the first channel layer 104, is patterned to form a second trench T2.

[0110] Subsequently, the sacrificial semiconductor layer 102 is etched in the second horizontal direction (Y direction) to form the third trench T3. The third trench T3 can be formed between the lower part of the molded cover layer 108 and the first channel layer 104 constituting the memory stack layer MST.

[0111] The third trench T3 may communicate with the second trench T2. The third trench T3 may be a recessed trench in the second horizontal direction (Y direction or -Y direction) from one sidewall of the molded cover layer 108. When the second trench T2 and the third trench T3 are formed, a portion of the first channel layer 104 may be exposed. In some embodiments, the thickness of the first channel layer 104 exposed to the second trench T2 and the third trench T3 may be further etched to reduce the thickness.

[0112] Reference Figure 9C On the memory stack layer MST, a molded overlay material layer is formed. Figure 8B The 108r layer is patterned to form a molded cover layer 108. The memory stack layer MST, including the sacrificial semiconductor layer 102 and the first channel layer 104, is patterned to form a second trench T2. The second trench T2 may contact the first molded layer 106 forming the molded pattern MPA.

[0113] Reference Figure 9D The sacrificial semiconductor layer forming the memory stack layer MST on the etched substrate 100 ( Figure 8D (102) to form a third trench T3. The third trench T3 can be formed below the molded cover layer 108. The third trench T3 can be formed between the first molded layer 106 constituting the molded pattern MPA and the first channel layer 104 constituting the memory stack layer MST.

[0114] Reference Figure 9E On the memory stack layer MST, a molded overlay material layer is formed. Figure 8E The 108r is patterned to form a molded cover layer 108. The molded cover layer 108 is formed on the first molded layer 106 and the memory stack layer MST. The first molded layer 106 may be formed in the first trench T1 in the memory stack layer MST below the molded cover layer 108.

[0115] Figure 10A , Figure 10B , Figure 10C , Figure 10D and Figure 10E The formation of a first lining layer 110, a second lining layer 112, and a first embedded insulation layer 114 is shown.

[0116] In detail, the first molding layer is etched ( Figure 9C and Figure 9D (106) to form the fourth trench T4 and the second molding layer 116. A first liner layer 110 and a second liner layer 112 are sequentially formed on the inner walls of the second trench T2, the third trench T3, and the fourth trench T4, and on the surface of the first trench layer 104. In some embodiments, the first liner layer 110 and the second liner layer 112 may comprise silicon nitride and silicon oxide, respectively.

[0117] A first embedded insulating layer 114 is formed such that the first embedded insulating layer 114 fills the second trench T2, the third trench T3, and the fourth trench T4 on the second liner layer 112. In some embodiments, the first embedded insulating layer 114 may include silicon oxide.

[0118] Reference Figure 10A Etching the first molding layer ( Figure 9A(106) to form a second molding layer 116. The second molding layer 116 can form a molding pattern MPA. In the layout, a first liner layer 110 and a second liner layer 112 are formed inside the second groove T2.

[0119] A first embedded insulating layer 114 is formed within the second trench T2. The second molded layer 116 may include a first lining layer 110, a second lining layer 112, and a first embedded insulating layer 114. The first lining layer 110, the second lining layer 112, and the first embedded insulating layer 114 extend in a first horizontal direction (X direction).

[0120] Reference Figure 10B A first liner layer 110 and a second liner layer 112 are sequentially formed on the inner walls of the second trench T2 and the third trench T3, a sidewall of the sacrificial semiconductor layer 102, the surface of the first channel layer 104 exposed in the second trench T2 and the third trench T3, and a sidewall of the molded cover layer 108.

[0121] A first embedded insulating layer 114 is formed such that the first embedded insulating layer 114 fills both the second trench T2 and the third trench T3 on the second lining layer 112. The first embedded insulating layer 114 is formed in the vertical direction (Z direction) between the first trench layers 104.

[0122] Reference Figure 10C Further etching of the first molding layer ( Figure 9C (106) to form the fourth groove T4. The fourth groove T4 can be formed below the molded cover layer 108. The first molded layer 106 can be retained on one sidewall of the fourth groove T4.

[0123] A first lining layer 110 and a second lining layer 112 are sequentially formed on the inner wall of the fourth trench T4, a sidewall of the first molding layer 106, and a sidewall of the molding cover layer 108. A first embedded insulation layer 114 is formed such that the first embedded insulation layer 114 fills both the second trench T2 and the fourth trench T4 on the second lining layer 112.

[0124] Reference Figure 10D Etching the first molding layer ( Figure 9D 106) to form a fourth trench T4. The fourth trench T4 can communicate with the third trench T3. Therefore, when forming the third trench T3 and the fourth trench T4, the first trench layer 104 can be formed to be spaced apart from each other in a first horizontal direction (X direction) and a vertical direction (Z direction) on the substrate 100. When etching the first molding layer ( Figure 9D When 106 is used, an uneven structure can be formed on the substrate 100.

[0125] A first liner layer 110 and a second liner layer 112 are sequentially formed to surround the first channel layer 104 in the third trench T3 and the fourth trench T4. A first embedded insulation layer 114 is formed to fill the interior of the third trench T3 and the fourth trench T4. The first embedded insulation layer 114 may be formed between the first channel layers 104.

[0126] Reference Figure 10E This structure can be combined with Figure 9E The structures are identical. A molded cover layer 108 is formed on the memory stack layer MST. The molded cover layer 108 is formed on the first molded layer 106 and the memory stack layer MST. The first molded layer 106 is formed in the first trench T1 in the memory stack layer MST below the molded cover layer 108.

[0127] Figure 11A , Figure 11B , Figure 11C , Figure 11D and Figure 11E The formation of trench 118 and etching of sacrificial semiconductor layer 102 that constitutes memory stack layer MST are shown.

[0128] Specifically, the memory stack layer MST located outside the third trench T3 and the fourth trench T4 is etched below the molded cover layer 108 to form the ground trench 118. Subsequently, the sacrificial semiconductor layer 102 outside the third trench T3 is recessed and etched below the molded cover layer 108 to form the first channel layer 104 so as to protrude relative to one sidewall of the third trench T3.

[0129] Reference Figure 11A In the layout, trenches 118 are formed outside the molded pattern MPA and the molded cover layer 108. The memory stack layer beneath the molded cover layer 108 can be etched. Figure 10B and Figure 10C MST is used to form trench 118.

[0130] Reference Figure 11B The memory stack layer outside the third trench T3 below the etched molded cover layer 108 ( Figure 10B The MST is used to form a trench 118. The trench 118 can expose the substrate 100.

[0131] Subsequently, the sacrificial semiconductor layer 102 outside the third trench T3 below the cover layer 108 is recessed and etched in the second horizontal direction (Y direction) to form the first channel layer 104, which protrudes relative to one sidewall of the third trench T3. In some embodiments, an impurity-doped region for forming a junction may also be formed in the first channel layer 104 protruding relative to one sidewall of the third trench T3.

[0132] Reference Figure 11C The memory stack layer outside the fourth trench T4 below the etched molded cover layer 108 ( Figure 10C The MST is used to form a trench 118. The trench 118 can expose the substrate 100.

[0133] In some embodiments, when forming the trench 118, one end of the molded cover layer 108 may also be etched such that a sidewall of the first molded layer 106 is flush with a sidewall of the molded cover layer 108 in the vertical direction (Z direction). In some embodiments, the first molded layer 106 below the molded cover layer 108 may be etched during or after forming the trench 118.

[0134] Reference Figure 11D ,and Figure 10D Similarly, a first liner layer 110 and a second liner layer 112 are formed to surround the first channel layer 104 in the third trench T3 and the fourth trench T4. A first embedded insulation layer 114 is formed to fill the interior of the third trench T3 and the fourth trench T4. The first embedded insulation layer 114 may be formed between the first channel layers 104.

[0135] Reference Figure 11E The sacrificial semiconductor layer 102 beneath the molded cover layer 108 is etched to form the third trench T3. Figure 11E The third groove T3 can be with Figure 9B and Figure 10B The third groove T3 shown is a connected groove. A molded cover layer 108 is formed on the first molding layer 106. The first channel layers 104 are spaced apart from each other in the first horizontal direction (X direction) and vertical direction (Z direction) through the first molding layer 106.

[0136] Figure 12A , Figure 12B , Figure 12C , Figure 12D and Figure 12E The diagram shows the formation of a third lining layer 120 and a second embedded insulation layer 122 within the trench 118.

[0137] Specifically, in the trenches formed in the substrate 100 ( Figure 11A , Figure 11B and Figure 11C A third lining layer 120 is formed on one sidewall of the trench (118), and a second embedded insulation layer 122 is formed on one side of the third lining layer 120 to fill the trench ( ). Figure 11A , Figure 11B and Figure 11C(118). In some embodiments, the third liner layer 120 may include silicon oxide. In some embodiments, the second buried insulating layer 122 may include silicon oxide.

[0138] Reference Figure 12A In the layout, there are trenches outside the molded pattern MPA and the molded cover layer 108. Figure 11A A third lining layer 120 and a second embedded insulating layer 122 are formed in (118). The third lining layer 120 and the second embedded insulating layer 122 may extend in a first horizontal direction (X direction).

[0139] Reference Figure 12B The trench outside the molded cover layer 108 and outside the third trench T3 ( Figure 11B A third liner layer 120 and a second buried insulating layer 122 are formed in (118). The second buried insulating layer 122 may be formed such that it covers the first channel layer 104 and the third liner layer 120 protruding outward from the second trench T2 and the third trench T3 on the substrate 100.

[0140] Reference Figure 12C The trench outside the fourth trench T4 below the molded cover layer 108 ( Figure 11C A third liner layer 120 and a second buried insulating layer 122 are formed in (118). The second buried insulating layer 122 may be formed such that the second buried insulating layer 122 covers the third liner layer 120 outside the second trench T2 and the fourth trench T4 on the substrate 100.

[0141] Reference Figure 12D ,and Figure 11D Similarly, a first liner layer 110 and a second liner layer 112 are formed such that the first liner layer 110 and the second liner layer 112 surround the first channel layer 104 in the third trench T3 and the fourth trench T4. A first embedded insulating layer 114 is formed such that the first embedded insulating layer 114 fills the interior of the third trench T3 and the fourth trench T4. The first embedded insulating layer 114 may be formed between the first channel layers 104.

[0142] Reference Figure 12E The first molding layer below the etched molding cover layer 108 ( Figure 11E (106) to form the fourth trench T4. Figure 12E The fourth groove T4 can be with Figure 9E and Figure 10E The third trench T3 shown is a connected trench. The first channel layer 104 is spaced apart from each other in the first horizontal direction (X direction) and the first vertical direction (Z direction) according to the third trench T3 and the fourth trench T4. When the first molding layer ( Figure 11EWhen 106 is used, an uneven structure can be formed on the substrate 100.

[0143] Subsequently, a third lining layer 120 is formed such that the third lining layer 120 surrounds the first trench layer 104. A second embedded insulating layer 122 is formed such that the second embedded insulating layer 122 fills the interior of the third trench T3 and the fourth trench T4 on the third lining layer 120. The second embedded insulating layer 122 can be formed between the first trench layers 104 in a first horizontal direction (X direction) and a vertical direction (Z direction).

[0144] Figure 13A , Figure 13B , Figure 13C , Figure 13D and Figure 13E The formation of an etch stop pattern 124 and the etching of a first buried insulating layer 114 are illustrated. Specifically, the etch stop pattern 124 is formed on a molded cover layer 108, a first liner layer 110, a second liner layer 112, a third liner layer 120, and a second buried insulating layer 122. In some embodiments, the etch stop pattern 124 may comprise silicon nitride. Subsequently, the first buried insulating layer 114 in the second trench T2, the third trench T3, and the fourth trench T4 is etched.

[0145] Reference Figure 13A In this layout, an etch stop pattern 124 is formed on the molded pattern MPA, the molded cover layer 108, the first liner layer 110, the second liner layer 112, the third liner layer 120, and the second buried insulating layer 122. The first buried insulating layer 114 is etched into a second trench T2 within the etch stop pattern 124. In this layout, the second trench T2 is placed within the etch stop pattern 124.

[0146] Reference Figure 13B An etch stop pattern 124 is formed on the molded cover layer 108, the first liner layer 110, the second liner layer 112, the third liner layer 120, and the second embedded insulating layer 122. The first embedded insulating layer 114 is etched into the second trench T2 and the third trench T3 inside the etch stop pattern 124.

[0147] Therefore, the second liner layer 112 can be exposed by the second trench T2 and the third trench T3. When the first buried insulating layer is etched ( Figure 12B When etching the first liner layer 110 and the second liner layer 112 formed at the bottom of the second trench T2, the substrate 100 as indicated by reference numeral 126 can be exposed.

[0148] Reference Figure 13CAn etch stop pattern 124 is formed on the molded cover layer 108, the first liner layer 110, the second liner layer 112, the third liner layer 120, and the second buried insulating layer 122. The first buried insulating layer 114 is etched within the second trench T2 and the fourth trench T4 inside the etch stop pattern 124. Thus, the second liner layer 112 can be exposed by the second trench T2 and the fourth trench T4. When the first buried insulating layer 114 is etched, the first liner layer 110 and the second liner layer 112 formed at the bottom of the second trench T2 can be etched to expose the substrate 100 as indicated by reference numeral 126.

[0149] Reference Figure 13D An etch stop pattern 124 is formed on the molded cover layer 108. The first buried insulating layer in the third trench T3 and the fourth trench T4 is etched. Figure 12D (114 in the middle). Therefore, a first lining layer 110 and a second lining layer 112 are formed such that the first lining layer 110 and the second lining layer 112 surround the first channel layer 104 in the third trench T3 and the fourth trench T4.

[0150] Reference Figure 13E An etch stop pattern 124 is formed on the molded cover layer 108. Figure 12E Similarly, a second embedded insulating layer 122 is formed within the third trench T3 and the fourth trench T4. The second embedded insulating layer 122 can be formed between the first trench layers 104 in the first horizontal direction (X direction) and the vertical direction (Z direction).

[0151] Figure 14A , Figure 14B , Figure 14C , Figure 14D and Figure 14E The etch stop pattern is shown. Figure 13A , Figure 13B , Figure 13C , Figure 13D and Figure 13E (124) and etching the first liner layer 110 and the second liner layer 112. Specifically, the etching forms an etch stop pattern on the molded cover layer 108. Figure 13A , Figure 13B , Figure 13C , Figure 13D and Figure 13E (124), and etch the first liner layer 110 and the second liner layer 112 within the second trench T2, the third trench T3 and the fourth trench T4.

[0152] Reference Figure 14A In the layout, the etch stop pattern is etched. Figure 13A 124), and etched on the inner side of the molded pattern MPA and the molded cover layer 108, the first liner layer ( Figure 13A 110) and the second lining layer ( Figure 13A (112). In this way, in the layout, a second groove T2 can be formed on the inner side of the molded pattern MPA and the molded cover layer 108.

[0153] Reference Figure 14B Etched molding cover layer ( Figure 13B Etching stop pattern on 108 (in the middle) Figure 13B 124 in the middle). Etching the first liner layer in the second trench T2 and the third trench T3 ( Figure 13B 110 in the middle) and the second lining layer ( Figure 13B (112 in the text). Therefore, the third lining layer 120 can be exposed by the second trench T2 and the third trench T3.

[0154] Reference Figure 14C Etched molding cover layer ( Figure 13C Etching stop pattern on 108 (in the middle) Figure 13C 124). Etching the first liner layer in the second trench T2 and the fourth trench T4 ( Figure 13C 110 in the middle) and the second lining layer ( Figure 13C (112 in the text). Therefore, the third lining layer 120 can be exposed by the second trench T2 and the fourth trench T4.

[0155] Reference Figure 14D Etched molding cover layer ( Figure 13D Etching stop pattern on 108 (in the middle) Figure 13D 124 in the middle). Etching the first liner layer in the third trench T3 and the fourth trench T4 (middle) Figure 13D 110) and the second lining layer ( Figure 13D (112 in the text). Therefore, the surface of the first trench layer 104 can be exposed by the third trench T3 and the fourth trench T4.

[0156] Reference Figure 14E Etched molding cover layer ( Figure 13E Etching stop pattern on 108 (in the middle) Figure 13E (124 in the middle). Figure 13E Similarly, a second embedded insulating layer 122 is formed within the third trench T3 and the fourth trench T4. The second embedded insulating layer 122 can be formed between the first trench layers 104 in the first horizontal direction (X direction) and the vertical direction (Z direction).

[0157] Figure 15A , Figure 15B , Figure 15C , Figure 15D and Figure 15EThe formation of a first gate insulating layer 126, a fourth liner layer 128, and a third buried insulating pattern 130 is shown.

[0158] Specifically, a first gate insulating layer 126 and a fourth liner layer 128 are formed on one sidewall of the third trench T3 and the fourth trench T4, and on the surface of the first channel layer 104. In some embodiments, the first gate insulating layer 126 may include, but is not limited to, silicon oxide (SiO2), aluminum oxide (AlO), hafnium oxide (HfO), zirconium oxide (ZrO), lanthanum oxide (LaO), etc. In some embodiments, the fourth liner layer 128 may include silicon nitride.

[0159] A fourth liner layer 128 is provided for forming the trench layer and storage nodes in subsequent processes. A third embedded insulating pattern 130 is formed to fill the interior of the third trench T3 and the fourth trench T4. In some embodiments, the third embedded insulating pattern 130 may include silicon oxide.

[0160] Reference Figure 15A In the layout, a first gate insulating layer 126 and a fourth liner layer 128 are formed on the inner side of the molded pattern MPA and the molded cover layer 108. In the layout, the first gate insulating layer 126 and the fourth liner layer 128 are formed on one sidewall of the second trench T2.

[0161] Reference Figure 15B A first gate insulating layer 126 and a fourth liner layer 128 are formed on one sidewall of the third trench T3 and on the surface of the first channel layer 104. The first gate insulating layer 126 and the fourth liner layer 128 can be formed on the upper and lower surfaces of the first channel layer 104.

[0162] A third embedded insulating pattern 130 is formed to fill the interior of the third trench T3. The third embedded insulating pattern 130 can be formed by forming an insulating layer to fill the interior of the second trench T2 and the third trench T3 and then performing etching.

[0163] Reference Figure 15C A first gate insulating layer 126 and a fourth liner layer 128 are formed on one sidewall of the fourth trench T4. A third buried insulating pattern 130 is formed to fill the interior of the fourth trench T4. The third buried insulating pattern 130 can be formed by forming an insulating layer to fill the interior of the fourth trench T4 and then performing etching.

[0164] Reference Figure 15DA first gate insulating layer 126 and a fourth liner layer 128 are formed such that the first gate insulating layer 126 and the fourth liner layer 128 surround the first channel layer 104. Furthermore, the first gate insulating layer 126 and the fourth liner layer 128 are formed on a molded capping layer 108. A third buried insulating pattern 130 is formed such that the third buried insulating pattern 130 fills the interior of the third trench T3 and the fourth trench T4.

[0165] Reference Figure 15E A first gate insulating layer 126 and a fourth liner layer 128 are formed on the molded cover layer 108. Figure 14E Similarly, a second embedded insulating layer 122 is formed within the third trench T3 and the fourth trench T4. The second embedded insulating layer 122 can be formed between the first trench layers 104 in the first horizontal direction (X direction) and the vertical direction (Z direction).

[0166] Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 16E and Figure 16F The fourth liner pattern 132, the memory node 134, and the second channel layer 136 are shown. In detail, the memory node 134 and the second channel layer 136 are formed on the upper and lower portions of the third trench T3, the upper and lower portions of the fourth trench T4, and the upper and lower surfaces of the first gate insulating layer 126.

[0167] A fourth liner layer 128 is recessed and etched in the second horizontal direction (Y direction) on one sidewall of the molded cover layer 108 to form a horizontal trench within the third embedded insulating pattern 130. Figure 16F (T5 in the middle). In the horizontal trench ( Figure 16F Storage node 134 and second channel layer 136 are formed within T5.

[0168] Reference Figure 16A In this layout, a first gate insulating layer 126 is formed on the inner side of the molded pattern MPA and the molded cover layer 108. In this layout, the first gate insulating layer 126 is disposed on the molded pattern MPA, the molded cover layer 108, the third liner layer 120, and the second buried insulating layer 122. A second trench T2 is disposed on the inner side of the molded pattern MPA and the molded cover layer 108.

[0169] Reference Figure 16B and Figure 16F Storage nodes 134 and second channel layers 136 are formed on the upper and lower parts of the third trench T3 and on the upper and lower surfaces of the first gate insulating layer 126.

[0170] In some embodiments, the second channel layer 136 may include at least one of oxide semiconductors, polysilicon, 2D material semiconductors, and combinations thereof. In some embodiments, the second channel layer 136 may include a depositable material, such as silicon or an oxide semiconductor (e.g., indium gallium zinc oxide (IGZO)).

[0171] In some embodiments, storage node 134 may include a conductive material. Storage node 134 may include a metallic material, such as titanium nitride, tungsten, ruthenium, molybdenum, etc. In some embodiments, storage node 134 may include polycrystalline silicon.

[0172] A fourth liner layer 128 is recessed and etched in the second horizontal direction (Y direction) on one sidewall of the molded cover layer 108 to form a horizontal trench within the third embedded insulating pattern 130. Figure 16F (T5 in the third trench). The fourth liner layer 128 can be recessed and etched to form a fourth liner pattern 132 within the first gate insulating layer 126 in the third trench T3.

[0173] In horizontal trenches ( Figure 16F Storage node 134 and second channel layer 136 are formed within T5. In some embodiments, storage node 134 and second channel layer 136 may not completely fill the horizontal trench (indicated by reference numeral T5r) Figure 16F (T5).

[0174] Reference Figure 16C Storage nodes 134 and a second channel layer 136 are formed above and below the fourth trench T4. A fourth liner layer 128 is recessed and etched in the second horizontal direction (Y direction) on one sidewall of the molded cover layer 108 to form a horizontal trench within the third buried insulation pattern 130.

[0175] The fourth liner layer 128 can be recessed and etched to form a fourth liner pattern 132 within the first gate insulating layer 126 in the fourth trench T4. A memory node 134 and a second channel layer 136 are formed within the horizontal trench. In some embodiments, the memory node 134 and the second channel layer 136 may not completely fill the horizontal trench.

[0176] Reference Figure 16D The fourth liner layer 128 is etched onto the first gate insulating layer 126 formed on the first channel layer 104 in the third trench T3 and the fourth trench T4.

[0177] A second channel layer 136 is formed such that it surrounds the first gate insulating layer 126 on top of the first channel layer 104 in the third trench T3 and the fourth trench T4. The second channel layer 136 can be formed within a third buried insulating pattern 130. Furthermore, a fourth liner layer is etched onto the first gate insulating layer 126 formed above the molded cover layer 108. Figure 15D (128 in the middle).

[0178] Reference Figure 16E The fourth liner layer formed on the first gate insulating layer 126 on the molded cover layer 108 is etched. Figure 15E (of 128). With Figure 15E Similarly, a second embedded insulating layer 122 is formed within the third trench T3 and the fourth trench T4. The second embedded insulating layer 122 can be formed between the first trench layers 104 in the first horizontal direction (X direction) and the vertical direction (Z direction).

[0179] Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 17E and Figure 17F The diagram shows the formation of a first capping insulating layer 138, a second gate insulating layer 140, a fifth liner layer 142, and a fourth buried insulating layer 144.

[0180] Specifically, a first capping insulating layer 138 is formed such that it covers a sidewall of the second channel layer 136 and a first gate insulating layer 126 above a sidewall of the first channel layer 104. In some embodiments, the first capping insulating layer 138 may comprise silicon oxide. The first capping insulating layer 138 may also be formed on the first gate insulating layer 126 on the sidewalls and surfaces of the molded capping layer 108.

[0181] A third buried insulating pattern 130 is etched inside the second trench T2, the third trench T3, and the fourth trench T4. A second gate insulating layer 140 is formed on the fourth liner pattern 132, the memory node 134, the second channel layer 136, and the first capping insulating layer 138 within the third trench T3 and the fourth trench T4. In some embodiments, the second gate insulating layer 140 may comprise the same material as the first gate insulating layer 126.

[0182] A fifth liner layer 142 is formed on the second gate insulating layer 140 inside the third trench T3 and the fourth trench T4. In some embodiments, the fifth liner layer 142 may include silicon nitride. A fourth buried insulating layer 144 is formed inside the second trench T2, the third trench T3, and the fourth trench T4. In some embodiments, the fourth buried insulating layer 144 may include silicon oxide.

[0183] Reference Figure 17A In the layout, a first gate insulating layer 126, a second gate insulating layer 140, and a fifth liner layer 142 are disposed on the inner side of the molded pattern MPA and the molded cover layer 108. The first gate insulating layer 126, the second gate insulating layer 140, and the fifth liner layer 142 are disposed on one sidewall of a second trench T2 located on the inner side of the molded pattern MPA and the molded cover layer 108. A fourth buried insulating layer 144 is placed inside the second trench T2.

[0184] Reference Figure 17B and Figure 17F A first capping insulating layer 138 is formed such that the first capping insulating layer 138 covers a sidewall of the second channel layer 136 and a sidewall of the first gate insulating layer 126 above a sidewall of the first channel layer 104 within the second trench T2 and the third trench T3. The first capping insulating layer 138 may also be formed on the first gate insulating layer 126 on the sidewall and surface of the molded capping layer 108.

[0185] A third buried insulating pattern 130 is etched inside the second trench T2 and the third trench T3. A second gate insulating layer 140 is formed on the fourth liner pattern 132, the memory node 134, the second channel layer 136, and the first capping insulating layer 138 inside the third trench T3. A fifth liner layer 142 is formed on the second gate insulating layer 140 inside the second trench and the third trench T3. A fourth buried insulating layer 144 is formed inside the second trench T2 and the third trench T3.

[0186] Reference Figure 17C A first capping insulating layer 138 is formed such that the first capping insulating layer 138 covers one sidewall of the second channel layer 136 within the second trench T2 and the fourth trench T4. The first capping insulating layer 138 may also be formed on the first gate insulating layer 126 on the sidewall and surface of the molded capping layer 108.

[0187] The third buried insulating pattern 130 is etched inside the second trench T2 and the fourth trench T4. The second gate insulating layer 140 is formed on the fourth liner pattern 132, the memory node 134, the second channel layer 136 and the first capping insulating layer 138 in the fourth trench T4.

[0188] A fifth liner layer 142 is formed on the second gate insulating layer 140 inside the second trench T2 and the fourth trench T4. The fifth liner layer 142 may be formed on one sidewall of the second gate insulating layer 140 inside the fourth trench T4. Furthermore, the fifth liner layers 142 may be formed to be spaced apart from each other in the vertical direction (Z direction) within the second trench T2 and the fourth trench T4. Subsequently, a fourth buried insulating layer 144 is formed inside the second trench T2 and the fourth trench T4.

[0189] Reference Figure 17D A first capping insulating layer 138 can be formed on the first gate insulating layer 126 above the molded capping layer 108. The third buried insulating pattern inside the third trench T3 and the fourth trench T4 is etched. Figure 16D (130 in the middle).

[0190] A second gate insulating layer 140 and a fifth liner layer 142 are formed on the second channel layer 136 inside the third trench T3 and the fourth trench T4. The second gate insulating layer 140 and the fifth liner layer 142 may also be formed on the first capping insulating layer 138 above the molded capping layer 108.

[0191] A fifth lining layer 142 is formed such that it surrounds the second channel layer 136 within the third trench T3 and the fourth trench T4. Subsequently, a fourth embedded insulation layer 144 is formed within the third trench T3 and the fourth trench T4.

[0192] Reference Figure 17E A first capping insulating layer 138, a second gate insulating layer 140, and a fifth liner layer 142 are formed on a first gate insulating layer 126 on a molded capping layer 108. Figure 16E Similarly, a second embedded insulating layer 122 is formed within the third trench T3 and the fourth trench T4. The second embedded insulating layer 122 can be formed between the first trench layers 104 in the first horizontal direction (X direction) and the vertical direction (Z direction).

[0193] Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 18E and Figure 18F The etching and removal of the fourth embedded insulation layer 144 and the formation of the fifth lining pattern 146, letter lines 148, the second capping insulation pattern 150 and the fifth embedded insulation layer 152 are shown.

[0194] Specifically, the fifth liner layer above the etched molding cover layer 108 ( Figure 17A , Figure 17B , Figure 17C , Figure 17D and Figure 17E After the second gate insulating layer 142) and the second gate insulating layer 140, the fourth buried insulating layer formed in the second trench T2, the third trench T3 and the fourth trench T4 is etched and removed. Figure 17A , Figure 17B , Figure 17C , Figure 17D and Figure 17E (144).

[0195] The fifth liner layer is etched in the second horizontal direction (Y direction) to form the second trench T2, the third trench T3, and the fourth trench T4. Figure 17A , Figure 17B , Figure 17C , Figure 17D and Figure 17E (142) A fifth liner pattern 146 is formed on one sidewall of the second gate insulating layer 140. Word lines 148 are formed on the second gate insulating layer 140 above and below the first channel layer 104 in the third trench T3. In the fourth trench T4, the word lines 148 are formed to be spaced apart from each other in the vertical direction (Z direction). In some embodiments, the word lines 148 may include, but are not limited to, metallic materials such as titanium nitride (TiN), tungsten (W), and molybdenum (Mo).

[0196] A second capping insulation pattern 150 is formed on one sidewall of the word lines 148 above and below the first channel layer 104 in the third trench T3. In some embodiments, the second capping insulation pattern 150 may include silicon nitride. The second capping insulation pattern 150 is formed on one sidewall of the word lines 148 spaced apart from each other in the vertical direction (Z direction) within the fourth trench T4. A fifth embedded insulation layer 152 is formed within the second trench T2, the third trench T3, and the fourth trench T4. In some embodiments, the fifth embedded insulation layer 152 may include silicon oxide.

[0197] Reference Figure 18A In the layout, a first gate insulating layer 126, a first capping insulating layer 138, and a second gate insulating layer 140 are arranged on the inner side of the molded pattern MPA and the molded cover layer 108. The first gate insulating layer 126, the first capping insulating layer 138, and the second gate insulating layer 140 are arranged on one sidewall of a second trench T2 located on the inner side of the molded pattern MPA and the molded cover layer 108. A fifth embedded insulating layer 152 is placed inside the second trench T2.

[0198] Reference Figure 18B and Figure 18F The fourth liner layer above the etched molding cover layer 108 ( Figure 17B 142) and the second gate insulating layer ( Figure 17B After (140), the fourth buried insulating layer formed in the second trench T2 and the third trench T3 is etched and removed. Figure 17B (144).

[0199] The fifth liner layer is etched in the second horizontal direction (Y direction) to form the second trench T2 and the third trench T3. Figure 17A , Figure 17B , Figure 17C , Figure 17D and Figure 17E(142) A fifth liner pattern 146 is formed on one sidewall of the second gate insulating layer 140. Word lines 148 are formed on the second gate insulating layer 140 above and below the first channel layer 104 in the third trench T3.

[0200] A second capping insulation pattern 150 is formed on one sidewall of the letter line 148 above and below the first channel layer 104 in the third trench T3. A fifth embedded insulation layer 152 is formed inside the second trench T2 and the third trench T3.

[0201] Reference Figure 18C The fourth liner layer above the etched molding cover layer 108 ( Figure 17C 142) and the second gate insulating layer ( Figure 17C After (140), the fourth buried insulating layer formed in the second trench T2 and the fourth trench T4 is etched and removed. Figure 17A , Figure 17B , Figure 17C , Figure 17D and Figure 17E (144).

[0202] The fifth liner layer is etched in the second horizontal direction (Y direction) to form the second trench T2 and the fourth trench T4. Figure 17C In section 142), a fifth liner pattern 146 is formed on one sidewall of the second gate insulating layer 140. Word lines 148 are formed to be spaced apart from each other in the vertical direction (Z direction) within the fourth trench T4. A second capping insulating pattern 150 is formed on one sidewall of the word lines 148 spaced apart from each other in the vertical direction (Z direction) within the fourth trench T4. A fifth embedded insulating layer 152 is formed inside the second trench T2 and the fourth trench T4.

[0203] Reference Figure 18D The fourth liner layer above the etched molding cover layer 108 ( Figure 17D 142) and the second gate insulating layer ( Figure 17D After (140), the fourth buried insulating layer formed in the third trench T3 and the fourth trench T4 is etched and removed. Figure 17D (144).

[0204] Word lines 148 are formed within the third trench T3 and the fourth trench T4. The word lines 148 extend in the first horizontal direction (X direction) and connect to each other in the vertical direction (Z direction). They can be arranged around the first trench layer (…). Figure 18B The shape of 104 in the middle forms the letter lines 148. A second capping insulation pattern 150 is formed between the letter lines 148. Subsequently, a fifth embedded insulation layer 152 is formed inside the second trench T2 and the fourth trench T4.

[0205] Reference Figure 18E The fourth liner layer above the etched molded cover layer 108 ( Figure 17E 142) and the second gate insulating layer ( Figure 17E (of 140). Figure 17E Similarly, a second embedded insulating layer 122 is formed within the third trench T3 and the fourth trench T4. The second embedded insulating layer 122 can be formed between the first trench layers 104 in the first horizontal direction (X direction) and the vertical direction (Z direction).

[0206] Figure 19A , Figure 19B , Figure 19C , Figure 19D , Figure 19E and Figure 19F This includes bit lines 154 that are formed in the layout, extending in the second horizontal direction (Y direction) and spaced apart in the first horizontal direction.

[0207] Specifically, the first gate insulating layer 126, the first capping insulating layer 138, the second gate insulating layer 140, the second capping insulating pattern 150, and the fifth buried insulating layer 152 are etched within the second trench T2. A bit line 154 is formed within the second trench T2.

[0208] Bit line 154 may contact one side of the first channel layer 104, the first gate insulating layer 126, the second channel layer 136, the second gate insulating layer 140, and the second capping insulating pattern 150 in the vertical direction (Z direction). In some embodiments, bit line 154 may include a conductive material. As described above, bit line 154 may include doped polysilicon or a metallic material.

[0209] Reference Figure 19A In the layout, bit lines 154 are arranged on the inner side of the molded cover layer 108 in the second groove T2. In the layout, the bit lines 154 are arranged to extend in the second horizontal direction (Y direction) and be spaced apart in the first horizontal direction.

[0210] Reference Figure 19B and Figure 19F The first gate insulating layer 126, the first capping insulating layer 138, the second gate insulating layer 140, the second capping insulating pattern 150, and the fifth buried insulating layer 152 are etched in the second trench T2 in the vertical direction (Z direction). In some embodiments, the fifth buried insulating layer 152 may not be completely etched in the vertical direction, but may be partially retained so that the substrate 100 is not exposed.

[0211] Bit line 154 is formed in the second trench T2. Bit line 154 may contact one side of the first channel layer 104, the first gate insulating layer 126, the second channel layer 136, the second gate insulating layer 140, and the second capping insulating pattern 150 in the vertical direction (Z direction).

[0212] Reference Figure 19C This structure can be combined with Figure 18C The structures are identical. A fifth liner pattern 146 is formed on one sidewall of the second gate insulating layer 140. Word lines 148 are formed to be spaced apart from each other in the vertical direction (Z direction) within the fourth trench T4. A second capping insulating pattern 150 is formed on one sidewall of the word lines 148 spaced apart from each other in the vertical direction (Z direction) within the fourth trench T4. A fifth embedded insulating layer 152 is formed inside the second trench T2 and the fourth trench T4.

[0213] Reference Figure 19D This structure can be combined with Figure 18D The structures are identical. Word lines 148 are formed within the third trench T3 and the fourth trench T4. The word lines 148 extend in the first horizontal direction (X direction) and connect to each other in the vertical direction (Z direction). They can be arranged around the first trench layer ( Figure 18B The shape of 104 in the middle forms the letter lines 148. A second capping insulation pattern 150 is formed between the letter lines 148. Subsequently, a fifth embedded insulation layer 152 is formed inside the second trench T2 and the fourth trench T4.

[0214] Reference Figure 19E ,and Figure 18E Similarly, a second embedded insulating layer 122 is formed within the third trench T3 and the fourth trench T4. The second embedded insulating layer 122 can be formed between the first trench layers 104 in the first horizontal direction (X direction) and the vertical direction (Z direction).

[0215] Then, return to the reference. Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G and Figure 2H . Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G and Figure 2H This includes a ground electrode 156 formed in the layout and extending in the first horizontal direction (X direction).

[0216] Specifically, the first gate insulating layer is etched on the outer side of the molded cover layer 108 and the outer side of the first channel layer 104. Figure 19B 126), First sealing insulation layer ( Figure 19B 138) and the second buried insulation layer ( Figure 19B 122). When etching the second buried insulating layer ( Figure 19B When 122 is reached, the third lining layer formed at one end of the first channel layer 104 can be exposed. Figure 19B (120 in the middle).

[0217] The third liner layer exposed at one end of the first channel layer 104 (etched) Figure 19B (120 in the text). After forming silicide at one end of the first channel layer 104, a ground electrode 156 is formed on one side of the first channel layer 104 and the first gate insulating layer 126. The ground electrode 156 may include a conductive material. The ground electrode 156 may include a metallic material, such as titanium nitride, tungsten, molybdenum, or ruthenium.

[0218] Reference Figure 2A In the layout, a ground electrode 156 extending in a first horizontal direction (X direction) is formed on the outer side of the molded cover layer 108.

[0219] Reference Figure 2B and Figure 2H The first gate insulating layer located on the outer side of the molded cover layer 108 and the outer side of the first channel layer 104 is etched. Figure 19B 126), First sealing insulation layer ( Figure 19B 138) and the second buried insulation layer ( Figure 19B 122). Etching of the second buried insulating layer located outside the third trench T3 ( Figure 19B 122 in the middle). When etching the second buried insulating layer ( Figure 19B When 122 is reached, the third lining layer formed at one end of the first channel layer 104 can be exposed. Figure 19B (120 in the middle).

[0220] The third liner layer (middle) exposed at one end of the first channel layer 104 is removed by etching. Figure 19B (120). After forming silicide at one end of the first channel layer 104, a ground electrode 156 is formed on one side of the first channel layer 104 and the first gate insulating layer 126. The ground electrode 156 can be formed in the vertical direction (Z direction).

[0221] Reference Figure 2C Etching is located in the molded cover layer ( Figure 19C The first gate insulating layer on the outer side of (108) Figure 19C 126), First sealing insulation layer ( Figure 19C 138) and the second buried insulation layer ( Figure 19C 122). Etching of the second buried insulating layer located outside the fourth trench T4 ( Figure 19C 122 in the middle). When etching the second buried insulating layer ( Figure 19C When 122 is in the middle, one side of the first gate insulating layer 126 can be exposed.

[0222] A ground electrode 156 is formed on one side of the exposed first gate insulating layer 126. The ground electrode 156 can be formed in the vertical direction (Z direction). The third liner layer exposed at one end of the first channel layer 104 is removed by etching. Figure 19B (120 in the middle).

[0223] Reference Figure 2D This structure can be combined with Figure 19D The structure is the same. Word lines 148 are formed outside the third trench T3. Word lines 148 extend in the first horizontal direction (X direction) and connect to each other in the vertical direction (Z direction). They can be arranged around the first trench layer ( Figure 18B The shape of 104 in the middle forms the letter lines 148. A second capping insulation pattern 150 is formed between the letter lines 148. Subsequently, a fifth embedded insulation layer 152 is formed inside the second trench T2 and the fourth trench T4.

[0224] Reference Figure 2E Etching the second buried insulating layer located outside the third trench T3 and the fourth trench T4 ( Figure 19E 122). Etch and remove the third liner layer surrounding the first trench layer 104 ( Figure 19E (120 in the middle). Ground electrodes 156 are formed outside the third trench T3 and the fourth trench T4.

[0225] Reference Figure 2F and Figure 2G A first gate insulating layer 126 can be formed to surround a first channel layer 104 in the vertical direction (Z direction). A second channel layer 136 and a memory node 134 can be formed to surround the first gate insulating layer 126. A second gate insulating layer 140 can be formed to surround the second channel layer 136 and the memory node 134. A word line 148 can be formed to surround the second gate insulating layer 140. A fifth buried insulating layer 152 can be formed above and below the word line 148.

[0226] Although this specification contains numerous details of specific embodiments, these should not be construed as limiting the scope of any invention or the scope that may be claimed, but rather as descriptions of features that may be specific to a particular invention. Certain features described in the context of individual embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations, one or more features from a combination may be removed from that combination in some cases, and the combination may be for sub-combinations or variations thereof.

[0227] Although this disclosure has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor memory device, comprising: A plurality of memory cells are arranged in three dimensions on a substrate in a first horizontal direction, a second horizontal direction and a vertical direction, wherein the second horizontal direction is orthogonal to the first horizontal direction and the vertical direction is perpendicular to the first horizontal direction and the second horizontal direction, and each of the plurality of memory cells includes a first transistor comprising a first channel layer and a second transistor comprising a second channel layer located above and below the first channel layer. The bit line is connected to the first end of the first channel layer and extends in the vertical direction; A ground electrode, which is connected to the second end of the first trench layer and extends in the vertical direction; A storage node is located above and below the first channel layer and in contact with a first surface of the second channel layer, the second channel layer and the storage node surrounding the first channel layer between the bit line and the ground electrode; as well as Word lines that surround the memory node and the second channel layer between the bit lines and the ground electrode.

2. The semiconductor memory device according to claim 1, wherein, The first transistor includes a read transistor, and the second transistor includes a write transistor.

3. The semiconductor memory device according to claim 1, wherein, The first transistor includes a PMOS transistor, and the second transistor includes an NMOS transistor.

4. The semiconductor memory device according to claim 1, wherein, The second surface of the second channel layer, which is opposite to the first surface, contacts the bit line.

5. The semiconductor memory device according to claim 1, wherein, The first gate insulating layer is located between the first channel layer and the memory node, and between the first channel layer and the second channel layer.

6. The semiconductor memory device according to claim 1, wherein, The second gate insulating layer is located between the second channel layer and the word line, and between the memory node and the word line.

7. The semiconductor memory device according to claim 1, wherein, The first channel layer comprises crystalline silicon.

8. The semiconductor memory device according to claim 1, wherein, The second channel layer includes at least one of oxide semiconductor, polysilicon, and 2D material semiconductor.

9. The semiconductor memory device according to claim 1, wherein, The storage node is the floating gate of the first transistor.

10. A semiconductor memory device, comprising: A first trench layer extends on a substrate in a second horizontal direction and is spaced apart in a first horizontal direction perpendicular to the second horizontal direction. The first trench layer has a first surface in the second horizontal direction and a second surface opposite to the first surface. A second channel layer is located above and below the first channel layer, and the second channel layer has a first surface and a second surface opposite to the first surface in the second horizontal direction; A storage node is disposed above and below the first channel layer and in contact with a first surface of the second channel layer, and is formed inward relative to the first surface of the first channel layer in the second horizontal direction; The bit line contacts a first end of each of the first channel layer and the second channel layer in a vertical direction, the vertical direction being perpendicular to the first horizontal direction and the second horizontal direction; The ground electrode is in contact with the second end of the first trench layer in the vertical direction; as well as The word line is located between the bit line and the ground electrode, above the second channel layer and the memory node. The second channel layer and the storage node surround the first channel layer, and the word line surrounds the second channel layer and the storage node.

11. The semiconductor memory device of claim 10, further comprising a first transistor and a second transistor, in, The first transistor includes the first channel layer and the word line, and the second transistor includes the second channel layer and the word line.

12. The semiconductor memory device according to claim 11, wherein, The first transistor includes a read transistor, and the second transistor includes a write transistor.

13. The semiconductor memory device according to claim 10, wherein, The word line surrounds both the storage node and the second channel layer.

14. The semiconductor memory device of claim 10, further comprising a work function adjustment layer, the work function adjustment layer being in contact with a word line on one side of the word line on the second channel layer.

15. The semiconductor memory device according to claim 10, wherein, The word line overlaps with the storage node in the vertical direction.

16. A semiconductor memory device, comprising: A first trench layer extends on a substrate in a second horizontal direction and is spaced apart in a first horizontal direction perpendicular to the second horizontal direction. The first trench layer has a first surface in the second horizontal direction and a second surface opposite to the first surface. A second channel layer is located above and below the first channel layer, and the second channel layer has a first surface and a second surface opposite to the first surface in the second horizontal direction; A storage node is disposed above and below the first channel layer and in contact with a first surface of the second channel layer, and is formed inwardly relative to the first surface of the first channel layer in the second horizontal direction, wherein the second channel layer and the storage node surround the first channel layer; The bit line contacts a first end of each of the first channel layer and the second channel layer in a vertical direction, the vertical direction being perpendicular to the first horizontal direction and the second horizontal direction; The ground electrode is in contact with the second end of the first trench layer in the vertical direction; A word line, located above the second channel layer between the bit line and the ground electrode, wherein the word line surrounds the second channel layer; A first gate insulating layer is located between the first channel layer and the memory node, and between the first channel layer and the second channel layer; and A second gate insulating layer is located between the second channel layer and the word line, and between the memory node and the word line.

17. The semiconductor memory device of claim 16, wherein, The bit-line side channel doped region contacts the bit line at the first end of the first channel layer.

18. The semiconductor memory device according to claim 17, wherein, The bit-line side channel doped region is aligned with the first end of the word line in the vertical direction, overlaps with the word line, or is recessed away from the first end of the word line.

19. The semiconductor memory device of claim 16, wherein, The ground-side channel doped region in contact with the ground electrode is located at the second end of the first channel layer.

20. The semiconductor memory device of claim 19, wherein, The ground-side channel doped region is aligned with the end of the storage node in the vertical direction, overlaps with the storage node in the vertical direction, or is recessed at the end away from the storage node.

Images