Semiconductor devices and their manufacturing methods, memory systems

Abstract

This application discloses a semiconductor device and its manufacturing method, as well as a memory system, to simplify the manufacturing process of the semiconductor device. The semiconductor device includes a channel structure, word lines, and a capacitor structure. The channel structure includes a first channel portion and a second channel portion interconnected. The first channel portion extends along a first direction. The second channel portion is disposed around the first channel portion. The word lines include a first word line portion and a second word line portion interconnected; the first word line portion extends along a second direction, and the material of the first word line portion includes polysilicon; at least a portion of the second word line portion is located between the first word line portion and the second channel portion, and the second direction intersects the first direction. The capacitor structure is connected to the second channel portion, and the capacitor structure and the word lines are located on different sides of the channel structure.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a semiconductor device and its manufacturing method, and a storage system. Background Technology

[0002] With the rapid growth in demand for storage capacity and bandwidth from applications such as artificial intelligence, the limitations of traditional two-dimensional (2D) Dynamic Random Access Memory (DRAM) in terms of area utilization, access bandwidth, and power consumption are becoming increasingly apparent. To overcome the bottleneck of planar expansion, three-dimensional (3D) stacked DRAM memory technology has become a recognized key direction for improving storage density and system-level performance. Currently, 3D stacked DRAM faces the challenge of complex manufacturing processes. Summary of the Invention

[0003] This application provides a semiconductor device and its manufacturing method, as well as a storage system, to at least partially solve the above-mentioned technical problems.

[0004] To achieve the above objectives, according to a first aspect of this application, a semiconductor device is provided, including a channel structure, word lines, and a capacitor structure. The channel structure includes a first channel portion and a second channel portion interconnected. The first channel portion extends along a first direction. The second channel portion is disposed around the first channel portion. The word lines include a first word line portion and a second word line portion interconnected, the first word line portion extending along a second direction, the first word line portion being made of polysilicon, and at least a portion of the second word line portion being located between the first word line portion and the second channel portion, the second direction intersecting the first direction. The capacitor structure is connected to the second channel portion, and the capacitor structure and the word lines are located on different sides of the channel structure.

[0005] In the semiconductor device of this application embodiment, based on the combined design of the channel structure, word lines, and capacitor structure, the semiconductor device can realize a three-dimensional stacked design of dynamic random access memory, thereby improving the storage density of the semiconductor device. Furthermore, the material of the first word line portion includes polysilicon, and the deposition and doping processes of polysilicon have low temperatures, improving the process compatibility of the formation process of the first word line portion with other structures. In addition, the material of the first word line portion including polysilicon provides the conditions for forming the first word line portion using a polysilicon layer as a sacrificial layer in the stacked structure, thereby eliminating the need for additional steps of forming grooves and forming word lines in the grooves, simplifying the manufacturing process of the semiconductor device.

[0006] According to a second aspect of this application, a method for manufacturing a semiconductor device is provided, comprising: forming a stacked structure including a conductive layer and an insulating layer stacked along a first direction, the conductive layer being made of polysilicon; forming a first through-hole extending through the conductive layer and the insulating layer along the first direction; and removing a portion of the conductive layer through the first through-hole to form a first lateral groove, the remaining conductive layer including a first word line extending along a second direction, the first direction intersecting the second direction.

[0007] In the semiconductor device manufacturing method of this application embodiment, after removing the conductive layer around the first through-opening to form a first lateral trench, the remaining conductive layer extending along the second direction forms a first word line portion. Thus, by using a conductive layer including polysilicon in the stacked structure to form the first word line portion, the additional process steps of forming a trench and forming word lines in the trench can be omitted, simplifying the semiconductor device manufacturing process. Furthermore, the mature processes for forming insulating layers and conductive layers including polysilicon further simplify the manufacturing process of stacked structures.

[0008] According to a third aspect of this application, a storage system is also provided, the storage system including a semiconductor device and a controller as described in any of the above embodiments. The controller is connected to the semiconductor device and is used to control the semiconductor device to store data.

[0009] The beneficial effects of the storage system in this application embodiment are the same as those of the semiconductor device described above, and will not be described in detail here. Attached Figure Description

[0010] Figure 1 This is a three-dimensional structural schematic diagram of a semiconductor device provided in an exemplary embodiment of this application; Figure 2 This is provided in an exemplary embodiment of this application. Figure 1 A schematic diagram of a planar structure of the semiconductor device shown from one perspective; Figure 3 The exemplary embodiments provided in this application are along Figure 2 A schematic diagram of the cross-sectional structure intercepted by the tangent line A1-A1' shown; Figure 4 The exemplary embodiments provided in this application are along Figure 2 A schematic diagram of the cross-sectional structure intercepted by the tangent line A2-A2' shown; Figure 5 This is a schematic flowchart of a method for manufacturing a semiconductor device provided in an exemplary embodiment of this application; Figure 6 This is a three-dimensional structural diagram of a layered structure provided in an exemplary embodiment of this application; Figure 7 The exemplary embodiments provided in this application are along Figure 6 A schematic diagram of a cross-sectional structure taken by the tangent line B-B' shown; Figure 8 This is a three-dimensional structural diagram of an isolation groove provided in an exemplary embodiment of this application; Figure 9 The exemplary embodiments provided in this application are along Figure 8 A schematic diagram of a cross-sectional structure taken by the C-C' tangent; Figure 10 This is a three-dimensional structural diagram of an isolation structure provided in an exemplary embodiment of this application; Figure 11 The exemplary embodiments provided in this application are along Figure 10 A schematic diagram of a cross-sectional structure taken by the tangent line D-D' shown; Figure 12 This is a three-dimensional structural diagram of a first through-hole provided in an exemplary embodiment of this application; Figure 13 The exemplary embodiments provided in this application are along Figure 12 A schematic diagram of a cross-sectional structure taken by the tangent line E-E' shown; Figure 14 This is a three-dimensional structural diagram of a first lateral groove provided in an exemplary embodiment of this application; Figure 15 The exemplary embodiments provided in this application are along Figure 14 A schematic diagram of a cross-sectional structure taken by the tangent line F-F' shown; Figure 16 This is a cross-sectional structural diagram of an example embodiment of the present application for forming an initial word line layer; Figure 17 This is a cross-sectional structural diagram of a second initial word line portion and a gate oxide layer provided in an exemplary embodiment of this application; Figure 18 The exemplary embodiments provided in this application are along Figure 17 A schematic diagram of a cross-sectional structure taken by the tangent line G-G' shown; Figure 19 This is a three-dimensional structural diagram of a sacrificial structure provided in an exemplary embodiment of this application; Figure 20 The exemplary embodiments provided in this application are along Figure 19 A schematic diagram of a cross-sectional structure taken by the tangent line H-H' shown; Figure 21This is a three-dimensional structural diagram of a second through-hole provided in an exemplary embodiment of this application; Figure 22 The exemplary embodiments provided in this application are along Figure 21 A schematic diagram of a cross-sectional structure taken by the tangent line I-I' shown; Figure 23 This is a three-dimensional structural diagram of a second lateral groove provided in an exemplary embodiment of this application; Figure 24 The exemplary embodiments provided in this application are along Figure 23 A schematic diagram of a cross-sectional structure taken by the tangent line J-J' shown; Figure 25 This is a three-dimensional structural diagram of a second character line portion provided in an exemplary embodiment of this application; Figure 26 The exemplary embodiments provided in this application are along Figure 25 A schematic diagram of a cross-sectional structure taken by the tangent line K-K' shown; Figure 27 This is a three-dimensional structural diagram of an isolation layer provided in an exemplary embodiment of this application; Figure 28 The exemplary embodiments provided in this application are along Figure 26 A schematic diagram of a cross-sectional structure taken by the L-L' tangent; Figure 29 This is a structural block diagram of a storage system provided in an exemplary embodiment of this application.

[0011] Explanation of reference numerals in the attached figures: 100. Semiconductor devices; 11. Trench structure; 111. First trench section; 112. Second trench section; 113. Top surface of trench; 114. Bottom surface of trench; 115. Connecting side of trench; 116. Non-connecting side of trench; 12. Character line; 121. First character line section; 122. Second character line section; 123A1. First side wall; 123A2. Second side wall; 123A3. First curved side surface; 123A4. Flat side surface; 124. Second curved side surface; 125. First side surface; 126. Second side surface; 13. Gate oxide layer; 14. Capacitor structure; 141. First capacitor electrode; 1411. Electrode body; 1412. Electrode extension; 142. Dielectric layer; 143. Second capacitor electrode; 15. Bit line; 16. Isolation structure; 17. Substrate; 20. Layered structure; 21. Insulation layer; 22. Conductive layer; 221. First conductive strip; 222. Second conductive strip; 231. First through opening; 232. First lateral groove; 233. Isolation groove; 234. Second through opening; 235. Second lateral groove; 24. Initial character line layer; 241. Second initial character line section; 25. Sacrifice structure; 26. Isolation layer; Z, first direction; X, second direction; Y, third direction; 200, Controller; 300, Storage System. Detailed Implementation

[0012] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0013] Please see Figures 1 to 4 This application provides a semiconductor device 100. The semiconductor device 100 includes a channel structure 11, a word line 12, and a capacitor structure 14.

[0014] The channel structure 11 includes a first channel portion 111 and a second channel portion 112. Each first channel portion 111 extends along a first direction Z, and a plurality of first channel portions 111 are arranged along a second direction X and a third direction Y. Each first channel portion 111 can be a hollow columnar structure, but is not limited thereto. The shape of the cross-section of the first channel portion 111 can include at least one of a circle and a rectangle, and the cross-section of the first channel portion 111 can be perpendicular to the first direction Z.

[0015] The third direction Y, the first direction Z, and the second direction X intersect each other. In one example, the first direction Z, the second direction X, and the third direction Y are perpendicular to each other, but this is not a limitation. In another example, the angle between any two of the third direction Y, the first direction Z, and the second direction X can be acute or obtuse.

[0016] A second channel portion 112 is disposed around a corresponding first channel portion 111 and connected to a corresponding first channel portion 111 and a capacitor structure 14. A plurality of second channel portions 112 are arranged in an array along a first direction Z, a second direction X, and a third direction Y. At least two second channel portions 112 spaced apart along the first direction Z are connected to a first channel portion 111. Therefore, the second channel portions 112 with multiple transistors disposed along the first direction Z share a single first channel portion 111, thereby enabling the semiconductor device 100 to achieve a three-dimensional stacked design to improve the storage density of the semiconductor device 100. Furthermore, different second channel portions 112 along each of the second direction X and the third direction Y are respectively connected to different corresponding first channel portions 111.

[0017] In some embodiments, a second channel portion 112 may include a channel top surface 113, a channel bottom surface 114, a channel connecting side surface 115, and a channel non-connecting side surface 116. The channel top surface 113 and the channel bottom surface 114 are disposed opposite to each other along a first direction Z, and both the channel top surface 113 and the channel bottom surface 114 are disposed around and connected to the first channel portion 111. The shapes of the channel top surface 113 and the channel bottom surface 114 may include annular shapes, such as circular annular, rectangular annular, or irregular annular. The channel connecting side surface 115 and the channel non-connecting side surface 116 are connected between the channel top surface 113 and the channel bottom surface 114. The channel connection side 115 is located on the side of the second channel portion 112 near the capacitor structure 14, adjacent to and in contact with the capacitor structure 14, to realize the connection between the second channel portion 112 and the capacitor structure 14. Therefore, the data read / write path between the capacitor structure 14 and the first channel portion 111 can be controlled through the second channel portion 112 of the transistor. The channel connection side 115 may include an arcuate surface to increase the contact area between the channel connection side 115 and the capacitor structure 14 and reduce the contact impedance between them. The channel non-connection side 116 is located on the side of the channel connection side 115 away from the capacitor structure 14, and the two ends of the channel non-connection side 116 are respectively connected to the two ends of the channel connection side 115. The channel non-connection side 116 may also include an arcuate side, and the channel non-connection side 116 may also include a planar side, with the planar side connected to the arcuate side.

[0018] The channel structure 11 includes a semiconductor material. This semiconductor material may include at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline germanium, and oxide semiconductors. The oxide semiconductors include, but are not limited to, at least one of indium gallium zinc oxide (In-Ga-Zn-O, abbreviated as IGZO), zinc oxide (ZnO), and indium zinc oxide. In one exemplary embodiment, the channel structure 11 includes indium gallium zinc oxide to reduce the transistor's turn-off current and extend the data retention time of the capacitor structure 14.

[0019] In a memory cell (including a transistor and a capacitor structure 14), the capacitor structure 14 and the word line 12 are located on different sides of a corresponding channel structure 11. In some embodiments, along the third direction Y, the capacitor structure 14 and the word line 12 are located on different sides of a corresponding channel structure 11.

[0020] The word line 12 includes a first word line portion 121 and a second word line portion 122. The first word line portion 121 serves as a gate line, and the second word line portion 122 serves as the gate of a transistor. The gate line provides a gate signal to the gate of the transistor.

[0021] The first word line portion 121 extends along the second direction X, and the material of the first word line portion 121 includes polysilicon. At least a portion of the second word line portion 122 is located between the first word line portion 121 and the second channel portion 112 and is connected to the first word line portion 121. Thus, based on the combination design of the channel structure 11, the word line 12, and the capacitor structure 14, the semiconductor device 100 can realize a three-dimensional stacked design of dynamic random access memory, thereby increasing the storage density of the semiconductor device 100. Furthermore, the material of the first word line portion 121 includes polysilicon, and the deposition and doping processes of polysilicon have low temperatures, improving the process compatibility of the formation process of the first word line portion 121 with other structures. In addition, the material of the first word line portion 121 includes polysilicon, which provides the conditions for forming the first word line portion 121 using the polysilicon layer as a sacrificial layer in the stacked structure 20, thereby eliminating the need for additional process steps of forming grooves and forming word lines 12 in the grooves, simplifying the manufacturing process of the semiconductor device 100.

[0022] In some embodiments, please refer to Figure 2 and Figure 3 Multiple spaced first word line portions 121 are arranged in an array at least along a first direction Z and a third direction Y. Multiple spaced second word line portions 122 are arranged along the first direction Z, a second direction X, and a third direction Y. At least two adjacent second word line portions 122 arranged along the third direction Y are connected to one first word line portion 121. This design reduces the total number of first word line portions 121 in the semiconductor device 100, providing more space for the storage cells (including transistor and capacitor structures 14), and further increasing the storage density of the semiconductor device 100. Furthermore, on each side of the first word line portion 121 along the third direction Y, at least two second word line portions 122 spaced along the second direction X are connected to one first word line portion 121.

[0023] In some embodiments, please refer to Figure 2A first character line portion 121 includes at least one first arcuate side surface 123A3, which is recessed inward and contacts the second character line portion 122. Thus, compared to the first character line portion 121 contacting the second character line portion 122 via a planar side surface, the first arcuate side surface 123A3 increases the contact area between the first character line portion 121 and the second character line portion 122, improves the connection yield between them, and reduces the contact resistance between them.

[0024] In some embodiments, please continue reading Figure 2 A first character line portion 121 may further include at least one planar side surface 123A4. A planar side surface 123A4 connects to adjacent first arcuate side surfaces 123A3 on one side of the first character line portion 121 and extends along the second direction X, with the first arcuate side surfaces 123A3 recessed relative to the planar side surface 123A4. Thus, when adjacent first arcuate side surfaces 123A3 on the same side of the first character line portion 121 are respectively connected to two second character line portions 122, the risk of a short circuit between the two second character line portions 122 is reduced.

[0025] In one example, a first word line portion 121 includes a first sidewall 123A1 and a second sidewall 123A2 disposed opposite each other along a third direction Y. Each of the first sidewall 123A1 and the second sidewall 123A2 includes a plurality of first arcuate sidewalls 123A3 and a plurality of planar sidewalls 123A4 arranged along a second direction X, with each planar sidewall 123A4 connected between adjacent first arcuate sidewalls 123A3. The plurality of first arcuate sidewalls 123A3 of each of the first sidewall 123A1 and the second sidewall 123A2 are respectively connected to a plurality of second word line portions 122 spaced apart along the second direction X, so as to transmit gate signals to the gates of a plurality of transistors opposite to the first word line portion 121 through a first word line portion 121.

[0026] In some embodiments, please refer to Figure 2 A second character line portion 122 includes a second arcuate side surface 124, which is located between the first arcuate side surface 123A3 and the second channel portion 112. The first arcuate side surface 123A3 is disposed around the second arcuate side surface 124 and contacts the second arcuate side surface 124, so that the contact surface between the first character line portion 121 and the second character line portion 122 is an arcuate surface, thereby increasing the contact area between the two.

[0027] In some embodiments, a second letter portion 122 may further include a first side surface 125 and a second side surface 126, with the second side surface 126 connected between the second arcuate side surface 124 and the first side surface 125. A second channel portion 112 is located between the first side surface 125, the second side surface 126, and the second arcuate side surface 124 and the first channel portion 111, such that the first side surface 125, the second side surface 126, and the second arcuate side surface 124 are arranged as a whole around the channel non-connected side surface 116. The first side surface 125 may be a planar side surface extending along a third direction Y, but is not limited thereto. The second side surface 126 may be a planar side surface along a second direction X, but is not limited thereto. In one example, a second letter portion 122 includes two first side surfaces 125 and two second side surfaces 126, with the two first side surfaces 125 arranged opposite each other along the second direction X, and the two second side surfaces 126 arranged opposite each other along the second direction X, with a second arcuate side surface 124 connected between the two second side surfaces 126.

[0028] In some embodiments, a second alphanumeric section 122 may further include an upper surface and a lower surface disposed opposite each other along a first direction Z, with a first side surface 125, a second side surface 126, and a second arcuate side surface 124 all connected between the upper and lower surfaces. The upper surface faces the top surface 113 of the channel, and the lower surface faces the bottom surface 114 of the channel, with the second channel section 112 located between the upper and lower surfaces. Thus, the second alphanumeric section 122 surrounds the non-connecting side surface 116 of the channel, the top surface 113 of the channel, and the bottom surface 114 of the channel, that is, the second alphanumeric section 122 surrounds the portion of the second channel section 112 except for the connecting side surface 115 of the channel. In this case, the second alphanumeric section 122 is a fully enclosed grid, thereby improving the control capability of the second alphanumeric section 122 over the second channel section 112.

[0029] In some embodiments, the dimension of the first character line portion 121 along the first direction Z can be equal to the dimension of the second character line portion 122 along the first direction Z.

[0030] In some embodiments, at least a portion of the second word line portion 122 may be made of a material different from that of the first word line portion 121, allowing for greater design flexibility in the second word line portion 122. For example, the material of the second word line portion 122 may include conductive materials such as metals and metal nitrides to reduce the resistance of the second word line portion 122. The metal may include at least one of tungsten, titanium, molybdenum, ruthenium, and copper.

[0031] In other embodiments, the material of the second word line portion 122 may be the same as that of the first word line portion 121, which facilitates the simultaneous formation of the first word line portion 121 and the second word line portion 122 from the same material, simplifying the manufacturing process of the semiconductor device 100. For example, the material of the second word line portion 122 may also include polysilicon or doped polysilicon.

[0032] In some embodiments, the semiconductor device 100 further includes a gate oxide layer 13 located between the second word line portion 122 and the second channel portion 112 to isolate the second word line portion 122 from the second channel portion 112, i.e., to isolate the gate of the transistor from the second channel portion 112. The gate oxide layer 13 may include an inorganic insulating material, including but not limited to at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0033] The capacitor structure 14 is used to store charge to achieve data storage. In some embodiments, the capacitor structure 14 includes a first capacitor electrode 141, a dielectric layer 142, and a second capacitor electrode 143. At least a portion of the first capacitor electrode 141 extends toward the second channel portion 112 in a third direction Y. The second capacitor electrode 143 extends in the third direction Y, surrounds at least a portion of the first capacitor electrode 141, and contacts the second channel portion 112. The dielectric layer 142 is located between the first capacitor electrode 141 and the second capacitor electrode 143. The second capacitor electrode 143 surrounds at least a portion of the first capacitor electrode 141 to increase the facing area between the first capacitor electrode 141 and the second capacitor electrode 143, thereby increasing the capacitance of the capacitor structure 14.

[0034] Both the first capacitor electrode 141 and the second capacitor electrode 143 include a conductive material, which includes at least one selected from metal nitrides and elemental metals. The metal nitride includes at least one selected from titanium nitride, tantalum nitride, and tungsten nitride, and the elemental metal may include at least one selected from tungsten, titanium, molybdenum, ruthenium, and copper. In one example, the first capacitor electrode 141 may include a stack of titanium nitride and tungsten layers, and the second capacitor electrode 143 may include a titanium nitride layer.

[0035] The dielectric layer 142 may include an insulating material having a high dielectric constant. The insulating material having a high dielectric constant may include at least one of hafnium oxide, aluminum oxide, zirconium oxide, titanium dioxide, hafnium zirconium oxide, and barium strontium titanate.

[0036] In some embodiments, an isolation layer 26 is further provided between the second capacitor electrode 143 and the second word line portion 122. The isolation layer 26 serves to electrically isolate the second capacitor electrode 143 from the second word line portion 122.

[0037] In some embodiments, the first capacitor electrode 141 may include an electrode body 1411 and a plurality of electrode extensions 1412 extending from the electrode body 1411. The electrode body 1411 extends along a first direction Z. The plurality of electrode extensions 1412 extend along a third direction Y and are arranged in an array along the first direction Z, the second direction X, and the third direction Y. Adjacent electrode extensions 1412 along the first direction Z, adjacent electrode extensions 1412 along the second direction X, and adjacent electrode extensions 1412 along the third direction Y are all connected to one electrode body 1411. Thus, the plurality of capacitor structures 14 arranged along the first direction Z, the second direction X, and the third direction Y all share one electrode body 1411, which helps to reduce the overall number of electrode bodies 1411 in the semiconductor device 100, providing space for setting more memory cells and increasing the storage density of the semiconductor device 100. Moreover, sharing one electrode body 1411 also helps to maintain the voltage stability of the plurality of first capacitor electrodes 141 in the memory array cell.

[0038] In some embodiments, the semiconductor device 100 further includes a bit line 15. The bit line 15 is used to transmit data signals and extends along a first direction Z. A first channel portion 111 is disposed around and connected to a corresponding bit line 15. In some embodiments, the bit line 15 may include at least one of a metal nitride and a metal element. The metal nitride includes at least one of titanium nitride, tantalum nitride, and tungsten nitride, and the metal element may include at least one of tungsten, titanium, molybdenum, ruthenium, and copper.

[0039] In some embodiments, please refer to Figures 2 to 4 The semiconductor device 100 may further include a plurality of isolation structures 16, each isolation structure 16 extending along a third direction Y and along a second direction X. The isolation structure 16 is located between adjacent capacitor structures 14 and adjacent second word lines 122, thus isolating adjacent second word lines 122 and adjacent capacitor structures 14 arranged along the second direction X. Furthermore, each isolation structure 16 also extends along a first direction Z to achieve isolation between the second word lines 122 and capacitor structures 14 in each layer of the multilayer memory cell.

[0040] In some embodiments, along the third direction Y, the first arcuate side surface 123A3 and the second arcuate side surface 124 are located on one side of the isolation structure 16. Thus, the area design of the first arcuate side surface 123A3 and the second arcuate side surface 124 is not limited by the space between adjacent isolation structures 16, which is beneficial to increasing the area of ​​the first arcuate side surface 123A3 and the second arcuate side surface 124, thereby increasing the contact area of ​​the first arcuate side surface 123A3 and the second arcuate side surface 124.

[0041] In some embodiments, the spacing between the two ends of each first arcuate side 123A3 and the spacing between the two ends of each second arcuate side 124 are both greater than the spacing between adjacent isolation structures 16 in the second direction X, so as to increase the area of ​​the first arcuate side 123A3 and the second arcuate side 124.

[0042] In some embodiments, the first side 125 is located between adjacent isolation structures 16 in the second direction X, and the second side 126 is located on one side of the isolation structure 16 in the third direction Y. In this way, the second letter line portion 122 extends from between adjacent isolation structures 16 to a region outside the adjacent isolation structures 16, which is beneficial to increase the area of ​​the second letter line portion 122 and increase the area in which the second letter line portion 122 acts on the second channel portion 112.

[0043] In some embodiments, the channel connecting side 115 is located between adjacent isolation structures 16 in the second direction X, and at least a portion of the channel non-connecting side 116 protrudes from the end face of the isolation structure 16. Thus, the second channel portion 112 extends from between adjacent isolation structures 16 in the second direction X beyond the area between adjacent isolation structures 16, which helps to increase the area of ​​the second channel portion 112 and increase the area where the second letter portion 122 acts on the second channel portion 112. In one example, the channel top surface 113, the channel bottom surface 114, and the channel non-connecting side 116 all extend from between adjacent isolation structures 16 in the second direction X beyond the area between adjacent isolation structures 16.

[0044] In some embodiments, the isolation structure 16 may include an inorganic insulating material, including but not limited to at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0045] In some embodiments, the semiconductor device 100 further includes an insulating layer 21 located between adjacent word lines 12 and adjacent capacitor structures 14 along the first direction Z, to achieve insulation between word lines 12 and capacitor structures 14 at different layers along the first direction Z. In one example, along the first direction Z, the insulating layer 21 is located between adjacent first word line portions 121, adjacent second word line portions 122, and adjacent second capacitor electrodes 143. In some embodiments, the material of the insulating layer 21 may be the same as the material of the isolation structure 16, in which case the insulating layer 21 and the isolation structure 16 are integrally formed. The insulating layer 21 may include an inorganic insulating material, including but not limited to at least one of silicon oxide, silicon nitride, and silicon oxynitride. In one example, the insulating layer 21 includes silicon oxide.

[0046] In some embodiments, the semiconductor device 100 may further include a substrate 17. The first channel portion 111, the bit line 15, and the electrode body portion 1411 of the first capacitor electrode 141 all extend into the substrate 17 along the first direction Z. The first channel portion 111 can be insulated from the substrate 17 through the gate oxide layer 13, and the electrode body portion 1411 can be insulated from the substrate 17 through the dielectric layer 142 of the capacitor structure 14.

[0047] In some embodiments, substrate 17 may include a semiconductor layer, which may include at least one of single-crystal silicon, single-crystal germanium, gallium arsenide, indium phosphide, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. In one example, substrate 17 includes single-crystal silicon.

[0048] Please see Figure 5 This application also provides a method for manufacturing a semiconductor device 100, which includes the following steps S100, S102 and S103.

[0049] S100, forming a stacked structure, the stacked structure including a conductive layer and an insulating layer stacked along the first direction Z, the material of the conductive layer including polycrystalline silicon.

[0050] See Figure 6 and Figure 7 A multilayer structure 20 is formed on the substrate 17. Along the first direction Z, multiple conductive layers 22 and multiple insulating layers 21 are alternately disposed on the substrate 17.

[0051] In some embodiments, the conductive layer 22 comprises polysilicon, providing conditions for the subsequent formation of the first word line portion 121 in the stacked structure 20. Furthermore, compared to the extremely demanding etching process required when a metal layer is applied to the high-stack structure 20, the process for the polysilicon-based conductive layer 22 is mature, reducing the manufacturing difficulty of the semiconductor device 100. Moreover, the polysilicon-based conductive layer 22 can also serve as a sacrificial layer, providing space for the transistors forming the memory cells and the capacitor structure 14.

[0052] The insulating layer 21 isolates the subsequently formed transistors and capacitor structures 14 stacked along the first direction Z. In some embodiments, the insulating layer 21 may include an inorganic insulating material, which may include at least one of silicon dioxide, silicon nitride, and silicon oxynitride.

[0053] Both the conductive layer 22 and the insulating layer 21 are formed by thin film deposition processes. The thin film deposition processes include, but are not limited to, at least one of physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), epitaxy, coating / spin coating, and electroplating.

[0054] In some embodiments, prior to step S102, the method for manufacturing the semiconductor device 100 may further include step S101, namely forming an isolation structure, wherein the isolation structure extends along a third direction and penetrates the conductive layer and the insulating layer along a first direction, and the third direction intersects with the first direction and the second direction.

[0055] In some embodiments, step S101 includes steps S1011 and S1012.

[0056] S1011: Remove part of the insulating layer and part of the conductive layer to form an isolation groove. The isolation groove penetrates the conductive layer and the insulating layer along a first direction and extends along a third direction. Each remaining conductive layer includes a first conductive strip and a second conductive strip. The first conductive strip extends along a second direction and is connected to the second conductive strip. The second conductive strip extends along a third direction and is adjacent to the isolation groove.

[0057] See Figure 8 and Figure 9 Then, perform step S1011 as described above. Part of the insulating layer 21 and part of the conductive layer 22 can be removed by an etching process to form an isolation trench 233. The etching process may include at least one of dry etching and wet etching.

[0058] In some embodiments, the plurality of isolation grooves 233 may be divided into a plurality of isolation groove groups, which are arranged along a third direction Y. Each isolation groove group includes two isolation groove subgroups, which are adjacent to and located on opposite sides of the first conductive strip 221 along the third direction Y. Each isolation groove group includes at least two isolation grooves 233 spaced apart along a second direction X. In one example, the two isolation groove groups are symmetrically located on opposite sides of the first conductive strip 221 along the third direction Y.

[0059] In some embodiments, the isolation trench 233 further extends into the substrate 17 along the first direction Z. In some embodiments, the shape of the cross section of each isolation trench 233 along the first direction Z may include at least one of a rectangle and an inverted trapezoid to simplify the formation process of the isolation trench 233; and the shape of the cross section of each isolation trench 233 along the second direction X and the third direction Y may include, but is not limited to, a rectangle.

[0060] After forming multiple isolation grooves 233, each remaining conductive layer 22 includes multiple first conductive strips 221 arranged at intervals along the third direction Y, and multiple second conductive strips 222 arranged in an array along the second direction X and the third direction Y.

[0061] In some embodiments, a plurality of first conductive strips 221 are arranged in an array at least along a first direction Z and a third direction Y, and may be divided into a plurality of first conductive strip columns spaced apart along the third direction Y. Each first conductive strip column includes at least two first conductive strips 221 spaced apart along the first direction Z, and adjacent two first conductive strips 221 in a first conductive strip column are insulated by an insulating layer 21. Two isolation groove subgroups of an isolation groove group are located on opposite sides of a first conductive strip column.

[0062] In some embodiments, a plurality of second conductive strips 222 are arranged in an array along a first direction Z, a second direction X, and a third direction Y, and may be divided into a plurality of second conductive strip groups arranged at intervals along the third direction Y. Each second conductive strip group includes two second conductive strip subgroups, and the two second conductive strip subgroups of each second conductive strip group are located on one side of a first conductive strip column along the third direction Y. Each second conductive strip subgroup includes a plurality of second conductive strip rows arranged at intervals along the first direction Z, and adjacent second conductive strip rows are insulated from each other by an insulating layer 21 along the first direction Z. Each second conductive strip row includes at least two second conductive strips 222 arranged at intervals along the second direction X and connected to an adjacent first conductive strip 221, and the at least two second conductive strips 222 of each second conductive strip row and at least two isolation grooves 233 of the isolation groove subgroup are alternately arranged along the second direction X.

[0063] S1012: Form an isolation structure, and fill the isolation groove with the isolation structure.

[0064] See Figure 10 and Figure 11 The above step S1012 is then performed. The isolation structure 16 can be formed using a thin-film deposition process such as chemical vapor deposition. In some embodiments, the isolation structure 16 may include an inorganic insulating material, which may include at least one of silicon dioxide, silicon nitride, and silicon oxynitride. In some embodiments, the material of the isolation structure 16 may be the same as the material of the insulating layer 21, so that the formation processes of the isolation structure 16 and the insulating layer 21 can be the same, thereby simplifying the manufacturing process of the semiconductor device 100. In one example, both the isolation structure 16 and the insulating layer 21 include silicon dioxide.

[0065] Each isolation structure 16 extends along a first direction Z and a third direction Y, and multiple isolation structures 16 are spaced apart along a second direction X and a third direction Y. Each isolation structure 16 is used to isolate adjacent second word line portions 122 structures and adjacent capacitor structures 14 subsequently formed along the second direction X. The isolation structures 16 cooperate with the insulating layer 21 to insulate the multiple memory cells arranged along the first direction Z, the second direction X, and the third direction Y from each other.

[0066] S102: A first through opening is formed, which penetrates the conductive layer and the insulating layer along a first direction.

[0067] See Figure 12 and Figure 13 Perform the above step S102. The first through-hole opening 231 can be formed by etching.

[0068] In some embodiments, forming the first through opening 231 may include removing a portion of the second conductive strip 222 and a portion of the insulating layer 21 to form the first through opening 231. Thus, the first through opening 231 penetrates the second conductive strip 222 and a portion of the insulating layer 21, providing conditions for subsequently removing the second conductive strip 222 through the first through opening 231 to form a accommodating space for the transistor.

[0069] In some embodiments, a plurality of first through openings 231 may be arranged at intervals along a second direction X and a third direction Y, and are divided into a plurality of first through opening groups arranged at intervals along the third direction Y. A first through opening group includes two first through opening subgroups located on opposite sides of a first conductive strip row along the third direction Y. Each first through opening subgroup includes at least two first through openings 231 arranged at intervals along the second direction X. Each first through opening 231 may penetrate along a first direction Z at least two second conductive strips 222 arranged at intervals along the first direction Z and the insulating layer 21 between adjacent second conductive strips 222. Each first through opening 231 also extends into the substrate 17.

[0070] In some embodiments, the shape of the cross-section of each first through opening 231 parallel to the second direction X and the third direction Y may include at least one of a circle and a rectangle. In some embodiments, the shape of the cross-section of each first through opening 231 along the first direction Z may include at least one of a rectangle and an inverted trapezoid.

[0071] S103: A portion of the conductive layer is removed through the first through-hole to form a first lateral groove, and the remaining conductive layer extending along the second direction forms a first letter line portion, wherein the first direction intersects the second direction.

[0072] In the manufacturing method of the semiconductor device 100 according to the embodiments of this application, the first word line portion 121 is formed by utilizing the conductive layer 22 including polysilicon in the stacked structure 20, thereby eliminating the need for additional process steps of forming grooves and forming word lines 12 in the grooves, thus simplifying the manufacturing process of the semiconductor device 100. Furthermore, the processes for forming the insulating layer 21 and the conductive layer 22 including polysilicon are mature, further simplifying the manufacturing process of the stacked structure 20.

[0073] See Figure 14 and Figure 15Then, the above step S103 is performed. In this step, the conductive layer 22 around the first through opening 231 is selectively removed by an etching process to form a first lateral groove 232. The first lateral groove 232 is located between adjacent insulating layers 21, communicates with the first through opening 231, and is disposed around the first through opening 231. The first letter line portion 121 is adjacent to the first lateral groove 232.

[0074] In some embodiments, see Figure 14 and Figure 15 Forming the first lateral groove 232 may include: removing a portion of the first conductive strip 221 and a portion of the second conductive strip 222 around the first through opening 231 and exposing the isolation structure 16 to form the first lateral groove 232. At this time, the first lateral groove 232 extends from between adjacent isolation structures 16 in the second direction X to a region outside the adjacent isolation structures 16 in the second direction X, thereby increasing the volume of the first lateral groove 232, increasing the area of ​​the second letter portion 122 subsequently formed in the first lateral groove 232, and increasing the volume of a portion of the channel structure 11. Furthermore, the remaining first conductive strip 221 forms the first letter portion 121, which extends along the second direction X and is located on one side of the isolation structure 16 along the third direction Y.

[0075] In some embodiments, forming the first lateral groove 232 may also include: removing a portion of the second conductive strip 222 around the first through opening 231 through the first through opening 231 to form the first lateral groove 232. In this case, a first lateral groove 232 is also located between adjacent isolation structures 16 in the second direction X. Furthermore, the remaining first conductive strip 221 and the remaining second conductive strip 222 between the first lateral groove 232 and the first conductive strip 221 form a first word line portion 121. In this case, the first word line portion 121 includes a word line body portion and a word line extension portion. The word line body portion extends along the second direction X, and the word line extension portion is connected to the word line body portion and located between adjacent isolation structures 16.

[0076] In some embodiments, please refer to Figures 16 to 18 The manufacturing method of the semiconductor device 100 further includes step S104, which involves sequentially forming a second initial word line portion 241 and a gate oxide layer 13 on the wall of the first lateral trench 232, wherein the second initial word line portion 241 is connected to the first word line portion 121. Figure 16 The structure shown is Figure 15 The cross-sections of the structures shown are identical.

[0077] In some embodiments, please refer to Figures 16 to 18Forming a second initial character line portion 241 on the groove wall of the first lateral groove 232 may include: forming an initial character line layer 24, the initial character line layer 24 being located on the groove walls of the plurality of first lateral grooves 232 and the side wall of the first through opening 231; and removing the initial character line layer 24 on the side wall of the first through opening 231, the remaining initial character line layer 24 being located on the groove walls of the plurality of first lateral grooves 232 and respectively constituting a plurality of second initial character line portions 241.

[0078] The initial word line layer 24 can be formed by the thin film deposition process described above. In some embodiments, the initial word line layer 24 may include at least one of a metal and a metal nitride. In one example, the material of the initial word line layer 24 may include tungsten.

[0079] In some embodiments, please refer to Figures 17 to 18 The gate oxide layer 13 covers the second initial word line portion 241 in the first lateral groove 232 and the sidewall of the first through opening 231.

[0080] The gate oxide layer 13 is used to isolate the second word line portion 122 formed via the second initial word line portion 241 from the subsequently formed channel structure 11. The gate oxide layer 13 can be formed by the thin film deposition process described above. In some embodiments, the gate oxide layer 13 may include an inorganic insulating material, including but not limited to at least one of silicon oxide, silicon nitride, and silicon oxynitride. In some embodiments, the material of the gate oxide layer 13 may be the same as the material of the insulating layer 21, so that the gate oxide layer 13 and the insulating layer 21 can be formed using the same material and process, simplifying the manufacturing process of the semiconductor device 100.

[0081] In some embodiments, please refer to Figure 19 and Figure 20 The method of manufacturing semiconductor device 100 further includes step S105, namely forming a sacrificial structure 25, wherein the sacrificial structure 25 fills the remaining first through opening 231 and the remaining first lateral groove 232.

[0082] The sacrificial structure 25 can be formed by the thin film deposition process described above. During the formation of the capacitor structure 14, the sacrificial structure 25 protects the gate oxide layer 13 and the second initial word line portion 241. In some embodiments, the sacrificial structure 25 may include, but is not limited to, at least one of silicon nitride, silicon germanium, and polysilicon.

[0083] In some embodiments, the method for manufacturing the semiconductor device 100 further includes steps S106 to S108.

[0084] Please see Figure 21 and Figure 22Step S106 is executed, that is, a second through opening 234 is formed. The second through opening 234 extends along the second direction X and penetrates the stacked structure 20 and multiple isolation structures 16 along the first direction Z. The second through opening 234 is located on the side of the sacrificial structure 25 away from the first word line portion 121. A portion of the conductive layer 22 is also located between the second through opening 234 and the sacrificial structure 25.

[0085] In this process, the insulating layer 21, the isolation structure 16, and the second conductive strip 222 are formed by etching to create a second through opening 234. In some embodiments, a plurality of second through openings 234 are arranged at intervals along a third direction Y, and each second through opening 234 is located between adjacent sacrificial structures 25 and is spaced apart from the adjacent sacrificial structures 25.

[0086] In some embodiments, please refer to Figure 23 and Figure 24 In step S107, a portion of the conductive layer 22 is removed through the second through opening 234 to form a plurality of second lateral grooves 235, which expose the second initial word line portion 241.

[0087] Multiple second lateral slots 235 communicate with the second through opening 234 and are arranged along the first direction Z, the second direction X, and the third direction Y, and are divided into multiple groups of second lateral slots spaced apart along the third direction Y. Each group of second lateral slots includes two subgroups of second lateral slots, which are adjacent to and located on the opposite side of a second through opening 234 along the third direction Y. Each group of second lateral slots includes multiple second lateral slots 235 arranged in an array spaced apart along the first direction Z and the second direction X. Each second lateral slot 235 extends along the third direction Y.

[0088] In some embodiments, please refer to Figure 25 and Figure 26 In step S108, a portion of the second initial word line portion 241 and the gate oxide layer 13 are removed through the second lateral groove 235, exposing the sacrificial structure 25, and the remaining second initial word line portion 241 constitutes the second word line portion 122.

[0089] In some embodiments of this application, through steps S106 to S108 described above, a second through opening 234 is first formed; then, a portion of the second conductive layer 22 is removed using the second through opening 234 to form a plurality of second lateral trenches 235; finally, a portion of the second initial word line portion 241 and the gate oxide layer 13 are removed using the second lateral trenches 235, and the remaining second initial word line portion 241 forms a second word line portion 122, exposing the sacrificial structure 25. This facilitates contact between the capacitor structure subsequently formed in the second lateral trenches 235 and the sacrificial structure 25. After removing the sacrificial structure 25 and forming a channel structure 11 at the location of the sacrificial structure 25, the channel structure 11 can be connected to the capacitor structure 14.

[0090] In some embodiments, the end of the second word line portion 122 near the second lateral groove 235 is recessed inward toward the first through opening 231 relative to the sacrificial structure 25 to reduce the risk of a short circuit between the second word line portion 122 and the second capacitor electrode 143 subsequently formed in the second lateral groove 235.

[0091] In some embodiments, please refer to Figure 27 and Figure 28 The method of manufacturing semiconductor device 100 further includes step S109, namely forming an isolation layer 26, the isolation layer 26 at least covering the end face of the second word line portion 122 near the second lateral groove 235.

[0092] In some embodiments, forming the isolation layer 26 includes: forming an isolation film that at least covers the second word line portion 122 and the gate oxide layer 13; and removing a portion of the isolation film and a portion of the gate oxide layer 13 through the second through opening 234 and the second lateral groove 235 until the sacrificial structure 25 is exposed, with the remaining isolation film constituting the isolation layer 26 covering the end face of the second word line portion 122 near the second lateral groove 235.

[0093] The insulating layer 26 serves to isolate the second word line portion 122 from the subsequently formed capacitor structure 14. In some embodiments, the insulating film may be located on the trench walls of the second lateral trench 235 and the trench walls of the second through opening 234, and cover the second word line portion 122 and the exposed gate oxide layer 13. The insulating layer 26 may include an inorganic insulating material. In some embodiments, the material of the insulating layer 26 may be the same as the material of the insulating layer 21 and the gate oxide layer 13. In one example, the insulating layer 26 may include silicon oxide.

[0094] In some embodiments of this application, through step S109, an isolation film covering the second word line portion 122 and the gate oxide layer 13 is first formed. Then, the isolation layer 26 and the gate oxide layer 13 in the second lateral trench are pushed back to expose the sacrificial structure 25. The remaining isolation film covers the end face of the second word line portion 122 near the second lateral trench 235, so that the isolation layer 26 isolates the second word line portion 122 from the subsequently formed second capacitor electrode 143. It also facilitates the contact between the second capacitor electrode 143 and the sacrificial structure 25 so that the channel structure 11 that replaces the sacrificial structure 25 can be connected to the second capacitor electrode 143. Furthermore, the isolation layer 26 is formed through one deposition and one pushback process, which not only ensures the reliability of the isolation layer 26 in isolating the capacitor structure 14 and the second word line portion 122, but also simplifies the manufacturing process of the semiconductor device 100.

[0095] In some embodiments, the method of manufacturing the semiconductor device 100 further includes step S110, which involves forming a capacitor structure located in the remaining second lateral slot and the remaining second through opening and in contact with the sacrificial structure.

[0096] In some embodiments, please refer to Figures 1 to 4 The capacitor structure 14 includes a second capacitor electrode 143, a dielectric layer 142, and a first capacitor electrode 141. The second capacitor electrode 143 is located on the wall of the second lateral groove 235 and is in contact with the sacrificial structure 25. The dielectric layer 142 covers the second capacitor electrode 143 and the wall of the second through opening 234. The first capacitor electrode 141 at least fills the remaining second lateral groove 235.

[0097] The second capacitor electrode 143 can be formed by a thin film deposition process. Multiple second capacitor electrodes 143 are respectively located in multiple second lateral trenches 235.

[0098] In some embodiments, the first capacitor electrode 141 fills the remaining second lateral groove 235 and is located in the remaining second through opening 234. The first capacitor electrode 141 includes an electrode body portion 1411 and an electrode extension portion 1412 extending from the electrode body portion 1411. The electrode body portion 1411 extends along a first direction Z and is located in the second through opening 234. The electrode extension portion 1412 is connected to the electrode body portion 1411 and is located in the second lateral groove 235.

[0099] In some embodiments, please refer to Figure 1 and Figure 3 The manufacturing method of semiconductor device 100 further includes steps S111 to S112.

[0100] Please see Figures 1 to 4Then, step S111 is performed, which involves removing the sacrificial structure 25. The sacrificial structure 25 can be removed by an etching process to form the remaining first through opening 231 and the remaining first lateral groove 232.

[0101] Please see Figures 1 to 4 Step S112 is executed, that is, a channel structure 11 is formed in the remaining first through opening 231 and the remaining first lateral groove 232. The channel structure 11 includes a first channel portion 111 and a second channel portion 112. The first channel portion 111 extends along the first direction Z and is located in the first through opening 231. The second channel portion 112 is disposed around the first channel portion 111 in the remaining first lateral groove 232 and is connected to the first channel portion 111 and the capacitor structure 14.

[0102] In some embodiments of this application, after forming the capacitor structure 14 in the second through opening 234 and the second lateral groove 235 through the above steps S111 to S112, the sacrificial structure 25 is removed, and a channel structure 11 is formed in the space where the sacrificial structure 25 is formed, which simplifies the connection process between the channel structure 11 and the second capacitor electrode 143, thereby simplifying the manufacturing process of the semiconductor device 100.

[0103] Please see Figures 1 to 4 In step S113, a bit line 15 is formed in the remaining first through opening 231. The bit line 15 extends along the first direction Z. The first channel portion 111 is disposed around the bit line 15 and connected to the bit line 15.

[0104] Please see Figure 29 Based on the same inventive concept, this application also provides a storage system 300, which may include the semiconductor device 100 and controller 200 of any of the above embodiments. The controller 200 is connected to the semiconductor device 100 and is used to control the semiconductor device 100 to store data.

[0105] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified. In the above embodiments, the descriptions of each embodiment have different emphases; parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. The embodiments, implementation methods, and related technical features of this application can be combined and substituted with each other without conflict. The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A semiconductor device, characterized in that, include: The channel structure includes a first channel portion and a second channel portion that are interconnected; the first channel portion extends along a first direction, and the second channel portion is disposed around the first channel portion. The character line includes a first character line portion and a second character line portion that are connected to each other; the first character line portion extends along a second direction, the material of the first character line portion includes polycrystalline silicon, and at least a portion of the second character line portion is located between the first character line portion and the second channel portion, the second direction intersecting the first direction; A capacitor structure is connected to the second channel portion, and the capacitor structure and the word line are located on different sides of the channel structure.

2. The semiconductor device according to claim 1, characterized in that, At least two adjacent second character lines arranged along a third direction are connected to a first character line, wherein the third direction intersects with the first direction and the second direction.

3. The semiconductor device according to claim 1, characterized in that, The first character line portion includes at least one first arcuate side surface, which is recessed into the interior of the first character line portion and contacts the second character line portion.

4. The semiconductor device according to claim 3, characterized in that, The second letter portion includes a second arc-shaped side surface, which is located between the first arc-shaped side surface and the second channel portion, and the first arc-shaped side surface is disposed around the second arc-shaped side surface and contacts the second arc-shaped side surface.

5. The semiconductor device according to claim 4, characterized in that, The semiconductor device further includes a plurality of isolation structures, which are located at least between adjacent capacitor structures and adjacent second word lines along the second direction.

6. The semiconductor device according to claim 5, characterized in that, The second character line portion also includes a first side surface and a second side surface, wherein the second side surface is connected between the second arc-shaped side surface and the first side surface; The first side is located between the adjacent isolation structures in the second direction, and the second side is located on one side of the isolation structure along the third direction, which intersects with the first direction and the second direction.

7. The semiconductor device according to claim 1, characterized in that, At least a portion of the material of the second letter line is different from the material of the first letter line.

8. The semiconductor device according to claim 1, characterized in that, The second channel section includes a channel top surface, a channel bottom surface, a channel connecting side surface, and a channel non-connecting side surface; The top surface and bottom surface of the channel are disposed opposite to each other along the first direction and connected to the first channel portion. The channel connecting side and the channel non-connecting side are connected between the top surface and the bottom surface of the channel, and the channel connecting side is in contact with the capacitor structure. The second letter line portion surrounds the non-connecting side of the channel, the top surface of the channel, and the bottom surface of the channel, and a gate oxide layer is disposed between the second letter line portion and the second channel portion.

9. The semiconductor device according to claim 8, characterized in that, The semiconductor device further includes a plurality of isolation structures, wherein the channel connection side is located between adjacent isolation structures in the second direction, and at least a portion of the channel non-connection side protrudes from the end face of the isolation structure in the third direction upward.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that, The semiconductor device further includes a bit line extending along the first direction; a first channel portion is disposed around and connected to a corresponding bit line.

11. A method for manufacturing a semiconductor device, characterized in that, include: A stacked structure is formed, the stacked structure comprising a conductive layer and an insulating layer stacked along a first direction, wherein the material of the conductive layer includes polycrystalline silicon; A first through-hole is formed, which penetrates the conductive layer and the insulating layer along the first direction; A portion of the conductive layer is removed through the first through-hole to form a first lateral groove, and the remaining conductive layer extending along the second direction forms a first letter line portion, wherein the first direction intersects the second direction.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that, After forming the laminated structure and before forming the first through opening, the method further includes: An isolation structure is formed, which extends along a third direction and penetrates the conductive layer and the insulating layer along the first direction, wherein the third direction intersects the first direction and the second direction.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that, The method further includes: A second initial word line portion and a gate oxide layer are sequentially formed on the groove wall of the first lateral groove; A sacrificial structure is formed, which fills the remaining first through opening and the remaining first lateral groove.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that, After forming the sacrificial structure, the method further includes: A second through opening is formed, which extends along a second direction and penetrates the stacked structure and the isolation structure along the first direction. The second through opening is located on the side of the sacrificial structure away from the first letter portion. A portion of the conductive layer is removed through the second through opening to form a second lateral groove, which exposes the second initial word line portion; The second initial word line portion and the gate oxide layer are removed by the second lateral groove, exposing the sacrificial layer, and the remaining second initial word line portion constitutes the second word line portion.

15. The method for manufacturing a semiconductor device according to claim 14, characterized in that, The method further includes: An isolation layer is formed, the isolation layer at least covering the end face of the second letter portion near the second lateral groove; A capacitor structure is formed, which is located in the second lateral groove and the second through opening and is in contact with the sacrificial structure.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that, The method further includes: Remove the sacrificial structure; A channel structure is formed in the remaining first through opening and the remaining first lateral groove. The channel structure includes a first channel portion and a second channel portion. The first channel portion extends along a first direction, and the second channel portion is disposed around the first channel portion and connected to the first channel portion and the capacitor structure. A bit line is formed, the bit line extending along the first direction and the first channel portion being disposed around the bit line.

17. A storage system, characterized in that, include: The semiconductor device as described in any one of claims 1 to 10; as well as A controller, connected to the semiconductor device, is used to control the semiconductor device to store data.

Images