Memory device and method of manufacturing memory device

Abstract

This application relates to a memory device and a method of manufacturing a memory device. A method of manufacturing a memory device includes the steps of: forming a channel opening extending through a laminate in a first direction; forming a first data storage pattern spaced apart from a second data storage pattern in a second direction perpendicular to the first direction within the channel opening; forming a channel layer inside the first data storage pattern and the second data storage pattern; forming a first barrier pattern spaced apart from a second barrier pattern in a second direction within the channel layer; and forming the first channel pattern spaced apart from the second channel pattern in a second direction by removing a section of the channel layer between the first barrier pattern and the second barrier pattern.

Description

Technical Field

[0001] This disclosure relates to memory devices and methods of manufacturing memory devices, including but not limited to a memory device comprising a memory block having a three-dimensional structure and a method of manufacturing the memory block. Background Technology

[0002] Memory devices may include non-volatile memory devices that retain stored data even during power interruptions. Depending on the arrangement of the memory cells, non-volatile memory devices can have a two-dimensional or three-dimensional structure. In a two-dimensional structure, the memory cells of a non-volatile memory device are arranged in a single layer on a substrate. In a three-dimensional structure, the memory cells are vertically stacked on the substrate. Because the integration density of non-volatile memory devices with a three-dimensional structure is higher than that of non-volatile memory devices with a two-dimensional structure, the use of non-volatile memory devices with a three-dimensional structure has recently increased in electronic devices. Summary of the Invention

[0003] According to an embodiment, a method of manufacturing a memory device may include the following steps: forming a channel opening extending through a laminate in a first direction; forming a first data storage pattern spaced apart from a second data storage pattern in a second direction perpendicular to the first direction in the channel opening; forming a channel layer inside the first data storage pattern and the second data storage pattern; forming a first barrier pattern spaced apart from a second barrier pattern in a second direction inside the channel layer; and forming the first channel pattern spaced apart from the second channel pattern in a second direction by removing a segment of the channel layer between the first barrier pattern and the second barrier pattern.

[0004] According to an embodiment, a memory device may include a stack comprising a cell plug disposed in a channel opening extending through the stack in a first direction, a first data storage pattern spaced apart from a second data storage pattern in a second direction perpendicular to the first direction within the cell plug, a first channel pattern spaced apart from the second channel pattern in the second direction within the cell plug, and a first tunneling pattern located between the first data storage pattern and the first channel pattern and a second tunneling pattern located between the second data storage pattern and the second channel pattern within the cell plug; wherein an end of the first data storage pattern extends beyond a corresponding end of the first channel pattern in the second direction, and an end of the first data storage pattern does not extend beyond a corresponding end of the first tunneling pattern in the second direction.

[0005] According to an embodiment, a memory device may include a stack comprising a cell plug disposed in a channel opening extending through the stack in a first direction, a first data storage pattern spaced apart from a second data storage pattern in a second direction perpendicular to the first direction within the cell plug, a first channel pattern spaced apart from the second channel pattern in the second direction within the cell plug, and a tunneling layer extending within the cell plug between the first data storage pattern and the first channel pattern and between the second data storage pattern and the second channel pattern; wherein the tunneling layer includes a first angled region located at an end of the first data storage pattern and a second angled region located at an end of the second data storage pattern. Attached Figure Description

[0006] Figure 1 This is a diagram illustrating a memory device according to an embodiment of the present disclosure;

[0007] Figure 2 This is a diagram illustrating a memory device according to an embodiment of the present disclosure;

[0008] Figure 3 This is a circuit diagram illustrating the connection configuration of a memory block according to an embodiment of the present disclosure;

[0009] Figure 4A and Figure 4B This is a diagram illustrating the structure of a memory device according to an embodiment of the present disclosure;

[0010] Figure 5 This is a plan view showing the structure of a memory device according to an embodiment of the present disclosure;

[0011] Figures 6A to 6H This is a diagram illustrating a memory device formed using a method for manufacturing a memory device according to an embodiment of the present disclosure;

[0012] Figure 7 This is a plan view showing the structure of a memory device according to an embodiment of the present disclosure;

[0013] Figures 8A to 8H This is a diagram illustrating a memory device formed using a method for manufacturing a memory device according to an embodiment of the present disclosure;

[0014] Figures 9A to 9E This is a diagram illustrating a memory device formed using a method for manufacturing a memory device according to an embodiment of the present disclosure;

[0015] Figure 10 This is a diagram illustrating a memory card system according to an embodiment of the present disclosure; and

[0016] Figure 11This is a diagram illustrating a solid-state drive (SSD) system including a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0017] Embodiments of this disclosure are described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples to illustrate the concepts disclosed in this application. Examples or embodiments based on these concepts can be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0018] Terms such as “vertical,” “top,” “above,” “overlapping,” “upper,” “side,” “lower,” “higher,” “column,” “row,” “height,” and other terms that suggest relative spatial relationships or orientations are used for ease of description or reference to the accompanying drawings only and are not intended to be limiting.

[0019] Crosshairs running through the accompanying drawings indicate corresponding or similar areas between figures, rather than indicating the material associated with those areas. The drawings are not necessarily drawn to scale, and some structures are not shown in their full form between cross-sectional views and corresponding plan views.

[0020] When one element is marked as “connected” to another element, these elements can be directly connected or connected through at least one intermediate element between the elements. When two elements are marked as “directly connected”, one element is directly connected to the other element, and there is no intermediate element between the two elements.

[0021] Terms such as "first" and "second" are used to distinguish between various components and do not imply the size, order, priority, number, or importance of the components. For example, in one example, the first component may be referred to as the second component, while in another example, the second component may be referred to as the first component.

[0022] To improve the integration of non-volatile memory devices with a three-dimensional structure, the memory device according to an embodiment includes two or more cell strings formed in a single channel opening.

[0023] Figure 1 This is a diagram illustrating a memory device 100 according to an embodiment of the present disclosure.

[0024] Reference Figure 1 The memory device 100 includes a memory cell array 110, peripheral circuitry 170, and control circuitry 180.

[0025] The memory cell array 110 may include first memory blocks BLK1 to i-th memory blocks BLKi, where i is an integer greater than 1. Each of the first memory blocks BLK1 to i-th memory blocks BLKi includes a memory cell for storing data. Drain select line DSL, word line WL, source select line SSL, and source line SL are connected to each of the memory blocks BLK1 to BLKi. Bit line BL is collectively connected to memory blocks BLK1 to BLKi.

[0026] Memory blocks BLK1 to BLKi have a three-dimensional structure. A memory block with a three-dimensional structure comprises memory cells vertically stacked on a substrate. The memory cells can be arranged in various ways within memory blocks BLK1 to BLKi. For example, two or more cell strings can be arranged in a single channel opening extending through the stack. When two or more cell strings are arranged in a single channel opening, the integration density of the memory cells increases compared to when a single cell string is arranged in a single channel opening.

[0027] Depending on how the memory cells are programmed, they can store one, two, or more bits of data. For example, a single memory cell storing one bit of data is called a single-level cell, a single memory cell storing two bits of data is called a multi-level cell, a single memory cell storing three bits of data is called a three-level cell, and a single memory cell storing four bits of data is called a four-level cell. Five or more bits of data can be stored in a single memory cell.

[0028] Peripheral circuitry 170 performs programming operations to store data in memory cell array 110, reading operations to output data stored in memory cell array 110, and erasing operations to erase data stored in memory cell array 110. For example, peripheral circuitry 170 includes voltage generator 120, row decoder 130, page buffer group 140, column decoder 150, and input / output circuitry 160.

[0029] Voltage generator 120 generates various operating voltages Vop used during programming, reading, or erasing operations in response to opcode OPCD. For example, voltage generator 120 generates programming voltage, turn-on voltage, turn-off voltage, negative voltage, pre-charge voltage, verification voltage, read voltage, pass voltage, and erase voltage in response to opcode OPCD. The operating voltage Vop generated by voltage generator 120 is applied to the drain select line DSL, word line WL, source select line SSL, and source line SL of the memory block selected via line decoder 130.

[0030] The programming voltage is applied to the selected word line WL during programming operations and is used to increase the threshold voltage of the memory cell connected to the selected word line. The turn-on voltage is applied to the drain select line DSL and the source select line SSL, and turns on the drain select transistor and the source select transistor. The turn-off voltage is applied to the drain select line DSL and the source select line SSL, and turns off the drain select transistor and the source select transistor. For example, the turn-off voltage can be 0V. The precharge voltage is higher than 0V and is applied to the bit line during read operations. The verification voltage is used during verification operations to determine when the threshold voltage of the selected memory cell reaches a target level. The verification voltage is at various levels depending on the target level and is applied to the selected word line.

[0031] A read voltage is applied to the selected word line during a read operation on the selected memory cell. For example, the read voltage is at various levels depending on how the selected memory cell is programmed. An unselected word line in the word line WL can be applied during a programming or read operation and is used to turn on memory cells connected to the unselected word line. An erase voltage is applied to the source line SL during an erase operation to erase memory cells included in the selected memory block.

[0032] The row decoder 130 transmits the operating voltage Vop to the drain select line DSL, word line WL, source select line SSL, and source line SL, which are connected to the selected memory blocks, based on the row address RADD. For example, the row decoder 130 is connected to the voltage generator 120 via a global line and is connected to memory blocks BLK1 to BLKi using the drain select line DSL, word line WL, source select line SSL, and source line SL.

[0033] Page buffer group 140 includes page buffers (not shown) respectively connected to the first memory block BLK1 through the i-th memory block BLKi. Each page buffer is connected to one of the memory blocks BLK1 through BLKi via bit line BL. During a read operation, the page buffer senses the current or voltage on the bit line that varies according to the threshold voltage of the selected memory cell in response to the page buffer control signal PBSIG, and temporarily stores the sensed data.

[0034] The column decoder 150 transmits data between the page buffer group 140 and the input / output circuitry 160 in response to the column address CADD. For example, the column decoder 150 is connected to the page buffer group 140 via the column line CL and transmits an enable signal via the column line CL. The page buffers included in the page buffer group 140 receive or output data via the data line DL in response to the enable signal.

[0035] Input / output circuitry 160 receives or outputs commands (CMD), addresses (ADD), or data via input / output lines (I / O). For example, input / output circuitry 160 transmits commands (CMD) and addresses (ADD) received from an external controller to control circuitry 180 via input / output lines (I / O), and transmits data received from an external controller to page buffer group 140 via input / output lines (I / O). Alternatively, input / output circuitry 160 outputs data received from page buffer group 140 to an external controller via input / output lines (I / O).

[0036] In response to the command CMD and address ADD, the control circuit 180 outputs at least one of the following: opcode OPCD, row address RADD, page buffer control signal PBSIG, and column address CADD. For example, when the command CMD input to the control circuit 180 corresponds to a programming operation, the control circuit 180 controls the peripheral circuit 170 to perform a programming operation on the memory block selected by the address ADD. When the command CMD input to the control circuit 180 corresponds to a read operation, the control circuit 180 controls the peripheral circuit 170 to perform a read operation on the memory block selected by the address ADD and outputs the read data. When the command CMD input to the control circuit 180 corresponds to an erase operation, the control circuit 180 controls the peripheral circuit 170 to perform an erase operation on the selected memory block.

[0037] Figure 2 This is a diagram illustrating a memory device 100 according to an embodiment of the present disclosure.

[0038] Reference Figure 2 The memory device 100 includes a peripheral circuit structure PC disposed on a substrate SUB and first memory blocks BLK1 to BLKi. Memory blocks BLK1 to BLKi are disposed above the peripheral circuit structure PC.

[0039] The substrate SUB can be a single-crystal semiconductor layer. For example, the substrate SUB can be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin layer formed by selective epitaxial growth.

[0040] The peripheral circuit structure PC includes a row decoder 130, a column decoder 150, a page buffer group 140, and control circuitry 180, which includes circuitry for controlling the operation of memory blocks BLK1 to BLKi. For example, the peripheral circuit structure PC may include NMOS transistors, PMOS transistors, resistors, and capacitors electrically connected to the first memory block BLK1 to the i-th memory block BLKi. The peripheral circuit structure PC may be arranged between the substrate SUB and the memory blocks BLK1 to BLKi.

[0041] Each of the memory blocks BLK1 to BLKi includes a source structure, bit lines, a string of cells electrically connected to the source structure and bit lines, word lines electrically connected to the string of cells, and select lines electrically connected to the string of cells. Each string of cells includes memory cells connected in series and select transistors. Each select line is the gate electrode of the corresponding select transistor, and each word line is the gate electrode of the corresponding memory cell.

[0042] In the implementation, the substrate SUB, the peripheral circuit structure PC, and the memory blocks BLK1 to BLKi are arranged in accordance with... Figure 2 The order of stacking can vary. For example, the peripheral circuitry PC can be arranged on top of memory blocks BLK1 to BLKi.

[0043] In an alternative embodiment, the peripheral circuit structure PC is arranged on a region of the substrate SUB that does not overlap with the memory blocks BLK1 to BLKi. For example, the peripheral circuit structure PC and the memory blocks BLK1 to BLKi may be located in different regions of the substrate SUB that do not overlap perpendicularly with each other.

[0044] Figure 3 This is a circuit diagram illustrating the connection configuration of a memory block according to an embodiment of the present disclosure.

[0045] Figure 3 This is a diagram illustrating, for example, the configuration included in the first storage block BLK1. Figure 3 This illustrates at least some configurations included in the first storage block BLK1. The second storage block BLK2 through the i-th storage block BLKi include configurations related to... Figure 3 The configuration of the first storage block BLK1 shown is similar.

[0046] Reference Figure 3 The first memory block BLK1 includes a string of cells ST connecting the source line SL and the first bit line BL1 to the nth bit line BLn. Because the bit lines BL1 to BLn extend in the Y direction and are spaced apart in the X direction, the string of cells ST is spaced apart in both the X and Y directions. For example, the string of cells ST is connected between the first bit line BL1 and the source line SL, and the string of cells ST is arranged between the second bit line BL2 and the source line SL. Similarly, the string of cells ST is arranged between the nth bit line BLn and the source line SL. The string of cells ST extends in the Z direction.

[0047] As an example, one of the cell strings ST connected to the nth bit line BLn is described. The cell string ST includes a source selection transistor SST, first memory cells MC1 to jth memory cells MCj, and a drain selection transistor DST, where j is an integer greater than 1. Figure 3As shown, the structure of the memory block is described based on the first memory block BLK1. The number of source selection transistors SST, memory cells MC1 to MCj, and drain selection transistors DST included in the cell string ST varies depending on the memory device.

[0048] The gates of the source select transistors (SST) in different cell strings are connected to either the first source select line SSL1 or the second source select line SSL2. The gates of memory cells MC1 to MCj are connected to word lines WL1 to WLj, respectively. The gates of each drain select transistor (DST) are connected to one of the first drain select lines DSL1 to the fourth drain select line DSL4.

[0049] Describe the lines connected to the first memory block BLK1. Source select transistors (SSTs) arranged in the X direction are connected to the same source select line, and source select transistors (SSTs) arranged in the Y direction are connected to separate source select lines. For example, the first set of source select transistors (SSTs) arranged in the Y direction is connected to the first source select line SSL1, and the second set of select transistors (SSTs) is connected to the second source select line SSL2. The second source select line SSL2 is separate from the first source select line SSL1. Therefore, the voltage applied to the first source select line SSL1 is either the same voltage as the voltage applied to the second source select line SSL2, or a different voltage.

[0050] Among memory cells MC1 to MCj, memory cells formed in the same layer are connected to the same word line. For example, the first memory cell MC1, which is included in different cell strings ST, is connected to the first word line WL1, and the j-th memory cell MCj, which is included in different cell strings ST, is connected to the j-th word line WLj. A group of memory cells included in different cell strings ST and connected to the same word line is a page PG. Programming operations and read operations can be performed based on the page PG.

[0051] The drain selection transistor DST, located in the Y direction, is connected to separate drain selection lines DSL1 to DSL4. The drain selection transistor DST, located in the X direction, is connected to the same drain selection line, while the drain selection transistor DST, located in the Y direction, is connected to separate drain selection lines DSL1 to DSL4. Because the drain selection lines DSL1 to DSL4 are isolated from each other, different voltages can be applied to the drain selection lines DSL1 to DSL4.

[0052] According to this disclosure, two or more cell strings ST can be disposed in respective channel openings extending through the stack. The structure and manufacturing method of a memory device in which two cell strings ST are located in one channel opening are described.

[0053] Figure 4A and Figure 4BThis is a diagram showing the structure of a memory device 100 according to an embodiment of the present disclosure.

[0054] Figure 4A This is a plan view of the memory device 100 according to the present disclosure. For example, Figure 4A It is a plan view of one of the storage blocks BLK1 to BLKi.

[0055] Reference Figure 4A The channel openings (CHO) are arranged in both the X and Y directions. For example, the channel openings (CHO) are aligned in the X direction. The channel openings (CHO) are arranged in an offset or staggered configuration in the Y direction.

[0056] The channel openings CHO have an elliptical planar shape. The plane of each channel opening CHO has a minor axis in the X direction and a major axis in the Y direction.

[0057] Each element plug CPL is formed in a corresponding channel opening CHO. The element plug CPL can fill the interior of the channel opening CHO. Each element plug CPL has an elliptical cross-section. The element plug CPLs are arranged in the X and Y directions.

[0058] Each cell plug CPL includes a first data storage pattern CT1, a second data storage pattern CT2, a first channel pattern CH1, and a second channel pattern CH2. Each cell plug CPL includes a first data storage pattern CT1 separate from the second data storage pattern CT2 and a first channel pattern CH1 separate from the second channel pattern CH2. The first data storage pattern CT1 is spaced apart from the second data storage pattern CT2 in the Y direction. The first channel pattern CH1 is spaced apart from the second channel pattern CH2 in the Y direction.

[0059] The first data storage pattern CT1 and the first channel pattern CH1 form the first cell string ST, and the second data storage pattern CT2 and the second channel pattern CH2 form the second cell string ST. For example... Figure 4A As shown in the example, one cell plug CPL corresponds to two cell strings ST.

[0060] Figure 4B Is with Figure 4A The cross-sectional view corresponding to line A-A'. Figure 4B No relative Figure 4A Draw to scale. (Refer to...) Figure 4B The stacked structure STK includes a conductive layer CD and an interlayer insulating layer IIL. The conductive layer CD is alternately stacked with the interlayer insulating layer IIL in the Z direction. The conductive layer CD may include at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), or polycrystalline silicon (poly-Si). The conductive layer CD corresponds to materials such as... Figure 3The gate lines are the drain select line (DSL), word line (WL), and source select line (SSL). The interlayer insulating layer (IIL) may include an oxide layer such as a silicon oxide layer.

[0061] The channel opening CHO extends through the laminate STK. The channel opening CHO extends through the conductive layer CD and the interlayer insulating layer IIL. The channel opening CHO extends in the Z direction. The cell plug CPL is formed in the channel opening CHO.

[0062] Each unit plug CPL includes a barrier layer BX, storage patterns CT1 and CT2, a first tunneling pattern TX1 and a second tunneling pattern TX2, channel patterns CH1 and CH2, and a core post CO. The barrier layer BX is in contact with or adjacent to the side surface of the laminate STK. The data storage patterns CT1 and CT2 are spaced apart in the Y direction. The first tunneling pattern TX1 is spaced apart from the second tunneling pattern TX2 in the Y direction. The first channel pattern CH1 is spaced apart from the second channel pattern CH2 in the Y direction. The core post CO is disposed between the channel patterns CH1 and CH2 and can be... Figure 5 As shown, it is adjacent to the inner wall of the barrier layer BX or as... Figure 7 The inner wall of the tunnel layer TX is shown adjacent to the tunnel layer. Although not shown, the unit plug CPL includes a cap pattern attached to the channel patterns CH1 and CH2 on the core post CO.

[0063] The barrier layer BX and tunneling patterns TX1 and TX2 may include at least one of an oxide layer (e.g., a silicon oxide layer) and an oxide-oxygen nitride layer (e.g., a silicon-oxygen nitride layer). The data storage patterns CT1 and CT2 may include a nitride layer or a variable resistance material. The channel patterns CH1 and CH2 and the capping pattern may include at least one of an undoped silicon layer and a doped silicon layer. The core CO may include an insulating layer such as an oxide layer.

[0064] exist Figure 4B In this disclosure, as an example, each cell plug CPL includes a first tunneling pattern TX1 separate from the second tunneling pattern TX2. For example, each cell plug CPL may include a single integral tunneling layer. Figure 5 The diagram illustrates an embodiment where the unit plug CPL includes separate tunneling patterns TX1 and TX2. Figure 7 The diagram shows an embodiment of the unit plug CPL including a single tunneling layer.

[0065] Reference Figure 4A and Figure 4BEach unit plug CPL has a shape that is symmetrical in the X and Y directions, for example, about one or more planes of symmetry. For example, a first data storage pattern CT1 is symmetrical with respect to a second data storage pattern CT2 in the Y direction about a first plane of symmetry. A first tunneling pattern TX1 is symmetrical with respect to a second tunneling pattern TX2 in the Y direction about a first plane of symmetry. A first channel pattern CH1 is symmetrical with respect to a second channel pattern CH2 in the Y direction about a first plane of symmetry. The first data storage pattern CT1, the first tunneling pattern TX1, and the first channel pattern CH1 are similar to the second data storage pattern CT2, the second tunneling pattern TX2, and the second channel pattern CH2.

[0066] Figure 5 This is a plan view showing the structure of a memory device 100 according to an embodiment of the present disclosure.

[0067] Figure 5 This is a plan view of a unit plug CPL according to an embodiment of the present disclosure. The unit plug CPL is located in a channel opening CHO having an elliptical cross-section. Figure 5 In the example, the channel opening CHO has a major axis in the Y direction.

[0068] The unit plug CPL includes a barrier layer BX, data storage patterns CT1 and CT2, tunneling patterns TX1 and TX2, channel patterns CH1 and CH2, and a core post CO. The barrier layer BX, data storage patterns CT1 and CT2, tunneling patterns TX1 and TX2, channel patterns CH1 and CH2, and core post CO extend in the Z direction.

[0069] The barrier layer BX contacts the side surface of the laminate STK. The barrier layer BX has an elliptical cylindrical shape, such as an elongated ellipse. The barrier layer BX extends between the laminate STK and the data storage patterns CT1 and CT2. The tunneling patterns TX1 and TX2 extend within the inner wall of the barrier layer BX between the data storage patterns CT1 and CT2 and the channel patterns CH1 and CH2.

[0070] Data storage patterns CT1 and CT2 are aligned along the major axis of an ellipse. For example, the first data storage pattern CT1 is spaced apart from the second data storage pattern CT2 in the Y direction. Tunneling patterns TX1 and TX2 are aligned along the major axis of an ellipse. For example, the first tunneling pattern TX1 is spaced apart from the second tunneling pattern TX2 in the Y direction. Channeling patterns CH1 and CH2 are aligned along the major axis of an ellipse. For example, the first channeling pattern CH1 is spaced apart from the second channeling pattern CH2 in the Y direction.

[0071] The data storage patterns CT1 and CT2, the tunneling patterns TX1 and TX2, and the channel patterns CH1 and CH2 have curved cross-sectional shapes.

[0072] The first tunneling pattern TX1 is located between the first data storage pattern CT1 and the first channel pattern CH1. The second tunneling pattern TX2 is located between the second data storage pattern CT2 and the second channel pattern CH2. The core post CO isolates the first data storage pattern CT1 from the second data storage pattern CT2. The core post CO isolates the first channel pattern CH1 from the second channel pattern CH2.

[0073] Each of the data storage patterns CT1 and CT2 includes an end CTE. The end CTE of the first data storage pattern CT1 faces the end CTE of the second data storage pattern CT2. The inner surfaces of the data storage patterns CT1 and CT2 contact the tunneling patterns TX1 and TX2, the outer surfaces of the data storage patterns CT1 and CT2 contact the barrier layer BX, and the side surfaces or end points of the data storage patterns CT1 and CT2 contact the core post CO. The end CTEs of the data storage patterns CT1 and CT2 include the side surfaces of the data storage patterns CT1 and CT2.

[0074] Each of the tunneling patterns TX1 and TX2 includes an end TXE. The end TXE of the first tunneling pattern TX1 faces the end TXE of the second tunneling pattern TX2. The inner surfaces of the tunneling patterns TX1 and TX2 contact the channel patterns CH1 and CH2 and the core post CO; the outer surfaces of the tunneling patterns TX1 and TX2 contact the storage patterns CT1 and CT2; and the side surfaces or ends of the tunneling patterns TX1 and TX2 contact the core post CO. The end TXE of the tunneling patterns TX1 and TX2 includes the side surfaces of the tunneling patterns TX1 and TX2.

[0075] Reference Figure 5 The end CTE of the first data storage pattern CT1 does not extend beyond the end TXE of the first tunneling pattern TX1. Similarly, the end CTE of the second data storage pattern CT2 does not extend beyond the end TXE of the second tunneling pattern TX2. For example, the side surface of the first data storage pattern CT1 may be formed continuously or linearly with the side surface of the first tunneling pattern TX1. The side surfaces of the first data storage pattern CT1 and the first tunneling pattern TX1 may be formed as straight lines or aligned, without any steps between the continuous side surfaces. Figure 5 As shown in the example, the end of the first data storage pattern CT1 extends beyond the corresponding end of the first channel pattern CH1, and the end of the first data storage pattern CT1 does not extend beyond the corresponding end of the first tunneling pattern TX1.

[0076] Reference Figure 5The end CTE of the first data storage pattern CT1 extends beyond the first channel pattern CH1. The end CTE of the second data storage pattern CT2 extends beyond the second channel pattern CH2. For example, compared to the first channel pattern CH1 extending towards the second data storage pattern CT2, the end CTE of the first data storage pattern CT1 is closer to the extension of the second data storage pattern CT2. Compared to the second channel pattern CH2 extending towards the first data storage pattern CT1, the end CTE of the second data storage pattern CT2 is closer to the extension of the first data storage pattern CT1. Compared to the extension of the first channel pattern CH1, the end TXE of the first tunneling pattern TX1 extends further. Compared to the extension of the second channel pattern CH2, the end TXE of the second tunneling pattern TX2 extends further.

[0077] The side surface of the first channel pattern CH1 may not be formed smoothly from the side surface of the first data storage pattern CT1 and the side surface of the first tunneling pattern TX1. Steps or offsets may form between the side surface of the first channel pattern CH1 and the adjacent side surface of the first data storage pattern CT1.

[0078] The side surface of the second channel pattern CH2 may not be formed smoothly from the side surface of the second data storage pattern CT2 and the side surface of the second tunneling pattern TX2. Steps or offsets may form between adjacent side surfaces of the second channel pattern CH2 and the second data storage pattern CT2.

[0079] Because the processes for separating the data storage layer into data storage patterns CT1 and CT2 and the processes for separating the channel layer into channel patterns CH1 and CH2 are performed separately, the data storage patterns CT1 and CT2, tunneling patterns TX1 and TX2, and channel patterns CH1 and CH2 included in the cell plug CPL may have uneven or offset features. (Refer to...) Figures 6A to 6H The etching process described in this disclosure is performed in two separate stages.

[0080] Figures 6A to 6H This is a diagram illustrating a memory device formed using a method for manufacturing a memory device according to an embodiment of the present disclosure.

[0081] Reference Figure 6A A channel opening CHO is formed through the laminate STK. The channel opening CHO extends through the laminate STK in the Z direction. The channel opening CHO has an elliptical planar shape with a major axis in the Y direction.

[0082] A barrier layer BX, a data storage layer CT, and a tunneling layer TX are sequentially formed within the channel opening CHO. The barrier layer BX is formed on a side surface or sidewall of the laminate STK. The data storage layer CT is formed on the inner surface of the barrier layer BX. The tunneling layer TX is formed on the inner surface of the data storage layer CT. For example, each of the barrier layer BX, data storage layer CT, and tunneling layer TX is sequentially formed through the channel opening CHO. The barrier layer BX and tunneling layer TX may each comprise an oxide material. The data storage layer CT may comprise a nitride material.

[0083] A capping layer CVL is formed on the inner surface of the tunneling layer TX. The capping layer CVL may be conformally formed on the inner surface of the tunneling layer TX. The capping layer CVL may not completely fill the tunneling layer TX. A first opening OP1 is formed within the capping layer CVL. The capping layer CVL may comprise a material that is etch-selective relative to the data storage layer CT and the tunneling layer TX.

[0084] The CVL (CVt layer) can be formed in an elliptical cylindrical space. The thickness of the CVL can vary depending on the orientation. For example, the CVL has a first thickness W1 along the major axis (e.g., the Y direction) of the ellipse and a second thickness W2 along the minor axis (e.g., the X direction) of the ellipse, wherein the first thickness W1 is wider than the second thickness W2.

[0085] Reference Figure 6B A segment of the cover layer CVL is removed to form a first cover pattern CV1 and a second cover pattern CV2. This can be achieved through... Figure 6A The first opening OP1 etches a section of the capping CVL. Because a section of the capping CVL is removed, the second opening OP2 extends beyond or is wider than the first opening OP1. An isotropic wet etching process can be performed such that a section of the capping CVL is etched, while the other sections (CV1 and CV2) of the capping CVL are retained.

[0086] Because the cover layer CVL is thickest along the major axis of the ellipse (in the Y direction) and thinnest along the minor axis (in the X direction), the segment of the cover layer CVL positioned along the minor axis of the ellipse can be removed before the segment positioned along the major axis. As a result, cover patterns CV1 and CV2 are aligned along the major axis of the ellipse. The first cover pattern CV1 is spaced apart from the second cover pattern CV2 in the Y direction.

[0087] Cover patterns CV1 and CV2 contact different segments of the tunneling layer TX. Another segment of the tunneling layer TX is exposed through a second opening OP2 between cover patterns CV1 and CV2. A segment of the data storage layer CT lies between cover patterns CV1 and CV2 and the blocking layer BX. Another segment of the data storage layer CT does not lie between cover patterns CV1 and CV2 and the blocking layer BX.

[0088] Reference Figure 6C Segments of the tunneling layer TX are removed to form tunneling patterns TX1 and TX2. Segments of the tunneling layer TX are etched using overlay patterns CV1 and CV2 as etching barriers. Therefore, as segments of the tunneling layer TX are removed, the segments of the tunneling layer TX covered by overlay patterns CV1 and CV2 (TX1 and TX2) are retained. The first tunneling pattern TX1 is spaced apart from the second tunneling pattern TX2 in the Y direction. Tunneling patterns TX1 and TX2 have curved shapes. Tunneling patterns TX1 and TX2 extend in the Z direction.

[0089] Segments of the data storage layer CT are removed to form data storage patterns CT1 and CT2. Overlay patterns CV1 and CV2 can be used as etching barriers to etch segments of the data storage layer CT. Therefore, as segments of the data storage layer CT are removed, segments of the data storage layer CT between overlay patterns CV1 and CV2 and the barrier layer BX are retained. The first data storage pattern CT1 is spaced apart from the second data storage pattern CT2 in the Y direction. Data storage patterns CT1 and CT2 have curved shapes. Data storage patterns CT1 and CT2 extend in the Z direction.

[0090] Because the tunneling layer TX and the data storage layer CT are etched using the same etch barrier (covering patterns CV1 and CV2), the side surfaces of the data storage patterns CT1 and CT2 extend uniformly or smoothly with the side surfaces of the tunneling patterns TX1 and TX2. Therefore, no steps are formed between the side surfaces of the data storage patterns CT1 and CT2 and the adjacent side surfaces of the tunneling patterns TX1 and TX2. For example, the side surface of the tunneling pattern TX1 and the adjacent side surface of the data storage pattern CT1 can form a line.

[0091] As a section of the tunneling layer TX and a section of the data storage layer CT are removed through the second opening OP2, the third opening OP3 extends or expands in the X direction relative to the second opening OP2. Figure 6C In the example, the third opening OP3 has a cross-sectional shape including an ellipse and an extension extending from the ellipse in the X direction.

[0092] about Figures 6A to 6C The described process can be referred to as the initial etching process that separates the data storage layer CT into a first data storage pattern CT1 and a second data storage pattern CT2.

[0093] Reference Figure 6D Remove the cover patterns CV1 and CV2. Form the channel layer CH in the third opening OP3. The channel layer CH is formed on the barrier layer BX, the data storage patterns CT1 and CT2, and the tunneling patterns TX1 and TX2. The channel layer CH may include polysilicon.

[0094] The channel layer CH covers the sides of data storage patterns CT1 and CT2. In this example, a section of the channel layer CH directly contacts the inner surface of the barrier layer BX. In this example, a section of the channel layer CH directly contacts the inner and side surfaces of the tunneling patterns TX1 and TX2. A section of the channel layer CH directly contacts the side surfaces of the data storage patterns CT1 and CT2. Because the channel layer CH is formed within the third opening OP3, the fourth opening OP4 is smaller than the third opening OP3.

[0095] The channel layer CH is conformally formed on the barrier layer BX, data storage patterns CT1 and CT2, and tunneling patterns TX1 and TX2. The channel layer CH includes a sloping region GR. For example, the channel layer CH includes a sloping region GR at the ends CTE of the data storage patterns CT1 and CT2 and at the ends TXE of the tunneling patterns TX1 and TX2. The sloping region GR of the channel layer CH includes a region protruding from an elliptical shape within the fourth opening OP4.

[0096] Reference Figure 6E A barrier layer BRL is formed in the fourth opening OP4. The barrier layer BRL is formed on the inner surface of the channel layer CH. The barrier layer BRL is conformally formed on the inner surface of the channel layer CH. The barrier layer BRL does not completely fill the fourth opening OP4. A fifth opening OP5 is formed in the barrier layer BRL. The barrier layer BRL comprises a material that has etch selectivity relative to the channel layer CH. For example, the barrier layer BRL may comprise a material similar to that of the capping layer CVL.

[0097] The thickness of the barrier layer BRL varies depending on the direction. For example, the barrier layer BRL has a third thickness W3 in the Y direction and a fourth thickness W4 in the X direction, wherein the third thickness W3 is wider than the fourth thickness W4. When the fourth opening OP4 has an elliptical shape and an extension protruding from the ellipse in the X direction, the thickness of the barrier layer BRL deposited along the major axis of the ellipse is greater than the other thicknesses of the barrier layer BRL.

[0098] According to Figures 6A to 6C The described initial etching process, with third opening OP3 and fourth opening OP4, includes extensions extending in the X direction from an elliptical shape. When the channel layer and barrier layer are formed in an opening with an elliptical cross-section, there may not be sufficient space along the minor axis of the ellipse to deposit the material layer. When the opening is enlarged along the minor axis of the ellipse, as in this example, sufficient space is obtained to deposit the channel layer CH and the barrier layer BRL. Therefore, the difficulty of depositing the channel layer CH and the barrier layer BRL in an elliptical channel opening is reduced.

[0099] Reference Figure 6F A segment of the barrier layer BRL is removed to form the first barrier pattern BR1 and the second barrier pattern BR2. This can be achieved through... Figure 6EThe fifth opening OP5 etches a section of the barrier layer BRL. Because a section of the barrier layer BRL is removed, the sixth opening OP6 extends beyond or enlarges the fifth opening OP5. An isotropic wet etching process can be performed such that a section of the barrier layer BRL is etched while the remaining section of the barrier layer BRL is preserved.

[0100] Because the barrier layer BRL is thicker in the Y direction than in the X direction, the segment of the barrier layer BRL in the X direction can be removed before the segment in the Y direction. Therefore, barrier patterns BR1 and BR2 are aligned in the Y direction. The first barrier pattern BR1 is spaced apart from the second barrier pattern BR2 in the Y direction.

[0101] Barrier patterns BR1 and BR2 contact sections of the channel layer CH. Sections of the channel layer CH are exposed through the sixth opening OP6 between barrier patterns BR1 and BR2. The inclined region GR of the channel layer CH is not covered by barrier patterns BR1 and BR2. Barrier patterns BR1 and BR2 are located on the channel layer CH near tunneling patterns TX1 and TX2 and data storage patterns CT1 and CT2.

[0102] Reference Figure 6G The segments of the channel layer CH are removed to form the first channel pattern CH1 and the second channel pattern CH2. The segments of the channel layer CH are etched using barrier patterns BR1 and BR2 as etching barriers. Therefore, as the segments of the channel layer CH are removed, the sections of the channel layer CH covered by barrier patterns BR1 and BR2 are retained. The first channel pattern CH1 is spaced apart from the second channel pattern CH2 in the Y direction. Channel patterns CH1 and CH2 extend in the Z direction. Because the segments of the channel layer CH are removed through the sixth opening OP6, a seventh opening OP7 is formed, extending or expanding in the X direction relative to the sixth opening OP6.

[0103] When barrier patterns BR1 and BR2 are used as etching barriers to remove segments of the channel layer CH, the sloping region GR of the channel layer CH is removed. Therefore, the channel patterns CH1 and CH2 have curved shapes corresponding to the vertices of the ellipse.

[0104] Because the tunneling layer TX or the data storage layer CT is used as an etching barrier to etch the channel layer CH, and different etching barriers (barrier patterns BR1 and BR2) are used to etch the tunneling layer TX and the data storage layer CT, the side surfaces of the channel patterns CH1 and CH2 do not extend smoothly from or align with the side surfaces of the data storage patterns CT1 and CT2 and the tunneling patterns TX1 and TX2. There are steps between the side surfaces of the channel patterns CH1 and CH2 and the side surfaces of the tunneling patterns TX1 and TX2, resulting in a lack of a continuous line between the side surfaces. For example, the side surface of the first channel pattern CH1 is offset relative to or not aligned with the side surface of the first tunneling pattern TX1.

[0105] Reference Figures 6D to 6G The described process can be referred to as a secondary etching process that separates the channel layer CH into a first channel pattern CH1 and a second channel pattern CH2.

[0106] Reference Figure 6H The barrier patterns BR1 and BR2 are removed. A core material layer (e.g., an oxide layer) fills the seventh opening OP7 to form a core post CO. The core post CO isolates the first data storage pattern CT1, the first tunneling pattern TX1, and the first channel pattern CH1 from the second data storage pattern CT2, the second tunneling pattern TX2, and the second channel pattern CH2.

[0107] Figure 7 This is a plan view showing the structure of a memory device according to an embodiment of the present disclosure.

[0108] Figure 7 This is a top view of a unit plug CPL according to an embodiment of the present disclosure. The unit plug CPL is located in a channel opening CHO having an elliptical cross-section. The channel opening CHO has a major axis in the Y direction.

[0109] The unit plug CPL includes a barrier layer BX, data storage patterns CT1 and CT2, a tunneling layer TX, channel patterns CH1 and CH2, and a core post CO. The barrier layer BX, data storage patterns CT1 and CT2, tunneling layer TX, channel patterns CH1 and CH2, and core post CO extend in the Z direction.

[0110] The barrier layer BX contacts the side surface of the stack STK. The barrier layer BX has an elliptical cylindrical shape. The barrier layer BX extends between the stack STK and the data storage patterns CT1 and CT2, and between the stack STK and the tunneling layer TX.

[0111] Data storage patterns CT1 and CT2 are formed along the inner wall of the barrier layer BX. Data storage patterns CT1 and CT2 have curved cross-sections. Data storage patterns CT1 and CT2 are aligned with the major axis of an ellipse. For example, the first storage pattern CT1 is spaced apart from the second data storage pattern CT2 in the Y direction. The first data storage pattern CT1 is insulated from the second data storage pattern CT2 through the tunneling layer TX and the core column CO.

[0112] Data storage patterns CT1 and CT2 include ends. The end of the first data storage pattern CT1 faces the end of the second data storage pattern CT2. The inner and side surfaces of data storage patterns CT1 and CT2 face the tunneling layer TX, and the outer surfaces of data storage patterns CT1 and CT2 face the barrier layer BX. The ends of data storage patterns CT1 and CT2 include the side surfaces of data storage patterns CT1 and CT2.

[0113] The tunneling layer TX extends along the inner surface of the barrier layer BX and the inner surfaces of the data storage patterns CT1 and CT2. The tunneling layer TX contacts a portion of the inner surface of the barrier layer BX. The tunneling layer TX extends between the first data storage pattern CT1 and the first channel pattern CH1, and between the second data storage pattern CT2 and the second channel pattern CH2. The tunneling layer TX contacts the inner and side surfaces of the data storage patterns CT1 and CT2.

[0114] Channel patterns CH1 and CH2 are formed along the inner wall of the tunneling layer TX. Channel patterns CH1 and CH2 have curved cross-sections. Channel patterns CH1 and CH2 are aligned along the major axis of an ellipse. For example, the first channel pattern CH1 is spaced apart from the second channel pattern CH2 in the Y direction.

[0115] The outer surfaces of channel patterns CH1 and CH2 contact the tunneling layer TX, and the inner and side surfaces of channel patterns CH1 and CH2 contact the core post CO. The core post CO insulates the first channel pattern CH1 from the second channel pattern CH2.

[0116] Reference Figure 7 The tunneling layer TX includes a sloping region GRt at the ends of the data storage patterns CT1 and CT2. The tunneling layer TX is conformally formed on the inner surface of the barrier layer BX and the inner surfaces of the data storage patterns CT1 and CT2. Because the tunneling layer TX is formed on the data storage patterns CT1 and CT2 which are separate from each other, the tunneling layer TX includes a sloping region GRt at the ends of the data storage patterns CT1 and CT2.

[0117] Because the processes for separating the data storage layer into data storage patterns CT1 and CT2 are performed separately from the processes for separating the channel layer into channel patterns CH1 and CH2, the tunneling layer TX included in the cell plug CPL has a different relationship with respect to the data storage layer. Figure 7The described features. (Refer to...) Figures 8A to 8H Describes an etching process performed in two separate stages.

[0118] Figures 8A to 8H This is a diagram illustrating a memory device formed using a method for manufacturing a memory device according to an embodiment of the present disclosure.

[0119] Reference Figure 8A A channel opening CHO is formed through the laminate STK. The channel opening CHO extends through the laminate STK in the Z direction. The channel opening CHO has an elliptical planar shape with a major axis in the Y direction.

[0120] A barrier layer BX and a data storage layer CT are sequentially formed within the channel opening CHO. The barrier layer BX is formed on a side surface or sidewall of the laminate STK. The data storage layer CT is formed on the inner surface of the barrier layer BX. For example, the barrier layer BX is formed along the sidewall of the laminate STK exposed through the channel opening CHO, and the data storage layer CT is formed on the inner surface of the barrier layer BX. The barrier layer BX may comprise an oxide material. The data storage layer CT may comprise a nitride material.

[0121] A capping layer (CVL) is formed on the inner surface of the data storage layer (CT). The capping layer (CVL) is conformally formed on the inner surface of the data storage layer (CT). The capping layer (CVL) may not completely fill the data storage layer (CT). A first opening (OP1) is formed in the capping layer (CVL). The capping layer (CVL) may include a material that is etch-selective relative to the data storage layer (CT).

[0122] A capping layer (CVL) is formed in an elliptical cylindrical space. The thickness of the capping layer CVL can vary depending on the orientation. For example, the capping layer CVL has a first thickness along the major axis of the ellipse (in the Y direction) and a second thickness along the minor axis of the ellipse (in the X direction), wherein the first thickness is wider than the second thickness.

[0123] Reference Figure 8B A segment of the cover layer CVL is removed to form a first cover pattern CV1 and a second cover pattern CV2. This is achieved by... Figure 8A The first opening OP1 etches a segment of the capping CVL. Because a segment of the capping CVL is removed, the second opening OP2 extends beyond or is wider than the first opening OP1. An isotropic wet etching process can be performed such that a segment of the capping CVL is etched, while the other segments (CV1 and CV2) of the capping CVL are retained.

[0124] Because the cover layer CVL is thickest along the major axis of the ellipse (in the Y direction) and thinnest along the minor axis (in the X direction), the segment of the cover layer CVL positioned along the minor axis of the ellipse can be removed before the segment positioned along the major axis. As a result, cover patterns CV1 and CV2 are aligned along the major axis of the ellipse. The first cover pattern CV1 is spaced apart from the second cover pattern CV2 in the Y direction.

[0125] Cover patterns CV1 and CV2 contact different segments of the data storage layer CT. Another segment of the data storage layer CT is exposed through a second opening OP2 between cover patterns CV1 and CV2.

[0126] Reference Figure 8C The data storage layer CT is segmented to form data storage patterns CT1 and CT2. Overlay patterns CV1 and CV2 are used as etching barriers to etch the segments of the data storage layer CT. Therefore, as the segments of data storage patterns CT1 and CT2 are removed, the segments of the data storage layer CT covered by overlay patterns CV1 and CV2 (CT1 and CT2) are retained. The first data storage pattern CT1 is spaced apart from the second data storage pattern CT2 in the Y direction. Data storage patterns CT1 and CT2 have curved shapes. Data storage patterns CT1 and CT2 extend in the Z direction.

[0127] Because the data storage layer CT segment is removed through the second opening OP2, the third opening OP3 extends beyond the second opening OP2 in the X direction. Figure 8C In the example, the third opening OP3 has a cross-sectional shape including an ellipse and an extension extending from the ellipse in the X direction.

[0128] about Figures 8A to 8C The described process can be referred to as the initial etching process that separates the data storage layer CT into a first data storage pattern CT1 and a second data storage pattern CT2.

[0129] Reference Figure 8D The overlay patterns CV1 and CV2 are removed. A tunneling layer TX is formed in the third opening OP3. The tunneling layer TX is formed on the barrier layer BX and the data storage patterns CT1 and CT2. The tunneling layer TX covers the separated data storage patterns CT1 and CT2. In this example, a section of the tunneling layer TX directly contacts the inner surface of the barrier layer BX. A section of the tunneling layer TX directly contacts the inner and side surfaces of the data storage patterns CT1 and CT2.

[0130] The tunneling layer TX is conformally formed on the barrier layer BX and the data storage patterns CT1 and CT2. The tunneling layer TX includes a sloping region GRt. For example, the tunneling layer TX includes a sloping region GRt at the ends of the data storage patterns CT1 and CT2. The sloping region GRt of the tunneling layer TX includes a region that slopes or protrudes from an elliptical shape within the fourth opening OP4.

[0131] A channel layer CH is formed in the third opening OP3. The channel layer CH is formed on the tunneling layer TX. The channel layer CH extends along the inner surface of the tunneling layer TX. The tunneling layer TX is disposed between the channel layer CH and the first data storage pattern CT1, which is separated from the second data storage pattern CT2. Because the tunneling layer TX and the channel layer CH are formed within the third opening OP3, the fourth opening OP4 is smaller than the third opening OP3.

[0132] The channel layer CH is conformally formed on the tunnel layer TX. The channel layer CH includes a sloping region GRc. For example, the channel layer CH includes a sloping region GRc at the sloping region GRt of the tunnel layer TX. The channel layer CH includes sloping regions GRc at the ends of the data storage patterns CT1 and CT2. The sloping region GRc of the channel layer CH includes a region protruding from an elliptical shape within the fourth opening OP4.

[0133] Reference Figure 8E A barrier layer BRL can be formed in the fourth opening OP4. The barrier layer BRL is formed on the inner surface of the channel layer CH. The barrier layer BRL is conformally formed on the inner surface of the channel layer CH. The barrier layer BRL does not completely fill the fourth opening OP4. A fifth opening OP5 is formed in the barrier layer BRL. The barrier layer BRL comprises a material with etch selectivity relative to the channel layer CH and the tunneling layer TX. For example, the barrier layer BRL may comprise a material similar to that of the capping layer CVL.

[0134] The thickness of the barrier layer BRL varies depending on the direction. For example, the barrier layer BRL has a third thickness in the Y direction and a fourth thickness in the X direction, where the third thickness W3 is wider than the fourth thickness W4. When the fourth opening OP4 has the shape of an ellipse and an extension protruding from the ellipse in the X direction, the thickness of the barrier layer BRL along the major axis of the ellipse is greater than the thickness of the other thicknesses of the barrier layer BRL.

[0135] According to Figures 8A to 8CThe described initial etching process includes extensions extending in the X direction from an elliptical shape, specifically the third opening OP3 and the fourth opening OP4. When the tunneling layer, channel layer, and barrier layer are formed in an opening with an elliptical cross-section, sufficient space along the minor axis of the ellipse may not be available for depositing the material layers. When the opening is enlarged along the minor axis of the ellipse, as in this example, sufficient space is obtained for depositing the tunneling layer TX, the channel layer CH, and the barrier layer BRL. Therefore, the difficulty of depositing the tunneling layer TX, the channel layer CH, and the barrier layer BRL in an elliptical channel opening is reduced.

[0136] Reference Figure 8F A section of the barrier layer BRL is removed to form barrier patterns BR1 and BR2. This can be achieved through... Figure 8E The fifth opening OP5 etches a section of the barrier layer BRL. Because a section of the barrier layer BRL is removed, the sixth opening OP6 extends beyond or enlarges the fifth opening OP5. An isotropic wet etching process can be performed so that a section of the barrier layer BRL is etched while the remaining section of the barrier layer is preserved.

[0137] Because the barrier layer BRL is thicker in the Y direction than in the X direction, the X-direction segment of the barrier layer BRL can be removed before the Y-direction segment is removed. Therefore, barrier patterns BR1 and BR2 are aligned in the Y direction. The first barrier pattern BR1 is spaced apart from the second barrier pattern BR2 in the Y direction.

[0138] Barrier patterns BR1 and BR2 contact the channel layer CH. The channel layer CH is exposed through the sixth opening OP6 between barrier patterns BR1 and BR2. The sloping region GRc of the channel layer CH is not covered by barrier patterns BR1 and BR2. Barrier patterns BR1 and BR2 are located on the channel layer CH near data storage patterns CT1 and CT2.

[0139] Reference Figure 8G The segments of the channel layer CH are removed to form channel patterns CH1 and CH2. The segments of the channel layer CH are etched using barrier patterns BR1 and BR2 as etching barriers. Therefore, as the segments of the channel layer CH are removed, the sections of the channel layer CH covered by barrier patterns BR1 and BR2 are retained. The first channel pattern CH1 is spaced apart from the second channel pattern CH2 in the Y direction. Channel patterns CH1 and CH2 extend in the Z direction. Because the segments of the channel layer CH are removed through the sixth opening OP6, a seventh opening OP7 is formed, extending or expanding in the X direction relative to the sixth opening OP6.

[0140] When barrier patterns BR1 and BR2 are used as etching barriers to remove segments of the channel layer CH, the sloping region GRc of the channel layer CH is removed. Therefore, the channel patterns CH1 and CH2 have curved shapes corresponding to the vertices of the ellipse.

[0141] With the removal of the inclined region GRc of the channel layer CH, the inclined region GRt of the tunnel layer TX is exposed through the seventh opening OP7. The inclined region GRt of the tunnel layer TX is located between the end of one of the channel patterns CH1 and CH2 and the end of one of the data storage patterns CT1 and CT2.

[0142] Reference Figures 8D to 8G The described process can be referred to as a secondary etching process that separates the channel layer CH into a first channel pattern CH1 and a second channel pattern CH2.

[0143] Reference Figure 8H Barrier patterns BR1 and BR2 are removed. The core material layer fills the 7th opening OP7 to form the core post CO. The core post CO insulates the first data storage pattern CT1 and the first channel pattern CH1 from the second data storage pattern CT2 and the second channel pattern CH2.

[0144] Figures 9A to 9E This is a diagram illustrating a memory device formed using a method for manufacturing a memory device according to an embodiment of the present disclosure.

[0145] Figures 9A to 9E This is a diagram illustrating a memory device formed using a method of inserting a forming unit CPL according to an embodiment of the present disclosure.

[0146] Reference Figure 9A A preliminary stack, pSTK, is formed, comprising an interlayer insulating layer, IIL, alternately stacked with a sacrificial layer, SF. The interlayer insulating layer IIL and the sacrificial layer SF are stacked in the Z direction. The interlayer insulating layer IIL may comprise an insulating material. For example, the interlayer insulating layer IIL may comprise an oxide layer (e.g., a silicon oxide layer). The sacrificial layer SF may comprise a material that can be selectively removed in subsequent processes. The sacrificial layer SF may comprise a material having a different etch selectivity than the interlayer insulating layer IIL. For example, the sacrificial layer SF may comprise a nitride layer.

[0147] Reference Figure 9B A channel opening CHO is formed through the initial laminate pSTK. The channel opening CHO extends through the initial laminate pSTK in the Z direction. The channel opening CHO is arranged in the X and Y directions. The side surfaces of the sacrificial layer SF and the interlayer insulation layer IIL are exposed through the channel opening CHO.

[0148] Reference Figure 9C Unit plugs CPL are formed in each channel opening CHO. The unit plugs CPL may have features according to reference... Figure 5 and Figures 6A to 6H The described implementation method or according to the reference Figure 7 and Figures 8A to 8HThe structure of the described implementation is as follows. For example, the cell plug CPL includes a barrier layer BX, data storage patterns CT1 and CT2, tunneling patterns TX1 and TX2 (or a tunneling layer TX), channel patterns CH1 and CH2, and a core post CO.

[0149] Reference Figure 9D The sacrificial layer SF is removed to form a recessed RC. Because the sacrificial layer SF is removed, a space is formed between the interlayer insulation layers IIL. The cell plug CPL supports the spaced-apart interlayer insulation layers IIL.

[0150] Reference Figure 9E A conductive layer CD is formed between consecutive interlayer insulating layers IIL to form a laminate STK. The conductive layer CD fills the depression RC formed during the removal of the sacrificial layer SF. The conductive layer CD may include a conductive material.

[0151] Figure 10 This is a block diagram illustrating a memory card system 3000 according to an embodiment of the present disclosure.

[0152] Reference Figure 10 The memory card system 3000 includes a controller 3100, a memory device 3200, and a connector 3300.

[0153] Controller 3100 is coupled to memory device 3200. Controller 3100 accesses memory device 3200. For example, controller 3100 controls programming operations, read operations, erase operations, and background operations of memory device 3200. Controller 3100 is configured as an interface between memory device 3200 and a host. Controller 3100 is configured to drive or execute firmware that controls memory device 3200. For example, controller 3100 may include components such as random access memory (RAM), processing unit, host interface, memory interface, and ECC circuitry.

[0154] Controller 3100 communicates with external devices via connector 3300. Controller 3100 may communicate with external devices (e.g., a host) based on a communication protocol. For example, controller 3100 may communicate with external devices using at least one of various communication protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Memory (UFS), WiFi, Bluetooth, and High Speed ​​Non-Volatile Memory (NVMe). In embodiments, connector 3300 is configured according to at least one of these various communication protocols.

[0155] Memory device 3200 includes multiple memory cells and is connected to Figure 1 The illustrated memory device 100 is similarly configured, including according to Figure 4A , Figure 4B , Figure 5 , Figures 6A to 6H , Figure 7 , Figures 8A to 8H as well as Figures 9A to 9E Any of the configured memory cells in the memory.

[0156] The controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to form memory cards such as PCMCIA cards, compact flash memory (CF) cards, smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro or eMMC), SD cards (SD, miniSD, microSD or SDHC), universal flash memory (UFS), etc.

[0157] Figure 11 This is a block diagram illustrating a solid-state drive (SSD) system 4000 including a memory device according to an embodiment of the present disclosure.

[0158] Reference Figure 11 The SSD system 4000 includes a host 4100 and an SSD 4200. The SSD system 4200 exchanges signals with the host 4100 via a signal connector 4001 and receives power via a power connector 4002. The SSD 4200 includes a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a cache memory 4240.

[0159] The controller 4210 controls a plurality of memory devices 4221 to 422n in response to signals received from the host 4100. In an embodiment, the signals are based on the interface between the host 4100 and the SSD 4200. For example, the signals may be configured according to at least one of a variety of interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Memory (UFS), WiFi, Bluetooth, and High Speed ​​Non-Volatile Memory (NVMe) interfaces.

[0160] The plurality of memory devices 4221 to 422n include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n is associated with... Figure 1 The illustrated memory device 100 is similarly configured, including according to Figure 4A , Figure 4B , Figure 5 , Figures 6A to 6H , Figure 7 , Figures 8A to 8H as well as Figures 9A to 9E Any of the configured memory cells in the array. Multiple memory devices 4221 to 422n communicate with the controller 4210 via channels CH1 to CHn.

[0161] Auxiliary power supply 4230 is connected to host 4100 via power connector 4002. Host 4100 supplies power to auxiliary power supply 4230 and uses this power to charge the SSD. When the power supply from host 4100 is unreliable or unsustainable, auxiliary power supply 4230 supplies power to SSD 4200. Auxiliary power supply 4230 may be located inside or outside SSD 4200. For example, auxiliary power supply 4230 may be located on the motherboard and supply auxiliary power to SSD 4200.

[0162] Buffer memory 4240 is a buffer memory for SSD 4200. For example, buffer memory 4240 stores data received from host 4100 or data received from multiple memory devices 4221 to 422n, or stores metadata (e.g., a mapping table) of memory devices 4221 to 422n. Buffer memory 4240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0163] According to this disclosure, by improving the process of forming cell plugs, the difficulty of manufacturing memory devices can be reduced, and the integration density of memory devices can be improved or increased.

[0164] The concepts have been disclosed in conjunction with examples and embodiments. Those skilled in the art will understand that various modifications, additions, combinations, and substitutions can be made without departing from the scope and technical concepts of this disclosure. The embodiments disclosed in this specification should be considered illustrative rather than restrictive. Therefore, the scope of this disclosure is not limited to these descriptions. All changes within the meaning of the claims and their equivalents are included within its scope.

[0165] Cross-references to related applications

[0166] This application claims priority to Korean Patent Application No. 10-2025-0018738, filed with the Korean Intellectual Property Office on February 13, 2025, the full disclosure of which is incorporated herein by reference.

Claims

1. A method for manufacturing a memory device, the method comprising the following steps: Forming a channel opening that extends through the stacked material in a first direction; A first data storage pattern is formed in the channel opening, spaced apart from the second data storage pattern in a second direction perpendicular to the first direction; A channel layer is formed inside the first data storage pattern and the second data storage pattern; A first barrier pattern, spaced apart from the second barrier pattern in the second direction, is formed inside the channel layer; as well as A first channel pattern, spaced apart from the second channel pattern, is formed in the second direction by removing the segment of the channel layer between the first barrier pattern and the second barrier pattern.

2. The method according to claim 1, wherein, The channel opening has an elliptical planar shape with a major axis in the second direction.

3. The method according to claim 1, wherein, The steps of forming the first data storage pattern and the second data storage pattern include the following steps: A data storage layer is formed inside the sidewall of the laminate exposed through the channel opening; A first overlay pattern is formed within the data storage layer, spaced apart from the second overlay pattern in the second direction; The first data storage pattern and the second data storage pattern are formed by removing the segment of the data storage layer between the first overlay pattern and the second overlay pattern; and Remove the first overlay pattern and the second overlay pattern.

4. The method according to claim 3, further comprising the following steps: Before the data storage layer is formed, a barrier layer is formed on the sidewall of the stack.

5. The method according to claim 4, further comprising the following steps: The section that forms the channel layer directly contacts the barrier layer.

6. The method according to claim 3, further comprising the following step: A tunneling layer is formed on the inner surface of the data storage layer.

7. The method according to claim 6, further comprising the following step: A first tunneling pattern, spaced apart from the second tunneling pattern, is formed in the second direction by removing the segment of the tunneling layer between the first covering pattern and the second covering pattern.

8. The method according to claim 7, further comprising the following step: A first section of the trench layer directly contacts the first tunneling pattern, and a second section of the trench layer directly contacts the second tunneling pattern.

9. The method according to claim 3, wherein, The first barrier pattern, the second barrier pattern, the first overlay pattern, and the second overlay pattern comprise similar materials.

10. The method according to claim 3, wherein, The steps of forming the first overlay pattern and the second overlay pattern include the following steps: An overlay layer is formed inside the data storage layer; and The first cover pattern and the second cover pattern are formed by removing a segment of the cover layer positioned along the short axis of the channel opening.

11. The method according to claim 1, further comprising the step of: The first data storage pattern and the second data storage pattern are formed extending in the first direction.

12. The method according to claim 1, further comprising the following steps: The channel layer is formed, the channel layer including a first inclined region located at a first end of the first data storage pattern and a second inclined region located at a second end of the second data storage pattern.

13. The method of claim 12, further comprising the step of: When forming the first channel pattern and the second channel pattern, the first inclined region and the second inclined region are removed from the channel layer.

14. The method according to claim 1, further comprising the step of: After forming the first groove pattern and the second groove pattern Remove the first barrier pattern and the second barrier pattern to form a shaped opening; as well as The shaped opening is filled using a core material layer.

15. The method according to claim 1, further comprising the step of: A tunneling layer is formed covering the first data storage pattern and the second data storage pattern.

16. The method of claim 15, further comprising the step of: A first inclined region located at the first end of the first data storage pattern and a second inclined region located at the second end of the second data storage pattern are formed in the tunneling layer.

17. The method of claim 16, further comprising the step of: The channel layer is formed, extending along the inner surface of the tunneling layer.

18. The method of claim 16, further comprising the step of: When forming the first trench pattern and the second trench pattern, the first inclined region and the second inclined region of the tunneling layer are exposed.

19. A memory device comprising: A stack comprising a unit plug disposed in a channel opening extending through the stack in a first direction; Within the unit plug, a first data storage pattern is spaced apart from the second data storage pattern in a second direction perpendicular to the first direction; Within the unit plug, a first channel pattern is spaced apart from the second channel pattern in the second direction; as well as Within the unit plug, there is a first tunneling pattern located between the first data storage pattern and the first channel pattern, and a second tunneling pattern located between the second data storage pattern and the second channel pattern. Wherein, the end of the first data storage pattern extends beyond the corresponding end of the first channel pattern in the second direction, and the end of the first data storage pattern does not extend beyond the corresponding end of the first tunneling pattern in the second direction.

20. The memory device according to claim 19, wherein, The channel opening has an elliptical planar shape with a major axis in the second direction.

21. The memory device of claim 19, further comprising: A barrier layer extends between the laminate and the first data storage pattern and the second data storage pattern; as well as A core post is disposed between the first channel pattern and the second channel pattern and inside the barrier layer.

22. The memory device according to claim 21, wherein, The first data storage pattern and the second data storage pattern are insulated by the core post; and The first and second channel patterns are insulated by the core post.

23. A memory device comprising: A stack comprising a unit plug disposed in a channel opening extending through the stack in a first direction; Within the unit plug, a first data storage pattern is spaced apart from the second data storage pattern in a second direction perpendicular to the first direction; Within the unit plug, a first channel pattern is spaced apart from the second channel pattern in the second direction; as well as Within the unit plug, a tunneling layer extends between the first data storage pattern and the first channel pattern, and between the second data storage pattern and the second channel pattern. The tunneling layer includes a first inclined region located at the end of the first data storage pattern and a second inclined region located at the end of the second data storage pattern.

24. The memory device according to claim 23, wherein, The channel opening has an elliptical planar shape with a major axis in the second direction.

25. The memory device of claim 23, further comprising: A barrier layer extends between the laminate and the first data storage pattern and the second data storage pattern; as well as A core post is disposed between the first channel pattern and the second channel pattern and inside the barrier layer.

26. The memory device according to claim 25, wherein, The first data storage pattern and the second data storage pattern are insulated by the tunneling layer and the core post; and The first and second channel patterns are insulated by the core post.

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