Three-dimensional memory structure and its formation method

Abstract

This invention relates to a three-dimensional memory structure and its formation method. The method for forming the three-dimensional memory structure includes the following steps: forming a substrate, the substrate comprising a base plate, a bottom dielectric layer on the substrate, a plurality of first contact structures penetrating the bottom dielectric layer, an intermediate dielectric layer covering the bottom dielectric layer and the first contact structures, and a plurality of memory vias penetrating the intermediate dielectric layer and exposing the plurality of first contact structures; forming a plurality of memory structures located within the plurality of memory vias, each memory structure comprising a bottom electrode layer, a memory layer, and a top electrode layer, wherein the top electrode layers of at least two memory structures are electrically connected to form a top electrode interconnect structure, and the plurality of top electrode interconnect structures are independent of each other; forming a plurality of first lead-out structures located above the substrate and electrically isolated from each other, wherein the plurality of first lead-out structures are electrically connected to the plurality of top electrode interconnect structures in a one-to-one correspondence. This invention reduces the number of process steps and lowers the manufacturing cost of the three-dimensional memory structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a three-dimensional memory structure and its formation method. Background Technology

[0002] Phase-change memory (PCM) or ferroelectric RAM (FeRAM) are devices that integrate memory cells in back-end-of-line (BEOL) processes, where the memory cells are inserted between two adjacent metal layers. A memory cell typically consists of upper and lower electrode layers and an intermediate ferroelectric storage layer. The storage performance of a ferroelectric memory is directly proportional to the effective area of ​​the ferroelectric storage layer and the electrode layer within the memory cell. Traditional 2D planar memory cells employ a three-layer planar structure: upper electrode layer, storage layer, and lower electrode layer. To ensure step coverage of the thin film, the upper electrode layer, storage layer, and lower electrode layer are all formed using atomic layer deposition (ALD). However, the storage density of memory with a 2D planar structure is limited by the miniaturization limits of the planar dimensions, making it difficult to achieve large-capacity storage. Three-dimensional memory structures with 3D memory cell architectures, by stacking memory cells vertically, significantly increase the storage capacity per unit area and have become the mainstream direction in the development of non-volatile memory.

[0003] In the process of forming a three-dimensional memory structure, multiple vias are typically formed simultaneously. Then, a lower electrode layer, a memory layer, and an upper electrode layer are formed continuously within the vias and covering the lower electrode layer. Next, the upper electrode layer, memory layer, and lower electrode layer are disconnected using photolithography and etching processes. The remaining upper electrode layer, memory layer, and lower electrode layer within each via collectively form a single memory device, and the memory devices within adjacent vias are disconnected. Then, the upper electrode layer in each memory device is brought out, and the circuit connections between the upper electrode layers are achieved through a top metal layer. However, current processes for forming three-dimensional memory structures are quite complex. Disconnecting the lower electrode layer, memory layer, and upper electrode layer requires multiple photomasks, which increases the manufacturing difficulty and cost of three-dimensional memory structures while also reducing production capacity. In addition, when disconnecting the lower electrode layer, the storage layer and the upper electrode layer, the lower electrode layer is often not completely disconnected, which can easily cause leakage between adjacent storage cells, resulting in a decrease in the stability and reliability of the three-dimensional memory structure.

[0004] Therefore, how to simplify the manufacturing process of three-dimensional memory structures, improve the manufacturing efficiency of three-dimensional memory structures, and improve the performance stability and reliability of three-dimensional memory structures are technical problems that urgently need to be solved. Summary of the Invention

[0005] This invention provides a three-dimensional memory structure and a method for forming the same, which simplifies the manufacturing process of the three-dimensional memory structure, improves the manufacturing efficiency of the three-dimensional memory structure, and enhances the performance stability and reliability of the three-dimensional memory structure.

[0006] According to some embodiments, the present invention provides a method for forming a three-dimensional memory structure, comprising the following steps: A substrate is formed, the substrate including a substrate, a bottom dielectric layer located on the substrate, a plurality of first contact structures that penetrate the bottom dielectric layer and are spaced apart along a first direction, an intermediate dielectric layer covering the bottom dielectric layer and the first contact structures, and a plurality of storage holes that penetrate the intermediate dielectric layer and expose the plurality of first contact structures respectively. Multiple storage structures are formed, each located within a plurality of storage holes. Each storage structure includes a lower electrode layer electrically connected to the first contact structure, a storage layer covering the lower electrode layer, and an upper electrode layer covering the storage layer. The upper electrode layers of at least two of the storage structures are electrically connected to form an upper electrode interconnect structure, and the plurality of upper electrode interconnect structures are independent of each other. A plurality of first lead-out structures are formed on the substrate and electrically isolated from each other, and the plurality of first lead-out structures are electrically connected to the plurality of upper electrode interconnect structures in a one-to-one correspondence.

[0007] In some embodiments, the specific steps for forming the substrate include: A substrate is provided, the substrate including a plurality of active regions, and the substrate including a top surface and a bottom surface that are distributed opposite to each other, the active regions including a channel region and source regions and drain regions distributed on opposite sides of the channel region; Form the bottom dielectric layer covering the top surface of the substrate; Multiple first contact structures are formed that penetrate the bottom dielectric layer along a second direction and are electrically connected to the multiple drain regions one by one, wherein the second direction intersects the top surface of the substrate perpendicularly; An intermediate dielectric layer is formed covering the bottom dielectric layer and the first contact structure; A plurality of storage holes are formed that penetrate the intermediate dielectric layer along the second direction and expose a plurality of the first contact structures one by one.

[0008] In some embodiments, the intermediate dielectric layer includes: A first intermediate dielectric layer covers the bottom dielectric layer and the first contact structure, and the material of the first intermediate dielectric layer includes silicon nitride; A second intermediate dielectric layer covering the first intermediate dielectric layer, wherein the material of the second intermediate dielectric layer includes silicon dioxide; A third intermediate dielectric layer covers the second intermediate dielectric layer, and the material of the third intermediate dielectric layer includes silicon oxynitride.

[0009] In some embodiments, the specific steps of forming a plurality of storage structures respectively located within a plurality of storage holes include: Multiple lower electrode layers are formed to cover the inner walls of the multiple storage holes respectively, and each lower electrode layer in the storage hole is electrically connected to the first contact structure below it; A storage material layer is formed that continuously covers the surfaces of the multiple lower electrode layers, and an upper electrode material layer is formed that covers the storage material layer; The storage material layer and the upper electrode material layer are etched to form a continuous partition trench that runs through the upper electrode material layer and the storage material layer. The partition trench divides the storage material layer into storage layers located in a plurality of storage holes and divides the upper electrode material layer into a plurality of upper electrode layers that cover the surfaces of the plurality of storage layers. At least two upper electrode layers are interconnected to form the upper electrode interconnect structure, and the plurality of upper electrode interconnect structures are independent of each other.

[0010] In some embodiments, the specific steps of forming a plurality of lower electrode layers that respectively cover the inner walls of the plurality of storage holes, and wherein each lower electrode layer in each storage hole is electrically connected to the first contact structure below it, include: A lower electrode material layer is formed that continuously covers the inner walls of the multiple storage holes; A sacrificial material layer is formed that covers the surface of the lower electrode material layer and continuously fills the plurality of storage holes; The lower electrode material layer and the sacrificial material layer are patterned to form multiple independent lower electrode layers and multiple sacrificial layers corresponding to the multiple lower electrode layers. The multiple lower electrode layers cover the inner walls of the multiple storage holes in a one-to-one correspondence. The lower electrode layer in each storage hole is electrically connected to the first contact structure below it. Remove the sacrificial layer to expose the surface of the lower electrode layer.

[0011] In some embodiments, the specific steps of forming a plurality of lower electrode layers that respectively cover the inner walls of the plurality of storage holes, and wherein each lower electrode layer in each storage hole is electrically connected to the first contact structure below it, include: A lower electrode material layer is formed that continuously covers the inner walls of the multiple storage holes; A sacrificial material layer is formed that covers the surface of the lower electrode material layer and continuously fills the plurality of storage holes; The lower electrode material layer and the sacrificial material layer are patterned to form a plurality of lower electrode layers and a plurality of sacrificial layers corresponding one-to-one with the plurality of lower electrode layers. The plurality of lower electrode layers cover the inner walls of the plurality of storage holes one-to-one. The lower electrode layer in each storage hole is electrically connected to the first contact structure below it. At least two lower electrode layers are interconnected to form a lower electrode interconnect structure, and the plurality of lower electrode interconnect structures are independent of each other. Remove the sacrificial layer to expose the surface of the lower electrode interconnect structure and the surface of the separate lower electrode layer.

[0012] In some embodiments, before etching the storage material layer and the upper electrode material layer, the following steps are further included: A conductive filling material layer is formed that covers the surface of the upper electrode material layer and continuously fills the plurality of storage holes; An insulating material layer is formed that covers the conductive filler material layer.

[0013] In some embodiments, the specific steps of etching the storage material layer and the upper electrode material layer to form a continuous partition trench penetrating the upper electrode material layer and the storage layer include: The insulating material layer, the conductive filling material layer, the upper electrode material layer, and the storage material layer are etched to form a partition trench that continuously penetrates the insulating material layer, the conductive filling material layer, the upper electrode material layer, and the storage material layer. The partition trench divides the insulating material layer into multiple insulating layers, the conductive filling material layer into multiple conductive filling layers, the storage material layer into storage layers located in multiple storage holes, and the upper electrode material layer into multiple upper electrode layers covering the surfaces of the multiple storage layers.

[0014] In some embodiments, the specific steps of forming a plurality of first lead-out structures located above the substrate and electrically isolated from each other, and electrically connecting the plurality of first lead-out structures to the plurality of upper electrode interconnect structures in a one-to-one correspondence, include: A top dielectric layer is formed covering the substrate and the storage structure; A first lead-out structure is formed that penetrates the top dielectric layer and is electrically connected to the upper electrode interconnect structure.

[0015] In some embodiments, the specific steps of forming the first lead-out structure that penetrates the top dielectric layer and is electrically connected to the upper electrode interconnect structure include: A first lead-out hole is formed that penetrates the top dielectric layer and exposes the upper electrode interconnect structure; A first lead-out post is formed to fill the first lead-out hole and a first pad is formed to cover the surface of the top dielectric layer and electrically connected to the first lead-out post. The plurality of first lead-out posts are electrically connected to the plurality of upper electrode interconnect structures one by one, and the plurality of first pads are independent of each other.

[0016] According to other embodiments, the present invention also provides a three-dimensional memory structure, comprising: The substrate includes a substrate, a bottom dielectric layer located on the substrate, a plurality of first contact structures that penetrate the bottom dielectric layer and are spaced apart along a first direction, an intermediate dielectric layer that covers the bottom dielectric layer and the first contact structures, and a plurality of storage holes that penetrate the intermediate dielectric layer and expose the plurality of first contact structures respectively. Multiple storage structures are located within multiple storage holes. Each storage structure includes a lower electrode layer electrically connected to the first contact structure, a storage layer covering the lower electrode layer, and an upper electrode layer covering the storage layer. The upper electrode layers of at least two storage structures are electrically connected to form an upper electrode interconnect structure, and the multiple upper electrode interconnect structures are independent of each other. Multiple first lead-out structures are located above the substrate and electrically isolated from each other, and the multiple first lead-out structures are electrically connected to the multiple upper electrode interconnect structures in a one-to-one correspondence.

[0017] In some embodiments, the lower electrode layers in the plurality of storage structures cover the inner walls of the plurality of storage holes in a one-to-one correspondence, the lower electrode layers in any two adjacent storage structures are independent of each other, and the lower electrode layer in each storage hole is electrically connected to the first contact structure below it.

[0018] In some embodiments, the lower electrode layers in the plurality of storage structures cover the inner walls of the plurality of storage holes one by one, and the lower electrode layer in each storage hole is electrically connected to the first contact structure below it. At least two lower electrode layers are interconnected to form a lower electrode interconnect structure, and the plurality of lower electrode interconnect structures are independent of each other.

[0019] In some embodiments, it also includes: A conductive filling layer covers the surface of the upper electrode layer and fills the storage hole. The conductive filling layer located on the upper electrode interconnect structure is connected to form a filled interconnect structure. The first lead-out structure is electrically connected to the filled interconnect structure.

[0020] In some embodiments, a top-layer medium layer covering the substrate and the storage structure is also included; The first lead-out structure includes a first lead-out post that penetrates the top dielectric layer and is electrically connected to the upper electrode interconnect structure, and a first pad that covers the surface of the top dielectric layer and is electrically connected to the first lead-out post. The plurality of first lead-out posts are electrically connected to the plurality of upper electrode interconnect structures one by one, and the plurality of first pads are independent of each other.

[0021] The three-dimensional memory structure and its formation method provided by this invention, during the formation of the memory structure, electrically connects the upper electrode layers of at least two of the memory structures to form an upper electrode interconnect structure, and the multiple upper electrode interconnect structures are independent of each other. This completes the interconnection process of the upper electrode layers before forming the interconnect structure, thus eliminating the need for manufacturing upper metal interconnect lines for electrically connecting the lower electrode layers after the memory structure is formed. This reduces the number of process steps in the three-dimensional memory structure manufacturing process, reduces the consumption of raw materials (such as dielectric materials and metal materials), and improves the manufacturing efficiency and reduces the manufacturing cost of the three-dimensional memory structure. Furthermore, since the upper electrode interconnect structure is formed through direct interconnection of the upper electrode layers, it helps to improve the flexibility of circuit design and interconnection to adapt to various chip integration requirements. In addition, the reduction in process steps helps to reduce the defect rate, thereby improving the manufacturing yield of the three-dimensional memory structure.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a flowchart of the manufacturing method of the three-dimensional memory structure in a specific embodiment of the present invention; Figure 2 This is a schematic diagram of the structure after the first contact structure is formed in a specific embodiment of the present invention; Figure 3 This is a schematic diagram of the structure after the intermediate dielectric layer is formed in a specific embodiment of the present invention; Figure 4 This is a schematic diagram of the structure after the storage hole is formed in a specific embodiment of the present invention; Figure 5 This is a schematic diagram of the structure after the lower electrode material layer is formed in a specific embodiment of the present invention; Figure 6 This is a schematic diagram of the structure after the sacrificial material layer is formed in a specific embodiment of the present invention; Figure 7 This is a schematic diagram of the structure after the lower electrode layer is formed in a specific embodiment of the present invention; Figure 8 This is a schematic diagram of the structure after the formation of the storage material layer and the upper electrode material layer in a specific embodiment of the present invention; Figure 9 This is a schematic diagram of the structure after the formation of the conductive filling material layer and the insulating material layer in a specific embodiment of the present invention; Figure 10 This is a schematic diagram of the structure after the storage structure is formed in a specific embodiment of the present invention; Figure 11 This is a schematic diagram of the structure after the top dielectric layer is formed in a specific embodiment of the present invention; Figure 12 This is a schematic diagram of a structure after the first lead-out structure is formed in a specific embodiment of the present invention; Figure 13 This is another structural schematic diagram after the lower electrode layer is formed in a specific embodiment of the present invention; Figure 14 This is another structural diagram after the first lead-out structure is formed in a specific embodiment of the present invention.

[0025] Explanation of reference numerals in the attached figures 20 substrate 21. Bottom Dielectric Layer 22 gate dielectric layer 23 Gate conductive layer 24 isolation sidewalls 25 First contact structure 30 First Intermediate Layer 31 Second Intermediate Layer 32 Third Intermediate Layer 40 storage holes 50 Lower electrode material layer 60 sacrificial material layers 61 First photoresist layer 62 First Etching Window 70 Lower Electrode Layer 80 storage material layers 81 Upper electrode material layer 81 Upper electrode material layer 90 conductive filler layer 91 layers of isolation material 100 storage layers 101 Upper Electrode Layer 102 conductive filler layer 103 isolation layer 111 First Top Dielectric Layer 112 Second Top Dielectric Layer 113 Third Top Dielectric Layer 121 First Lead-out Column 122 First pad Detailed Implementation The technical solutions in the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] This specific embodiment provides a method for forming a three-dimensional memory structure. Figure 1 This is a flowchart illustrating the manufacturing method of a three-dimensional memory structure according to a specific embodiment of the present invention. Figure 1 As shown, the method for forming the three-dimensional memory structure includes the following steps: Step S11: Form a substrate, the substrate including a substrate, a bottom dielectric layer on the substrate, a plurality of first contact structures that penetrate the bottom dielectric layer and are spaced apart along a first direction, an intermediate dielectric layer that covers the bottom dielectric layer and the first contact structures, and a plurality of storage holes that penetrate the intermediate dielectric layer and expose the plurality of first contact structures respectively. Step S12: Form multiple storage structures located in the multiple storage holes respectively. Each storage structure includes a lower electrode layer electrically connected to the first contact structure, a storage layer covering the lower electrode layer, and an upper electrode layer covering the storage layer. The upper electrode layers of at least two of the storage structures are electrically connected to form an upper electrode interconnect structure, and the multiple upper electrode interconnect structures are independent of each other. Step S13: A plurality of first lead-out structures are formed above the substrate and electrically isolated from each other, and the plurality of first lead-out structures are electrically connected to the plurality of upper electrode interconnect structures in a one-to-one correspondence.

[0027] Figure 2 This is a schematic diagram of the structure after the first contact structure is formed in a specific embodiment of the present invention. Figure 3 This is a schematic diagram of the structure after the intermediate dielectric layer is formed in a specific embodiment of the present invention. Figure 4 This is a schematic diagram of the structure after the storage hole is formed in a specific embodiment of the present invention. In some embodiments, such as... Figure 2 , Figure 3 and Figure 4As shown, the specific steps for forming the substrate include: A substrate 20 is provided, the substrate 20 including a plurality of active regions, and the substrate 20 including a top surface and a bottom surface that are distributed opposite to each other. The active regions include a channel region and source regions and drain regions distributed on opposite sides of the channel region. The bottom dielectric layer 21 is formed to cover the top surface of the substrate 20; A plurality of first contact structures 25 are formed that penetrate the bottom dielectric layer 21 along the second direction D2 and are electrically connected to the plurality of drain regions one by one. The second direction D2 intersects the top surface of the substrate perpendicularly. An intermediate dielectric layer is formed that covers the bottom dielectric layer and the first contact structure 25; A plurality of storage holes 40 are formed that penetrate the intermediate dielectric layer along the second direction D2 and expose a plurality of the first contact structures 25 in a one-to-one correspondence.

[0028] In some embodiments, the intermediate dielectric layer includes: A first intermediate dielectric layer 30 covers the bottom dielectric layer 21 and the first contact structure 25, and the material of the first intermediate dielectric layer 30 includes silicon nitride; A second intermediate dielectric layer 31 covers the first intermediate dielectric layer 30, and the material of the second intermediate dielectric layer 31 includes silicon dioxide; A third intermediate dielectric layer 32 covers the second intermediate dielectric layer 31, and the material of the third intermediate dielectric layer 32 includes silicon oxynitride.

[0029] Specifically, the substrate 20 may be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example for illustration. The substrate 20 includes a top surface and a bottom surface that are distributed opposite to each other. The substrate 20 includes at least a plurality of active regions arranged at intervals along the first direction D1 and shallow trench isolation regions located between adjacent active regions. The first direction D1 is parallel to the top surface of the substrate 20. Each active region includes a channel region and source and drain regions distributed on opposite sides of the channel region along a third direction. The third direction is parallel to the top surface of the substrate 20 and intersects the first direction D1 (e.g., perpendicularly or obliquely). A gate structure is also disposed on the top surface of the substrate 20. The gate structure includes a gate dielectric layer 22 located above the channel region, a gate conductive layer 23 covering the surface of the gate dielectric layer 22, and isolation sidewalls 24 covering the sidewalls of the gate dielectric layer 22 and the sidewalls of the gate conductive layer 23, such as Figure 2As shown. The bottom dielectric layer 21 covers the top surface of the substrate 20 and the gate structure. In one example, the material of the bottom dielectric layer 21 can be an oxide material, such as silicon dioxide. After forming the bottom dielectric layer 21, a first contact hole penetrating the bottom dielectric layer 21 along the second direction D2 and exposing the drain region and a second contact hole penetrating the bottom dielectric layer 21 along the second direction D2 and exposing the source region can be formed by etching. Then, a material such as tungsten is deposited in the first contact hole and the second contact hole by deposition, forming a plurality of first contact structures 25 that are electrically connected to the drain regions of the plurality of active regions one by one, and forming a second contact structure that is electrically connected to the source region. In this specific embodiment, "plural" refers to two or more.

[0030] After forming the first contact structure 25 and the second contact structure, silicon nitride is deposited on the bottom dielectric layer 21 to form a first intermediate dielectric layer 30 covering the bottom dielectric layer 21, the first contact structure 25, and the second contact structure. Next, silicon dioxide is deposited on the first intermediate dielectric layer 30 to form a second intermediate dielectric layer 31 covering the first intermediate dielectric layer 30. Then, silicon oxynitride is deposited on the second intermediate dielectric layer 31 to form a third intermediate dielectric layer 32 covering the second intermediate dielectric layer 31, as follows... Figure 3 As shown, the first intermediate dielectric layer 30, the second intermediate dielectric layer 31, and the third intermediate dielectric layer 32 together serve as the intermediate dielectric layer.

[0031] After the intermediate dielectric layer is formed, etching is performed downwards from the top surface of the intermediate dielectric layer away from the substrate 20 (e.g., the surface of the third intermediate dielectric layer 32 away from the substrate 20) to form the storage via 40, which penetrates the intermediate dielectric layer at least along the second direction D2 and exposes at least the top surface of the first contact structure 25 away from the substrate 20. Figure 4 As shown. In one example, the storage hole 40 only penetrates the intermediate dielectric layer, meaning that the bottom of the storage hole 40 only exposes the top surface of the first contact structure 25. In another example, the storage hole 40 penetrates the intermediate dielectric layer and extends into the bottom dielectric layer 21, such that the storage hole 40 exposes the top surface and part of the sidewall of the first contact structure 25, thereby increasing the area of ​​the subsequently formed storage structure.

[0032] Figure 5 This is a schematic diagram of the structure after the lower electrode material layer is formed in a specific embodiment of the present invention. Figure 6 This is a schematic diagram of the structure after the sacrificial material layer is formed in a specific embodiment of the present invention. Figure 7This is a schematic diagram of the structure after the lower electrode layer is formed in a specific embodiment of the present invention. Figure 8 This is a schematic diagram of the structure after the formation of the storage material layer and the upper electrode material layer in a specific embodiment of the present invention. Figure 9 This is a schematic diagram of the structure after the formation of the conductive filling material layer and the insulating material layer in a specific embodiment of the present invention. Figure 10 This is a schematic diagram of the structure after the storage structure has been formed in a specific embodiment of the present invention. In some embodiments, the specific steps for forming multiple storage structures located within the multiple storage holes 40 include: Multiple lower electrode layers 70 are formed, each covering the inner wall of one of the storage holes 40, and each lower electrode layer 70 within each storage hole 40 is electrically connected to the first contact structure 25 below it, such as... Figure 7 As shown; A storage material layer 80 is formed that continuously covers the surfaces of the plurality of lower electrode layers 70, and an upper electrode material layer 81 is formed that covers the storage material layer 80, such as... Figure 8 As shown; The storage material layer 80 and the upper electrode material layer 81 are etched to form a continuous partition trench penetrating the upper electrode material layer 81 and the storage material layer 80. The partition trench divides the storage material layer 80 into storage layers 100 located within a plurality of storage vias 40, and divides the upper electrode material layer 81 into a plurality of upper electrode layers 101 covering the surfaces of the plurality of storage layers 100. At least two upper electrode layers 101 are interconnected to form an upper electrode interconnect structure, and the plurality of upper electrode interconnect structures are independent of each other, such as... Figure 10 As shown.

[0033] In some embodiments, the specific steps of forming a plurality of lower electrode layers 70 that respectively cover the inner walls of the plurality of storage holes 40, and wherein each lower electrode layer 70 in each storage hole 40 is electrically connected to the first contact structure 25 below it include: A lower electrode material layer 50 is formed to continuously cover the inner walls of the plurality of storage holes 40, such as... Figure 5 As shown; A sacrificial material layer 60 is formed, covering the surface of the lower electrode material layer 50 and continuously filling the plurality of storage holes 40, such as... Figure 6 As shown; The lower electrode material layer 50 and the sacrificial material layer 60 are patterned to form multiple independent lower electrode layers 70 and multiple sacrificial layers corresponding to each lower electrode layer 70. Each lower electrode layer 70 covers the inner wall of a plurality of storage holes 40, and each lower electrode layer 70 within a storage hole 40 is electrically connected to the first contact structure 25 below it. Figure 7 As shown; Remove the sacrificial layer to expose the surface of the lower electrode layer 70.

[0034] For example, after forming a plurality of storage holes 40 spaced apart along the first direction D1 in the substrate, an electrode material such as titanium nitride is deposited on the substrate using a chemical vapor deposition process or an atomic layer deposition process to form a lower electrode material layer 50 that continuously covers the inner walls of the plurality of storage holes 40 and the top surface of the intermediate dielectric layer (i.e., the surface of the intermediate dielectric layer facing away from the substrate 20). Figure 5 As shown. In one example, the thickness of the lower electrode material layer 50 is 10 nm to 20 nm. Next, a bottom anti-reflective layer (BARC) or similar material is deposited on the substrate to form the sacrificial material layer 60, which covers the surface of the lower electrode material layer 50 and continuously fills the plurality of memory holes 40, as shown. Figure 6 As shown. Using a bottom anti-reflective layer as the sacrificial material layer 60 eliminates reflection and standing wave effects in subsequent photolithography processes, thereby improving the accuracy of the photolithography pattern. Next, a first photoresist layer 61 is formed on the surface of the sacrificial material layer 60 facing away from the substrate 20. A first etching window 62 exposing the sacrificial material layer 60 is formed in the first photoresist layer 61 using photolithography. A dry etching process is used to etch the sacrificial material layer 60 and the lower electrode material layer 50 downwards along the first etching window 62, forming a plurality of first openings penetrating the sacrificial material layer 60 and the lower electrode material layer 50 along the second direction D2. The plurality of first openings divide the lower electrode material layer 50 into a plurality of independent lower electrode layers 70, and divide the sacrificial layer 60 into a plurality of sacrificial layers corresponding one-to-one with the plurality of lower electrode layers 70. The plurality of lower electrode layers 70 correspond one-to-one with the inner walls of the plurality of storage holes 40, and the lower electrode layer 70 in each storage hole 40 is electrically connected to the first contact structure 25 below it.

[0035] In this specific embodiment, before forming the memory layer and the upper electrode layer, the lower electrode material layer 50 is etched using a combination of photolithography and dry etching to form multiple independent lower electrode layers 70. On the one hand, this allows for precise control of the shape and size of the lower electrode layers 70, ensuring the stability and reliability of the subsequently formed memory structure. On the other hand, pre-dividing the lower electrode material layer 50 ensures that the connections between lower electrode layers 70 in adjacent memory structures are fully disconnected, improving the manufacturing yield of the three-dimensional memory structure. Furthermore, pre-dividing the lower electrode material layer 50 before forming the lower electrode layers 70 increases the flexibility of the lower electrode layer 70 design (e.g., the design of the lower electrode layer 70 structure and morphology) to meet the specific manufacturing requirements of the three-dimensional memory structure.

[0036] In some embodiments, before etching the storage material layer 80 and the upper electrode material layer 81, the following steps are further included: A conductive filling material layer 90 is formed that covers the surface of the upper electrode material layer 81 and is continuously filled into the plurality of storage holes 40; An insulating material layer 91 is formed covering the conductive filling material layer 90, such as... Figure 9 As shown.

[0037] Specifically, in the formation of such Figure 7 After the plurality of lower electrode layers 70 are shown, a ferroelectric material or a phase change material is deposited on the substrate to form a storage material layer 80 that continuously covers the surfaces of the plurality of lower electrode layers 70. Next, an electrode material such as titanium nitride is deposited on the substrate to form an upper electrode material layer 81 that covers the storage material layer 80, such as... Figure 8 As shown. Next, a conductive material such as tungsten is deposited on the substrate using a chemical vapor deposition process to form a conductive filler material layer 90 that covers the surface of the upper electrode material layer 81 and continuously fills the plurality of storage holes 40. Then, the conductive filler material layer 90 is subjected to planarization treatments such as chemical mechanical polishing to improve the flatness of its surface. Next, a thin layer of silicon oxynitride or silicon nitride is deposited on the surface of the conductive filler material layer 90 as the isolation material layer 91. The isolation material layer 91 protects the conductive filler material layer 90, preventing subsequent processes from contaminating or damaging the underlying conductive filler material layer 90.

[0038] In some embodiments, the specific steps of etching the storage material layer 80 and the upper electrode material layer 81 to form a continuous partition trench penetrating the upper electrode material layer 81 and the storage material layer 80 include: The insulating material layer 91, the conductive filling material layer 90, the upper electrode material layer 81, and the storage material layer 80 are etched to form a continuous partition trench penetrating the insulating material layer 91, the conductive filling material layer 90, the upper electrode material layer 81, and the storage material layer 80. The partition trench divides the insulating material layer 91 into multiple insulating layers 103, the conductive filling material layer 90 into multiple conductive filling layers 102, the storage material layer 80 into storage layers 100 located within multiple storage holes 40, and the upper electrode material layer 81 into multiple upper electrode layers 101 covering the surfaces of the multiple storage layers 100. Figure 10 As shown.

[0039] Specifically, by etching the isolation material layer 91, the conductive filling material layer 90, the upper electrode material layer 81, and the storage material layer 80, a plurality of partition grooves are formed that continuously penetrate the isolation material layer 91, the conductive filling material layer 90, the upper electrode material layer 81, and the storage material layer 80. This allows for patterning of the isolation material layer 91, the conductive filling material layer 90, the upper electrode material layer 81, and the storage material layer 80. The partition grooves divide the isolation material layer 91 into a plurality of isolation layers 103, the conductive filling material layer 90 into a plurality of conductive filling layers 102, the storage material layer 80 into storage layers 100 located within a plurality of storage holes 40, and the upper electrode material layer 81 into a plurality of upper electrode layers 101 covering the surfaces of the plurality of storage layers 100. Through the above-described graphical processing, not only is electrical isolation between adjacent memory structures achieved (since the lower electrode layers 70 in adjacent memory structures are isolated from each other, the adjacent memory structures are electrically isolated), but also the interconnection between multiple upper electrode layers 101 is achieved by forming the upper electrode interconnect structure, thus realizing the function of upper metal interconnect lines.

[0040] Figure 11 This is a schematic diagram of the structure after the top dielectric layer is formed in a specific embodiment of the present invention. Figure 12 This is a schematic diagram of a structure after the formation of the first lead-out structure in a specific embodiment of the present invention. In some embodiments, the specific steps of forming a plurality of first lead-out structures located above the substrate and electrically isolated from each other, and electrically connecting the plurality of first lead-out structures to the plurality of upper electrode interconnect structures in a one-to-one correspondence, include: A top dielectric layer is formed covering the substrate and the storage structure; A first lead-out structure is formed that penetrates the top dielectric layer and is electrically connected to the upper electrode interconnect structure.

[0041] In some embodiments, the specific steps of forming the first lead-out structure that penetrates the top dielectric layer and is electrically connected to the upper electrode interconnect structure include: A first lead-out hole is formed that penetrates the top dielectric layer and exposes the upper electrode interconnect structure; A first lead-out post 121 is formed and filled in the first lead-out hole, and a first pad 122 is formed on the surface of the top dielectric layer and electrically connected to the first lead-out post 121. The plurality of first lead-out posts 121 are electrically connected to the plurality of upper electrode interconnect structures one by one, and the plurality of first pads 122 are independent of each other.

[0042] Specifically, such as Figure 11 As shown, silicon nitride is deposited on the substrate to form a first top dielectric layer 111 covering the top surface of the intermediate dielectric layer and the storage structure. Silicon dioxide is deposited on the substrate to form a second top dielectric layer 112 covering the first top dielectric layer 111. Silicon oxynitride is deposited on the substrate to form a third top dielectric layer 113 covering the second top dielectric layer 112, and the first top dielectric layer 111, the second top dielectric layer 112, and the third top dielectric layer 113 together constitute the top dielectric layer. Figure 11 As shown. Then, the top dielectric layer is etched using an etching process to form a first lead-out hole exposing the upper electrode interconnect structure. A metal material such as tungsten is filled into the first lead-out hole to form the first lead-out post. Next, a metal material such as copper is deposited on the top surface of the top dielectric layer facing away from the substrate 20 to form a first pad 122 electrically connected to the first lead-out post 121. The first lead-out post 121 and the first pad 122 electrically connected to it together constitute a first lead-out structure, as shown. Figure 12 As shown.

[0043] In this specific embodiment, because the interconnection between multiple upper electrode layers 101 is achieved during the process of forming the upper electrode layer 101 by patterning the upper electrode material layer 81, the function of upper metal interconnect lines is realized. Therefore, during the formation of the first lead-out structure, it is not necessary to form a metal interconnect layer for electrically connecting multiple upper electrode layers 101 on the top dielectric layer, saving the entire manufacturing process of the metal interconnect layer. This not only simplifies the manufacturing process of the three-dimensional memory structure and improves the manufacturing yield of the three-dimensional memory structure, but also reduces the loss of raw materials and equipment occupation, thereby reducing the manufacturing cost of the three-dimensional memory structure. In addition, because the interconnection between multiple upper electrode layers 101 is achieved during the process of forming the upper electrode layer 101 by patterning the upper electrode material layer 81, the interconnection between different upper electrode layers 101 can be flexibly selected as needed, realizing the diversity and freedom of circuit design.

[0044] Figure 13 This is another structural schematic diagram after the lower electrode layer is formed in a specific embodiment of the present invention. Figure 14 This is another structural diagram after the formation of the first lead-out structure in a specific embodiment of the present invention. In some other embodiments, the specific steps of forming a plurality of lower electrode layers 70 respectively covering the inner walls of the plurality of storage holes 40, and wherein each lower electrode layer 70 in the storage hole 40 is electrically connected to the first contact structure 25 below it, include: A lower electrode material layer 50 is formed to continuously cover the inner walls of the plurality of storage holes 40, such as... Figure 5 As shown; A sacrificial material layer 60 is formed to cover the surface of the lower electrode material layer 50 and continuously fill the plurality of storage holes 40; The lower electrode material layer 50 and the sacrificial material layer 60 are patterned to form a plurality of lower electrode layers 70 and a plurality of sacrificial layers corresponding one-to-one with the plurality of lower electrode layers 70. The plurality of lower electrode layers 70 cover the inner walls of the plurality of storage holes 40. Each lower electrode layer 70 within a storage hole 40 is electrically connected to the first contact structure 25 below it. At least two lower electrode layers 70 are interconnected to form a lower electrode interconnect structure, and the plurality of lower electrode interconnect structures are independent of each other. Figure 13 As shown; Remove the sacrificial layer to expose the surface of the lower electrode interconnect structure and the surface of the separate lower electrode layer 70.

[0045] For example, after forming a plurality of storage holes 40 spaced apart along the first direction D1 in the substrate, an electrode material such as titanium nitride is deposited on the substrate using a chemical vapor deposition process or an atomic layer deposition process to form a lower electrode material layer 50 that continuously covers the inner walls of the plurality of storage holes 40 and the top surface of the intermediate dielectric layer (i.e., the surface of the intermediate dielectric layer facing away from the substrate 20). Figure 5As shown. In one example, the thickness of the lower electrode material layer 50 is 10nm~20nm. Next, a bottom anti-reflective layer (BARC) or similar material is deposited on the substrate to form a sacrificial material layer 60 that covers the surface of the lower electrode material layer 50 and continuously fills the plurality of memory holes 40. Then, a second photoresist layer is formed on the surface of the sacrificial material layer 60 facing away from the substrate 20. A second etching window exposing the sacrificial material layer 60 is formed in the second photoresist layer using a photolithography process. A dry etching process is used to etch the sacrificial material layer 60 and the lower electrode material layer 50 downwards along the second etching window, forming a plurality of second openings penetrating the sacrificial material layer 60 and the lower electrode material layer 50 along the second direction D2. The plurality of second openings divide the lower electrode material layer 50 into a plurality of lower electrode layers 70, and the plurality of lower electrode layers 70 are interconnected to form the lower electrode interconnect structure, such as... Figure 13 As shown.

[0046] After removing the sacrificial layer and the second photoresist layer, a ferroelectric material or phase change material is deposited on the substrate to form a storage material layer that continuously covers the surfaces of the plurality of lower electrode layers 70. Next, an electrode material such as titanium nitride is deposited on the substrate to form an upper electrode material layer covering the storage material layer. Then, a conductive material such as tungsten is deposited on the substrate using a chemical vapor deposition process to form a conductive filling material layer that covers the surface of the upper electrode material layer and continuously fills the plurality of storage holes. Next, the conductive filling material layer is planarized using chemical mechanical polishing or other methods to improve the flatness of its surface. Finally, a thin layer of silicon oxynitride or silicon nitride is deposited on the surface of the conductive filling material layer as the isolation material layer. Next, the isolation material layer, the conductive filling material layer, the upper electrode material layer, and the storage material layer are etched to form a partition trench that continuously penetrates the isolation material layer, the conductive filling material layer, the upper electrode material layer, and the storage material layer. The partition trench divides the isolation material layer into multiple isolation layers 103, the conductive filling material layer into multiple conductive filling layers 102, the storage material layer into storage layers 100 located within multiple storage vias 40, and the upper electrode material layer into multiple upper electrode layers 101 covering the surfaces of the multiple storage layers 100. The multiple upper electrode layers 101 are electrically connected to form the upper electrode interconnect structure. (See [reference]) Figure 14During the etching process of patterning the memory material layer and the upper electrode material layer, the formed partition trench should be aligned with the second opening formed during the patterning of the lower electrode material layer 50. Subsequently, a top dielectric layer covering the substrate and the memory structure, and a first lead-out structure penetrating the top dielectric layer and electrically connected to the upper electrode interconnect structure are formed, such as... Figure 14 As shown.

[0047] By forming the lower electrode layer 70 through the patterning of the lower electrode material layer, multiple lower electrode layers 70 are electrically connected to form the lower electrode interconnect structure. The partition grooves formed during the patterning of the storage material layer and the upper electrode material layer are aligned with the second opening formed during the patterning of the lower electrode material layer 50. This not only enables the interconnection between multiple upper electrode layers 101 during the patterning of the upper electrode material layer 81 to form the upper electrode layer 101, realizing the function of upper metal interconnects, but also enables the electrical connection between adjacent storage structures. This increases the polarization area, enhances the storage performance of the device, and helps to realize more complex circuit connection topologies, further improving the diversity and flexibility of circuit design.

[0048] This specific embodiment also provides a three-dimensional memory structure. The three-dimensional memory structure can adopt, for example... Figures 1-14 The method for forming the three-dimensional memory structure shown is used, and a schematic diagram of the three-dimensional memory structure can be found in [reference needed]. Figure 12 and Figure 14 .like Figures 1-14 As shown, the three-dimensional memory structure includes: The substrate includes a substrate 20, a bottom dielectric layer 21 located on the substrate, a plurality of first contact structures 25 that penetrate the bottom dielectric layer 21 and are spaced apart along a first direction D1, an intermediate dielectric layer that covers the bottom dielectric layer 21 and the first contact structures 25, and a plurality of storage holes 40 that penetrate the intermediate dielectric layer and expose the plurality of first contact structures 25 respectively. Multiple storage structures are located within multiple storage holes 40. Each storage structure includes a lower electrode layer 70 electrically connected to the first contact structure 25, a storage layer 100 covering the lower electrode layer 70, and an upper electrode layer 101 covering the storage layer 100. The upper electrode layers 101 in at least two of the storage structures are electrically connected to form an upper electrode interconnect structure, and the multiple upper electrode interconnect structures are independent of each other. Multiple first lead-out structures are located above the substrate and electrically isolated from each other, and the multiple first lead-out structures are electrically connected to the multiple upper electrode interconnect structures in a one-to-one correspondence.

[0049] In some embodiments, the lower electrode layers 70 in the plurality of storage structures cover the inner walls of the plurality of storage holes 40 in a one-to-one correspondence. The lower electrode layers 70 in any two adjacent storage structures are independent of each other, and the lower electrode layer 70 in each storage hole 40 is electrically connected to the first contact structure 25 below it.

[0050] In some embodiments, the lower electrode layers 70 in the plurality of storage structures cover the inner walls of the plurality of storage holes 40 in a one-to-one correspondence. The lower electrode layer 70 in each storage hole 40 is electrically connected to the first contact structure 25 below it. At least two lower electrode layers 70 are interconnected to form a lower electrode interconnect structure, and the plurality of lower electrode interconnect structures are independent of each other.

[0051] In some embodiments, the three-dimensional memory structure further includes: A conductive filling layer 102 covers the surface of the upper electrode layer 101 and fills the storage hole 40. The conductive filling layer 102 located on the upper electrode interconnect structure is connected to form a filled interconnect structure. The first lead-out structure is electrically connected to the filled interconnect structure.

[0052] In some embodiments, the three-dimensional memory structure further includes a top dielectric layer covering the substrate and the memory structure; The first lead-out structure includes a first lead-out post 121 that penetrates the top dielectric layer and is electrically connected to the upper electrode interconnect structure, and a first pad 122 that covers the surface of the top dielectric layer and is electrically connected to the first lead-out post 121. The plurality of first lead-out posts 121 are electrically connected to the plurality of upper electrode interconnect structures one by one, and the plurality of first pads 122 are independent of each other.

[0053] The three-dimensional memory structure and its formation method provided in this specific embodiment, by electrically connecting the upper electrode layers of at least two memory structures to form an upper electrode interconnect structure during the formation of the memory structure, and with multiple upper electrode interconnect structures being independent of each other, completes the interconnection process of the upper electrode layers before forming the interconnect structure. Therefore, after forming the memory structure, there is no need to perform the manufacturing process of upper metal interconnect lines for electrically connecting the lower electrode layers, reducing the number of process steps in the three-dimensional memory structure manufacturing, reducing the consumption of raw materials (such as dielectric materials and metal materials), improving the manufacturing efficiency of the three-dimensional memory structure, and reducing the manufacturing cost. Furthermore, since the upper electrode interconnect structure is formed through direct interconnection of the upper electrode layers, it helps to improve the flexibility of circuit design and interconnection to adapt to various chip integration requirements. In addition, the reduction of process steps helps to reduce the defect rate, thereby improving the manufacturing yield of the three-dimensional memory structure.

[0054] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0055] It should be noted that the terms "comprising" and "having," and their variations, used in this invention document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context. It should be understood that such data used interchangeably where appropriate. Furthermore, embodiments and features within embodiments of this invention can be combined with each other unless otherwise specified. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar or identical parts between embodiments can be referred to interchangeably.

[0056] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for forming a three-dimensional memory structure, characterized in that, Includes the following steps: A substrate is formed, the substrate including a substrate, a bottom dielectric layer located on the substrate, a plurality of first contact structures that penetrate the bottom dielectric layer and are spaced apart along a first direction, an intermediate dielectric layer covering the bottom dielectric layer and the first contact structures, and a plurality of storage holes that penetrate the intermediate dielectric layer and expose the plurality of first contact structures respectively. Multiple storage structures are formed, each located within a plurality of storage holes. Each storage structure includes a lower electrode layer electrically connected to the first contact structure, a storage layer covering the lower electrode layer, and an upper electrode layer covering the storage layer. The upper electrode layers of at least two of the storage structures are electrically connected to form an upper electrode interconnect structure, and the plurality of upper electrode interconnect structures are independent of each other. A plurality of first lead-out structures are formed on the substrate and electrically isolated from each other, and the plurality of first lead-out structures are electrically connected to the plurality of upper electrode interconnect structures in a one-to-one correspondence.

2. The method for forming a three-dimensional memory structure according to claim 1, characterized in that, The specific steps for forming the substrate include: A substrate is provided, the substrate including a plurality of active regions, and the substrate including a top surface and a bottom surface that are distributed opposite to each other, the active regions including a channel region and source regions and drain regions distributed on opposite sides of the channel region; Form the bottom dielectric layer covering the top surface of the substrate; Multiple first contact structures are formed that penetrate the bottom dielectric layer along a second direction and are electrically connected to the multiple drain regions one by one, wherein the second direction intersects the top surface of the substrate perpendicularly; An intermediate dielectric layer is formed covering the bottom dielectric layer and the first contact structure; A plurality of storage holes are formed that penetrate the intermediate dielectric layer along the second direction and expose a plurality of the first contact structures one by one.

3. The method for forming a three-dimensional memory structure according to claim 1, characterized in that, The intermediate dielectric layer includes: A first intermediate dielectric layer covers the bottom dielectric layer and the first contact structure, and the material of the first intermediate dielectric layer includes silicon nitride; A second intermediate dielectric layer covering the first intermediate dielectric layer, wherein the material of the second intermediate dielectric layer includes silicon dioxide; A third intermediate dielectric layer covers the second intermediate dielectric layer, and the material of the third intermediate dielectric layer includes silicon oxynitride.

4. The method for forming a three-dimensional memory structure according to claim 1, characterized in that, The specific steps for forming multiple storage structures located within the multiple storage holes include: Multiple lower electrode layers are formed to cover the inner walls of the multiple storage holes respectively, and each lower electrode layer in the storage hole is electrically connected to the first contact structure below it; A storage material layer is formed that continuously covers the surfaces of the multiple lower electrode layers, and an upper electrode material layer is formed that covers the storage material layer; The storage material layer and the upper electrode material layer are etched to form a continuous partition trench that runs through the upper electrode material layer and the storage material layer. The partition trench divides the storage material layer into storage layers located in a plurality of storage holes and divides the upper electrode material layer into a plurality of upper electrode layers that cover the surfaces of the plurality of storage layers. At least two upper electrode layers are interconnected to form the upper electrode interconnect structure, and the plurality of upper electrode interconnect structures are independent of each other.

5. The method for forming a three-dimensional memory structure according to claim 4, characterized in that, The specific steps of forming a plurality of lower electrode layers that respectively cover the inner walls of the plurality of storage holes, and wherein each lower electrode layer in each storage hole is electrically connected to the first contact structure below it, include: A lower electrode material layer is formed that continuously covers the inner walls of the multiple storage holes; A sacrificial material layer is formed that covers the surface of the lower electrode material layer and continuously fills the plurality of storage holes; The lower electrode material layer and the sacrificial material layer are patterned to form multiple independent lower electrode layers and multiple sacrificial layers corresponding to the multiple lower electrode layers. The multiple lower electrode layers cover the inner walls of the multiple storage holes in a one-to-one correspondence. The lower electrode layer in each storage hole is electrically connected to the first contact structure below it. Remove the sacrificial layer to expose the surface of the lower electrode layer.

6. The method for forming a three-dimensional memory structure according to claim 4, characterized in that, The specific steps of forming a plurality of lower electrode layers that respectively cover the inner walls of the plurality of storage holes, and wherein each lower electrode layer in each storage hole is electrically connected to the first contact structure below it, include: A lower electrode material layer is formed that continuously covers the inner walls of the multiple storage holes; A sacrificial material layer is formed that covers the surface of the lower electrode material layer and continuously fills the plurality of storage holes; The lower electrode material layer and the sacrificial material layer are patterned to form a plurality of lower electrode layers and a plurality of sacrificial layers corresponding one-to-one with the plurality of lower electrode layers. The plurality of lower electrode layers cover the inner walls of the plurality of storage holes one-to-one. The lower electrode layer in each storage hole is electrically connected to the first contact structure below it. At least two lower electrode layers are interconnected to form a lower electrode interconnect structure, and the plurality of lower electrode interconnect structures are independent of each other. Remove the sacrificial layer to expose the surface of the lower electrode interconnect structure and the surface of the separate lower electrode layer.

7. The method for forming a three-dimensional memory structure according to claim 4, characterized in that, Before etching the storage material layer and the upper electrode material layer, the following steps are also included: A conductive filling material layer is formed that covers the surface of the upper electrode material layer and continuously fills the plurality of storage holes; An insulating material layer is formed that covers the conductive filler material layer.

8. The method for forming a three-dimensional memory structure according to claim 7, characterized in that, The specific steps of etching the storage material layer and the upper electrode material layer to form a continuous partition trench penetrating the upper electrode material layer and the storage material layer include: The insulating material layer, the conductive filling material layer, the upper electrode material layer, and the storage material layer are etched to form a partition trench that continuously penetrates the insulating material layer, the conductive filling material layer, the upper electrode material layer, and the storage material layer. The partition trench divides the insulating material layer into multiple insulating layers, the conductive filling material layer into multiple conductive filling layers, the storage material layer into storage layers located in multiple storage holes, and the upper electrode material layer into multiple upper electrode layers covering the surfaces of the multiple storage layers.

9. The method for forming a three-dimensional memory structure according to claim 1, characterized in that, The specific steps for forming a plurality of first lead-out structures located above the substrate and electrically isolated from each other, and for electrically connecting the plurality of first lead-out structures to the plurality of upper electrode interconnect structures in a one-to-one correspondence, include: A top dielectric layer is formed covering the substrate and the storage structure; A first lead-out structure is formed that penetrates the top dielectric layer and is electrically connected to the upper electrode interconnect structure.

10. The method for forming a three-dimensional memory structure according to claim 9, characterized in that, The specific steps for forming the first lead-out structure that penetrates the top dielectric layer and is electrically connected to the upper electrode interconnect structure include: A first lead-out hole is formed that penetrates the top dielectric layer and exposes the upper electrode interconnect structure; A first lead-out post is formed to fill the first lead-out hole and a first pad is formed to cover the surface of the top dielectric layer and electrically connected to the first lead-out post. The plurality of first lead-out posts are electrically connected to the plurality of upper electrode interconnect structures one by one, and the plurality of first pads are independent of each other.

11. A three-dimensional memory structure, characterized in that, include: The substrate includes a substrate, a bottom dielectric layer located on the substrate, a plurality of first contact structures that penetrate the bottom dielectric layer and are spaced apart along a first direction, an intermediate dielectric layer that covers the bottom dielectric layer and the first contact structures, and a plurality of storage holes that penetrate the intermediate dielectric layer and expose the plurality of first contact structures respectively. Multiple storage structures are located within multiple storage holes. Each storage structure includes a lower electrode layer electrically connected to the first contact structure, a storage layer covering the lower electrode layer, and an upper electrode layer covering the storage layer. The upper electrode layers of at least two storage structures are electrically connected to form an upper electrode interconnect structure, and the multiple upper electrode interconnect structures are independent of each other. Multiple first lead-out structures are located above the substrate and electrically isolated from each other, and the multiple first lead-out structures are electrically connected to the multiple upper electrode interconnect structures in a one-to-one correspondence.

12. The three-dimensional memory structure according to claim 11, characterized in that, The lower electrode layers in the plurality of storage structures correspond one-to-one with the inner walls of the plurality of storage holes. The lower electrode layers in any two adjacent storage structures are independent of each other, and the lower electrode layer in each storage hole is electrically connected to the first contact structure below it.

13. The three-dimensional memory structure according to claim 11, characterized in that, The lower electrode layers in the plurality of storage structures correspond one-to-one with the inner walls of the plurality of storage holes. The lower electrode layer in each storage hole is electrically connected to the first contact structure below it. At least two lower electrode layers are interconnected to form a lower electrode interconnect structure, and the plurality of lower electrode interconnect structures are independent of each other.

14. The three-dimensional memory structure according to claim 11, characterized in that, Also includes: A conductive filling layer covers the surface of the upper electrode layer and fills the storage hole. The conductive filling layer located on the upper electrode interconnect structure is connected to form a filled interconnect structure. The first lead-out structure is electrically connected to the filled interconnect structure.

15. The three-dimensional memory structure according to claim 11, characterized in that, It also includes a top-layer media layer covering the substrate and the storage structure; The first lead-out structure includes a first lead-out post that penetrates the top dielectric layer and is electrically connected to the upper electrode interconnect structure, and a first pad that covers the surface of the top dielectric layer and is electrically connected to the first lead-out post. The plurality of first lead-out posts are electrically connected to the plurality of upper electrode interconnect structures one by one, and the plurality of first pads are independent of each other.

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