A multi-bit resistive random access memory and its fabrication method, and electronic devices.

Abstract

This invention relates to the field of semiconductor memory technology, and discloses a multi-bit resistive switching memory (RSM) and its fabrication method and electronic device. The RSM includes a lower electrode, a resistive switching layer, a metal oxygen-absorbing layer, and a upper electrode. The resistive switching layer and the metal oxygen-absorbing layer are stacked between the lower and upper electrodes. The resistive switching layer comprises multiple alternately stacked oxygen barrier layers and multiple internal resistive switching layers. Along the direction close to the metal oxygen-absorbing layer, the physical thickness of the internal resistive switching layers increases in a gradient. This invention balances the local electric field strength and oxygen exchange capacity by configuring internal resistive switching layers with increasing thickness gradients. This allows each resistive switching region to undergo a sequential resistive state transition under a stepped voltage, achieving precise multi-level resistance state switching. Simultaneously, the oxygen barrier layers physically separate the resistive switching regions, cutting off the natural diffusion path of oxygen vacancies along the concentration gradient and preventing crosstalk between adjacent regions. This effectively improves the distinguishability and long-term data retention capability of the device's multi-bit storage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor storage technology, specifically to a multi-bit resistive random access memory (RRAM), its fabrication method, and an electronic device. Background Technology

[0002] Resistive random access memory (RANM) has become an important candidate technology for next-generation non-volatile memory due to its advantages such as simple structure, fast read / write speed, low power consumption, and high compatibility with mainstream microelectronic processes. In order to further improve storage density and meet the application requirements of high computing power scenarios, realizing multi-bit storage in a single storage cell has become an important development direction for current RAN technology.

[0003] Existing multi-bit resistive switching memories (RSMs) typically achieve multiple intermediate resistance states by applying different limiting currents or stepped scanning voltages during operation to alter the size of the conductive filaments or the concentration of oxygen vacancies within the resistive switching layer. However, conventional resistive switching layers usually employ a single, continuous thin-film structure, in which the distribution of oxygen ions and oxygen vacancies exhibits a high degree of randomness. When an external electric field is applied, the generation and diffusion paths of oxygen vacancies are difficult to precisely control, resulting in a lack of stable physical control mechanisms for variations in the morphology and thickness of the conductive filaments.

[0004] This microscopic uncontrollability causes significant resistance fluctuations in intermediate resistance states when the device repeatedly switches resistance states, resulting in overlapping resistance state distribution windows and making it difficult to achieve highly differentiated multi-level resistance states. Existing solutions often achieve multi-level states by adjusting doping elements or changing the composition of the resistive switching layer. However, simply optimizing device characteristics by doping with elements such as Al and Si often leads to an increase in the device's operating voltage. At the same time, there is a trade-off between multi-level windows and multi-bit writing capability; the low-resistance state of the device is difficult to further write to even lower resistance states, limiting the multi-bit storage density. In addition, to suppress the degradation of the high-resistance state, existing technologies often use inert metals (such as Ru) as the bottom electrode or interface layer. However, such materials are usually locked to the electrode side and do not fully utilize their low resistance and strong oxygen barrier capabilities to regulate the oxygen vacancy distribution and local electric field in different regions within the resistive switching layer.

[0005] Meanwhile, during the power-off retention phase of multi-bit devices, due to the significant local oxygen vacancy concentration gradient within the continuous resistive switching layer, the accumulated oxygen vacancies inevitably diffuse naturally into the surrounding low-concentration areas, causing spontaneous dissolution or reconstruction of the conductive filaments. This internal diffusion behavior, lacking physical barriers, leads to severe resistance drift in the device's intermediate resistance state over time. Therefore, effectively controlling the distribution and diffusion path of oxygen vacancies while achieving multi-bit storage, and addressing the issues of low resistance state differentiation and poor long-term stability, is a pressing technical challenge in current technologies. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the technical problem solved by this invention is that, when implementing multi-bit storage, existing resistive random access memories (RRAMs) suffer from uneven oxygen vacancy distribution and difficult-to-control diffusion paths within the resistive switching layer. This results in a lack of stable control mechanisms when the device switches between different resistance states, making it difficult to achieve multi-level resistance states with high distinguishability and long-term stability. Consequently, this limits the large-scale application of RRAMs in advanced fields such as in-memory computing, high-density memory arrays, and neuromorphic computing.

[0007] To address the above problems, the present invention provides the following technical solution:

[0008] In a first aspect, the present invention provides a multi-bit resistive switching memory, comprising: a lower electrode, a resistive switching layer, a metal oxygen-absorbing layer, and an upper electrode, wherein the resistive switching layer and the metal oxygen-absorbing layer are stacked between the lower electrode and the upper electrode; wherein the metal oxygen-absorbing layer is located between the resistive switching layer and the upper electrode, or the metal oxygen-absorbing layer is located between the lower electrode and the resistive switching layer.

[0009] The resistive switching layer comprises multiple oxygen barrier layers and multiple internal resistive switching layers, which are alternately stacked. Along the direction closest to the metal oxygen-absorbing layer, the physical thickness of the internal resistive switching layers increases in a gradient manner. This thickness gradient design utilizes the distance required for the filaments to penetrate within the extremely thin film, compensating for the attenuation of oxygen exchange capacity caused by distance from the metal oxygen-absorbing layer. Under a uniform external programming voltage, each internal resistive switching layer can balance the hierarchical differences in oxygen vacancy demand and supply, balancing the set / reset voltage conditions of the multilayer resistive switching unit, reducing the operating voltage during multi-bit writing, and thus achieving a precise and layer-by-layer controllable mechanism for the growth and breakage of conductive filaments.

[0010] Furthermore, the multiple oxygen barrier layers include a first end oxygen barrier layer, a second end oxygen barrier layer, and multiple internal oxygen barrier layers disposed between them. The first end oxygen barrier layer is located at the bottom of the resistive switching layer, and the second end oxygen barrier layer is located at the top of the resistive switching layer. The aforementioned two end oxygen barrier layers not only isolate the diffusion of elements at the electrode interface but also effectively regulate the oxidation kinetics between the metal oxygen-absorbing layer and the resistive switching layer, preventing the resistive switching layer from being excessively depleted of oxygen ions, which could lead to device failure.

[0011] Furthermore, the thickness of each of the internal oxygen barrier layers is 1 Å to 5 Å, and the thickness of the first end oxygen barrier layer and the second end oxygen barrier layer is 5 Å to 10 Å. Strictly controlling the microscopic thickness of the internal oxygen barrier layers can effectively block the free diffusion of oxygen vacancies along the vertical direction while maximally suppressing the excessive increase in the overall parasitic series resistance of the device caused by the insertion isolation structure. This avoids significantly sacrificing low-resistivity write capability, thereby alleviating the problem of low-resistivity write limitation (LRSwritelimitation) and ensuring that the device can be successfully programmed to the target low-resistivity state.

[0012] Furthermore, each internal resistive switching layer is made of a high dielectric constant resistive switching material. The thickness of the internal resistive switching layer farthest from the metal oxygen-absorbing layer is 1 Å to 3 Å, while the thickness of the internal resistive switching layer closest to the metal oxygen-absorbing layer is 9 Å to 11 Å. The setting of the size range is the key to balancing the microscopic penetration distance and the oxygen ion migration capability, ensuring that the thinnest layer can still undergo resistive state reversal first under the relatively weak oxygen absorption traction force at the far end.

[0013] Furthermore, the oxygen barrier layer is made of a material with conductive and oxygen-isolating properties, or it is made of an inert metal material, or it is made of a metal nitride material, and the number of nitrogen atoms in the film composition is greater than the number of metal atoms.

[0014] Furthermore, the metal nitride material is a TiN thin film, and the nitrogen-titanium atomic ratio of the TiN thin film is controlled between 1.1 and 1.3. This nitrogen-rich structure can not only effectively passivate grain boundaries and vacancy defects inside the film and improve the overall lattice density, but also cut off the random diffusion path of oxygen ions along unexpected defect channels at the microscale, thereby significantly reducing the leakage current level of the device.

[0015] A second aspect of the present invention provides a method for fabricating a multi-bit resistive switching memory (RSM), used to fabricate the multi-bit RSM described in the first aspect, comprising a fabrication step with one of the following two stacking sequences: The first preparation step is as follows: a lower electrode is formed on a semiconductor substrate, a resistive switching layer is formed on the lower electrode using a continuous atomic layer deposition process, and a metal oxygen-absorbing layer and an upper electrode are formed sequentially on the resistive switching layer. In this process, when depositing multiple internal resistive switching layers, the number of cycles of the precursor is increased sequentially along the deposition sequence to form a thickness gradient arrangement structure that gradually increases from 3 Å to 11 Å.

[0016] The second preparation step involves forming a lower electrode on a semiconductor substrate, first forming a metal oxygen-absorbing layer on the lower electrode, then continuously depositing a resistive switching layer in situ, and finally forming an upper electrode on the resistive switching layer. In this process, when depositing multiple internal resistive switching layers, the number of cycles of the precursor is reduced sequentially along the deposition sequence to form a thickness gradient arrangement structure that gradually decreases from 11 Å to 3 Å.

[0017] Atomic layer deposition technology enables precise control of thickness at the atomic level, ensuring the structural accuracy of the thickness gradient arrangement. At the same time, the in-situ continuous growth process eliminates the risk of exposure of the interfaces of each thin film to the atmospheric environment, avoiding the degradation of resistive switching performance caused by water vapor adhesion and impurity introduction.

[0018] Furthermore, when using a continuous atomic layer deposition process to alternately deposit multiple internal resistive switching layers and multiple oxygen barrier layers, metal precursors and oxidant gases are alternately introduced without breaking the vacuum in the reaction chamber of the deposition equipment, and nitrogen-containing reactant gases are introduced in conjunction with the deposition of metal nitrides. The oxygen vacancy concentration in the internal resistive switching layer can be adjusted by modifying the oxygen source pulse time, purge time, deposition temperature, or post-annealing atmosphere. A ruthenium-oxygen barrier layer can be formed by adjusting the ruthenium precursor cycle number, or a metal nitride oxygen barrier layer with controllable thickness and composition can be formed by adjusting the cycle ratio of the metal precursor to the nitrogen-containing reactants. Controlling the oxygen vacancy concentration, combined with thin film thickness gradient design, can further optimize the electrical switching conditions of each independent resistive switching region, improving the device's multi-bit memory resolution and long-term data retention capability.

[0019] Furthermore, after forming the top electrode, the process includes: patterning the stacked thin films using photolithography and dry etching processes to form independent memory array pillars; depositing a passivation layer on the sidewall surface of the pillars; and performing a thermal annealing treatment on the device at 300°C to 400°C. The thermal annealing step helps repair lattice damage caused by the physical etching process, eliminates residual stress within the thin film, and further stabilizes the ohmic or Schottky contact state at the multilayer thin film interface.

[0020] A third aspect of the present invention provides an electronic device comprising an integrated circuit board and a memory chip disposed on the integrated circuit board, wherein the array structure of the multi-bit resistive random access memory described in the first aspect is manufactured inside the memory chip.

[0021] This invention provides a multi-bit resistive random access memory (RRAM), its fabrication method, and an electronic device. It offers the following advantages: 1. This invention configures the physical thickness of multiple internal resistive switching layers in a gradient increasing manner towards the metal oxygen-absorbing layer. When an operating voltage is applied, the internal resistive switching layers that are farther away from the metal oxygen-absorbing layer and have a thinner thickness have a significantly reduced number of oxygen vacancies required to form conductive filaments penetrating the layer due to their extremely short physical barrier distance. This size effect compensates for the reduced local oxygen vacancy concentration caused by the distance from the metal oxygen-absorbing layer. Through the balance between the local oxygen ion attraction force and the film penetration distance, each internal resistive switching layer can undergo resistive state transitions in a predetermined order under the action of a stepped voltage. This balances the SET / RESET operating voltage of different resistive switching regions, reduces the voltage required for multi-bit writing, and thus achieves highly distinguishable and easily controllable multi-level resistive state switching.

[0022] 2. This invention utilizes alternating layers of oxygen barrier layers to physically divide the overall resistive switching layer into multiple independent resistive switching regions. When the device is in a power-off holding state, the conductive oxygen barrier layer with oxygen isolation properties effectively cuts off the natural diffusion path of local oxygen vacancies along the concentration gradient, preventing crosstalk between oxygen vacancies in adjacent resistive switching regions and suppressing the high-resistivity degradation phenomenon of the device. This ensures the long-term data retention capability and stability of the device under different multi-bit resistance states.

[0023] 3. In preparing the oxygen barrier layer, this invention uses a metal nitride material with an excess of nitrogen atoms. The excess nitrogen atoms can effectively fill the grain boundaries and vacancy defects inside the film, improve the lattice density of the film, block the unexpected channels of random diffusion of oxygen ions along defects, suppress the generation of leakage current, and thus improve the durability of the memory cell and the consistency of the device during repeated erase and write operations. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the resistive switching layer structure design of the present invention; Figure 2 This is a schematic diagram illustrating a bit storage example of the present invention.

[0025] Among them, 110 is the lower electrode; 120 is the resistive switching layer; 130 is the metal oxygen absorption layer; and 140 is the upper electrode. Detailed Implementation

[0026] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] Example 1: Please see the appendix Figure 1 - Appendix Figure 2 This invention provides a multi-bit resistive switching memory (RSM). The RSM includes a lower electrode 110, a resistive switching layer 120, a metal oxygen-absorbing layer 130, and an upper electrode 140, stacked sequentially. The resistive switching layer 120 is located between the lower electrode 110 and the metal oxygen-absorbing layer 130, and the metal oxygen-absorbing layer 130 is located between the resistive switching layer 120 and the upper electrode 140. In another stacking order, the metal oxygen-absorbing layer 130 is disposed between the resistive switching layer 120 and the lower electrode 110.

[0028] The lower electrode 110 and the upper electrode 140 are made of conductive materials, specifically selected from TiN (titanium nitride), W (tungsten), Ru (ruthenium), TaN (tantalum nitride), Pt (platinum), Cu (copper), or Al (aluminum). The thickness of the lower electrode 110 and the upper electrode 140 is from 10 nm to 50 nm.

[0029] The metal oxygen absorber layer 130 is made of an active metal, metal nitride, or metal-rich oxide, specifically selected from Ti (titanium), Ta (tantalum), Hf (hafnium), Zr (zirconium), Al (aluminum), TiN (titanium nitride), WN (tungsten nitride), or TaN (tantalum nitride). The thickness of the metal oxygen absorber layer 130 is from 3 nm to 10 nm.

[0030] The resistive switching layer 120 includes multiple oxygen barrier layers and multiple internal resistive switching layers, which are alternately stacked along the direction from the lower electrode 110 to the upper electrode 140. The multiple oxygen barrier layers include a first end oxygen barrier layer, a second end oxygen barrier layer, and multiple internal oxygen barrier layers disposed between them.

[0031] The first end oxygen barrier layer is located at the bottom of the resistive switching layer 120 and contacts the lower electrode 110, while the second end oxygen barrier layer is located at the top of the resistive switching layer 120 and contacts the metal oxygen-absorbing layer 130. The thickness of the first and second end oxygen barrier layers is between 5 Å and 10 Å. This thickness configuration is used to limit the diffusion of oxygen at the interface between the lower electrode 110 and the resistive switching layer 120 and to control the metal oxidation rate of the metal oxygen-absorbing layer 130.

[0032] Multiple internal oxygen barrier layers have a consistent thickness parameter, with each layer ranging from 3 Å to 5 Å in thickness. This thickness parameter limits oxygen vacancy diffusion between adjacent internal resistive switching layers while controlling the increase in parasitic series resistance caused by the overall increase in the thickness of the resistive switching layer 120. Controlling the series resistance enables the multi-bit resistive switching memory to switch to a target low-resistance state.

[0033] Multiple internal resistive switching layers are alternately disposed between the aforementioned multiple oxygen barrier layers. Along the direction close to the metal oxygen absorber layer 130, the physical thickness of the multiple internal resistive switching layers is arranged in a gradient increasing manner. By adopting a size design that gradually increases the thickness, the internal resistive switching layers farther away from the metal oxygen absorber layer 130 have a smaller film thickness.

[0034] Taking a structure with five internal resistive switching layers as an example, the resistive switching layer 120 includes, in sequence from the lower electrode 110 toward the metal oxygen-absorbing layer 130: a first end oxygen barrier layer, a first internal resistive switching layer, a first internal oxygen barrier layer, a second internal resistive switching layer, a second internal oxygen barrier layer, a third internal resistive switching layer, a third internal oxygen barrier layer, a fourth internal resistive switching layer, a fourth internal oxygen barrier layer, a fifth internal resistive switching layer, and a second end oxygen barrier layer.

[0035] Among them, the first internal resistive switching layer is farthest from the metal oxygen-absorbing layer 130, and its thickness is 1 Å to 3 Å; the thickness of the second internal resistive switching layer is 3 Å to 5 Å; the thickness of the third internal resistive switching layer is 5 Å to 7 Å; the thickness of the fourth internal resistive switching layer is 7 Å to 9 Å; and the thickness of the fifth internal resistive switching layer is closest to the metal oxygen-absorbing layer 130, and its thickness is 9 Å to 11 Å.

[0036] Each of the aforementioned internal resistive switching layers is made of a high dielectric constant resistive switching material, specifically selected from HfO. x Hafnium oxide, TaOx (tantalum oxide), HfTaOx (hafnium tantalum oxide), HfAlOx (hafnium aluminum oxide), HfSiOx (hafnium silicon oxide), TiOx (titanium oxide), AlOx (aluminum oxide), or ZrOx (zirconia).

[0037] Each of the aforementioned oxygen barrier layers is made of a material with both electrical conductivity and oxygen isolation properties. In this embodiment, the material is an inert metal, selected from at least one of Ru (ruthenium), Pt (platinum), Ir (iridium), Pd (palladium), Rh (rhodium), or Au (gold). Using an inert metal material limits the increase in device resistance caused by introducing multiple internal oxygen barrier layers.

[0038] Example 2: Another configuration method for resistive switching memory is provided. The stacked structure of this second embodiment is the same as that of the first embodiment, except that the oxygen barrier layer in this embodiment is made of a metal nitride material, specifically selected from TiN (titanium nitride), WN (tungsten nitride), TaN (tantalum nitride) or RuN (ruthenium nitride).

[0039] When metal nitride materials are selected, nitrogen atoms are arranged in an excess proportion relative to metal atoms in the film composition. Taking TiN (titanium nitride) films as an example, the nitrogen-titanium atom ratio is controlled between 1.1 and 1.3. The nitrogen-rich composition improves the density of the film structure and eliminates the physical path of oxygen ion diffusion along grain boundary defects.

[0040] Example 3: This invention also provides a method for fabricating a resistive random access memory (RRAM).

[0041] A conductive layer is deposited on a semiconductor substrate, and the conductive layer is planarized using a chemical mechanical polishing process to form a lower electrode 110. A resistive switching layer 120 is then formed on the lower electrode 110 using a continuous atomic layer deposition process.

[0042] Without disrupting the vacuum in the reaction chamber of the deposition equipment, metal precursors and oxidant gases are alternately introduced, and nitrogen-containing reactant gases are introduced during the deposition of metal nitrides, sequentially depositing multiple internal resistive switching layers and multiple oxygen barrier layers. This continuous deposition process creates an in-situ physical interface between the internal resistive switching layers and the oxygen barrier layers, eliminating the problems of water vapor adhesion and impurity introduction caused by the film being exposed to the atmosphere.

[0043] During the preparation process, the thickness of each resistive switching layer can be controlled by the number of ALD cycles. The oxygen vacancy concentration of the resistive switching layer can be adjusted by regulating the oxygen source pulse time, purge time, deposition temperature, or post-annealing atmosphere. A Ru oxygen barrier layer can be formed by adjusting the number of Ru (ruthenium) precursor cycles, or a high-nitrogen-content TiN (titanium nitride) oxygen barrier layer can be formed by adjusting the Ti / N (titanium / nitrogen) ratio.

[0044] When depositing multiple internal oxygen barrier layers, the number of precursor pulse cycles is kept constant to obtain a consistent thickness from 1 Å to 5 Å. When depositing the first and second end oxygen barrier layers, the number of precursor pulse cycles is increased accordingly to obtain a thickness from 5 Å to 10 Å. When depositing multiple internal resistive switching layers, the number of precursor pulse cycles is increased sequentially along the deposition sequence to form a thickness gradient arrangement structure that gradually increases from 1 Å to 11 Å. Subsequently, a metal oxygen-absorbing layer 130 and an upper electrode 140 are sequentially formed on the resistive switching layer 120.

[0045] If another stacking sequence is adopted, the deposition sequence and thickness gradient direction are adjusted: first, a metal oxygen-absorbing layer 130 is formed on the lower electrode 110, and then the resistive switching layer 120 is continuously deposited in situ; at this time, when depositing multiple internal resistive switching layers, the number of cycles of the precursor is reduced sequentially along the deposition sequence to form a thickness gradient arrangement structure that gradually decreases from 11 Å to 1 Å, and finally the upper electrode 140 is formed on the resistive switching layer 120.

[0046] Finally, the stacked thin films are patterned using photolithography and dry etching processes to form independent memory array pillars. A passivation layer is deposited on the sidewall surface of the pillars, and the devices are subjected to thermal annealing at 300°C to 400°C.

[0047] Example 4: This invention also provides an electronic device, which includes an integrated circuit board and a memory chip disposed on the integrated circuit board. The array structure of the aforementioned multi-bit resistive random access memory is manufactured inside the memory chip.

[0048] Working principle: During the multi-bit data writing operation of the device, an operating voltage pulse is applied to the lower electrode 110 and the upper electrode 140. The metal oxygen-absorbing layer 130 attracts oxygen ions from adjacent regions, causing oxygen vacancies to be generated in the resistive switching layer 120. The internal oxygen barrier layers of each layer physically divide the resistive switching layer 120 into multiple independent resistive switching regions. Under the same applied voltage, the internal resistive switching layers farther from the metal oxygen-absorbing layer 130 have the shortest physical barrier distance for forming a conductive path due to their thinner thickness. This size characteristic effectively compensates for the decrease in oxygen vacancy generation capacity caused by the increase in physical distance in the far-end region. The above-mentioned thickness gradient design balances the electrical transition conditions of each independent resistive switching region (i.e., the local oxygen vacancy supply concentration matches the physical distance required for the filament to penetrate), so that multiple internal resistive switching layers undergo conductive state transitions in a predetermined order under the action of stepped voltage. In the power-off state, the internal oxygen barrier layers cut off the diffusion path of the local oxygen vacancy concentration gradient, stabilizing the multi-level resistance state of the resistive switching layer 120.

[0049] Combined with appendix Figure 1 As shown, the wavy curve on the right represents the oxygen vacancy concentration distribution within the resistive switching layer. Due to the alternating insertion of oxygen barrier layers, the oxygen vacancy concentration is higher in the inner resistive switching layer and significantly lower at the oxygen barrier layer, forming a periodic gradient distribution feature, thereby blocking the natural diffusion path of oxygen vacancy on the physical barrier.

[0050] Combined with appendix Figure 2 As shown, this diagram illustrates the probability density distribution of cell currents in a multi-bit storage state. The horizontal axis represents the cell current (Icell), and the vertical axis represents the probability density function (PDF). Through precise control of the thickness gradient, the device can achieve highly differentiated multi-level resistance states, including a high-resistance state (HRS) and multiple low-resistance states (such as LRS). m-3 LRS m-1 To LRS m ).

[0051] The number of bits n and the total number of storage states m satisfy the formula m=2. nThe distribution windows of adjacent resistor states do not overlap, effectively solving the problem of resistance drift in traditional devices and realizing long-term and stable multi-bit data storage.

Claims

1. A multi-bit resistive random access memory, characterized in that, include: The device comprises a lower electrode (110), a resistive switching layer (120), a metal oxygen-absorbing layer (130), and an upper electrode (140). The resistive switching layer (120) is located between the lower electrode (110) and the metal oxygen-absorbing layer (130). The metal oxygen-absorbing layer (130) is located between the resistive switching layer (120) and the upper electrode (140). Alternatively, the metal oxygen-absorbing layer (130) is disposed between the resistive switching layer (120) and the lower electrode (110). The resistive switching layer (120) includes multiple oxygen barrier layers and multiple internal resistive switching layers. The multiple internal resistive switching layers and the multiple oxygen barrier layers are stacked alternately. Along the direction close to the metal oxygen absorption layer (130), the physical thickness of the multiple internal resistive switching layers is arranged in a gradient increasing manner.

2. The multi-bit resistive random access memory according to claim 1, characterized in that, The plurality of oxygen barrier layers include a first end oxygen barrier layer, a second end oxygen barrier layer, and a plurality of internal oxygen barrier layers disposed between the two, wherein the first end oxygen barrier layer is located at the bottom of the resistive switching layer (120), and the second end oxygen barrier layer is located at the top of the resistive switching layer (120).

3. The multi-bit resistive random access memory according to claim 2, characterized in that, The thickness of each of the internal oxygen barrier layers is 1 Å to 5 Å, and the thickness of the first end oxygen barrier layer and the second end oxygen barrier layer is 5 Å to 10 Å.

4. The multi-bit resistive random access memory according to claim 1, characterized in that, Each of the internal resistive switching layers is made of a high dielectric constant resistive switching material. The thickness of the internal resistive switching layer farthest from the metal oxygen-absorbing layer (130) is 1 Å to 3 Å, and the thickness of the internal resistive switching layer closest to the metal oxygen-absorbing layer (130) is 9 Å to 11 Å.

5. The multi-bit resistive random access memory according to claim 1, characterized in that, The oxygen barrier layer is made of a material with conductive and oxygen-isolating properties, or it is made of an inert metal material, or it is made of a metal nitride material, and the number of nitrogen atoms in the film composition is greater than the number of metal atoms.

6. The multi-bit resistive random access memory according to claim 5, characterized in that, The metal nitride material is a TiN thin film, and the ratio of nitrogen to titanium atoms in the TiN thin film is controlled between 1.1 and 1.

3.

7. A method for fabricating a multi-bit resistive switching memory (RSM), used to fabricate the RSM as described in any one of claims 1 to 6, characterized in that, The preparation steps include one of the following two stacking sequences: The first preparation step is as follows: a lower electrode (110) is formed on a semiconductor substrate. Multiple oxygen barrier layers and multiple internal resistive switching layers are alternately deposited on the lower electrode (110) using a continuous atomic layer deposition process to form a resistive switching layer (120). A metal oxygen absorption layer (130) and an upper electrode (140) are sequentially formed on the resistive switching layer (120). When depositing multiple internal resistive switching layers, the number of cycles of the precursor is increased sequentially along the deposition sequence to form a thickness gradient arrangement structure that gradually increases from 1 Å to 11 Å. The second preparation step is as follows: a lower electrode (110) is formed on a semiconductor substrate. First, a metal oxygen-absorbing layer (130) is formed on the lower electrode (110). Then, multiple oxygen barrier layers and multiple internal resistive switching layers are continuously and alternately deposited in situ to form a resistive switching layer (120). Finally, an upper electrode (140) is formed on the resistive switching layer (120). In the process of depositing multiple internal resistive switching layers, the number of cycles of the precursor is reduced sequentially along the deposition sequence to form a thickness gradient arrangement structure that gradually decreases from 11 Å to 1 Å.

8. The preparation method according to claim 7, characterized in that, When using a continuous atomic layer deposition process to alternately deposit multiple internal resistive switching layers and multiple oxygen barrier layers, without breaking the vacuum in the reaction chamber of the deposition equipment, metal precursor and oxidant gas are alternately introduced, and nitrogen-containing reactant gas is introduced in conjunction with the deposition of metal nitrides; the oxygen vacancy concentration of the internal resistive switching layers is adjusted by regulating the oxygen source pulse time, purging time, deposition temperature or post-annealing atmosphere; the ruthenium oxygen barrier layer is formed by adjusting the number of ruthenium precursor cycles, or the metal nitride oxygen barrier layer is deposited by adjusting the cycle ratio of metal precursor and nitrogen-containing reactant gas.

9. The preparation method according to claim 7, characterized in that, After forming the upper electrode (140), the process further includes: patterning the stacked thin film using photolithography and dry etching processes to form an independent storage array pillar, depositing a passivation layer on the sidewall surface of the pillar, and performing thermal annealing treatment on the device at 300°C to 400°C.

10. An electronic device, characterized in that, The electronic device includes an integrated circuit board and a memory chip disposed on the integrated circuit board, wherein the array structure of the multi-bit resistive random access memory as described in any one of claims 1 to 6 is manufactured inside the memory chip.

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