Three-dimensional memory with wrap-around storage structure and its manufacturing method

Abstract

This invention relates to a three-dimensional memory with an encapsulated storage structure and a method for manufacturing the same. The method for manufacturing the three-dimensional memory with the encapsulated storage structure includes the following steps: forming a substrate, the substrate comprising a base, a bottom dielectric layer, a first contact structure penetrating the bottom dielectric layer, an intermediate dielectric layer, and a storage via penetrating the intermediate dielectric layer and exposing the first contact structure; forming a storage structure at least within the storage via, the storage structure comprising an inner electrode layer, a storage layer encapsulating the inner electrode layer, and an outer electrode layer encapsulating the storage layer, the outer electrode layer being electrically connected to the first contact structure, and the inner electrode layer comprising polysilicon material and doped elements; and forming a first lead-out structure located above the substrate and electrically connected to the inner electrode layer. This invention increases the effective storage area under the same chip area conditions, achieving a significant improvement in the storage performance of the three-dimensional memory.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a three-dimensional memory with an encapsulated storage structure and a method for manufacturing the same. Background Technology

[0002] Phase-change memory (PCM) or ferroelectric RAM (FeRAM) are devices that integrate memory cells in back-end-of-line (BEOL) processes, where the memory cells are inserted between two adjacent metal layers. A memory cell typically consists of upper and lower electrode layers and an intermediate ferroelectric storage layer. The storage performance of a ferroelectric memory is directly proportional to the effective area of ​​the ferroelectric storage layer and the electrode layer within the memory cell. The traditional fabrication process for memory cells in three-dimensional memory involves etching memory holes in a dielectric layer, followed by the sequential deposition of a lower electrode material, a phase-change material or ferroelectric material, and an upper electrode material, forming a sandwich structure of lower electrode layer-memory layer-upper electrode layer.

[0003] However, traditional sandwich-structured memory cells suffer from at least the following problems: Firstly, the limited contact area between the storage layer and the electrode layer (including the upper and lower electrode layers) results in a small effective phase transition area, thus restricting the improvement of 3D memory performance. Secondly, traditional processes use metal materials to form the upper and lower electrode layers, leading to a high interface defect density between the electrode layers (including the upper and lower electrode layers) and the storage layer (phase change material layer or ferroelectric material layer), resulting in weak ferroelectric polarization and low phase transition efficiency, which in turn affects the power consumption and data retention capabilities of 3D memory. Furthermore, the current process steps for forming sandwich-structured memory cells are cumbersome, resulting in a high defect rate, which is not conducive to large-scale mass production. Moreover, traditional sandwich-structured memory cells have a narrow range of electrode material choices and insufficient circuit design flexibility, making it difficult to adapt to the high-density integration requirements of advanced process nodes.

[0004] Therefore, how to increase the effective storage area of ​​the memory structure within the same chip area, while reducing the read and write power consumption of the 3D memory, improving the data retention capability and device reliability of the 3D memory, and simplifying the manufacturing process and reducing the manufacturing cost of the 3D memory are the technical problems that urgently need to be solved. Summary of the Invention

[0005] This invention provides a three-dimensional memory with a wraparound storage structure and a method for manufacturing the same, which can increase the effective storage area of ​​the storage structure under the same chip area, while reducing the read and write power consumption of the three-dimensional memory, improving the data retention capability and device reliability of the three-dimensional memory, and simplifying the manufacturing process and reducing the manufacturing cost of the three-dimensional memory.

[0006] According to some embodiments, the present invention provides a method for manufacturing a three-dimensional memory with a wrap-around storage structure, comprising the following steps: A substrate is formed, the substrate including a substrate, a bottom dielectric layer on the substrate, a first contact structure penetrating the bottom dielectric layer, an intermediate dielectric layer covering the bottom dielectric layer and the first contact structure, and a storage via penetrating the intermediate dielectric layer and exposing the first contact structure. A storage structure is formed at least within the storage hole. The storage structure includes an inner electrode layer that is at least filled within the storage hole, a storage layer that is at least within the storage hole and encloses the inner electrode layer, and an outer electrode layer that at least covers the inner wall of the storage hole and encloses the storage layer. The outer electrode layer is electrically connected to the first contact structure. The inner electrode layer includes polycrystalline silicon material and doped elements. A first lead-out structure is formed above the substrate and electrically connected to the inner electrode layer.

[0007] In some embodiments, the specific steps of forming a substrate, the substrate including a substrate, a bottom dielectric layer on the substrate, a first contact structure penetrating the bottom dielectric layer, an intermediate dielectric layer covering the bottom dielectric layer and the first contact structure, and a storage via penetrating the intermediate dielectric layer and exposing the first contact structure include: A substrate is provided, the substrate including an active region, and the substrate including a top surface and a bottom surface that are distributed opposite to each other, the active region including a channel region and a source region and a drain region distributed on opposite sides of the channel region along a first direction, the first direction being parallel to the top surface of the substrate; Form the bottom dielectric layer covering the top surface of the substrate; A first contact structure is formed that penetrates the bottom dielectric layer along a second direction and is electrically connected to the drain region, wherein the second direction intersects the top surface of the substrate perpendicularly; An intermediate dielectric layer is formed covering the bottom dielectric layer and the first contact structure; The storage hole is formed by penetrating the intermediate medium layer along the second direction and exposing the first contact structure.

[0008] In some embodiments, the intermediate dielectric layer includes: A first intermediate dielectric layer covers the bottom dielectric layer and the first contact structure, and the material of the first intermediate dielectric layer includes silicon nitride; A second intermediate dielectric layer covering the first intermediate dielectric layer, wherein the material of the second intermediate dielectric layer includes silicon dioxide; A third intermediate dielectric layer covers the second intermediate dielectric layer, and the material of the third intermediate dielectric layer includes silicon oxynitride.

[0009] In some embodiments, a storage structure is formed at least within the storage aperture. The storage structure includes an inner electrode layer at least filled within the storage aperture, a storage layer at least within the storage aperture and enclosing the inner electrode layer, and an outer electrode layer at least covering the inner wall of the storage aperture and enclosing the storage layer. The specific steps for the outer electrode layer to make contact with the first contact structure include: A first sub-outer electrode layer is formed that at least covers the inner wall of the storage hole; A first sub-memory layer is formed covering the first sub-outer electrode layer; The polycrystalline silicon material is deposited on the substrate, and the doping element is implanted into the polycrystalline silicon material to form the inner electrode layer that covers the first sub-memory layer and fills the memory hole; A second sub-storage layer is formed that covers the inner electrode layer and the first sub-storage layer, and the first sub-storage layer and the second sub-storage layer together serve as the storage layer; A second sub-external electrode layer is formed that covers the second sub-memory layer and the first sub-external electrode layer, wherein the first sub-external electrode layer and the second sub-external electrode layer together serve as the external electrode layer.

[0010] In some embodiments, the specific steps of depositing the polycrystalline silicon material on the substrate and implanting the dopant element into the polycrystalline silicon material to form the inner electrode layer covering the first sub-memory layer and filling the memory hole include: The polycrystalline silicon material is deposited on the substrate using a low-pressure chemical vapor deposition process to form a polycrystalline silicon material layer. The doping element is implanted into the polycrystalline silicon material layer using an ion implantation process to form the inner electrode layer that covers the first sub-memory layer and fills the memory hole.

[0011] In some embodiments, before forming a second sub-memory layer covering the inner electrode layer and the first sub-memory layer, the following steps are further included: The inner electrode layer is planarized using a chemical mechanical polishing process, so that the top surface of the planarized inner electrode layer is flush with the top surface of the first sub-storage layer.

[0012] In some embodiments, the inner electrode layer continuously covers the first sub-storage layer of the memory aperture and the second sub-storage layer located on the top surface of the intermediate dielectric layer; the specific steps for forming the second sub-storage layer covering the inner electrode layer and the first sub-storage layer include: A second sub-storage layer is formed, covering the exposed top surface and sidewalls of the inner electrode layer and the first sub-storage layer.

[0013] In some embodiments, the first sub-external electrode layer covers the inner wall of the storage via and a portion of the top surface of the intermediate dielectric layer; the specific steps for forming the second sub-external electrode layer covering the second sub-storage layer and the first sub-external electrode layer include: Remove a portion of the storage layer on the top surface of the intermediate dielectric layer to expose the first sub-external electrode layer; A second sub-external electrode layer is formed that covers the remaining storage layer and the exposed first sub-external electrode layer.

[0014] In some embodiments, the specific steps of forming a first lead-out structure located above the substrate and electrically connected to the inner electrode layer include: Part of the outer electrode layer and part of the storage layer are etched away to form an opening that exposes part of the surface of the inner electrode layer; A top layer is formed on the substrate, covering the intermediate medium layer and the storage structure and filling the opening; A first lead-out structure is formed that penetrates the top dielectric layer and is electrically connected to the inner electrode layer through the opening.

[0015] In some embodiments, the orthographic projection of the opening onto the substrate is located at the end of the storage hole along a third direction, the substrate including a top surface and a bottom surface that are oppositely distributed, and the third direction is parallel to the top surface of the substrate.

[0016] According to other embodiments, the present invention also provides a three-dimensional memory with a wraparound storage structure, comprising: The substrate includes a substrate, a bottom dielectric layer on the substrate, a first contact structure penetrating the bottom dielectric layer, an intermediate dielectric layer covering the bottom dielectric layer and the first contact structure, and a storage via penetrating the intermediate dielectric layer and exposing the first contact structure. A storage structure, at least located within the storage hole, the storage structure including an inner electrode layer at least filled within the storage hole, a storage layer at least located within the storage hole and enclosing the inner electrode layer, and an outer electrode layer at least covering the inner wall of the storage hole and enclosing the storage layer, the outer electrode layer being electrically connected to the first contact structure, the inner electrode layer comprising polycrystalline silicon material and doping elements; The first lead-out structure is located above the substrate and is electrically connected to the inner electrode layer.

[0017] In some embodiments, the external electrode layer includes a first sub-external electrode layer and a second sub-external electrode layer, the first sub-external electrode layer covering the inner wall of the storage hole, and the second sub-external electrode layer located above the first sub-external electrode layer and in contact with and electrically connected to the first sub-external electrode layer. The storage layer includes a first sub-storage layer covering the surface of the first sub-outer electrode layer and the sidewalls and bottom surface of the inner electrode layer, and a second sub-storage layer covering at least the top surface of the inner electrode layer, wherein the second sub-outer electrode layer covers the surface of the second sub-storage layer.

[0018] In some embodiments, the top surface of the inner electrode layer is flush with the top surface of the first sub-storage layer, and the second sub-storage layer covers only the top surface of the inner electrode layer and the surface of the first sub-storage layer.

[0019] In some embodiments, the top surface of the inner electrode layer is higher than the top surface of the first sub-storage layer, and the second sub-storage layer covers the top surface and part of the sidewalls of the inner electrode layer and covers the surface of the first sub-storage layer.

[0020] In some embodiments, the substrate includes a top surface and a bottom surface that are oppositely distributed, and the inner electrode layer protrudes from the storage layer and the outer electrode layer in a third direction parallel to the top surface of the substrate; The first lead-out structure is electrically connected to the inner electrode layer protruding along the third direction.

[0021] In some embodiments, it also includes: A top dielectric layer is located on the substrate and covers the intermediate dielectric layer and the storage structure. The first lead-out structure penetrates the top dielectric layer along a second direction and is electrically connected to the inner electrode layer protruding along the third direction, wherein the second direction intersects perpendicularly with the top surface of the substrate.

[0022] In some embodiments, the doping element is any one or a combination of two or more of arsenic, phosphorus and boron, and the material of the external electrode layer includes TiN, and the material of the storage layer includes a phase change material or a ferroelectric material.

[0023] The present invention provides a three-dimensional memory with an enclosed storage structure and a method for manufacturing the same. By configuring the storage structure located at least within the storage hole as an inner electrode layer that fills at least the storage hole, a storage layer located at least within the storage hole and enclosing the inner electrode layer, and an outer electrode layer that at least covers the inner wall of the storage hole and encloses the storage layer, the outer electrode layer is electrically connected to a first contact structure. The inner electrode layer includes polycrystalline silicon material and doped elements, so that the storage layer can simultaneously cover the side, bottom, and top surfaces of the inner electrode layer, and the outer electrode layer fully encloses the side, bottom, and top surfaces of the storage layer, forming an enclosed storage structure. This results in an increase in effective storage area under the same chip area conditions, and a significant improvement in the storage performance, read / write sensitivity, and reliability of the three-dimensional memory. Meanwhile, using polycrystalline silicon material including doped elements as the inner electrode layer can not only reduce the defect density between the inner electrode layer and the storage layer, improve the conversion efficiency of the phase change material and the polarization intensity of the ferroelectric material, reduce the functionality of the three-dimensional memory, and improve the data retention performance of the three-dimensional memory, but also adjust the stress state of the inner electrode layer by adjusting the doping parameters of the doped elements in the inner electrode layer (such as the type and concentration of the doped elements), thereby actively changing the relative stress between the inner electrode layer and the storage layer, optimizing the phase change crystal phase transition and ferroelectric polarization reversal efficiency, improving storage performance, and increasing the diversity of electrode material selection and circuit design.

[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a flowchart of a method for manufacturing a three-dimensional memory with a wrap-around storage structure according to a specific embodiment of the present invention; Figure 2 This is a cross-sectional schematic diagram after the first contact structure is formed in a specific embodiment of the present invention; Figure 3 This is a cross-sectional schematic diagram after the intermediate dielectric layer is formed in a specific embodiment of the present invention; Figure 4 This is a cross-sectional schematic diagram after the storage hole is formed in a specific embodiment of the present invention; Figure 5 This is a cross-sectional schematic diagram after the formation of the first sub-external electrode layer and the first sub-storage layer in a specific embodiment of the present invention; Figure 6 This is a cross-sectional schematic diagram after the inner electrode layer is formed in a specific embodiment of the present invention; Figure 7 This is a cross-sectional schematic diagram after the formation of the second sub-memory layer in a specific embodiment of the present invention; Figure 8 This is a cross-sectional schematic diagram after the storage layer is formed in a specific embodiment of the present invention; Figure 9 This is a top view schematic diagram after the storage layer is formed in a specific embodiment of the present invention; Figure 10 This is a cross-sectional schematic diagram after the formation of the second sub-external electrode layer in a specific embodiment of the present invention; Figure 11 This is a cross-sectional schematic diagram after the connection between adjacent storage structures is disconnected in a specific embodiment of the present invention; Figure 12 This is a top view schematic diagram after disconnecting the connection between adjacent storage structures in a specific embodiment of the present invention; Figure 13 This is a cross-sectional schematic diagram after the top dielectric layer is formed in a specific embodiment of the present invention; Figure 14 This is a cross-sectional schematic diagram after the first lead-out structure is formed in a specific embodiment of the present invention; Figure 15 This is a top view schematic diagram after the first lead-out structure is formed in a specific embodiment of the present invention; Figure 16 This is a cross-sectional schematic diagram after the first pad is formed in a specific embodiment of the present invention; Figure 17 This is another cross-sectional schematic diagram after the formation of the inner electrode layer in a specific embodiment of the present invention; Figure 18 This is another cross-sectional schematic diagram after the formation of the second sub-memory layer in a specific embodiment of the present invention; Figure 19 This is another cross-sectional schematic diagram after the storage layer is formed in a specific embodiment of the present invention; Figure 20 This is another cross-sectional schematic diagram after the first pad is formed in a specific embodiment of the present invention.

[0027] Explanation of reference numerals in the attached figures 20. Substrate 21. Bottom dielectric layer 22. Gate dielectric layer 23. Gate conductive layer 24. Isolation sidewall 25. Second contact structure 26. First contact structure 30. First intermediate dielectric layer 31. Second intermediate dielectric layer 32. Third intermediate dielectric layer 40. Storage Hole 50. First Sub-electrode Layer 51. First Sub-Storage Layer 60. Inner Electrode Layer 70. Second Sub-Storage Layer 100. Second Sub-electrode Layer 131. First Top Dielectric Layer 132. Second Top Dielectric Layer 133. Third Top Dielectric Layer 140. First lead-out structure 141. Second lead-out structure 160. First pad 161. Second pad Detailed Implementation The technical solutions in the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] This specific embodiment provides a method for manufacturing a three-dimensional memory with a wrap-around storage structure. Figure 1 This is a flowchart illustrating a manufacturing method for a three-dimensional memory with a wraparound storage structure according to a specific embodiment of the present invention. For example... Figure 1 As shown, the manufacturing method of the three-dimensional memory with the enclosed storage structure includes the following steps: Step S11, forming a substrate, the substrate including a substrate, a bottom dielectric layer on the substrate, a first contact structure penetrating the bottom dielectric layer, an intermediate dielectric layer covering the bottom dielectric layer and the first contact structure, and a storage hole penetrating the intermediate dielectric layer and exposing the first contact structure; Step S12: Form a storage structure at least within the storage hole. The storage structure includes an inner electrode layer at least filled within the storage hole, a storage layer at least within the storage hole and enclosing the inner electrode layer, and an outer electrode layer at least covering the inner wall of the storage hole and enclosing the storage layer. The outer electrode layer is electrically connected to the first contact structure. The inner electrode layer includes polycrystalline silicon material and doped elements. Step S13: Form a first lead-out structure located above the substrate and electrically connected to the inner electrode layer.

[0029] Figure 2 This is a cross-sectional schematic diagram after the first contact structure is formed in a specific embodiment of the present invention. Figure 3 This is a cross-sectional schematic diagram after the intermediate dielectric layer is formed in a specific embodiment of the present invention. Figure 4 This is a cross-sectional schematic diagram after the storage hole is formed in a specific embodiment of the present invention. In some embodiments, such as Figure 2 , Figure 3 and Figure 4 As shown, the specific steps for forming a substrate, the substrate including a substrate 20, a bottom dielectric layer 21 located on the substrate 20, a first contact structure 26 penetrating the bottom dielectric layer 21, an intermediate dielectric layer covering the bottom dielectric layer 21 and the first contact structure 26, and a storage via 40 penetrating the intermediate dielectric layer and exposing the first contact structure 26, include: A substrate 20 is provided, the substrate 20 including an active region, and the substrate 20 including a top surface and a bottom surface that are distributed opposite to each other. The active region includes a channel region and a source region and a drain region distributed on opposite sides of the channel region along a first direction D1, the first direction D1 being parallel to the top surface of the substrate 20. The bottom dielectric layer 21 is formed to cover the top surface of the substrate 20; A first contact structure 26 is formed, extending along a second direction D2 through the bottom dielectric layer 21 and electrically connected to the drain region. The second direction D2 intersects perpendicularly with the top surface of the substrate 20. Figure 2 As shown; The intermediate dielectric layer is formed to cover the bottom dielectric layer 21 and the first contact structure 26, such as Figure 3 As shown; The storage hole 40 is formed by penetrating the intermediate dielectric layer along the second direction D2 and exposing the first contact structure 26, such as... Figure 4 As shown.

[0030] In some embodiments, the intermediate dielectric layer includes: A first intermediate dielectric layer 30 covers the bottom dielectric layer 21 and the first contact structure 26, and the material of the first intermediate dielectric layer 30 includes silicon nitride; A second intermediate dielectric layer 31 covers the first intermediate dielectric layer 30, and the material of the second intermediate dielectric layer 31 includes silicon dioxide; A third intermediate dielectric layer 32 covers the second intermediate dielectric layer 31, and the material of the third intermediate dielectric layer 32 includes silicon oxynitride.

[0031] Specifically, the substrate 20 may be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example for illustration. The substrate 20 includes at least a plurality of active regions arranged at intervals along the first direction D1 and shallow trench isolation regions located between adjacent active regions. Each active region includes a channel region and source and drain regions located on opposite sides of the channel region along the first direction D1. The substrate 20 includes a top surface and a bottom surface distributed opposite each other along the second direction D2. A gate structure is also disposed on the top surface of the substrate 20. The gate structure includes a gate dielectric layer 22 located above the channel region, a gate conductive layer 23 covering the surface of the gate dielectric layer 22, and isolation sidewalls 24 covering the sidewalls of the gate dielectric layer 22 and the sidewalls of the gate conductive layer 23, such as Figure 2 As shown. The bottom dielectric layer 21 covers the top surface of the substrate 20 and the gate structure. In one example, the material of the bottom dielectric layer 21 can be an oxide material, such as silicon dioxide. After forming the bottom dielectric layer 21, a first contact hole penetrating the bottom dielectric layer 21 along the second direction D2 and exposing the drain region and a second contact hole penetrating the bottom dielectric layer 21 along the second direction D2 and exposing the source region can be formed by etching. Then, a material such as tungsten is deposited in the first contact hole and the second contact hole by deposition, forming a plurality of first contact structures 26 that are electrically connected to the drain regions of the plurality of active regions, and forming a second contact structure 25 that is electrically connected to the source regions. In one example, two adjacent active regions along the first direction D1 share the source region. In this specific embodiment, "plural" refers to two or more.

[0032] After forming the first contact structure 26 and the second contact structure 25, silicon nitride is deposited on the bottom dielectric layer 21 to form a first intermediate dielectric layer 30 covering the bottom dielectric layer 21, the first contact structure 26, and the second contact structure 25. Next, silicon dioxide is deposited on the first intermediate dielectric layer 30 to form a second intermediate dielectric layer 31 covering the first intermediate dielectric layer 30. Then, silicon oxynitride is deposited on the second intermediate dielectric layer 31 to form a third intermediate dielectric layer 32 covering the second intermediate dielectric layer 31, as follows... Figure 3As shown, the first intermediate dielectric layer 30, the second intermediate dielectric layer 31, and the third intermediate dielectric layer 32 together serve as the intermediate dielectric layer.

[0033] After the intermediate dielectric layer is formed, etching is performed downwards from the top surface of the intermediate dielectric layer away from the substrate 20 (e.g., the surface of the third intermediate dielectric layer 32 away from the substrate 20) to form the storage via 40, which penetrates the intermediate dielectric layer at least along the second direction D2 and exposes at least the top surface of the first contact structure 26 away from the substrate 20. Figure 4 As shown. In one example, the storage hole 40 only penetrates the intermediate dielectric layer, meaning that the bottom of the storage hole 40 only exposes the top surface of the first contact structure 26. In another example, the storage hole 40 penetrates the intermediate dielectric layer and extends into the bottom dielectric layer 21, such that the storage hole 40 exposes the top surface and part of the sidewall of the first contact structure 26, thereby increasing the area of ​​the subsequently formed storage structure.

[0034] Figure 5 This is a cross-sectional schematic diagram after the formation of the first sub-external electrode layer and the first sub-memory layer in a specific embodiment of the present invention. Figure 6 This is a cross-sectional schematic diagram after the inner electrode layer has been formed in a specific embodiment of the present invention. Figure 7 This is a cross-sectional schematic diagram after the formation of the second sub-memory layer in a specific embodiment of the present invention. Figure 8 This is a cross-sectional schematic diagram after the storage layer has been formed in a specific embodiment of the present invention. Figure 9 This is a top view schematic diagram after the storage layer has been formed in a specific embodiment of the present invention. Figure 10 This is a cross-sectional schematic diagram after the formation of the second sub-outer electrode layer in a specific embodiment of the present invention. Figure 11 This is a cross-sectional schematic diagram after the connection between adjacent storage structures is disconnected in a specific embodiment of the present invention. Figure 12 This is a top view schematic diagram after disconnecting the connection between adjacent storage structures in a specific embodiment of the present invention. Figure 13 This is a cross-sectional schematic diagram after the top dielectric layer has been formed in a specific embodiment of the present invention. In some embodiments, such as Figures 5-13 As shown, a storage structure is formed at least within the storage hole 40. The storage structure includes an inner electrode layer 60 at least filled within the storage hole 40, a storage layer at least within the storage hole 40 and enclosing the inner electrode layer 60, and an outer electrode layer at least covering the inner wall of the storage hole 40 and enclosing the storage layer. The specific steps for the outer electrode layer to make contact with the first contact structure 26 include: A first sub-outer electrode layer 50 is formed to at least cover the inner wall of the storage hole 40; Forming a first sub-storage layer 51 covering the first sub-external electrode layer 50, such as Figure 5 As shown; The polycrystalline silicon material is deposited on the substrate, and the dopant element is implanted into the polycrystalline silicon material to form the inner electrode layer 60 covering the first sub-memory layer 51 and filling the memory via 40, as shown below. Figure 6 As shown; A second sub-storage layer 70 is formed covering the inner electrode layer 60 and the first sub-storage layer 51, such as Figure 7 As shown, the first sub-storage layer 51 and the second sub-storage layer 70 together serve as the storage layer; A second external electrode layer 100 is formed covering the second sub-memory layer 70 and the first sub-external electrode layer 50, as follows: Figure 10 As shown, the first sub-external electrode layer 50 and the second sub-external electrode layer 100 together serve as the external electrode layer.

[0035] In some embodiments, the specific steps of depositing the polycrystalline silicon material on the substrate and implanting the dopant element into the polycrystalline silicon material to form the inner electrode layer 60 covering the first sub-memory layer 51 and filling the memory via 40 include: The polycrystalline silicon material is deposited on the substrate using a low-pressure chemical vapor deposition process to form a polycrystalline silicon material layer. The doping element is implanted into the polycrystalline silicon material layer using an ion implantation process to form the inner electrode layer 60, which covers the first sub-storage layer 51 and fills the storage hole 40.

[0036] In some embodiments, before forming a second sub-storage layer 70 covering the inner electrode layer 60 and the first sub-storage layer 51, the following steps are further included: The inner electrode layer 60 is planarized using a chemical mechanical polishing process, so that the top surface of the planarized inner electrode layer 60 is flush with the top surface of the first sub-storage layer 51.

[0037] Specifically, after forming multiple storage holes 40 that expose multiple first contact structures 26, electrode materials such as TiN, tungsten, or doped polycrystalline silicon are deposited on the substrate using chemical vapor deposition, physical vapor deposition, metal-organic chemical vapor deposition, or atomic layer deposition. This forms a first sub-external electrode layer 50 covering the inner wall of the storage holes 40 and the top surface of the intermediate dielectric layer. Each first sub-external electrode layer 50 within a storage hole 40 is directly electrically connected to the first contact structure 26 below that storage hole. At this time, the first sub-external electrode layers 50 within multiple storage cells are interconnected, such as... Figure 5As shown. Next, a ferroelectric material or a phase change material is deposited on the substrate to form a first sub-storage layer 51 covering the surface of the first sub-external electrode layer 50, and the first sub-storage layers 51 in multiple memory cells are interconnected, as shown. Figure 5 As shown. Then, a low-pressure chemical vapor deposition process is used to deposit the polycrystalline silicon material onto the substrate, forming a polycrystalline silicon material layer that continuously fills the plurality of memory holes 40 and covers the surface of the first sub-memory layer 51 away from the first sub-external electrode layer 50. The dopant element is then implanted into the polycrystalline silicon material layer using an ion implantation process, forming an inner electrode layer 60 that covers the first sub-memory layer 51 and fills the memory holes 40. At this time, the inner electrode layers 60 in adjacent memory cells are interconnected. Then, a chemical mechanical polishing process is used to planarize the inner electrode layers 60, making the top surface of the planarized inner electrode layer 60 flush with the top surface of the first sub-memory layer 51, thereby breaking the connection between the inner electrode layers 60 in adjacent memory cells, as shown. Figure 6 As shown. Next, the ferroelectric material or the phase change material is deposited again on the substrate to form a second sub-storage layer 70 covering the inner electrode layer 60 and the first sub-storage layer 51, and the first sub-storage layer 70 and the second sub-storage layer 51 are in direct contact and connection, as shown. Figure 7 As shown. The first sub-memory layer 51 and the second sub-memory layer 70 together serve as the memory layer. In one example, the material of the first sub-memory layer 51 is the same as the material of the second sub-memory layer 70. By patterning processes such as etching on the first sub-memory layer 51 and the second sub-memory layer 70, the connection between the memory layers in adjacent memory cells is broken, and the first sub-external electrode layer 50 is exposed, as shown. Figure 8 and Figure 9 As shown.

[0038] Using the polycrystalline silicon material including the doped elements to form the inner electrode layer 60 can not only reduce the defect density between the inner electrode layer and the storage layer, improve the conversion efficiency of the phase change material and the polarization intensity of the ferroelectric material, reduce the functionality of the three-dimensional memory, and improve the data retention performance of the three-dimensional memory, but also adjust the stress state of the inner electrode layer by adjusting the doping parameters of the doped elements in the inner electrode layer (such as the type and concentration of the doped elements), thereby actively changing the relative stress between the inner electrode layer and the storage layer, optimizing the phase change crystal phase transition and ferroelectric polarization reversal efficiency, and improving the storage performance. Furthermore, by depositing polycrystalline silicon material on the substrate using a low-pressure chemical vapor deposition (LPCVD) process to form the polycrystalline silicon material layer, and then implanting dopant elements into the polycrystalline silicon material layer using an ion implantation process to form the inner electrode layer 60, the deposition temperature of the LCVD process is relatively low (e.g., around 600°C). This significantly reduces the thermal effect during the formation of the filling material, preventing damage to the first sub-memory layer 51 due to high temperatures. This effectively improves the thermal effect problem during the manufacturing process of the three-dimensional memory, thereby enhancing the memory's performance and lifespan. Moreover, in this specific embodiment, by filling the memory hole 40 with the inner electrode layer, subsequent filling of the metal conductive layer and alloying processes are unnecessary, simplifying the three-dimensional memory manufacturing process, improving manufacturing yield, and effectively reducing the manufacturing cost of the three-dimensional memory. Moreover, the polycrystalline silicon material deposited by low-pressure chemical vapor deposition has good step coverage, which can effectively fill memory holes with high aspect ratio or even extremely high aspect ratio, reduce or even avoid the generation of filling holes or gaps, ensure uniform contact resistance between the first sub-memory layer 51 and the inner electrode layer 60, and increase depth while reducing the area of ​​memory cells, so as to reduce the device size while maintaining the phase change performance of the memory.

[0039] In some embodiments, the doping element is any one or a combination of two or more of arsenic, phosphorus and boron.

[0040] Specifically, arsenic, phosphorus, and boron, or a combination of two or more of these elements, are implanted into the polycrystalline silicon material layer via ion implantation to form the conductive inner electrode layer 60. By implanting these dopants into the polycrystalline silicon material layer and then performing rapid thermal annealing, the doping concentration of the dopants and the stress within the inner electrode layer 60 can be precisely controlled. This actively adjusts the tensile and compressive stress distribution between the inner electrode layer 60 and the first sub-memory layer 51, thereby promoting the phase transformation of the phase change material in the final memory layer or promoting the polarization reversal of the ferroelectric material in the memory layer. Ultimately, this improves the read / write speed, fatigue characteristics, and data retention capabilities of the three-dimensional memory. For example, the material of the storage layer (e.g., the first sub-storage layer 51 and the second sub-storage layer 70) is HfO2. By implanting arsenic or phosphorus, the inner electrode layer 60 can generate compressive stress on the storage layer, while by implanting boron, the inner electrode layer 60 can generate tensile stress on the storage layer. By adjusting the implantation dose of the dopant element (i.e., the doping concentration of the dopant element in the inner electrode layer 60), the magnitude of the compressive and tensile stresses can be adjusted accordingly. Subsequently, rapid thermal annealing is used to fix the stress, thereby maximizing the storage effect of the storage layer and thus actively adjusting the distribution of tensile and compressive stresses between the inner electrode layer 60 and the storage layer.

[0041] In some embodiments, the first sub-external electrode layer 50 covers the inner wall of the storage hole 40 and a portion of the top surface of the intermediate dielectric layer; the specific steps for forming the second sub-external electrode layer 100 covering the second sub-storage layer 70 and the first sub-external electrode layer 50 include: Remove a portion of the storage layer on the top surface of the intermediate dielectric layer to expose the first sub-external electrode layer 50; A second sub-external electrode layer 100 is formed, covering the remaining storage layer and the exposed first sub-external electrode layer 50.

[0042] Specifically, after disconnecting the connection between the storage layers in adjacent storage cells, an electrode material such as TiN is deposited again on the substrate to form a second sub-external electrode layer 100 covering the second sub-storage layer 70 and the first sub-external electrode layer 50, as shown below. Figure 10 As shown, the first sub-external electrode layer 50 and the second sub-external electrode layer 100 together serve as the external electrode layer. By performing patterning processes such as etching on the first sub-external electrode layer 50 and the second sub-external electrode layer 100, the connection between the external electrode layers in adjacent memory cells is broken, such as... Figure 11As shown. In one example, the connection between the external electrode layers in adjacent memory cells is broken by patterning processes such as etching the first sub-external electrode layer 50 and the second sub-external electrode layer 100, and the third intermediate dielectric layer 32 is exposed away from the top surface of the substrate 20. In another example, the connection between the external electrode layers in adjacent memory cells is broken by patterning processes such as etching the first sub-external electrode layer 50, the second sub-external electrode layer 100, and the third intermediate dielectric layer 32, and a portion of the third intermediate dielectric layer 32 is etched away, exposing the second intermediate dielectric layer 31 away from the top surface of the substrate 20, to ensure that the external electrode layers in adjacent memory cells are sufficiently isolated, such as... Figure 11 As shown.

[0043] In the storage structure formed by this specific embodiment, the storage layer continuously covers the side, bottom, and top surfaces of the inner electrode layer 60, that is, the storage layer is distributed around the inner electrode layer 60 360 degrees, and the outer electrode layer fully wraps around the side, bottom, and top surfaces of the storage layer, that is, the outer electrode layer is distributed around the storage layer 360 degrees, thereby forming a wraparound storage structure. This directly increases the contact area between the storage layer and the inner electrode layer 60 and the contact area between the storage layer and the outer electrode layer under the same chip area conditions, thereby increasing the effective storage area in the storage structure and significantly improving the storage performance, read / write sensitivity, and reliability of the three-dimensional memory. Furthermore, the wraparound storage structure formed by this specific embodiment is compact, has low manufacturing difficulty, and occupies a small area, which helps to further reduce the size of the storage cell and improve the integration density of the three-dimensional memory.

[0044] Figure 14 This is a cross-sectional schematic diagram after the first lead-out structure is formed in a specific embodiment of the present invention. Figure 15 This is a top view schematic diagram after the first lead-out structure is formed in a specific embodiment of the present invention. Figure 16 This is a cross-sectional schematic diagram after the formation of the first pad in a specific embodiment of the present invention. In some embodiments, the specific steps of forming the first lead-out structure located above the substrate and electrically connected to the inner electrode layer 60 include: Part of the outer electrode layer and part of the storage layer are etched away to form an opening that exposes part of the surface of the inner electrode layer 60; A top dielectric layer is formed on the substrate, covering the intermediate dielectric layer and the storage structure and filling the opening, such as... Figure 13 As shown; A first lead-out structure 140 is formed, penetrating the top dielectric layer and electrically connected to the inner electrode layer 60 through the opening, as shown in the example. Figure 14 As shown.

[0045] In some embodiments, the orthographic projection of the opening on the substrate is located at the end of the storage hole 40 along the third direction D3, the substrate 20 includes a top surface and a bottom surface that are distributed opposite to each other, and the third direction D3 is parallel to the top surface of the substrate 20.

[0046] Specifically, by patterning the first sub-external electrode layer 50 and the second sub-external electrode layer 100 through etching, and disconnecting the connection between the external electrode layers in adjacent memory cells, a portion of the external electrode layer and a portion of the memory layer are etched away within each memory cell, forming an opening that exposes a portion of the surface of the inner electrode layer 60, such as... Figure 12 As shown. Next, silicon nitride material is deposited over the substrate to form a first top dielectric layer 131 that continuously covers the top surface of the second intermediate dielectric layer 31, the surface of the outer electrode layer, and the exposed surface of the inner electrode layer 60. Then, silicon dioxide material is deposited over the substrate to form a second top dielectric layer 132 covering the first top dielectric layer 131. Silicon oxynitride material is deposited over the substrate to form a third top dielectric layer 133 covering the second top dielectric layer 132, as shown. Figure 13 As shown, the first top dielectric layer 131, the second top dielectric layer 132, and the third top dielectric layer 133 together form the top dielectric layer. Next, along a position aligned with the opening, etching begins from the top surface of the third top dielectric layer 133 away from the substrate 20, forming a first lead-out hole that continuously penetrates the third top dielectric layer 133, the second top dielectric layer 132, and the first top dielectric layer 131 along the second direction D2, exposing the inner electrode layer 60. A second lead-out hole is also formed that continuously penetrates the third top dielectric layer 133, the second top dielectric layer 132, the first top dielectric layer 131, and the intermediate dielectric layer along the second direction D2, exposing the second contact structure 25. Conductive material such as tungsten is deposited in the first lead-out hole and the second lead-out hole. A first lead-out structure 140 is formed in the first lead-out hole, passing through the opening and electrically connected to the inner electrode layer 60. A second lead-out structure 141 is formed in the second lead-out hole, electrically connected to the second contact structure 25. Figure 14 and Figure 15 As shown. Subsequently, a first pad 160 electrically connected to the first lead-out structure 140 and a second pad 161 electrically connected to the second lead-out structure 141 are formed on the top surface of the top dielectric layer.

[0047] The orthographic projection of the opening on the substrate is located at the end of the storage via 40 along the third direction D3. This not only simplifies the formation process of the opening but also reduces the facing area between the first lead-out structure 140 and the external electrode layer, thereby reducing the parasitic capacitance effect between the first lead-out structure 140 and the external electrode layer. The top dielectric layer fills the space between the first lead-out structure 140, the external electrode layer, and the storage layer to electrically isolate the first lead-out structure 140 from the external electrode layer and the storage layer.

[0048] Figure 17 This is another cross-sectional schematic diagram after the inner electrode layer has been formed in a specific embodiment of the present invention. Figure 18 This is another cross-sectional schematic diagram after the formation of the second sub-memory layer in a specific embodiment of the present invention. Figure 19 This is another cross-sectional view after the storage layer has been formed in a specific embodiment of the present invention. Figure 20 This is another cross-sectional view after the formation of the first pad in a specific embodiment of the present invention. In some other embodiments, the inner electrode layer continuously covers the first sub-memory layer 51 of the memory hole 40 and the second sub-memory layer 70 located on the top surface of the intermediate dielectric layer; the specific steps for forming the second sub-memory layer 60 covering the inner electrode layer 60 and the first sub-memory layer 51 include: A second sub-storage layer 70 is formed, covering the exposed top surface and sidewalls of the inner electrode layer 60 and the first sub-storage layer 51.

[0049] Specifically, after depositing the inner electrode layer 60, comprising polycrystalline silicon material and doped elements, on the substrate, the inner electrode layer 60 is etched so that it not only fills the memory via 40 but also covers the first sub-memory layer 51 on the top surface of the intermediate dielectric layer, as shown below. Figure 17 As shown. Subsequently, a ferroelectric material or phase change material is deposited on the substrate to form a second sub-storage layer 70 covering the exposed top surface and sidewalls of the inner electrode layer 60 and the first sub-storage layer 51, as shown. Figure 18 As shown. By performing patterning processes such as etching on the first sub-memory layer 51 and the second sub-memory layer 70, the connection between the memory layers in adjacent memory cells is broken, and the first sub-external electrode layer 50 is exposed, as shown. Figure 19As shown. Next, an electrode material such as TiN is deposited again on the substrate to form a second sub-external electrode layer 100 covering the second sub-memory layer 70 and the first sub-external electrode layer 50. The connection between the external electrode layers in adjacent memory cells is broken by patterning processes such as etching the first sub-external electrode layer 50 and the second sub-external electrode layer 100. Then, a top dielectric layer covering the intermediate dielectric layer and the external electrode layer is formed on the substrate, and a first lead-out structure 140 is formed that penetrates the top dielectric layer and is electrically connected to the inner electrode layer 60, as shown. Figure 20 As shown. The inner electrode layer 60 not only fills the memory hole 40, but also covers the first sub-memory layer 51 on the top surface of the intermediate dielectric layer, thereby further increasing the effective storage area of ​​the memory structure and increasing the process window for subsequently forming the first lead-out structure 140, simplifying the formation process of the first lead-out structure 140.

[0050] This specific embodiment also provides a three-dimensional memory with a wraparound storage structure, wherein the three-dimensional memory with a wraparound storage structure can adopt, for example... Figures 1-20 The method for manufacturing the three-dimensional memory with a wrap-around storage structure shown is illustrated. The structure of the three-dimensional memory with the wrap-around storage structure can be found in [reference needed]. Figure 16 and Figure 20 .like Figures 1-20 As shown, the three-dimensional memory with a wrap-around storage structure includes: The substrate includes a substrate 20, a bottom dielectric layer 21 located on the substrate 20, a first contact structure 26 penetrating the bottom dielectric layer 21, an intermediate dielectric layer covering the bottom dielectric layer 21 and the first contact structure 26, and a storage via 40 penetrating the intermediate dielectric layer and exposing the first contact structure 26. A storage structure, at least located within the storage hole 40, the storage structure includes an inner electrode layer 60 at least filling the storage hole 40, a storage layer at least located within the storage hole 40 and enclosing the inner electrode layer 60, and an outer electrode layer at least covering the inner wall of the storage hole 40 and enclosing the storage layer, the outer electrode layer being electrically connected to the first contact structure 26, and the inner electrode layer 60 comprising polycrystalline silicon material and doped elements; The first lead-out structure 140 is located above the substrate and is electrically connected to the inner electrode layer 60.

[0051] Specifically, in the storage structure, the storage layer continuously covers the sides, bottom, and top of the inner electrode layer 60, meaning the storage layer is distributed 360 degrees around the inner electrode layer 60. Furthermore, the outer electrode layer fully encloses the sides, bottom, and top of the storage layer, also 360 degrees around it, forming a wraparound storage structure. This directly increases the contact area between the storage layer and the inner electrode layer 60, as well as the contact area between the storage layer and the outer electrode layer, under the same chip area conditions. This results in a larger effective storage area, significantly improving the storage performance, read / write sensitivity, and reliability of the 3D memory. Moreover, the wraparound storage structure formed in this specific embodiment is compact, has low manufacturing difficulty, and occupies a small area, which helps to further reduce the size of storage cells and improve the integration density of the 3D memory.

[0052] In some embodiments, the external electrode layer includes a first sub-external electrode layer 50 and a second sub-external electrode layer 100, wherein the first sub-external electrode layer 50 covers the inner wall of the storage hole 40, and the second sub-external electrode layer 100 is located above the first sub-external electrode layer 50 and is in contact with and electrically connected to the first sub-external electrode layer 50. The storage layer includes a first sub-storage layer 51 covering the surface of the first sub-outer electrode layer 50 and the sidewalls and bottom surface of the inner electrode layer 60, and a second sub-storage layer 70 covering at least the top surface of the inner electrode layer 60, wherein the second sub-outer electrode layer 100 covers the surface of the second sub-storage layer 70.

[0053] In some embodiments, the top surface of the inner electrode layer 60 is flush with the top surface of the first sub-storage layer 51, and the second sub-storage layer 70 only covers the top surface of the inner electrode layer 60 and the surface of the first sub-storage layer 51, such as... Figure 16 As shown.

[0054] In other embodiments, the top surface of the inner electrode layer 60 is higher than the top surface of the first sub-storage layer 51, and the second sub-storage layer 70 covers the top surface and part of the sidewalls of the inner electrode layer 60 and covers the surface of the first sub-storage layer 51, such as... Figure 20 As shown.

[0055] In some embodiments, the substrate 20 includes a top surface and a bottom surface that are distributed opposite to each other, and the inner electrode layer 60 protrudes from the storage layer and the outer electrode layer along a third direction D3 parallel to the top surface of the substrate 20. The first lead-out structure 140 is electrically connected to the inner electrode layer 60 protruding along the third direction D3.

[0056] In some embodiments, the three-dimensional memory with a wrap-around storage structure further includes: A top dielectric layer is located on the substrate and covers the intermediate dielectric layer and the storage structure. The first lead-out structure 140 penetrates the top dielectric layer along a second direction D2 and is electrically connected to the inner electrode layer 60 protruding along a third direction D3, wherein the second direction D2 intersects perpendicularly with the top surface of the substrate 20.

[0057] In some embodiments, the doping element is any one or a combination of two or more of arsenic, phosphorus and boron, and the material of the external electrode layer includes TiN, and the material of the storage layer includes a phase change material or a ferroelectric material.

[0058] For example, the inner electrode layer 60 is a low-pressure chemical vapor deposition layer, which is formed by depositing the polycrystalline silicon material through a low-pressure chemical vapor deposition process and implanting the dopant elements through an ion implantation process. Using polycrystalline silicon material including dopant elements as the inner electrode layer not only reduces the defect density between the inner electrode layer and the storage layer, improves the conversion efficiency of the phase change material and the polarization intensity of the ferroelectric material, reduces the functionality of the 3D memory, and improves the data retention performance of the 3D memory, but also allows for adjustment of the stress state of the inner electrode layer by adjusting the doping parameters of the dopant elements (such as the type and concentration of the dopant elements). This actively changes the relative stress between the inner electrode layer and the storage layer, optimizes the phase change crystal phase transition and ferroelectric polarization reversal efficiency, and improves storage performance.

[0059] This specific embodiment provides a three-dimensional memory with an enclosed storage structure and a method for manufacturing the same. By configuring the storage structure located at least within the storage hole as an inner electrode layer that at least fills the storage hole, a storage layer located at least within the storage hole and enclosing the inner electrode layer, and an outer electrode layer that at least covers the inner wall of the storage hole and encloses the storage layer, the outer electrode layer is electrically connected to a first contact structure. The inner electrode layer includes polycrystalline silicon material and doped elements, enabling the storage layer to simultaneously cover the side, bottom, and top surfaces of the inner electrode layer, and the outer electrode layer to fully enclose the side, bottom, and top surfaces of the storage layer, forming an enclosed storage structure. This results in an increased effective storage area under the same chip area conditions, significantly improving the storage performance, read / write sensitivity, and reliability of the three-dimensional memory. Meanwhile, using polycrystalline silicon material including doped elements as the inner electrode layer can not only reduce the defect density between the inner electrode layer and the storage layer, improve the conversion efficiency of the phase change material and the polarization intensity of the ferroelectric material, reduce the functionality of the three-dimensional memory, and improve the data retention performance of the three-dimensional memory, but also adjust the stress state of the inner electrode layer by adjusting the doping parameters of the doped elements in the inner electrode layer (such as the type and concentration of the doped elements), thereby actively changing the relative stress between the inner electrode layer and the storage layer, optimizing the phase change crystal phase transition and ferroelectric polarization reversal efficiency, improving storage performance, and increasing the diversity of electrode material selection and circuit design.

[0060] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0061] It should be noted that the terms "comprising" and "having," and their variations, used in this invention document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context. It should be understood that such data used interchangeably where appropriate. Furthermore, embodiments and features within embodiments of this invention can be combined with each other unless otherwise specified. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar or identical parts between embodiments can be referred to interchangeably.

[0062] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for manufacturing a three-dimensional memory with a wraparound storage structure, characterized in that, Includes the following steps: A substrate is formed, the substrate including a substrate, a bottom dielectric layer on the substrate, a first contact structure penetrating the bottom dielectric layer, an intermediate dielectric layer covering the bottom dielectric layer and the first contact structure, and a storage via penetrating the intermediate dielectric layer and exposing the first contact structure. A storage structure is formed at least within the storage hole. The storage structure includes an inner electrode layer that is at least filled within the storage hole, a storage layer that is at least within the storage hole and encloses the inner electrode layer, and an outer electrode layer that at least covers the inner wall of the storage hole and encloses the storage layer. The outer electrode layer is electrically connected to the first contact structure. The inner electrode layer includes polycrystalline silicon material and doping elements. A first lead-out structure is formed above the substrate and electrically connected to the inner electrode layer.

2. The method for manufacturing a three-dimensional memory with a wraparound storage structure according to claim 1, characterized in that, The specific steps of forming a substrate, the substrate comprising a substrate, a bottom dielectric layer on the substrate, a first contact structure penetrating the bottom dielectric layer, an intermediate dielectric layer covering the bottom dielectric layer and the first contact structure, and a storage via penetrating the intermediate dielectric layer and exposing the first contact structure, include: A substrate is provided, the substrate including an active region, and the substrate including a top surface and a bottom surface that are distributed opposite to each other, the active region including a channel region and a source region and a drain region distributed on opposite sides of the channel region along a first direction, the first direction being parallel to the top surface of the substrate; Form the bottom dielectric layer covering the top surface of the substrate; A first contact structure is formed that penetrates the bottom dielectric layer along a second direction and is electrically connected to the drain region, wherein the second direction intersects the top surface of the substrate perpendicularly; An intermediate dielectric layer is formed covering the bottom dielectric layer and the first contact structure; The storage hole is formed by penetrating the intermediate medium layer along the second direction and exposing the first contact structure.

3. The method for manufacturing a three-dimensional memory with a wraparound storage structure according to claim 1, characterized in that, The intermediate dielectric layer includes: A first intermediate dielectric layer covers the bottom dielectric layer and the first contact structure, and the material of the first intermediate dielectric layer includes silicon nitride; A second intermediate dielectric layer covering the first intermediate dielectric layer, wherein the material of the second intermediate dielectric layer includes silicon dioxide; A third intermediate dielectric layer covers the second intermediate dielectric layer, and the material of the third intermediate dielectric layer includes silicon oxynitride.

4. The method for manufacturing a three-dimensional memory with a wraparound storage structure according to claim 1, characterized in that, Forming a storage structure at least within the storage aperture, the storage structure including an inner electrode layer at least filled within the storage aperture, a storage layer at least within the storage aperture and enclosing the inner electrode layer, and an outer electrode layer at least covering the inner wall of the storage aperture and enclosing the storage layer, wherein the outer electrode layer is electrically connected to the first contact structure includes the following steps: A first sub-outer electrode layer is formed that at least covers the inner wall of the storage hole; A first sub-memory layer is formed covering the first sub-outer electrode layer; The polycrystalline silicon material is deposited on the substrate, and the doping element is implanted into the polycrystalline silicon material to form the inner electrode layer that covers the first sub-memory layer and fills the memory hole; A second sub-storage layer is formed that covers the inner electrode layer and the first sub-storage layer, and the first sub-storage layer and the second sub-storage layer together serve as the storage layer; A second sub-external electrode layer is formed that covers the second sub-memory layer and the first sub-external electrode layer, wherein the first sub-external electrode layer and the second sub-external electrode layer together serve as the external electrode layer.

5. The method for manufacturing a three-dimensional memory with a wraparound storage structure according to claim 4, characterized in that, The specific steps of depositing the polycrystalline silicon material on the substrate and implanting the dopant element into the polycrystalline silicon material to form the inner electrode layer covering the first sub-memory layer and filling the memory holes include: The polycrystalline silicon material is deposited on the substrate using a low-pressure chemical vapor deposition process to form a polycrystalline silicon material layer. The doping element is implanted into the polycrystalline silicon material layer using an ion implantation process to form the inner electrode layer that covers the first sub-memory layer and fills the memory hole.

6. The method for manufacturing a three-dimensional memory with a wraparound storage structure according to claim 4, characterized in that, Before forming the second sub-memory layer covering the inner electrode layer and the first sub-memory layer, the following steps are also included: The inner electrode layer is planarized using a chemical mechanical polishing process, so that the top surface of the planarized inner electrode layer is flush with the top surface of the first sub-storage layer.

7. The method for manufacturing a three-dimensional memory with a wraparound storage structure according to claim 4, characterized in that, The inner electrode layer continuously covers the first sub-storage layer of the storage hole and the second sub-storage layer located on the top surface of the intermediate dielectric layer; the specific steps for forming the second sub-storage layer covering the inner electrode layer and the first sub-storage layer include: A second sub-storage layer is formed, covering the exposed top surface and sidewalls of the inner electrode layer and the first sub-storage layer.

8. The method for manufacturing a three-dimensional memory with a wraparound storage structure according to claim 4, characterized in that, The first sub-external electrode layer covers the inner wall of the storage hole and part of the top surface of the intermediate dielectric layer; The specific steps for forming the second sub-external electrode layer covering the second sub-memory layer and the first sub-external electrode layer include: Remove a portion of the storage layer on the top surface of the intermediate dielectric layer to expose the first sub-external electrode layer; A second sub-external electrode layer is formed that covers the remaining storage layer and the exposed first sub-external electrode layer.

9. The method for manufacturing a three-dimensional memory with a wraparound storage structure according to claim 1, characterized in that, The specific steps for forming the first lead-out structure located above the substrate and electrically connected to the inner electrode layer include: Part of the outer electrode layer and part of the storage layer are etched away to form an opening that exposes part of the surface of the inner electrode layer; A top layer is formed on the substrate, covering the intermediate medium layer and the storage structure and filling the opening; A first lead-out structure is formed that penetrates the top dielectric layer and is electrically connected to the inner electrode layer through the opening.

10. The method for manufacturing a three-dimensional memory with a wraparound storage structure according to claim 9, characterized in that, The orthographic projection of the opening on the substrate is located at the end of the storage hole along a third direction. The substrate includes a top surface and a bottom surface that are distributed opposite to each other, and the third direction is parallel to the top surface of the substrate.

11. A three-dimensional memory with a wrap-around storage structure, characterized in that, include: The substrate includes a substrate, a bottom dielectric layer on the substrate, a first contact structure penetrating the bottom dielectric layer, an intermediate dielectric layer covering the bottom dielectric layer and the first contact structure, and a storage via penetrating the intermediate dielectric layer and exposing the first contact structure. A storage structure, at least located within the storage hole, the storage structure including an inner electrode layer at least filled within the storage hole, a storage layer at least located within the storage hole and enclosing the inner electrode layer, and an outer electrode layer at least covering the inner wall of the storage hole and enclosing the storage layer, the outer electrode layer being electrically connected to the first contact structure, the inner electrode layer comprising polycrystalline silicon material and doping elements; The first lead-out structure is located above the substrate and is electrically connected to the inner electrode layer.

12. The three-dimensional memory with a wraparound storage structure according to claim 11, characterized in that, The outer electrode layer includes a first sub-outer electrode layer and a second sub-outer electrode layer. The first sub-outer electrode layer covers the inner wall of the storage hole, and the second sub-outer electrode layer is located above the first sub-outer electrode layer and is in contact with and electrically connected to the first sub-outer electrode layer. The storage layer includes a first sub-storage layer covering the surface of the first sub-outer electrode layer and the sidewalls and bottom surface of the inner electrode layer, and a second sub-storage layer covering at least the top surface of the inner electrode layer, wherein the second sub-outer electrode layer covers the surface of the second sub-storage layer.

13. The three-dimensional memory with a wraparound storage structure according to claim 12, characterized in that, The top surface of the inner electrode layer is flush with the top surface of the first sub-storage layer, and the second sub-storage layer only covers the top surface of the inner electrode layer and the surface of the first sub-storage layer.

14. The three-dimensional memory with a wraparound storage structure according to claim 12, characterized in that, The top surface of the inner electrode layer is higher than the top surface of the first sub-storage layer, and the second sub-storage layer covers the top surface and part of the sidewalls of the inner electrode layer and covers the surface of the first sub-storage layer.

15. The three-dimensional memory with a wraparound storage structure according to claim 11, characterized in that, The substrate includes a top surface and a bottom surface that are oppositely distributed, and the inner electrode layer protrudes from the storage layer and the outer electrode layer in a third direction parallel to the top surface of the substrate. The first lead-out structure is electrically connected to the inner electrode layer protruding along the third direction.

16. The three-dimensional memory with a wrap-around storage structure according to claim 15, characterized in that, Also includes: A top dielectric layer is located on the substrate and covers the intermediate dielectric layer and the storage structure. The first lead-out structure penetrates the top dielectric layer along a second direction and is electrically connected to the inner electrode layer protruding along the third direction, wherein the second direction intersects perpendicularly with the top surface of the substrate.

17. The three-dimensional memory with a wraparound storage structure according to claim 11, characterized in that, The doping element is any one or a combination of two or more of arsenic, phosphorus and boron, and the material of the external electrode layer includes TiN, while the material of the storage layer includes a phase change material or a ferroelectric material.

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