Semiconductor structure, methods for forming semiconductor structures, memory and electronic devices

Abstract

This application relates to a semiconductor structure, a method for forming the semiconductor structure, a memory, and an electronic device. The semiconductor structure includes multiple semiconductor dies arranged in a stacked configuration; each semiconductor die has: multiple memory arrays arranged along a first direction; solder ball regions disposed in the gaps between adjacent memory arrays and located on the edge of the memory arrays closest to the gaps; data ports arranged adjacent to the solder ball regions and serving only the data channels of their respective semiconductor dies; a control module located between two data ports of its respective semiconductor die; and array power lines arranged along a second direction, perpendicular to the first direction. This application can improve chip performance.

Description

Technical Field

[0001] This application relates to the field of semiconductor storage technology, and in particular to a semiconductor structure, a method for forming a semiconductor structure, a memory, and an electronic device. Background Technology

[0002] High-speed memory is widely used in graphics cards, high-performance computing, and artificial intelligence acceleration. To achieve high-bandwidth data transmission, dual-channel architecture has become the core of memory chip design. However, most memory chips adopt a single-die dual-channel architecture design, integrating two data channels onto the same die. This easily leads to long wiring and long paths, affecting chip performance. Summary of the Invention

[0003] Therefore, it is necessary to provide a semiconductor structure, a method for forming the semiconductor structure, a memory, and an electronic device that can improve chip performance in response to the above-mentioned technical problems.

[0004] In a first aspect, this application provides a semiconductor structure including a plurality of semiconductor dies spliced ​​together; each semiconductor die is provided with: a plurality of memory arrays arranged along a first direction; a solder ball region disposed in the gap between adjacent memory arrays and located on the edge of the memory array near the gap; a data port arranged adjacent to the solder ball region and serving only the data channel of its respective semiconductor die; a control module located between two data ports of its respective semiconductor die; and an array power line arranged along a second direction, the second direction being perpendicular to the first direction.

[0005] In one embodiment, adjacent semiconductor dies have the same function and specifications.

[0006] In one embodiment, after adjacent semiconductor dies are spliced ​​together, the corresponding control modules are symmetrically distributed in the second direction and located in the middle of the semiconductor structure in the first direction.

[0007] In one embodiment, the semiconductor die is a single-channel die; each single-channel die independently carries the function of a data channel.

[0008] In one embodiment, the number of single-channel dies is determined based on the total bandwidth and storage capacity of the single-die packaged semiconductor chip.

[0009] In one embodiment, the number of single-channel dies is two.

[0010] In one embodiment, the second direction includes the short side direction of the single-channel die.

[0011] In one embodiment, the length of the package wiring between the data port and the solder ball area does not exceed 1 / 4 of the side length of a single-channel die.

[0012] In one embodiment, the solder ball region located on one side edge of one adjacent memory array near the gap is a first solder ball region, and the solder ball region located on one side edge of another adjacent memory array near the gap is a second solder ball region; the first solder ball region and the second solder ball region are arranged separately in a second direction; or, the first solder ball region and the second solder ball region are arranged opposite to each other in a second direction.

[0013] In one embodiment, each semiconductor die also has an on-chip data path; the on-chip data path is used to connect the data port of a single data channel to the memory array.

[0014] In one embodiment, the memory array of each semiconductor die is divided into independent Bank groups, and the distribution of on-chip data paths corresponds one-to-one with the distribution of Bank groups.

[0015] Secondly, this application also provides a method for forming a semiconductor structure, comprising: acquiring a plurality of semiconductor dies, each semiconductor die having a plurality of memory arrays arranged along a first direction; on each semiconductor die, setting solder ball regions in the gaps between adjacent memory arrays and located on the edge of the memory arrays near the gaps; arranging data ports adjacent to the solder ball regions, such that the data ports only serve the data channels of their respective semiconductor dies; arranging a control module between two data ports of their respective semiconductor dies; arranging array power lines along a second direction, the second direction being perpendicular to the first direction; and splicing the plurality of semiconductor dies to form a semiconductor structure.

[0016] In one embodiment, splicing multiple semiconductor dies includes physically splicing adjacent semiconductor dies so that the corresponding control modules are symmetrically distributed in the second direction and located in the middle of the semiconductor structure in the first direction.

[0017] In one embodiment, the method further includes: dividing the memory array of each semiconductor die into independent Bank groups; and planning on-chip data paths according to the distribution of the Bank groups so that the on-chip data paths only cover the memory cells of the data channels of the semiconductor die to which they belong.

[0018] Thirdly, this application also provides a memory, which includes the above-described semiconductor structure.

[0019] Fourthly, this application also provides an electronic device, which includes the aforementioned memory.

[0020] The aforementioned semiconductor structure, method for forming the semiconductor structure, memory, and electronic device include a semiconductor structure comprising multiple semiconductor dies joined together; each semiconductor die has multiple memory arrays arranged along a first direction, solder ball regions located in the gaps between adjacent memory arrays and situated on the edge of the memory arrays near the gaps, data ports located adjacent to the solder ball regions and serving only the data channels of its respective semiconductor die, a control module located between two data ports of its respective semiconductor die, and array power lines arranged along a second direction perpendicular to the first direction. This application proposes a split-chip architecture and layout method, which shortens critical wiring and path lengths and improves the chip's signal stability, power supply anti-interference capability, and data transmission performance through the split design of multiple semiconductor dies. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of a traditional single-die dual-channel architecture;

[0023] Figure 2 This is a schematic diagram of the semiconductor structure in one embodiment;

[0024] Figure 3 This is a schematic diagram of the semiconductor structure in another embodiment;

[0025] Figure 4 This is a schematic diagram of a specific semiconductor structure in one embodiment;

[0026] Figure 5 This is a schematic flowchart of a method for forming a semiconductor structure in one embodiment. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0028] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0029] High-speed memory, taking GDDR6 (Graphics Double Data Rate 6 Synchronous Dynamic Random-Access Memory) as an example, is a new generation of high-speed graphics double data rate synchronous dynamic random-access memory, widely used in graphics cards, high-performance computing, artificial intelligence acceleration, and other fields. GDDR6's dual-channel architecture is the core of achieving high-bandwidth data transmission. However, traditional dual-channel GDDR6 memory chips mostly adopt a single-die dual-channel architecture design, integrating two data channels onto the same die.

[0030] like Figure 1 As shown, the traditional single-die dual-channel architecture has at least the following problems: ① Signal integrity degradation: The distance between the DQ (DATA) solder ball area and one of the DQ / WCK (Write Clock) signal modules is too far, resulting in excessively long DQ package wiring. This easily leads to signal integrity (SI) degradation during high-speed signal transmission, affecting the accuracy of data transmission; ② Power supply noise sensitivity: To cover the memory array of two data channels, the array power lines need to extend along the long side of the die. The excessive length makes the power lines highly susceptible to power supply noise interference, reducing the operational stability of the memory array; ③ Performance loss: The on-chip data path needs to span the memory cells of two data channels. The excessively long path leads to increased data read / write latency, significantly reducing the overall performance of the chip.

[0031] It should be noted that the DQ / WCK signal module can be referred to as a data port. Figure 1 The multiple rectangular blocks shown represent memory chips (such as video memory chips). Read and write operations on these chips require clock and data alignment during transmission, known as WCK / DQ. CA / CK stands for Command Address and its clock, used for instruction time-domain synchronization and address selection with the memory chips. Optionally, the DQ solder ball area can be filled with solder. This is understandable. Figure 1The dashed arrows indicate the on-chip data paths. All long traces degrade signal and power, posing risks to signal and power integrity and causing insufficient drive.

[0032] To address this, this application provides a split chip architecture and layout method. Through a split design of single-channel / single die, it shortens critical wiring and path lengths, improves chip signal stability, power supply anti-interference capability, and data transmission performance, overcoming the shortcomings of traditional single-die dual-channel architectures such as GDDR6. For example, this application can be applied to high-speed memory chip design, specifically relating to a split chip architecture and layout scheme for dual-channel GDDR6 memory chips. It is suitable for die design and package layout optimization of GDDR6 memory chips, improving the PHY (Physical Layer) layout and chip layout of GDDR6.

[0033] It should be noted that the beneficial effects or technical problems solved by the embodiments of this application are not limited to this one, but may also include other implicit or related problems. Please refer to the description of the embodiments below for details. The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0034] In one exemplary embodiment, such as Figure 2 As shown, a semiconductor structure is provided, including multiple semiconductor dies 100 spliced ​​together; each semiconductor die 100 is provided with a memory array 102, a solder ball region 104, a data port 106, a control module 108, and an array power line 110, wherein the multiple memory arrays 102 are arranged along a first direction, the solder ball region 104 is disposed in the gap 20 between adjacent memory arrays 102 and is located on the edge of the memory array 102 near the gap 20; the data port 106 is arranged adjacent to the solder ball region 104 and serves only the data channel of its respective semiconductor die; the control module 108 is located between two data ports of its respective semiconductor die; the array power line 110 is arranged along a second direction, which is perpendicular to the first direction.

[0035] Specifically, the semiconductor structure in this application embodiment may include multiple semiconductor dies 100 spliced ​​together. Furthermore, each semiconductor die 100 has an independent function. Through this split architecture, the multi-channel function is split onto each functionally independent semiconductor die, and the layout of each functional module on the die is optimized, thereby fundamentally shortening the critical path length and thus comprehensively improving the overall performance of the chip.

[0036] In this application's embodiments, "stitching" can refer to physical stitching, such as the process of combining, aligning, and connecting two or more independent die layouts at the software level during the semiconductor layout design phase to ultimately generate a single, manufacturable, complete chip layout. Exemplarily, physical stitching can be performed by a layout engineer or a physical engineer (PD).

[0037] Each semiconductor die 100 is functionally independent, meaning that the semiconductor die is physically independent and can independently carry the circuitry required for the data channel (such as memory array, signal processing, control drive, etc.). Figure 2 The 10 in the diagram refers to the PHY, or physical layer, while the storage array 102 can be a matrix area on the chip composed of massive memory cells, which is the core part that actually performs data storage functions. In this embodiment, the storage array 102 can include multiple chips. Reading and writing operations to these chips can be performed by the CPU (Central Processing Unit) transmitting corresponding signals to the chips through the physical layer. For example, the circuit layout of this application can be generated by changing the arrangement of the chips.

[0038] Each semiconductor die 100 has multiple memory arrays 102. Optionally, a solder ball region 104, a data port 106, and a control module 108 are also provided in the gap 20 between adjacent memory arrays 102 of each semiconductor die 100. The solder ball region 104 is located on the edge of the memory array 102 near the gap 20, and this region is the physical interface for data signal connection between the chip and the external packaging substrate. Furthermore, a data port 106 is arranged adjacent to the solder ball region 104. This close proximity arrangement results in a very short connection path from the internal physical layer circuitry of the chip to the external solder balls. Each data port 106 serves only its own data channel, thereby greatly improving the transmission quality of high-speed data signals. It should be noted that, although not shown, Figure 2 The data port 106 on the right side is also located right next to the solder ball area.

[0039] Taking the DQ solder ball area as an example and the DQ / WCK signal module as the data port, the DQ solder ball area is concentrated on one edge of each semiconductor die, providing a physical interface for the input and output of the DQ signal. The DQ / WCK signal module is arranged adjacent to the DQ solder ball area, so that each DQ / WCK signal module only serves its own data channel, which greatly shortens the length of the DQ package wiring and solves the signal integrity degradation problem caused by excessive wiring in the traditional architecture.

[0040] Regarding the control module 108, it is disposed in the gap 20 between adjacent memory arrays 102, and located between the two data ports of the semiconductor die. It can be understood that in this embodiment, the control module is disposed on the same side as the data ports, specifically between these two data ports. This layout concentrates the control core and the data transceiver physical layer on the same side, facilitating unified management of the high-speed signal area. Taking the data port using a DQ / WCK signal module and the control module using a CA / CK control module as an example, compared to the traditional design where the DQ / WCK signal module and CA / CK control module are placed together to correspond to two channels, this application separates these components into two independent channels, thereby achieving a split-die design.

[0041] Furthermore, regarding the array power lines supplying power to the storage array, this application proposes that the array power lines 110 be arranged along a second direction, which is perpendicular to the first direction. For example... Figure 2 As shown, the storage array 102 is a rectangular area, and the second direction is parallel to the short side of the rectangular area. The routing direction of the array power line 110 is planned to be arranged along the short side of the rectangular area. Compared with the traditional design where the power line needs to cross the entire long side of the chip, this design significantly shortens the length of the power line.

[0042] It should be noted that the number of memory arrays on both sides of gap 20 can be the same; it is understood that the modules in the above semiconductor die can also adopt other arrangements, not limited to the forms mentioned in the above embodiments, as long as they can make the functions of each semiconductor die independent.

[0043] The aforementioned semiconductor structure, by employing a split die design, shortens the package wiring length and reduces the array power line length. By shortening the critical wiring and path length, it improves the chip's signal stability, power supply anti-interference capability, and data transmission performance.

[0044] In one embodiment, adjacent semiconductor dies have the same function and specifications. Specifically, adjacent semiconductor dies that are spliced ​​together have the same function and specifications. For example, the functions and specifications of two semiconductor dies are completely identical, and the function of each semiconductor die is independent, thereby realizing a split-die design with a single channel / single die, which can shorten the length of critical wiring and paths.

[0045] Taking the traditional single-die dual-channel architecture as an example, based on the embodiments of this application, the traditional single-die dual-channel architecture can be split into two independent single-channel dies. The two dies are spliced ​​together to form a complete dual channel, wherein the functions and specifications of the two single-channel dies are completely identical.

[0046] This application employs a split-die design, allowing for independent development and optimization of single channels / single dies, reducing the overall chip development difficulty and risk. This split design improves technology reusability, accelerates product iteration, and provides high design and iteration flexibility, effectively controlling costs. Specifically, the split-die design enables independent optimization and iteration of individual channels, reducing chip development difficulty and cost, improving product iteration efficiency, and offering high design flexibility.

[0047] In some embodiments, after adjacent semiconductor dies are spliced ​​together, the corresponding control modules are symmetrically distributed in the second direction and located in the middle of the semiconductor structure in the first direction. Specifically, for the control modules, after the adjacent semiconductor dies are spliced ​​together, their respective control modules present a symmetrical layout in the middle of the final semiconductor structure. This ensures that the physical path lengths of commands, addresses, and clock signals issued from the central region of the chip to the corresponding circuits inside the two independent semiconductor dies are strictly equal, thereby eliminating clock offset between channels and ensuring synchronous operation between data channels.

[0048] Taking two semiconductor dies as an example, after adjacent semiconductor dies are spliced ​​together, as follows: Figure 3 As shown, the first direction is parallel to the long side of the semiconductor die, and the second direction is parallel to the short side of the semiconductor die. The corresponding control modules are symmetrically distributed along the short side of the semiconductor die and located in the middle of the semiconductor structure along the long side. That is, after the two dies are joined, the control modules are symmetrically distributed in the middle of the semiconductor structure (e.g., a chip), ensuring synchronous driving of the two data channels by the control signals. Figure 3 As shown, the control modules of the two semiconductor dies are symmetrical both vertically and horizontally. Compared with the traditional solution, this reduces the routing distance and improves routing matching.

[0049] Regarding the semiconductor dies in the embodiments of this application, in some embodiments, the semiconductor die is a single-channel die; each single-channel die independently carries the function of one data channel. Specifically, the semiconductor structure includes multiple single-channel dies spliced ​​together, and each single-channel die is completely identical in function and specifications. In this application, each single-channel die can independently carry the function of a complete data channel, thereby avoiding signal crosstalk and resource contention that may occur between multiple channels on the same die from the source, that is, avoiding mutual interference between multiple channels on a single die.

[0050] In this context, a single-channel die refers to a semiconductor die that is physically independent and functionally complete, carrying all the circuitry required for a single data channel. Taking the application of semiconductor structures in GDDR6 memory chips as an example, based on this application, the traditional single-die dual-channel architecture can be split into two independent single-channel dies, which are then spliced ​​together to form a complete dual-channel architecture. The two single-channel dies designed separately have completely identical functions and specifications, with each single-channel die independently carrying all the functions of a data channel, including memory array, signal processing, and control driving, thus avoiding mutual interference between multiple channels on a single die.

[0051] In one embodiment, the number of single-channel dies is determined based on the total bandwidth and storage capacity of the single-die packaged semiconductor chip. Specifically, the number of single-channel dies that can be split can be determined based on the specifications of the single-die packaged semiconductor chip to be split, such as the total bandwidth and storage capacity. Taking a dual-channel GDDR6 memory chip as an example, it can be split by specification, that is, based on the specifications of the dual-channel GDDR6 memory chip, such as the total bandwidth and storage capacity, it can be split into two functionally independent single-channel dies with the same specifications, each single-channel die undertaking the function of one data channel.

[0052] In one embodiment, the number of single-channel dies is two. Specifically, the semiconductor structure in this application may include two single-channel dies physically joined together, the two single-channel dies having the same function and specifications, and each single-channel die independently carrying the function of one data channel.

[0053] In some embodiments, the second direction includes the short side direction of the single-channel die. Specifically, the second direction in this application may include the short side direction of the single-channel die; in the embodiments of this application, the array power lines that power the memory array are routed along the short side direction of the single-channel die, which significantly shortens the power line length compared to conventional designs.

[0054] like Figure 3 As shown, the array power lines are arranged along the short side of the single-channel die, and their length is only half that of the traditional single-die dual-channel architecture. This effectively reduces power supply noise interference to the memory array and improves power supply stability. In practical applications, the power line layout in semiconductor structures can arrange the array power lines along the short side of the single-channel die to match the range of the single-channel memory array, reducing the power line impedance by more than 30% compared to the traditional architecture and improving power supply anti-interference capability.

[0055] The aforementioned semiconductor structure enhances power supply anti-interference capabilities, halves the array power line length, reduces impedance by more than 30%, effectively resists power supply noise interference, improves the operational stability of the storage array, and ensures the reliability of data storage.

[0056] In one embodiment, the package wiring length between the data port and the solder ball area does not exceed 1 / 4 of the single-channel die side length. Specifically, to ensure signal integrity, the package wiring length between the data port and the solder ball area needs to be set in this application. For example, the wiring length does not exceed 1 / 4 of the single-channel die side length. Taking the solder ball area as a packaged DQ solder ball area and the data port as a DQ / WCK signal module as an example, this application arranges the packaged DQ solder ball area on one edge of the single-channel die and then sets the DQ / WCK signal module adjacent to the solder ball area to ensure that the DQ package wiring length is minimized (not exceeding 1 / 4 of the die side length) and to avoid signal integrity degradation.

[0057] The aforementioned semiconductor structure, by constraining the package wiring length to an extremely short range, can ensure signal integrity. For example, it effectively suppresses impedance mismatch effects and parasitic inductance and capacitance effects during high-frequency signal transmission, thereby significantly reducing signal distortion and achieving higher data transmission rates. This application, by employing a split die design, places the DQ / WCK signal modules adjacent to the DQ solder ball area of ​​the package, significantly improving signal integrity. The DQ package wiring length is shortened by more than 50%, completely solving the SI degradation problem caused by excessive wiring in traditional architectures, and improving the accuracy of high-speed signal transmission by 40%.

[0058] In one embodiment, the solder ball region located on one side edge of one adjacent memory array near the gap is a first solder ball region, and the solder ball region located on one side edge of another adjacent memory array near the gap is a second solder ball region; the first solder ball region and the second solder ball region are arranged separately in a second direction; or, the first solder ball region and the second solder ball region are arranged opposite to each other in a second direction.

[0059] Specifically, regarding the solder ball regions (e.g., the first and second solder ball regions) located on one side edge of the memory array near the gap, they can be staggered or not. In practical applications, signal integrity analysis can be used to determine whether the solder ball regions should be staggered. Placing the solder ball regions on one side edge of a single-channel die, for example, concentrating the DQ package solder ball regions on one side edge of each single-channel die, provides a physical interface for the input and output of the DQ signal, such as... Figure 3As shown, the first solder ball region and the second solder ball region can be arranged separately in a second direction (e.g., the short side direction of the semiconductor die), or they can be arranged opposite each other in the second direction. It should be noted that the first solder ball region and the second solder ball region can also be arranged intersecting in the second direction.

[0060] Regarding on-chip data paths, in some embodiments, each semiconductor die also has an on-chip data path used to connect the data port of a single data channel to the memory array. Specifically, such as... Figure 3 As shown, in this embodiment, the on-chip data path connects only the data port of a single data channel to the storage array. Taking the DQ / WCK signal module as an example, the on-chip data path connects only the DQ / WCK signal module of a single data channel to the storage array. The path length is shortened by 40% to 60% compared to the traditional architecture, avoiding the performance degradation caused by long paths and improving data read and write efficiency.

[0061] In the aforementioned semiconductor structure, each semiconductor die also has an on-chip data path, which is specifically used to connect the DQ / WCK signal module and the memory array within this channel, thus achieving localization of the data path. This application can significantly optimize data transmission performance. Because the on-chip data path only needs to be connected within a single channel, its length is shortened by 40% to 60%, significantly reducing data read / write latency (by more than 25%), and ultimately improving the overall effective bandwidth performance of the chip by 15% to 20%.

[0062] Furthermore, in one embodiment, the memory array of each semiconductor die is divided into independent Bank groups, and the distribution of on-chip data paths corresponds one-to-one with the distribution of Bank groups. Specifically, this application shortens data transmission paths through data path planning. For example... Figure 3 As shown, the memory array matching design divides the memory array of each semiconductor die into independent Bank groups. The on-chip data paths correspond one-to-one with the distribution of Bank groups, realizing localized data transmission within a single channel and further optimizing data transmission latency.

[0063] Taking a single-channel semiconductor die as an example, the on-chip data path is planned according to the Bank group distribution of the single-channel die, ensuring that the path only covers the memory cells of the current channel, thus shortening the data transmission path. It can be understood that the memory array of each single-channel die can be divided into multiple independent Bank groups, thereby further reducing data access latency and improving parallel processing capabilities. Here, a Bank group is a logical and physical partitioning unit within the memory array, and access to different Bank groups can be performed in parallel to a certain extent. Correspondingly, the distribution of on-chip data paths also corresponds one-to-one with the distribution of Bank groups. That is, the data path from the DQ / WCK signal module to the relevant Bank group is dedicated or at least localized, avoiding the situation where data needs to traverse the entire memory array to reach its destination. This achieves a high degree of localization of data access within a single channel, significantly reducing on-chip access latency.

[0064] To further illustrate the solution of this application, a specific example is provided below, using a split-chip architecture of a dual-channel GDDR6 memory chip as an example, such as... Figure 4 As shown, the core architecture of this application is a split-die design with a single channel / single die, which splits the traditional single die dual-channel architecture into two independent single-channel dies, and the two dies are spliced ​​together to form a complete dual channel.

[0065] The specific structure of the GDDR6 memory chip includes a single-channel die split design. The two single-channel dies have completely identical functions and specifications. Each die independently carries all the functions of a data channel, including memory array, signal processing, control drive, etc., avoiding mutual interference between multiple channels on a single die.

[0066] Furthermore, this application proposes a layout optimization for the core module: the DQ solder ball area is centrally located on one edge of each single-channel die, providing a physical interface for the input and output of DQ signals. The DQ / WCK signal modules are arranged adjacent to the DQ solder ball area, ensuring that each DQ / WCK signal module serves only its own single channel, significantly shortening the length of the DQ package wiring and completely solving the signal integrity degradation problem caused by excessive wiring in traditional architectures.

[0067] Furthermore, the CA / CK control module is positioned on the same side as the DQ / WCK signal module, and between the two DQ / WCK signal modules of a single die. After the two dies are spliced ​​together, the CA / CK control modules are symmetrically distributed in the middle of the chip, ensuring synchronous drive of the control signals for the two data channels. The array power lines are arranged along the short side of the single-channel die, and their length is only half that of the traditional single-die dual-channel architecture, effectively reducing power supply noise interference to the memory array and improving power supply stability.

[0068] The on-chip data path connects only the DQ / WCK signal module of a single data channel to the memory array, shortening the path length by 40% to 60% compared to traditional architectures. This avoids performance degradation caused by long paths and improves data read / write efficiency. The memory array matching design divides the memory array of each single-channel die into independent Bank groups. The on-chip data path corresponds one-to-one with the distribution of Bank groups, enabling localized data transmission within a single channel and further optimizing data transmission latency.

[0069] It should be noted that, Figure 4 The two F's in the text indicate that the physical layout is mirror-symmetric.

[0070] Based on the same inventive concept, this application also provides a method for forming the aforementioned semiconductor structure. The solution provided by this method is similar to the implementation described in the above-described semiconductor structure; therefore, the specific limitations in one or more method embodiments provided below can be found in the limitations regarding the semiconductor structure described above, and will not be repeated here.

[0071] In one exemplary embodiment, such as Figure 5 As shown, a method for forming a semiconductor structure is provided. Taking the formation of the above-mentioned semiconductor structure by this method as an example, the method includes the following steps 202 to 206.

[0072] Step 202: Obtain multiple semiconductor dies, each semiconductor die having multiple memory arrays arranged along a first direction.

[0073] Specifically, the semiconductor dies obtained in this application embodiment are functionally independent, thereby realizing a split-die design with a single channel and a single die. Each semiconductor die has multiple memory arrays arranged along a first direction.

[0074] For example, multiple semiconductor dies can be obtained by splitting specifications.

[0075] Step 204: On each semiconductor die, a solder ball region is placed in the gap between adjacent memory arrays and located on the edge of the memory array near the gap; a data port is arranged adjacent to the solder ball region, and the data port serves only the data channel of its respective semiconductor die; a control module is arranged between the two data ports of its respective semiconductor die; and the array power lines are arranged along a second direction, which is perpendicular to the first direction.

[0076] Specifically, this application proposes a split-layout method that shortens critical wiring and path lengths by optimizing the layout of functional modules on a semiconductor die. Specifically, module layout is performed on each semiconductor die. In the layout of the solder ball area and data ports, the solder ball area is placed on one edge of the semiconductor die, and the data ports are then positioned adjacent to this solder ball area. The core objective of this step is to minimize the package lead-out length of high-speed data signals, ensuring that each data port serves only its own single channel. Subsequently, in the control module layout, the control module is placed on the same edge as the two data ports, positioned between them. Following this, power line planning is performed. In the power line layout, the array of power lines can be arranged along the short side of the semiconductor die, thereby shortening the power line length and reducing its impedance.

[0077] Step 206: Multiple semiconductor dies are spliced ​​together to form a semiconductor structure.

[0078] Specifically, in die splicing, two semiconductor die layouts that have been laid out through the above steps can be physically spliced ​​together to form the final complete layout of the semiconductor structure.

[0079] The above-mentioned semiconductor structure formation method provides a layout method for a split chip architecture. Through a split design of single channel / single die, the length of critical wiring and path is shortened, thereby improving the chip's signal stability, power supply anti-interference capability, and data transmission performance.

[0080] In one embodiment, splicing multiple semiconductor dies includes physically splicing adjacent semiconductor dies so that the corresponding control modules are symmetrically distributed in a second direction and located in the middle of the semiconductor structure in a first direction. Specifically, during the physical splicing of the semiconductor dies, alignment operations can be performed. Taking two single-channel dies as an example, when splicing two single-channel dies, precise alignment is required to ensure that the two CA / CK control modules are symmetrically distributed in the middle of the final chip layout. This symmetry can be guaranteed by setting alignment constraints in the layout splicing tool. The embodiments of this application can achieve synchronous arrival of control signals between the two channels, ensuring the overall timing performance of the chip.

[0081] In one embodiment, the method further includes: dividing the memory array of each semiconductor die into independent Bank groups; and planning on-chip data paths according to the distribution of the Bank groups, so that the on-chip data paths only cover the memory cells of the data channels of their respective semiconductor dies. Specifically, this application can plan the routing of on-chip data paths according to the physical distribution of the pre-divided Bank groups, thereby ensuring that the distribution of on-chip data paths corresponds one-to-one with the distribution of Bank groups, thus ensuring that the data localization access strategy can be implemented at the physical level.

[0082] To further illustrate the solution of this application, a specific example is provided below. Taking the split layout method of dual-channel GDDR6 memory chips as an example, based on the above architecture, this application embodiment also provides a corresponding layout method, the specific steps of which are as follows:

[0083] Specification splitting: Based on the total bandwidth, storage capacity and other specifications of the dual-channel GDDR6 memory chip, it is split into two functionally independent single-channel dies with the same specifications. Each single-channel die undertakes the function of one data channel.

[0084] Solder ball and signal module layout: Arrange the DQ package solder ball area on one edge of the single-channel die, and then place the DQ / WCK signal module adjacent to the solder ball area to ensure that the DQ package wiring length is minimized (not exceeding 1 / 4 of the die side length) and to avoid signal integrity degradation.

[0085] Control module layout: The CA / CK control module is placed between the two DQ / WCK signal modules on a single die to ensure the synchronization of control signals and driving capability.

[0086] Power line layout: The array power lines are arranged along the short side of the single-channel die to match the range of the single-channel memory array, so that the power line impedance is reduced by more than 30% compared with the traditional architecture, and the power supply anti-interference capability is improved.

[0087] Data path planning: Based on the Bank group distribution of a single-channel die, plan the on-chip data path so that the path only covers the storage unit of this channel, shortening the data transmission path.

[0088] Die splicing: Two completed single-channel dies are physically spliced ​​together so that the CA / CK control modules of the two dies are symmetrically distributed in the middle of the chip, forming a complete dual-channel GDDR6 memory chip.

[0089] The embodiments of this application significantly improve signal integrity, reduce DQ package wiring length by more than 50%, completely solve the SI degradation problem caused by excessive wiring in traditional architectures, and improve the accuracy of high-speed signal transmission by 40%. Power supply anti-interference capability is enhanced; array power line length is halved, impedance is reduced by more than 30%, effectively resisting power supply noise interference, and improving the working stability of the memory array by 50%. Performance is significantly optimized; on-chip data paths are shortened by 40%~60%, data read / write latency is reduced by more than 25%, and overall chip bandwidth performance is improved by 15%~20%. Design flexibility is high; the split die design allows for independent optimization and iteration of individual channels, reducing chip development difficulty and cost, and improving product iteration efficiency.

[0090] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0091] In one embodiment, a memory is also provided, the memory comprising the semiconductor structure described above.

[0092] In one embodiment, an electronic device is also provided, which includes the memory described above.

[0093] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0094] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0095] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0096] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0097] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0098] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, This includes multiple semiconductor dies arranged in a spliced ​​configuration; each semiconductor die is provided with: Multiple storage arrays arranged along the first direction; The solder ball area is located in the gap between adjacent memory arrays and on the edge of the memory array closest to the gap; The data port is located adjacent to the solder ball area and serves only the data channel of the corresponding semiconductor die; The control module is located between the two data ports of the semiconductor die. as well as The array power lines are arranged along a second direction, which is perpendicular to the first direction.

2. The semiconductor structure according to claim 1, characterized in that, The adjacent semiconductor dies have the same function and specifications.

3. The semiconductor structure according to claim 1, characterized in that, After adjacent semiconductor dies are spliced ​​together, the corresponding control modules are symmetrically distributed in the second direction and located in the middle of the semiconductor structure in the first direction.

4. The semiconductor structure according to claim 1, characterized in that, The semiconductor die is a single-channel die; each single-channel die independently carries the function of one data channel.

5. The semiconductor structure according to claim 4, characterized in that, The number of single-channel dies is determined based on the total bandwidth and storage capacity of the single-die packaged semiconductor chip.

6. The semiconductor structure according to claim 5, characterized in that, The number of single-channel dies is two.

7. The semiconductor structure according to claim 4, characterized in that, The second direction includes the short side direction of the single-channel die.

8. The semiconductor structure according to claim 4, characterized in that, The length of the package wiring between the data port and the solder ball area shall not exceed 1 / 4 of the side length of the single-channel die.

9. The semiconductor structure according to claim 1, characterized in that, The solder ball region located on one side edge of one adjacent memory array near the gap is the first solder ball region, and the solder ball region located on one side edge of another adjacent memory array near the gap is the second solder ball region. The first solder ball region and the second solder ball region are arranged alternately in the second direction; or... The first solder ball region and the second solder ball region are arranged opposite to each other in the second direction.

10. The semiconductor structure according to claim 1, characterized in that, Each of the semiconductor dies is also provided with an on-chip data path; The on-chip data path is used to connect the data port of a single data channel to the storage array.

11. The semiconductor structure according to claim 10, characterized in that, The memory array of each semiconductor die is divided into independent Bank groups, and the distribution of the on-chip data paths corresponds one-to-one with the distribution of the Bank groups.

12. A method for forming a semiconductor structure, used to form the semiconductor structure according to any one of claims 1 to 11, characterized in that, include: Multiple semiconductor dies are acquired, and each semiconductor die is provided with multiple memory arrays arranged along a first direction; On each of the semiconductor dies, solder ball regions are disposed in the gaps between adjacent memory arrays and located on the edge of the memory arrays closest to the gaps; The data port is arranged close to the solder ball area, and the data port serves only the data channel of the semiconductor die to which it belongs; The control module is positioned between the two data ports of the semiconductor die; the array power lines are arranged along a second direction, which is perpendicular to the first direction. as well as Multiple semiconductor dies are spliced ​​together to form the semiconductor structure.

13. The method according to claim 12, characterized in that, Splicing together multiple semiconductor dies includes: Adjacent semiconductor dies are physically joined together so that the corresponding control modules are symmetrically distributed in the second direction and located in the middle of the semiconductor structure in the first direction.

14. The method according to claim 12, characterized in that, The method further includes: The memory array for each of the semiconductor dies is divided into independent Bank groups; The on-chip data path is planned according to the distribution of the Bank group so that the on-chip data path only covers the memory cells of the data channel of the semiconductor die to which it belongs.

15. A memory, characterized in that, The memory includes the semiconductor structure described in any one of claims 1 to 11.

16. An electronic device, characterized in that, The electronic device includes the memory as described in claim 15.

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