strain-insensitive Zener diode

Abstract

This disclosure relates to a Zener diode that is insensitive to external stress, and a method for manufacturing such a Zener diode. Compressive stress is induced in the junction of the Zener diode in the direction of current flow using a lattice mismatch. The lattice mismatch can be generated by carbon doping.

Description

Technical Field

[0001] This disclosure relates to a Zener diode and a method for manufacturing a Zener diode. Background Technology

[0002] A Zener diode is a diode designed to operate without being damaged in the event of reverse breakdown. Zener diodes are designed to have a well-defined breakdown voltage, such as 3.3 V, 5.0 V, or 5.3 V.

[0003] Precision analog circuit systems typically require accurate voltage reference circuits. Zener diodes are often a critical component in such circuits, and any change in the breakdown voltage of the Zener diode in the voltage reference can be problematic.

[0004] Silicon devices are typically packaged to allow for device handling and provide suitable electrical connections (e.g., surface mount packages for printed circuit boards). Silicon has a relatively low coefficient of thermal expansion (CTE): approximately 2.6 microstrain / K at 300 K. Packages typically include materials with higher CTEs. For example, die-attach adhesives can have a CTE of 1–5 microstrain / K, PCB substrates (e.g., made of FR4 or another suitable material) can have a CTE of ~4–17 microstrain / K, while plastics can have a CTE of 13–20 microstrain / K or greater.

[0005] Due to temperature changes, this mismatch in the CTE leads to strain within the junction of the Zener diode. The junction's breakdown voltage is sensitive to strain. As a result, the Zener diode's breakdown voltage may suffer unwanted fluctuations due to temperature changes or strain induced in any other way.

[0006] Various processes can induce strain in Zener diodes: including packaging and solder reflow. Aging can alleviate some of these stresses (e.g., via creep). This can lead to undesirable variations in breakdown voltage.

[0007] A stress-insensitive Zener diode is needed. Summary of the Invention

[0008] According to a first aspect, a Zener diode is provided, comprising:

[0009] The first region includes the first dopant;

[0010] The second region, having a second dopant, is in contact with the first region, and the first and second regions define the junction of the Zener diode at the interface between the first and second regions;

[0011] in:

[0012] i) The first and second dopants are different types of dopants that provide charge carriers; and

[0013] ii) The junction includes compressive stress in the direction of current flow through the junction, the compressive stress being caused by lattice mismatch between: a) the first region and the second region; or b) the first region and another region of the Zener diode.

[0014] Both the first and second regions may include semiconductors. The semiconductors may be silicon, such as crystalline silicon.

[0015] Lattice mismatch can occur between the crystal layers of a Zener diode.

[0016] The lattice mismatch can be located between the first and second regions. The second region may include 0.5 mol% to 2 mol% carbon doping. The first region may have a lattice constant equal to that of intrinsic silicon.

[0017] The compressive stress can be between 100 MPa and 250 MPa.

[0018] The compressive stress can be between 150 MPa and 200 MPa.

[0019] The first zone can have 10 17 cm -3 Up to 10 19 cm -3 The dopant concentration of the first dopant within the range. The second region can have a dopant concentration of 10. 18 cm -3 Up to 10 21 cm -3 The dopant concentration of the second dopant within the range.

[0020] The lattice mismatch can be located between the first region and another region of the diode. The first region may include a lattice constant equal to that of intrinsic silicon, and the other region may include silicon-germanium.

[0021] The first dopant can be n-type, and the second dopant can be p-type.

[0022] According to a second aspect, a voltage regulator is provided, the voltage regulator including a Zener diode according to a first aspect, including any optional features of the Zener diode.

[0023] According to a third aspect, a method for manufacturing a Zener diode is provided, comprising:

[0024] The first region of crystalline silicon is implanted using the first dopant;

[0025] Etching a portion of the first region,

[0026] Doped crystalline silicon is deposited onto the etched portion to define the second region and the junction between the first and second regions;

[0027] Wherein: the doped crystalline silicon in the second region includes a second dopant; the first and second dopants are different types of dopants that provide charge carriers; and the junction includes compressive stress in the direction of current flow through the junction caused by lattice mismatch between the first and second regions.

[0028] The second region may include carbon doping between 0.5 mol% and 2 mol%.

[0029] The compressive stress can be between 100 MPa and 250 MPa.

[0030] The compressive stress can be between 150 MPa and 200 MPa.

[0031] The first zone can have 10 17 cm -3 Up to 10 19 cm -3 The dopant concentration of the first dopant within the range, and / or wherein the second region has a dopant concentration of 10 18 cm -3 Up to 10 21 cm -3 The dopant concentration of the second dopant within the range.

[0032] The first dopant can be n-type, and the second dopant can be p-type.

[0033] The features of the first and second aspects can be applied to the third aspect, including its optional features.

[0034] According to the fourth aspect, a method for manufacturing a Zener diode is provided, comprising:

[0035] The region with the first lattice constant that forms the Zener diode;

[0036] A first region is formed in the Zener diode, the first region being in contact with a region of the Zener diode having a first lattice constant, wherein the first region has a second lattice constant different from the first lattice constant, and the first region includes a first dopant;

[0037] A second region that forms a Zener diode in contact with the first region, wherein the second region has a second dopant;

[0038] The first dopant and the second dopant are different types of dopant that provide charge carriers, and the lattice mismatch between the first lattice constants is chosen to generate compressive stress in the junction region between the first region and the second region in the direction of current flow.

[0039] The region of a Zener diode having a first lattice constant may include or be formed of silicon or germanium.

[0040] The Zener diode of the first aspect may include any feature of the third aspect as well as any feature of the first or second aspect.

[0041] These and other aspects of the invention will be apparent from the embodiments described below, and will be illustrated with reference to these embodiments. Attached Figure Description

[0042] The embodiments will now be described by way of example only, with reference to the accompanying drawings, in which:

[0043] Figure 1 This is a schematic diagram of an example Zener diode;

[0044] Figure 2 This is a schematic diagram of a bending test setup used to check the strain sensitivity of a Zener diode breakdown voltage, showing: a) applying tensile stress at the junction in the direction of current flow, and b) applying compressive stress at the junction in the direction of current flow.

[0045] Figure 3 It is a graph showing the change in breakdown voltage during a bending test, where tensile stress is applied at the junction in the direction of current flow;

[0046] Figure 4 It is a graph showing the change in breakdown voltage during a bending test, where compressive stress is applied at the junction in the direction of current flow;

[0047] Figure 5 This is a graph showing a simulation of the shift in Zener breakdown voltage relative to the stress at the junction in the direction of current flow, including from... Figure 2 The test results obtained from the experiment are shown below;

[0048] Figure 6 An example method for manufacturing Zener diodes is shown;

[0049] Figure 7 This is another example of a Zener diode; and

[0050] Figure 8 An alternative method for achieving strain-insensitive Zener diodes is shown.

[0051] It should be noted that the drawings are illustrative and not to scale. For clarity and convenience in the drawings, the relative dimensions and proportions of the parts have been shown in enlarged or reduced form. The same reference numerals are used generally to refer to corresponding or similar features in modified and different embodiments. Detailed Implementation

[0052] Figure 1 An example Zener diode 100 is shown. The Zener diode 100 includes a first region 102 (in this example, an N-doped semiconductor region or N-well) and a second region 103 (in this example, a P-doped semiconductor region or P-well) in contact. The interface between the first region 102 and the second region 103 defines a junction 104. The Zener diode 100 further includes a substrate 101 (in this example, N-doped), a contact region 106 (in this example, N-doped), and a dielectric layer 105. The N-well and P-well comprise crystalline silicon.

[0053] In this example, dielectric layer 105 comprises silicon nitride, but other suitable dielectric layers (e.g., silicon oxide) can also be used. Electrical contact can be established with the N-doped contact region 106 and the P-well 103 (e.g., by depositing an additional patterned metal layer). A voltage can be applied to one side of junction 104 via substrate 101 and first region 102 using the electrical contact established at contact region 106. A voltage can be applied to the other side of junction 104 using the electrical contact at second region 102. In use, the Zener diode is typically reverse-biased and operates at a lower negative voltage across the P-well (second region 103 in this example) relative to the N-well (first region 102 in this example). Current will flow when the voltage difference across junction 104 exceeds the breakdown voltage. When the voltage difference across the junction is below the breakdown voltage, no current will flow (or very little current will flow).

[0054] In use, the current flowing through the Zener diode 100 is perpendicular to the plane of junction 104 (in the vertical direction, relative to the plane of junction 104). Figure 1 (or orientation).

[0055] The second region 103 has intrinsic biaxial in-plane tensile stress. This in-plane tensile stress generates compressive stress in the direction of current flow (perpendicular to the plane of the second region 103). This compressive stress is selected to reduce the sensitivity of the breakdown voltage of the junction 104 to stresses that may be applied to the packaged Zener diode 100 during use. (Refer to...) Figure 5To illustrate more clearly, the relationship between breakdown voltage and stress is not linear, and there exists a range of stress values ​​within which the junction breakdown voltage is relatively less sensitive to stress changes. By carefully designing the Zener diode, intrinsic stress can be provided at junction 104, which alleviates the stress sensitivity of the breakdown voltage. A more stable Zener diode can achieve a more stable voltage reference, or a simpler design for a voltage reference that meets specific performance criteria.

[0056] A suitable way to induce an appropriate amount of stress at junction 104 is to grow a second region 103 that exhibits a lattice mismatch with the underlying first region 102. In some examples, the second region 103 (in this example, the P-well) can be doped to adjust its lattice constant, and the lattice constant of the first region 102 (in this example, the N-well) can be a lattice constant corresponding to that of normally doped silicon (e.g., the same as the intrinsic lattice constant, or within 0.05% of the intrinsic lattice constant). In other examples, the first region 102 can have an adjusted lattice constant, and the second region 103 can have a lattice constant corresponding to that of normally doped silicon (e.g., within 0.05% of the lattice constant of normally doped silicon).

[0057] For example, the first region 102 may comprise crystalline silicon doped with phosphorus and having a lattice constant equal to that of intrinsic silicon. The second region 103 may be epitaxially grown crystalline silicon with a dopant (which may be referred to as a stress-controlled dopant) that affects the lattice constant of the second region 103, thereby creating a lattice mismatch between the second region 103 and the first region 102, resulting in stress at the junction 104. The stress-controlled dopant preferably does not provide charge carriers or affect the electronic properties of the material it is positively doped with.

[0058] A suitable stress-controlling dopant is carbon, which has a smaller atomic radius than silicon and thus lowers the lattice constant of silicon. 1 mol% carbon doping results in a biaxial in-plane stress (i.e., tensile) of approximately +600 MPa, and 3 mol% carbon doping results in a biaxial in-plane stress of approximately +2 GPa. The resulting stresses perpendicular to the plane due to Poisson contraction are approximately -200 MPa and -600 MPa, respectively. The relationship between doping concentration and resulting stress is approximately linear, so approximate values ​​of stress can be obtained by interpolation between these values, and suitable processes for achieving specific desired stresses can be experimentally implemented. References will follow below. Figure 5To elaborate further, a suitable value for the compressive stress in the junction could be 200 MPa (or a value close to that). A suitable range for the carbon concentration could be between 0.5 mol% and 2 mol%. A suitable stress range at junction 104 in the direction of current flow could be between -225 MPa and -125 MPa, or more specifically between -200 MPa and -150 MPa.

[0059] although Figure 1 An example is shown where the P-well is the second region, but this is not necessary, and the doping types can be reversed, such that each region described as N-doped is replaced with P-doped, and each region described as P-doped is replaced with N-doped. The amount of carbon dopant and / or the associated stress state in the second region can be compared with the reference. Figure 1 The dopant types shown are the same as those described.

[0060] Figure 2 A test setup for studying the sensitivity of a Zener diode 100 to strain is schematically shown. In this setup, the Zener diode 100 is bonded to a beam 120. For simplicity, the Zener diode 100 is shown as consisting only of a second region 103 and a first region 102, with a junction formed between the second region 103 and the first region 102. The beam 120 is simply supported and loaded with pure bending moments via four spaced-apart support points 125, 126.

[0061] exist Figure 2 In step a), an upward force is applied to each outer support point 125, and an equal downward force is applied to each inner support point 126. This results in compression of the upper surface of the beam 120, and consequently in-plane compressive stress on the Zener diode 100 and tensile stress at the junction between the first region 102 and the second region 103 in the direction of current flow.

[0062] exist Figure 2 In b), a downward force is applied to each outer support point 125, and an equal upward force is applied to each inner support point 126. This results in tension on the upper surface of the beam 120, and consequently in-plane tensile stress on the Zener diode 100 and compressive stress at the junction in the direction of current flow.

[0063] Figure 3 This illustrates the tensile stress at a junction in the direction of current flow, as shown in... Figure 2The breakdown voltage value 201 is shown in a) during the bending test relative to time. After the bending moment is removed, the breakdown voltage value 202 returns to the baseline level. In this experiment, the maximum bending stress at the top layer of the beam is -212 MPa. Assuming the material is elastic (i.e., linear), the stress in the joint will follow a linear relationship with the stress at the beam surface. The stress in the joint in the direction of current flow is also shown. Based on the equation Stress at the beam surface Related, among which This is a proportionality constant associated with the Zener diode. Experiments show that the breakdown voltage of the Zener diode decreases in response to tensile stress in the direction of current flow at the junction.

[0064] Figure 4 This illustrates the compressive stress at a junction in the direction of current flow, as shown in... Figure 2 The breakdown voltage value 211 is shown in b) during the bending test relative to time. After the bending moment was removed, the breakdown voltage value 212 returned to the baseline level. In this experiment, the maximum bending stress at the top layer of the beam was +300 MPa. The maximum bending stress resulted in a breakdown voltage change of +3.7 mV.

[0065] It can be executed repeatedly, such as Figure 3 and Figure 4 The experiment shown can be compared with computer simulations based on fundamental semiconductor physics. The value is determined as the value that produces the best fit in this comparison.

[0066] Figure 5 The simulated breakdown voltage of a Zener diode is shown as a function of the stress at the junction in the direction of current flow. Each data point obtained from experiment 220 is labeled. Data points 220 are from reference... Figure 2 , Figure 3 and Figure 4 The bending experiment described was obtained, and is based on The value 0.12 is used for plotting. All other data points 221 were obtained through simulation. A polynomial fit 222 for data points 220 and 221 is shown. Figure 5 The data indicates that there exists a stress range between -200 MPa and -150 MPa (at the junction, in the direction of current flow), within which the breakdown voltage is relatively less sensitive to stress.

[0067] This finding is consistent with semiconductor physics. The following equation describes the carrier tunneling probability. :

[0068]

[0069] in It is the effective mass of the charge carriers; It is the band gap energy of a semiconductor; It is the electric field across the junction; It is the elementary charge; It is the reduced Planck constant. Strain (which is proportional to stress in a linear material) modifies the band gap through lattice deformation. Tensile strain decreases the band gap, while compressive strain increases it. The tunneling probability depends on... Therefore, small changes in the bandgap can have a significant impact on the tunneling probability and thus the breakdown voltage. Strain also affects the effective mass of charge carriers (electrons and holes) due to modifications in the conduction and valence band structures. Tensile strain typically reduces the effective mass, thus enhancing tunneling. Compressive strain increases the effective mass, thus reducing tunneling. Therefore, there is a possibility of a crossover point under compressive stress, where these effects balance out, and at this crossover value of compressive stress, the Zener diode is insensitive to stress, such as... Figure 5 The polynomial fitting in 222 is described.

[0070] Figure 6 Another example method is shown, by which a Zener diode can be produced, in which stress induced by lattice mismatch is generated. Four stages in the process are depicted. The method begins with a p-doped crystalline silicon layer 110. A first n-doped region 102 for forming an N-well is defined by shallow reimplantation and deep implantation. Example implantation doses and energies for shallow reimplantation and deep implantation are: phosphorus, 500 keV, 10 15 / cm 2 ; and phosphorus, 2000 keV, 10 13 / cm 2 A lighter N-doped region 101 is defined to provide an electrical link from the N-well region 102 to the device cathode. The doped regions 101 and 102 can be defined in a normal manner using a photolithographically patterned soft mask (including a resist) and / or a hard mask (defined in a material such as silicon oxide or silicon nitride).

[0071] A dielectric layer 105 (e.g., silicon nitride or silicon oxide) is deposited and patterned (e.g., using photolithography and etching) to mark the boundary between the heavily doped P-type and N-type regions. A heavily doped N-type region 106 is defined to provide a region for ohmic contact with a metal cathode. An etched region is formed by etching, the etched region being at least partially masked by the dielectric layer. A second doped crystalline silicon region 103 is regrown (e.g., by vapor phase epitaxy) in the etched region. The doped crystalline silicon region 103 may include silicon doped with up to 10 18 cm -3 With 10 20 cm-3 The concentrations of boron are between 0.5 mol% and 2 mol%. The lattice mismatch between the second region 103 and the first region 102 produces in-plane tensile stress in the second region 103, which in turn applies compressive stress in the direction of current flow at the junction 104 between the first region 102 and the second region 103.

[0072] Figure 7 Another stage in an example method for manufacturing a Zener diode is shown, in which electrical connections (e.g., metal traces including gold, copper, aluminum, etc.) are formed to a heavily doped n-type region 106 and a second region 103. These electrical connections can connect the Zener diode to other components of an integrated circuit.

[0073] Figure 8 An alternative method for achieving strain-insensitive Zener diodes is shown, wherein lattice mismatch is used to induce compressive stress in the junction in the direction of current flow. Zener diode 100 has a reference... Figure 1 The Zener diode described has similar characteristics, and the description of that example applies to this example, except that there is no lattice mismatch between the first region 102 and the second region 103, and the second region is not doped with a stress-controlled dopant. The Zener diode 100 includes a crystalline SiGe layer 109 having a lattice mismatch with the first region 102. Therefore, the first region 102 is subjected to in-plane tensile stress, which will cause the junction 104 to be subjected to compressive stress in the direction of current flow.

[0074] Germanium has a higher atomic radius than silicon. It can be expected that Ge's effect on the lattice constant will be about 5 times lower in magnitude than that of C, and in the opposite direction. About 5% Ge is likely to produce a lattice mismatch similar to that of 1% C (in the opposite direction).

[0075] The advantage of the methods and apparatus disclosed herein is that they can produce Zener diodes with more stable or consistent breakdown voltages. More specifically, they can produce Zener diodes with breakdown voltages that are relatively insensitive to stress. Stress may be induced by manufacturing and packaging, or it may be experienced during use. In the case of manufacturing-induced stress, the inherently lower sensitivity to these stresses can result in a lower statistically significant variation in the breakdown voltage of the device. In the case of “in-use” stress, Zener diodes with lower stress sensitivity are less likely to experience changes in their breakdown voltage during use. Such Zener diodes can be very useful in voltage regulation and precision voltage regulation scenarios.

[0076] By reading this disclosure, those skilled in the art will understand other variations and modifications. Such variations and modifications may involve equivalent features that are already known in the field of automatic speech recognition systems and can be used as substitutes for or supplements to the features already described herein.

[0077] Although the appended claims relate to specific combinations of features, it should be understood that the scope of the disclosure of this invention also includes any novel feature or any novel combination of features or any generalized form thereof explicitly or implicitly disclosed herein, whether or not it relates to the same invention as currently claimed in any of the claims, and whether or not it alleviates any or all of the same technical problems as those alleviated by this invention.

[0078] Features described in the context of a single embodiment may also be provided in combination in a single embodiment. Conversely, for the sake of brevity, various features described in the context of a single embodiment may also be provided individually or in any suitable sub-combination. The applicant hereby reminds that new claims may be formulated based on such features and / or combinations of such features during the examination of this application or any other application derived therefrom.

[0079] For the sake of completeness, it is also stipulated that the term "comprising" does not exclude other elements or steps, the term "a / an" does not exclude multiple, a single processor or other unit can perform the functions of several components recited in the claims, and the reference numerals in the claims should not be interpreted as limiting the scope of the claims.

Claims

1. A Zener diode (100), characterized in that, include: The first region (102) includes a first dopant; The second region (103), having a second dopant, is in contact with the first region (102), and the first region (102) and the second region (103) define a junction (104) of the Zener diode (100) at the interface between the first region (102) and the second region (103). in: i) The first dopant and the second dopant are different types of dopants that provide charge carriers; and ii) The junction (104) includes compressive stress in the direction of current flow through the junction (104), the compressive stress being caused by lattice mismatch between: a) the first region (102) and the second region (103); or b) the first region (102) and another region of the Zener diode (100).

2. The Zener diode (100) according to claim 1, characterized in that, The lattice mismatch is located between the first region (102) and the second region (103), and the second region (103) includes 0.5 mol% to 2 mol% carbon doping, and the first region (102) has a lattice constant equal to that of intrinsic silicon.

3. The Zener diode (100) according to claim 1 or 2, characterized in that, The compressive stress is between 100 MPa and 250 MPa.

4. The Zener diode (100) according to any one of the preceding claims, characterized in that, The first region (102) has 10 17 cm -3 Up to 10 19 cm -3 The dopant concentration of the first dopant within the range, and / or wherein the second region (103) has a dopant concentration of 10 18 cm -3 Up to 10 21 cm -3 The dopant concentration of the second dopant within the range.

5. The Zener diode (100) according to any one of the preceding claims, characterized in that, The lattice mismatch is located between the first region (102) and another region (109) of the diode (100), wherein the first region (102) comprises a lattice constant equal to that of intrinsic silicon, and the other region (109) comprises silicon germanium.

6. The Zener diode (100) according to any one of the preceding claims, characterized in that: i) The first dopant is n-type and the second dopant is p-type; or ii) The first dopant is p-type and the second dopant is n-type.

7. A voltage regulator, characterized in that, Includes the Zener diode (100) according to any of the preceding claims.

8. A method for manufacturing a Zener diode (100), characterized in that, include: The first region (102) of the crystalline silicon is implanted with the first dopant; Etch a portion of the first region (102), Doped crystalline silicon is deposited into the etched portion to define a second region (103) and a junction (104) between the first region (102) and the second region (103). Wherein: the doped crystalline silicon in the second region (103) includes a second dopant; the first dopant and the second dopant are different types of dopant that provide charge carriers; and the junction (104) includes compressive stress in the direction of current flow through the junction caused by lattice mismatch between the first region (102) and the second region (103).

9. The method according to claim 8, characterized in that, The second region (103) includes carbon doping between 0.5 mol% and 2 mol%.

10. The method according to claim 8 or 9, characterized in that, The compressive stress is between 100 MPa and 250 MPa.

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