Semiconductor devices and methods for manufacturing semiconductor devices

Abstract

This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device, which provides a carrier lifetime reduction region in the semiconductor device while suppressing the increase in the number of manufacturing steps. The semiconductor device includes a bipolar semiconductor element, which has: a semiconductor substrate on which a drift layer (1) of a first conductivity type is formed; a plurality of trenches (8) formed on a first main surface of the semiconductor substrate; electrodes (11a, 12a) embedded in the trenches (8) via insulating films (11b, 12b); a mesa region, which is the region between the trenches (8) in the semiconductor substrate; and a source layer (13) of the first conductivity type or a contact layer (14) of the second conductivity type formed on the surface portion of the first main surface side of the mesa region. Dislocations (201) with a total length longer than the width of the mesa region are formed in the mesa region at a position on the second main surface side than the source layer (13) or the contact layer (14).

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] For example, Patent Document 1 discloses a technique that improves the switching characteristics of IGBTs and diodes in semiconductor devices by partially setting a region with high defect density and reduced carrier lifetime in the drift region using charged particles.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2019-129250

[0004] As with the technology in Patent Document 1, the method of forming a region with high defect density and reduced carrier lifetime using charged particles leads to an increase in the manufacturing cost of semiconductor devices due to the increase in the number of manufacturing steps. Summary of the Invention

[0005] This disclosure is made to solve the problems mentioned above, and its purpose is to provide a region with reduced carrier lifetime in a semiconductor device while suppressing the increase in the number of manufacturing steps.

[0006] The semiconductor device disclosed herein includes a bipolar semiconductor element comprising: a semiconductor substrate having a first main surface and a second main surface, and having a drift layer of a first conductivity type formed thereon; a plurality of trenches formed on the first main surface of the semiconductor substrate; electrodes embedded in the trenches via an insulating film; a mesa region being the region between the trenches of the semiconductor substrate; and a source layer of the first conductivity type or a contact layer of the second conductivity type formed on the surface portion of the mesa region on the first main surface side, wherein a dislocation in the mesa region, at a position on the second main surface side of the mesa region, has a total length longer than the width of the mesa region.

[0007] According to this disclosure, it is possible to provide a carrier lifetime reduction region in a semiconductor device while suppressing the increase in the number of manufacturing steps. Attached Figure Description

[0008] Figure 1 This is a diagram used to illustrate the outline of the technology involved in this disclosure.

[0009] Figure 2 This is a diagram representing a three-dimensional image of the second dislocation.

[0010] Figure 3 It is a graph showing the relationship between the thickness of the gate trench insulating film and the depth of the second dislocation.

[0011] Figure 4 This is a top view of the chip in a strip-type semiconductor device.

[0012] Figure 5 This is a top view of the chip in an island-shaped semiconductor device.

[0013] Figure 6 This is a top view of the IGBT area.

[0014] Figure 7 This is a cross-sectional view of the IGBT region.

[0015] Figure 8 This is a cross-sectional view of the IGBT region.

[0016] Figure 9 This is a top view of the diode region.

[0017] Figure 10 This is a cross-sectional view of the diode region.

[0018] Figure 11 This is a cross-sectional view of the diode region.

[0019] Figure 12 It is a cross-sectional view (GG section) of the boundary between the IGBT region and the diode region.

[0020] Figure 13 This is a sectional view of the terminal area.

[0021] Figure 14 This is a sectional view of the terminal area.

[0022] Figure 15 This is a diagram used to illustrate the manufacturing process of a semiconductor device.

[0023] Figure 16 This is a diagram used to illustrate the manufacturing process of a semiconductor device.

[0024] Figure 17 This is a diagram used to illustrate the manufacturing process of a semiconductor device.

[0025] Figure 18 This is a diagram used to illustrate the manufacturing process of a semiconductor device.

[0026] Figure 19 This is a diagram used to illustrate the manufacturing process of a semiconductor device.

[0027] Figure 20 This is a diagram used to illustrate the manufacturing process of a semiconductor device.

[0028] Figure 21 This is a diagram used to illustrate the manufacturing process of a semiconductor device.

[0029] Figure 22 This is a diagram used to illustrate the manufacturing process of a semiconductor device.

[0030] Figure 23 This is a diagram used to illustrate the manufacturing process of a semiconductor device.

[0031] Figure 24 This is a diagram used to illustrate the manufacturing process of a semiconductor device.

[0032] Figure 25 This is a diagram used to illustrate the manufacturing process of a semiconductor device.

[0033] Figure 26 This is a diagram used to illustrate the manufacturing process of a semiconductor device.

[0034] Figure 27 This is a diagram illustrating a structural example of the semiconductor device involved in Embodiment 1.

[0035] Figure 28 This is a diagram illustrating a structural example of the semiconductor device involved in Embodiment 1.

[0036] Figure 29 This is a diagram illustrating a structural example of the semiconductor device involved in Embodiment 1.

[0037] Figure 30 This is a diagram illustrating a structural example of the semiconductor device involved in Embodiment 2.

[0038] Figure 31 This is a diagram illustrating a structural example of the semiconductor device involved in Embodiment 2.

[0039] Figure 32 This is a diagram illustrating a structural example of the semiconductor device involved in Embodiment 2.

[0040] Figure 33 This is a diagram illustrating a structural example of the semiconductor device involved in Embodiment 3.

[0041] Figure 34 This is a diagram illustrating a structural example of the semiconductor device involved in Embodiment 3.

[0042] Figure 35 This is a diagram illustrating a structural example of the semiconductor device involved in Embodiment 3.

[0043] Figure 36 This is a diagram illustrating a structural example of the semiconductor device involved in Embodiment 4.

[0044] Figure 37 This is a diagram illustrating a structural example of the semiconductor device involved in Embodiment 4.

[0045] Figure 38 This is a diagram illustrating a structural example of the semiconductor device involved in Embodiment 5.

[0046] Figure 39 This is a diagram illustrating a structural example of the semiconductor device involved in Embodiment 6.

[0047] Figure 40 This is a diagram illustrating a structural example of the semiconductor device involved in Embodiment 6.

[0048] Figure 41 This is a diagram illustrating a structural example of the semiconductor device involved in Embodiment 6.

[0049] Explanation of reference numerals in the attached figures

[0050] 1...n － 1. n-type drift layer; 2. n-type carrier accumulation layer; 3. n-type buffer layer; 4. interlayer insulating film; 5. barrier metal; 6. emitter electrode; 6a. terminal electrode; 7. collector electrode; 8. trench; 9. oxide film; 10. IGBT region; 11. active trench gate; 11a. gate trench electrode; 11b. gate trench insulating film; 12. dummy trench gate; 12a. dummy trench electrode; 12b. dummy trench insulating film; 13. n ＋ Type source electrode layer; 14...p ＋ 15...p-type contact layer; 16...p-type base layer; 16...p-type collector layer; 16a...p-type terminal collector layer; 20...diode region; 21...diode trench gate; 21a...diode trench electrode; 21b...diode trench insulating film; 24...p ＋ Type 25...p anode contact layer; Type 26...n anode layer ＋ 30... p-type cathode layer; 31... terminal region; 32... n-type terminal well layer ＋ 33...Semi-insulating film; 34...Terminal protection film; 35...Terminal dummy trench gate; 35a...Terminal dummy trench electrode; 35b...Terminal dummy trench insulating film; 36...Double trench gate; 36a...Upper gate trench electrode; 36b...Upper gate trench insulating film; 36c...Lower gate trench electrode; 36d...Lower gate trench insulating film; 36e...Intermediate insulating film; 40...Pad area; 41...Control pad; 41a...Current sensing pad; 41b...Kelvin emitter pad; 41c...Gate pad; 41d...Temperature sensing diode pad; 41e...Temperature sensing diode pad; 100, 101...Semiconductor device; 200...First dislocation; 201...Second dislocation. Detailed Implementation

[0051] [Foreword]

[0052] In the following description, n and p represent the conductivity type of the semiconductor. In this disclosure, the first conductivity type is described as n-type and the second conductivity type as p-type, but it is also possible to describe the first conductivity type as p-type and the second conductivity type as n-type. Additionally, n － This indicates that the impurity concentration is below n, where n is the concentration of impurities. ＋ This indicates that the impurity concentration is higher than n. Similarly, p － This indicates that the impurity concentration is below p, where p ＋ This indicates that the impurity concentration is higher than p.

[0053] In addition, the level of impurity concentration in each region is defined by the peak concentration. That is, a region with a high (or low) impurity concentration means a region with a high (or low) peak concentration of impurities.

[0054] In the following description, the semiconductor elements included in a semiconductor device are exemplified by IGBT (Insulated Gate Bipolar Transistor) or RC-IGBT (Reverse Conducting IGBT). However, the technology disclosed herein can be widely applied to bipolar devices and is not limited to IGBTs or RC-IGBTs; for example, it can also be applied to diodes.

[0055] Furthermore, in the following description, silicon is cited as a primary material (constituent element) for semiconductor devices. However, the primary material for semiconductor devices may also be, for example, silicon carbide, gallium nitride, gallium oxide, diamond, or similar materials.

[0056] In the following description, a first main surface and a second main surface are defined as the main surfaces of the semiconductor device. The first main surface is sometimes also referred to as the "surface". In the case of an IGBT, an emitter electrode is formed on the first main surface. In the case of an RC-IGBT, in addition to the emitter electrode, an anode electrode of a diode integrated into the RC-IGBT is formed on the first main surface. The second main surface is sometimes also referred to as the "back side". In the case of an IGBT, a collector electrode is formed on the second main surface. In the case of an RC-IGBT, in addition to the collector electrode, a cathode electrode of a diode integrated into the RC-IGBT is formed on the second main surface.

[0057] In addition, similar to the semiconductor device, a first main surface and a second main surface are also defined as the main surfaces of the semiconductor substrate constituting the semiconductor device. That is, the first main surface of the semiconductor substrate is the surface of the semiconductor substrate on the side of the first main surface of the semiconductor device, and the second main surface of the semiconductor substrate is the surface of the semiconductor substrate on the side of the second main surface of the semiconductor device.

[0058] [Basic principles of the technology involved in this disclosure]

[0059] Examples of bipolar devices used in power applications include IGBTs, diodes, and RC-IGBTs. In these devices, the removal of minority carriers during turn-off is often a key challenge.

[0060] Carrier lifetime is a physical property that facilitates carrier discharge. Carrier lifetime refers to the time it takes for free carriers to effectively dissipate; the shorter the carrier lifetime, the more effectively carrier discharge is promoted. In bipolar devices used in power applications, a high-resistivity drift layer is typically provided, and techniques are employed to reduce conduction losses by modulating the conductivity of the drift layer to allow electrons and holes to accumulate. However, discharging the accumulated electrons and holes takes time; for IGBTs, this leads to deterioration of turn-off losses, and for diodes, it leads to deterioration of recovery losses. To address these issues, techniques for controlling carrier lifetime are widely used.

[0061] A common method for controlling carrier lifetime is to form point defects as described in Patent Document 1. Point defects, in the case of silicon semiconductors, are crystal defects of atomic size, such as silicon atom holes, inter-lattice silicon, or complexes thereof. Point defects in semiconductors mostly have energy levels in the band gap and, by trapping free carriers, reduce carrier lifetime. Patent Document 1 discloses a technique for intentionally and partially forming point defects by irradiating charged particles, thereby reducing the carrier lifetime in a desired region of a semiconductor substrate.

[0062] However, methods to reduce carrier lifetime by irradiation with charged particles require not only the irradiation process itself, but also the process of forming a pattern for a masking material (mask) to create the non-irradiated area, thus increasing the number of manufacturing steps in the semiconductor device. Therefore, a method is desired that can reduce carrier lifetime at a desired location without increasing the number of manufacturing steps.

[0063] This disclosure proposes a novel bipolar device utilizing dislocations. Dislocations are linear crystal defects caused by disordered periodic structures of atoms, distinct from point defects formed by irradiation by charged particles. Dislocations sometimes unintentionally exist in semiconductor substrates, which are believed to negatively impact the electrical characteristics and reliability of semiconductor devices. Furthermore, to date, there is no technology for forming dislocations at arbitrary locations within a semiconductor substrate, and no device actively utilizing dislocations has been proposed.

[0064] However, dislocations may possess energy levels within the band gap, thus potentially trapping free carriers and reducing carrier lifetime. The inventors of the technology disclosed herein have discovered a technique that improves electrical characteristics by forming dislocations, which differ from known dislocations, at arbitrary locations without compromising reliability.

[0065] [Observation method for the second positional fault 201]

[0066] The method for observing dislocations in the technology disclosed herein will be described. Here, a known dislocation formed unintentionally is referred to as a "first dislocation", and a newly formed dislocation in the technology disclosed herein is referred to as a "second dislocation".

[0067] use Figure 1 as well as Figure 2 This illustrates a summary of the technologies involved in this disclosure. Figure 1 This is a cross-sectional view of a semiconductor device. Figure 2 This is a 3D image of the second dislocation. Figure 1 This shows n between the active trench gates 11 of the IGBT. － An example of a second dislocation 201 forming within drift layer 1. Figure 2 The second dislocation 201 between the two active trench gates 11 is shown in three dimensions. Figure 1 Details of each element shown will be explained later, so they are omitted here.

[0068] The second dislocation 201 has a structure that extends in a three-dimensional linear form. If P is defined as the position of the second dislocation 201 closest to the second principal surface of the semiconductor substrate, the distance from the first principal surface of the semiconductor substrate to P is defined as the depth T1 of the second dislocation 201. The total length L1 of the second dislocation 201 refers to the length of the three-dimensionally extended linear dislocation. The total length L1 of the second dislocation 201 is longer than the width of the mesa-shaped semiconductor layer sandwiched by the trench gate, i.e., the mesa width W1. Additionally, the total length L1 of the second dislocation 201 may also include a component of the propagation distance L2 of the second dislocation 201 relative to the extension direction of the trench gate.

[0069] Figure 1 The second dislocation 201 shown Figure 1 The paper extends in the depth direction and has Figure 2 The three-dimensional linear structure shown makes it impossible to grasp its overall shape when observed using a conventional transmission electron microscope (TEM). The inventors of the technology disclosed herein achieve observation of a previously unknown second dislocation 201 and control over its formation location by analyzing the dislocations extending in three dimensions in detail.

[0070] [Configuration method for the second bit error]

[0071] The formation mechanism of the second dislocation 201 is described. The second dislocation 201 is formed using the first dislocation 200. The first dislocation 200 is a known dislocation formed unintentionally, usually associated with n formed by contact with the first main surface of the semiconductor substrate. ＋ Type source layer 13 or p ＋ This is achieved through contact layer 14. As described above, "n" ＋ “p” ＋ The "high impurity concentration" region refers to an area formed through ion implantation with a high implantation dose. A high implantation dose refers to 10... 14 cm －2 ~10 16 cm －2 The magnitude.

[0072] In general, when doping impurities via ion implantation, the crystallinity of the semiconductor substrate becomes disordered within the region (range) traversed by the implanted atoms. That is, a high-density defect region forms in the area traversed by the implanted atoms. If a heat treatment is performed to activate the dopant, the defect region will recover or recrystallize. However, when the implantation dose is high enough, even with heat treatment, crystallinity cannot be completely restored, and dislocations and point defects will remain. The dislocation formed in this way is called dislocation 1 200, which can be easily observed using a conventional TEM.

[0073] The second dislocation 201 is formed by heat-treating the first dislocation 200, causing it to move to an arbitrary depth. The depth T1 at which the second dislocation 201 forms is related to the stress within the semiconductor substrate. Various models can be proposed for the formation mechanism of dislocations, but the common principle is energy mitigation. It is known that crystals under high stress are in a high-energy state, which often releases energy (becoming a low-energy state) by forming dislocations. That is, dislocations are easily formed in high-stress regions. Therefore, if the stress within the semiconductor substrate can be controlled, the location of the second dislocation 201 can be controlled.

[0074] One of the stress control parameters is the thickness of the gate trench insulating film 11b. Experiments show that if the gate trench insulating film 11b is thickened, the n of the mesa-shaped portion (hereinafter referred to as the "mesa region") will increase. － The stress in drift layer 1 increases. Although the stress can be quantitatively evaluated using convergent beam electron diffraction (CBED), its magnitude can also be roughly compared by comparing the contrast of TEM images.

[0075] exist Figure 3 It shows Figure 1 The relationship between the thickness of the gate trench insulating film 11b and the depth T1 of the second dislocation 201 is shown. Figure 3 The results are obtained from the analysis of an actual prototype semiconductor device. The depth T1 of the second dislocation 201 is normalized using the depth of the active trench gate 11, and the thickness of the gate trench insulating film 11b is normalized using the spacing of the active trench gate 11.

[0076] If the gate trench insulating film 11b is thickened, then n, which includes the mesa region － The stress in drift layer 1 increases. To alleviate this stress (or strain energy), the first dislocation 200 moves towards n, which contains the mesa region. － The drift layer 1 moves, forming the second dislocation 201.

[0077] This model, exemplified by the second dislocation 201, illustrates the formation of the second dislocation 201 through the movement of the first dislocation 200. However, the possibility of the second dislocation 201 originating from other sources can also be considered. However, since accurately understanding the source of the second dislocation 201 requires extremely complex analysis, and even if the source of the dislocation is incorrect, it will not affect the effectiveness of this technique, a detailed discussion is omitted.

[0078] Here, the differences in manufacturing processes between conventional methods for reducing lifetime by irradiation with charged particles (e.g., Patent Document 1) and the technology disclosed herein will be explained. As mentioned above, conventional methods for reducing lifetime require processes such as irradiating charged particles and creating patterns of masking material (mask) for non-irradiated areas, thus increasing the number of manufacturing steps in the semiconductor device. On the other hand, in the technology disclosed herein, design parameters such as the thickness of the insulating film (gate trench insulating film 11b) are adjusted. This allows for adjustment of the position of the second dislocation 201 (the position of the control stress). Although the formation of the second dislocation 201 requires heat treatment of the first dislocation 200, this heat treatment does not require additional steps for dislocation movement, and can be combined with steps for moving n ＋ Type source layer 13 or p ＋The heat treatment for activating the contact layer 14 is performed simultaneously. Therefore, in the technology disclosed herein, the lifespan of the desired location can be reduced without increasing the number of manufacturing steps.

[0079] Furthermore, in the technology disclosed herein, the stress control parameters are not limited to the thickness of the gate trench insulating film 11b. For example, the spacing, shape, depth of the trenches in the gate trench insulating film 11b, or the design parameters of the electrodes embedded in the trenches (gate trench electrodes 11a), can also be considered as control parameters for adjusting the position of the second dislocation 201 (the position for controlling stress). In addition, the thickness of the insulating film used as a stress control parameter is not limited to the gate trench insulating film 11b; the thicknesses of the dummy trench insulating film 12b, diode trench insulating film 21b, terminal dummy trench insulating film 35b, upper gate trench insulating film 36b, and lower gate trench insulating film 36d, described later, are also considered stress control parameters. If the above design parameters are adjusted according to the region where the second dislocation 201 is to be configured, the second dislocation 201 can be configured at any position, and the formation of the second dislocation 201 does not require a special process.

[0080] [Common effects of all implementation methods]

[0081] In the technology disclosed herein, the electrical characteristics of semiconductor devices are improved by locally reducing carrier lifetime through the utilization of dislocations. An application example in a power control semiconductor device (power semiconductor) is described here.

[0082] Reducing carrier lifetime generally promotes the replenishment of minority carriers. In bipolar devices used for power control, regions with high impurity concentrations are typically located on the first and second main surfaces, while a low-impurity region, known as the drift layer, is formed between the first and second main surfaces. Although the drift layer has high resistance due to its low impurity concentration, the conductance modulation effect unique to bipolar devices can reduce the resistance during conduction, thus reducing conduction losses. In the case of diodes, the power loss incurred during the transition from a conducting (on) state to a non-conducting (off) state by applying a voltage in the opposite direction is called recovery loss. In the case of IGBTs, the on and off states are switched at any time by the gate potential. The power loss incurred during the transition from the on state to the off state is called turn-off loss, and conversely, the power loss incurred during the transition from the off state to the on state is called turn-on loss. The total of recovery loss, turn-off loss, and turn-on loss is called switching loss. Although the conductance modulation effect is effective in reducing power loss during the on state, there is a problem of increased switching losses. Switching losses and conduction losses are a trade-off, and are adjusted based on the impurity concentration in the collector layer and the impurity concentration in the cathode region.

[0083] There exists a technique to improve the trade-off between switching losses and conduction losses by reducing carrier lifetime. Turn-off and recovery losses, which are the main components of switching losses, arise from the removal of minority carriers. That is, switching losses can be reduced by efficiently removing minority carriers. Reducing carrier lifetime is one method for efficiently removing minority carriers. Furthermore, by efficiently removing minority carriers, an increase in cutoff capacity can also be expected.

[0084] When carrier lifetime is reduced in any region of a semiconductor device, considering which electrical characteristics are important design considerations is crucial. On the other hand, introducing defects into the semiconductor device beyond dislocations raises concerns about increased leakage current during disconnection, changes in threshold voltage, and reduced gate reliability. Furthermore, in the case of bipolar devices, while reducing carrier lifetime can predict reduced switching losses and increased turn-off capability, conversely, it reduces conductance modulation effects and increases conduction losses. Designers need to understand these trade-offs and place dislocations in optimal locations.

[0085] The second dislocation 201 is characterized in that its total length L1 is longer than the width W1 of the table. The total length L1 of the second dislocation 201 refers to its propagation distance in three-dimensional space. Figure 2 The component also includes the depth direction of the paper surface. By configuring a second dislocation 201 with a total length L1, the region where the carrier lifetime is reduced can be expanded. The second dislocation 201 can be bent or convex towards the second main surface. By bending the second dislocation 201, the propagation distance of the second dislocation 201 is increased, thereby expanding the region where the carrier lifetime is reduced. In addition, when the second dislocation 201 is formed to control the stress near the active trench gate 11, such as Figure 1 as well as Figure 2 Thus, a second dislocation 201 is formed at the location in contact with the active trench gate 11. This reduces n － In the case of carrier lifetime in the direction of the second principal surface of the drift layer 1, a higher effect can be achieved by making the second dislocation 201 bulge towards the second principal surface.

[0086] [Common aspects across all implementation methods]

[0087] Here, we will explain the common aspects of all the embodiments described below.

[0088] Figure 4 This is a top view showing a semiconductor device that functions as an RC-IGBT. Additionally, Figure 5 This is a top view showing a semiconductor device with an RC-IGBT structure. Figure 4The semiconductor device 100 shown has IGBT region 10 and diode region 20 arranged in a strip, which can also be simply referred to as "strip type". Figure 5 The semiconductor device 101 shown has multiple diode regions 20 arranged in the longitudinal and transverse directions, and IGBT regions 10 are arranged around the diode regions 20, which can also be simply referred to as "island type".

[0089] (1) Strip-type integral planar structure

[0090] exist Figure 4 In this semiconductor device 100, an IGBT region 10 and a diode region 20 are included within the semiconductor device 100. The IGBT region 10 and the diode region 20 extend from one end of the semiconductor device 100 to the other end, and are alternately arranged in a strip shape in a direction orthogonal to the extending direction of the IGBT region 10 and the diode region 20. Figure 4 The diagram shows three IGBT regions 10 and two diode regions 20, with all diode regions 20 sandwiched between IGBT regions 10. However, the number of IGBT regions 10 and diode regions 20 is not limited to this; there can be more or fewer IGBT regions 10, and more or fewer diode regions 20. Alternatively, they can be interchanged. Figure 4 The structure can be formed by the positions of the IGBT region 10 and the diode region 20, or it can be a structure in which all the IGBT regions 10 are sandwiched between the diode regions 20. Alternatively, it can be a structure in which the IGBT regions 10 and the diode regions 20 are arranged one after another adjacent to each other.

[0091] like Figure 4As shown, a pad region 40 is disposed adjacent to the lower side of the IGBT region 10. The pad region 40 is the region where control pads 41 for controlling the semiconductor device 100 are disposed. The IGBT region 10 and the diode region 20 are collectively referred to as the cell region. In order to maintain the withstand voltage of the semiconductor device 100, a terminal region 30 is disposed around the region formed by the combined cell region and the pad region 40. A known withstand voltage maintenance structure can be appropriately selected to be disposed in the terminal region 30. The withstand voltage maintenance structure can be configured, for example, by providing an FLR (Field Limiting Ring) in the region formed by the combined cell region and the pad region 40 surrounded by a p-type terminal well layer of a p-type semiconductor on the surface side of the semiconductor device 100, i.e., the first main surface side, and a VLD (Variation of Lateral Doping) in the region formed by the combined cell region and the pad region 40 surrounded by a p-type terminal well layer with a concentration gradient. The number of annular p-type terminal well layers for the FLR and the concentration distribution for the VLD can be appropriately selected according to the withstand voltage design of the semiconductor device 100. Alternatively, a p-type terminal well layer can be set over approximately the entire area of ​​the pad region 40, or IGBT units and diode units can be set in the pad region 40.

[0092] The control pad 41 can be, for example, a current sensing pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, or a temperature sensing diode pad 41d or 41e. The current sensing pad 41a is a control pad used to detect the current flowing in the cell region of the semiconductor device 100, and is electrically connected to a portion of the IGBT cell or diode cell in the cell region when the current flows in the cell region of the semiconductor device 100, in a manner that the current flows in a fraction of the total current flowing in the cell region to a fraction of the total current flowing in the cell region.

[0093] Kelvin emitter pad 41b and gate pad 41c are control pads for applying gate drive voltages to control the on / off state of the semiconductor device 100. Kelvin emitter pad 41b is connected to the p-type base layer and n-type base layer of the IGBT cell. ＋ The emitter layer is electrically connected, and the gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b can also be connected to the p-type base layer via p... ＋ The temperature sensing diode pads 41d and 41e are control pads electrically connected to the anode and cathode of the temperature sensing diode disposed in the semiconductor device 100. The temperature of the semiconductor device 100 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) disposed in the cell area.

[0094] (2) Overall planar structure of the island

[0095] exist Figure 5 In this semiconductor device 101, an IGBT region 10 and a diode region 20 are included within the semiconductor device. Multiple diode regions 20 are arranged longitudinally and laterally within the semiconductor device, and each diode region 20 is surrounded by the IGBT region 10. That is, multiple diode regions 20 are arranged in an island-like configuration within the IGBT region 10. Figure 5 The diagram shows a matrix structure in which the diode regions 20 are arranged in four columns in the left-right direction and two rows in the top-bottom direction. However, the number and arrangement of the diode regions 20 are not limited to this. One or more diode regions 20 can be distributed within the IGBT region 10, with each diode region 20 surrounded by the IGBT region 10.

[0096] like Figure 5 As shown, a pad region 40 is disposed adjacent to the lower side of the IGBT region 10. The pad region 40 is a region where control pads 41 for controlling the semiconductor device 101 are disposed. The IGBT region 10 and the diode region 20 are collectively referred to as a cell region. For the withstand voltage maintenance of the semiconductor device 101, a termination region 30 is disposed around the region formed by the combined cell region and the pad region 40. A known withstand voltage maintenance structure can be appropriately selected to be disposed in the termination region 30. For example, the withstand voltage maintenance structure can be configured by providing an FLR (Flat Zone Reduction) in the region formed by the combined cell region and the pad region 40 surrounded by a p-type terminal well layer of a p-type semiconductor on the surface side of the semiconductor device 101, i.e., the first main surface side, and a VLD (Volume Depletion Layer) in the region formed by the combined cell region and the pad region 40 surrounded by a p-type terminal well layer with a concentration gradient. The number of annular p-type terminal well layers for the FLR and the concentration distribution for the VLD can be appropriately selected according to the withstand voltage design of the semiconductor device 101. Alternatively, a p-type terminal well layer can be set over approximately the entire area of ​​the pad region 40, or IGBT units and diode units can be set in the pad region 40.

[0097] The control pad 41 can be, for example, a current sensing pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, or a temperature sensing diode pad 41d or 41e. The current sensing pad 41a is a control pad used to detect the current flowing in the cell region of the semiconductor device 101, and is electrically connected to a portion of the IGBT cell or diode cell in the cell region when the current flows in the cell region of the semiconductor device 101, in a manner that the current flows in a fraction of the total current flowing in the cell region to a fraction of the total current flowing in the cell region.

[0098] Kelvin emitter pad 41b and gate pad 41c are control pads for applying gate drive voltages to control the on / off state of semiconductor device 101. Kelvin emitter pad 41b is connected to the p-type base layer and n-type base layer of the IGBT cell. ＋ The source layer is electrically connected, and the gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer can also be connected via p... ＋ The contact layer is electrically connected. Temperature sensing diode pads 41d and 41e are control pads electrically connected to the anode and cathode of the temperature sensing diode disposed in the semiconductor device 101. The temperature of the semiconductor device 101 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) disposed in the cell area.

[0099] (3) Example of the construction of IGBT region 10

[0100] Figure 6 This is a partially enlarged top view showing the structure of the IGBT region of the semiconductor device, which is an RC-IGBT. Additionally, Figure 7 as well as Figure 8 This is a cross-sectional view showing the structure of the IGBT region of the semiconductor device, which is an RC-IGBT. Figure 6 Enlarged display Figure 4 The semiconductor device 100 shown or Figure 5 The region enclosed by dashed line 82 in the semiconductor device 101 shown. Figure 7 yes Figure 6 The cross-sectional view of semiconductor device 100 or semiconductor device 101 shown at the dashed line AA. Figure 8 yes Figure 6 A cross-sectional view of the semiconductor device 100 or semiconductor device 101 shown at the dashed line BB.

[0101] like Figure 6 As shown, in the IGBT region 10, an active trench gate 11 and a dummy trench gate 12 are arranged in a strip shape. In the semiconductor device 100, the active trench gate 11 and the dummy trench gate 12 extend along the long side direction of the IGBT region 10, and the long side direction of the IGBT region 10 becomes the long side direction of the active trench gate 11 and the dummy trench gate 12. On the other hand, in the semiconductor device 101, although there is no particular distinction between the long side direction and the short side direction for the IGBT region 10, the left-right direction of the paper can be set as the long side direction of the active trench gate 11 and the dummy trench gate 12, and the up-down direction of the paper can also be set as the long side direction of the active trench gate 11 and the dummy trench gate 12.

[0102] The active trench gate 11 is constructed by providing a gate trench electrode 11a via a gate trench insulating film 11b within a trench formed in a semiconductor substrate. The dummy trench gate 12 is constructed by providing a dummy trench electrode 12a via a dummy trench insulating film 12b within a trench formed in a semiconductor substrate. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 41c. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode disposed on the first main surface of the semiconductor device 100 or semiconductor device 101.

[0103] n ＋ The source layer 13 is disposed on both sides of the active trench gate 11 in the width direction in a manner that contacts the gate trench insulating film 11b. ＋ The source layer 13 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, with an n-type impurity concentration of 1.0E+17 / cm³. 3 ~1.0E+20 / cm 3 n ＋ The source layer 13 extends along the direction of the active trench gate 11, and is adjacent to the p-type source layer 13. ＋ Type contact layers 14 are alternately arranged. ＋ The contact layer 14 is also disposed between two adjacent dummy trench gates 12. ＋ The p-type contact layer 14 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, with a p-type impurity concentration of 1.0E+15 / cm³. 3 ~1.0E+20 / cm 3 .

[0104] In addition, Figure 6 In the process, although only p are arranged between each other in the dummy trench gate 12 ＋ Type contact layer 14, but n can also be configured between each other in the form of dummy trench gates 12. ＋ Type source pole layer 13.

[0105] like Figure 6 As shown, in the IGBT region 10 of semiconductor device 100 or semiconductor device 101, three dummy trench gates 12 are arranged next to three active trench gates 11, and three active trench gates 11 are arranged next to three dummy trench gates 12. The IGBT region 10 is thus configured with alternating groups of active trench gates 11 and groups of dummy trench gates 12. Although in Figure 6In this configuration, the number of active trench gates 11 in a group of active trench gates 11 can be set to 3, but any number greater than 1 is acceptable. Additionally, the number of dummy trench gates 12 in a group of dummy trench gates 12 can be 1 or more, or the number of dummy trench gates 12 can be 0. That is, all trenches in the IGBT region 10 can also be designated as active trench gates 11.

[0106] Figure 7 It is semiconductor device 100 or semiconductor device 101 Figure 6 The cross-sectional view at the dashed line AA is a cross-sectional view of the IGBT region 10. Semiconductor device 100 or semiconductor device 101 has an n-shaped structure made of a semiconductor substrate. － Type 1 drift layer. － The n-type drift layer 1 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, with a concentration of 1.0E+12 / cm³. 3 ~1.0E+15 / cm 3 Semiconductor substrates in Figure 7 The middle is from n ＋ Type source layer 13 and p ＋ The range from the p-type contact layer 14 to the p-type collector layer 16. Figure 7 In the middle, n ＋ Type source layer 13 and p ＋ The upper end of the p-type contact layer 14 on the paper surface is referred to as the first main surface of the semiconductor substrate, and the lower end of the p-type collector layer 16 on the paper surface is referred to as the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the surface-side main surface of the semiconductor device 100 or semiconductor device 101, and the second main surface of the semiconductor substrate is the back-side main surface of the semiconductor device 100 or semiconductor device 101. In the IGBT region 10, which is a unit region, the semiconductor device 100 or semiconductor device 101 has an n-type contact layer between the first main surface and the second main surface opposite to the first main surface. － Type 1 drift layer.

[0107] Depending on the manufacturing method, various impurities may be introduced into the semiconductor substrate. Examples include oxygen, carbon, boron, and nitrogen. These are known to affect electrical properties and the diffusion of impurity elements.

[0108] like Figure 7 As shown, in IGBT region 10, at n － The first principal surface of the drift layer 1 is provided with a concentration ratio of n-type impurities to n － The n-type carrier accumulation layer 2 has a high n-type drift layer 1. The n-type carrier accumulation layer 2 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, with an n-type impurity concentration of 1.0E+13 / cm³. 3 ~1.0E+17 / cm 3Furthermore, semiconductor device 100 or semiconductor device 101 may also be a device without an n-type carrier accumulation layer 2, but instead... Figure 7 The region of the n-type carrier accumulation layer 2 shown also has n － The structure of the n-type drift layer 1. By setting the n-type carrier accumulation layer 2, the current loss when the IGBT region 10 flows can be reduced. Alternatively, the n-type carrier accumulation layer 2 and n... － The drift layers 1 are collectively referred to as drift layers.

[0109] n-type carrier accumulation layer 2, through the formation of n － The semiconductor substrate of the n-type drift layer 1 is subjected to ion implantation of n-type impurities, and then annealing is used to oxidize the implanted n-type impurities into n-type drift layers. － The drift layer 1 is formed by diffusion within the semiconductor substrate.

[0110] A p-type base layer 15 is formed on the first main surface side of the n-type carrier accumulation layer 2. The p-type base layer 15 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+12 / cm³. 3 ~1.0E+19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11. An n-type base layer 15 is provided on its first main surface side in such a way that it contacts the gate trench insulating film 11b of the active trench gate 11. ＋ Type source layer 13, with p in the remaining region ＋ Type contact layer 14. ＋ Type source layer 13 and p ＋ The p-type contact layer 14 constitutes the first main surface of the semiconductor substrate. Wherein, p ＋ The p-type contact layer 14 is a region where the concentration of p-type impurities is higher than that of the p-type base layer 15, in which p-type impurities need to be distinguished. ＋ In the case of p-type contact layer 14 and p-type base layer 15, these two can be referred to separately, or p-type base layer 15 can be referred to as p-type base layer 15. ＋ The p-type contact layer 14 and the p-type base layer 15 are collectively referred to as the p-type base layer.

[0111] Additionally, semiconductor device 100 or semiconductor device 101 in n － The second principal surface of the drift layer 1 is provided with a concentration ratio of n-type impurities to n － The n-type buffer layer 3 is a high-density n-type drift layer 1. The n-type buffer layer 3 is provided to suppress punch-through of the depletion layer extending from the p-type base layer 15 towards the second main surface when the semiconductor device 100 or semiconductor device 101 is in an off state. The n-type buffer layer 3 can be implanted with, for example, phosphorus (P) or protons (H). ＋ It can be formed by the injection of phosphorus (P) and protons (H). ＋This is formed by these two factors. The concentration of n-type impurities in n-type buffer layer 3 is 1.0E+12 / cm³. 3 ~1.0E+18 / cm 3 .

[0112] Furthermore, semiconductor device 100 or semiconductor device 101 may also be a device without an n-type buffer layer 3 but instead... Figure 7 The area of ​​the n-type buffer layer 3 shown also has n － The structure of type n drift layer 1. Alternatively, type n buffer layer 3 and type n... － The drift layers 1 are collectively referred to as drift layers.

[0113] Semiconductor device 100 or semiconductor device 101 has a p-type collector layer 16 disposed on the second main surface side of the n-type buffer layer 3. That is, on the n-type buffer layer 3... － A p-type collector layer 16 is disposed between the p-type drift layer 1 and the second main surface. The p-type collector layer 16 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+16 / cm³. 3 ~1.0E+20 / cm 3 The p-type collector layer 16 constitutes the second main surface of the semiconductor substrate. The p-type collector layer 16 is disposed not only in the IGBT region 10 but also in the termination region 30, and the portion of the p-type collector layer 16 disposed in the termination region 30 constitutes the p-type termination collector layer 16a. Alternatively, the p-type collector layer 16 may also be configured such that a portion extends from the IGBT region 10 towards the diode region 20.

[0114] like Figure 7 As shown, semiconductor device 100 or semiconductor device 101 has a p-type base layer 15 extending from the first main surface of the semiconductor substrate and reaching the n-type base layer 15. － The trench of the drift layer 1. An active trench gate 11 is formed by providing a gate trench electrode 11a within the trench via a gate trench insulating film 11b. The gate trench electrode 11a is connected to the n-type drift layer via the gate trench insulating film 11b. － The drift layer 1 is opposite to the type. Furthermore, a dummy trench gate 12 is formed by providing a dummy trench electrode 12a within the trench via a dummy trench insulating film 12b. The dummy trench electrode 12a is connected to n via the dummy trench insulating film 12b. － The p-type drift layer 1 is opposite to the active trench gate 11. The gate trench insulating film 11b of the active trench gate 11 is connected to the p-type base layer 15 and the n-type base layer 15. ＋ The p-type source layer 13 is in contact. When a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 that is in contact with the gate trench insulating film 11b of the active trench gate 11.

[0115] Although not illustrated, two gate trench electrodes 11a with different potentials can be provided on the active trench gate 11 to control the gate capacitance. That is, the gate trench electrodes 11a can be divided into an upper layer and a lower layer, and an insulating film can be used to electrically isolate the upper layer from the lower layer. Such a gate structure is called a two-layer gate structure.

[0116] like Figure 7 As shown, an interlayer insulating film 4 is disposed on the gate trench electrode 11a of the active trench gate 11. A barrier metal 5 is formed on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not disposed, and on the interlayer insulating film 4. The barrier metal 5 can be, for example, a conductor containing titanium (Ti), such as titanium nitride, or TiSi, an alloy of titanium and silicon (Si). Figure 7 As shown, the barrier metal 5 and n ＋ Type source layer 13, p ＋ The contact layer 14 and the dummy trench electrode 12a make ohmic contact with n. ＋ Type source layer 13, p ＋ The contact layer 14 and the dummy trench electrode 12a are electrically connected. An emitter electrode 6 is disposed on top of the barrier metal 5. The emitter electrode 6 can be formed, for example, of an aluminum alloy such as an aluminum-silicon alloy (Al-Si alloy) or a material composed primarily of copper, or it can be an electrode composed of a multilayer metal film on which a coating has been formed by chemical plating or electroplating. The coating formed by chemical plating or electroplating can be, for example, a nickel (Ni) coating. Furthermore, in cases where there are small regions, such as between adjacent interlayer insulating films 4, and where good embedment cannot be obtained in the emitter electrode 6, tungsten, which has better embedment than the emitter electrode 6, can be disposed in the small regions, and the emitter electrode 6 can be disposed on top of the tungsten. Alternatively, the barrier metal 5 may not be disposed, but instead... ＋ Type source layer 13, p ＋ An emitter electrode 6 is disposed on the contact layer 14 and the dummy trench electrode 12a. Alternatively, an emitter electrode 6 may be disposed only on n. ＋ A barrier metal 5 is disposed on top of an n-type semiconductor layer such as the source layer 13. The barrier metal 5 and the emitter electrode 6 can also be collectively referred to as the emitter electrode. Furthermore, in... Figure 7 The diagram shows a dummy trench electrode 12a of the dummy trench gate 12 without the interlayer insulating film 4, but the interlayer insulating film 4 can also be formed on the dummy trench electrode 12a of the dummy trench gate 12. When the interlayer insulating film 4 is formed on the dummy trench electrode 12a of the dummy trench gate 12, it is sufficient to electrically connect the emitter electrode 6 to the dummy trench electrode 12a at other cross-sections.

[0117] A collector electrode 7 is disposed on the second main surface side of the p-type collector layer 16. The collector electrode 7 may also be made of aluminum alloy or a material with copper as the main element, or a combination of these and a coating, similar to the emitter electrode 6. Alternatively, the collector electrode 7 may have a different structure than the emitter electrode 6. The collector electrode 7 makes an ohmic contact with the p-type collector layer 16 and is electrically connected to it.

[0118] Figure 8 It is semiconductor device 100 or semiconductor device 101 Figure 6 The cross-sectional view at the dashed line BB is the cross-sectional view of IGBT region 10. Figure 7 The difference in the sectional view shown at the dashed line AA is that, Figure 8 The cross-section at the dashed line BB does not show the n-type structure disposed on the first main surface side of the semiconductor substrate in a manner that contacts the active trench gate 11. ＋ Type source layer 13. That is, as shown in Figure 13. Figure 7 As shown, n ＋ The source layer 13 is selectively disposed on the first main surface side of the p-type base layer. Furthermore, the p-type base layer referred to here means a p-type base layer 15 and a p-type base layer 16. ＋ The p-type base layer is collectively referred to as the p-type contact layer 14.

[0119] like Figure 7 as well as Figure 8 As shown, the second dislocation 201 is disposed on the semiconductor substrate at a ratio of n ＋ Type source layer 13 and p ＋ The contact layer 14 is positioned near the second main surface. Although in n ＋ Type source layer 13 and p ＋ The contact layer 14 contains a known first dislocation 200, but it is not shown in the diagram. The second dislocation 201 is a crystal defect that extends three-dimensionally into the depth direction of the paper, and its total length L1 is longer than the mesa width W1. The total length L1 refers to the curve length when viewed in three dimensions, not the curve length when viewed from above. Although it is not easy to measure the curve length when viewed in three dimensions, in... Figure 7 as well as Figure 8 In the case of a curve extending into the depth of the paper, it can generally be assumed that "the straight-line distance when viewed from above" < "the curve length when viewed from above" < "the curve length when viewed in three dimensions". Here, the case where "the curve length when viewed from above" = "the curve length when viewed in three dimensions" refers to the state where the dislocation does not extend into the depth of the paper. Conversely, the case where "the straight-line distance when viewed from above" = "the curve length when viewed from above" refers to the state where the dislocation does not extend into the depth of the paper and is a straight line.

[0120] The second dislocation 201 is selectively located at a different position in three-dimensional space than the first dislocation 200. The first dislocation 200 is an n-type dislocation typically formed through high-dose ion implantation. ＋ Type source layer 13, p ＋ The first dislocation 200 is formed by the formation of the contact layer 14, a known type of dislocation. At least a portion of the semiconductor substrate is amorphized by high-dose ion implantation, followed by a heat treatment for activation, thereby forming the first dislocation 200 at high density. This is achieved by appropriately controlling the n-type dislocations, including the mesa region. － The stress in the drift layer 1 causes the first dislocation 200 to shift, selectively forming the second dislocation 201. For example... Figure 7 as well as Figure 8 As shown, the position that forms the second dislocation 201 is n ＋ Type source layer 13 and p ＋ Type contact layer 14 is located on the side of the second main surface.

[0121] (4) Construction of diode region 20

[0122] Figure 9 This is a partially enlarged top view showing the structure of the diode region of the semiconductor device, which is an RC-IGBT. Additionally, Figure 10 as well as Figure 11 This is a cross-sectional view showing the structure of the diode region of the semiconductor device, which is an RC-IGBT. Figure 9 Enlarged display Figure 4 The semiconductor device 100 shown or Figure 5 The region enclosed by dashed line 83 in the semiconductor device 101 shown. Figure 10 yes Figure 9 A cross-sectional view of the semiconductor device 100 or semiconductor device 101 shown at the dashed line CC. Figure 11 yes Figure 9 A cross-sectional view of the semiconductor device 100 or semiconductor device 101 shown at the dashed line DD.

[0123] The diode trench gate 21 extends along the first main surface of the semiconductor device 100 or semiconductor device 101 from one end of the diode region 20, which is a unit region, toward the opposite end. The diode trench gate 21 is formed by providing a diode trench electrode 21a via a diode trench insulating film 21b within a trench formed in the semiconductor substrate of the diode region 20. The diode trench electrode 21a is connected to the diode trench region 20 via the diode trench insulating film 21b. － Type-shifting layer 1 is opposite. A p-type drift layer is disposed between the gates 21 of two adjacent diode trenches. ＋ Type 24 anode contact layer and type p anode layer 25. ＋The anode contact layer 24 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, with a p-type impurity concentration of 1.0E+15 / cm³. 3 ~1.0E+20 / cm 3 The p-type anode layer 25 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, with a p-type impurity concentration of 1.0E+12 / cm³. 3 ~1.0E+19 / cm 3 p ＋ The p-type anode contact layer 24 and the p-type anode layer 25 are alternately disposed along the long side of the diode trench gate 21.

[0124] Figure 10 It is semiconductor device 100 or semiconductor device 101 Figure 8 The cross-sectional view at the dashed line CC is a cross-sectional view of diode region 20. Semiconductor device 100 or semiconductor device 101 also has, in diode region 20, an n-shaped structure made of a semiconductor substrate, similar to IGBT region 10. － Type drift layer 1. Diode region 20 n － Type drift layer 1 and IGBT region 10 n － The drift layer 1 is integrally formed continuously on the same semiconductor substrate. Figure 10 In the process, the semiconductor substrate is made from p ＋ Type 24 to n anode contact layer ＋ The range up to the cathode layer 26. Figure 10 In the middle, p ＋ The upper end of the anode contact layer 24 on the paper is called the first main surface of the semiconductor substrate, and n ＋ The lower end of the cathode layer 26 is called the second main surface of the semiconductor substrate. The first main surface of the diode region 20 and the first main surface of the IGBT region 10 are the same surface, and the second main surface of the diode region 20 and the second main surface of the IGBT region 10 are the same surface.

[0125] like Figure 10 As shown, in diode region 20, similarly to IGBT region 10, in n － An n-type carrier accumulation layer 2 is disposed on the first main surface side of the n-type drift layer 1. －An n-type buffer layer 3 is provided on the second main surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 and n-type buffer layer 3 provided in the diode region 20 have the same structure as those provided in the IGBT region 10. Furthermore, it is not necessary to provide the n-type carrier accumulation layer 2 in both the IGBT region 10 and the diode region 20. Even if the n-type carrier accumulation layer 2 is provided in the IGBT region 10, it can be configured such that the n-type carrier accumulation layer 2 is not provided in the diode region 20. Additionally, similar to the IGBT region 10, the n-type buffer layer 3 can also be... － The n-type drift layer 1, the n-type carrier accumulation layer 2, and the n-type buffer layer 3 are collectively referred to as the drift layer.

[0126] A p-type anode layer 25 is disposed on the first main surface side of the n-type carrier storage layer 2. The p-type anode layer 25 is disposed on the n-type carrier storage layer 2. － Between the p-type drift layer 1 and the first main surface. The p-type anode layer 25 can also have the concentration of p-type impurities set to the same concentration as the p-type base layer 15 of the IGBT region 10, thus simultaneously forming the p-type anode layer 25 and the p-type base layer 15. Alternatively, the p-type anode layer 25 can be configured to have a lower concentration of p-type impurities than the p-type base layer 15 of the IGBT region 10, thereby reducing the amount of holes injected into the diode region 20 during diode operation. By reducing the amount of holes injected during diode operation, the recovery loss during diode operation can be reduced.

[0127] A p-type anode layer 25 is provided on the first main surface side. ＋ Type 24 anode contact layer. ＋ The concentration of p-type impurities in the anode contact layer 24 can be the same as that in the IGBT region 10. ＋ The concentration of p-type impurities in the contact layer 14 can be the same or different. ＋ The anode contact layer 24 forms the first main surface of the semiconductor substrate. Furthermore, p... ＋ The p-type anode contact layer 24 is a region where the concentration of p-type impurities is higher than that of the p-type anode layer 25, in areas where it is necessary to distinguish between p-type and p-type impurities. ＋ In the case of p-type anode contact layer 24 and p-type anode layer 25, these two can be referred to separately, or p can be referred to as p-type anode contact layer 25. ＋ The p-type anode contact layer 24 and the p-type anode layer 25 are collectively referred to as the p-type anode layer.

[0128] In diode region 20, an n-type buffer layer 3 is provided on the second main surface side. ＋ Type 26 cathode layer. ＋ Type 26 cathode layer is disposed in n － Between drift layer 1 and the second principal surface. ＋The cathode layer 26 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, with an n-type impurity concentration of 1.0E+16 / cm³. 3 ~1.0E+21 / cm 3 .like Figure 10 As shown, n ＋ The cathode layer 26 is disposed in part or all of the diode region 20. ＋ The cathode layer 26 forms the second main surface of the semiconductor substrate. Furthermore, although not shown, it can also be formed as described above. ＋ The region of the cathode layer 26 is further selectively implanted with p-type impurities, thereby forming n-type impurities. ＋ A portion of the region of the p-type cathode layer 26 is used as a p-type semiconductor to form the p-type cathode layer.

[0129] like Figure 10 As shown, a p-type anode layer 25 is formed in the diode region 20 of semiconductor device 100 or semiconductor device 101, extending from the first main surface of the semiconductor substrate and reaching the n-type anode. － The trench of the type drift layer 1. A diode trench electrode 21a is formed by providing a diode trench electrode 21a within the trench of the diode region 20 via a diode trench insulating film 21b, thereby constituting the diode trench gate 21. The diode trench electrode 21a is connected to the n-type drift layer 1 via the diode trench insulating film 21b. － Type drift layer 1 is opposite.

[0130] like Figure 10 As shown, in the diode trench electrode 21a and p ＋ A barrier metal 5 is disposed on the anode contact layer 24. The barrier metal 5 is connected to the diode trench electrode 21a and p. ＋ The anode contact layer has a 24-ohm contact, while the diode trench electrode and p... ＋ The anode contact layer 24 is electrically connected. The barrier metal 5 can have the same structure as the barrier metal 5 in the IGBT region 10. An emitter electrode 6 is disposed on the barrier metal 5. The emitter electrode 6 disposed in the diode region 20 is continuously formed with the emitter electrode 6 disposed in the IGBT region 10. Alternatively, similar to the case of the IGBT region 10, the barrier metal 5 may not be disposed, and the diode trench electrode 21a and p may be made... ＋ The anode contact layer 24 makes an ohmic contact with the emitter electrode 6. Furthermore, although in Figure 10The diagram shows a configuration where the interlayer insulating film 4 is not provided on the diode trench electrode 21a of the diode trench gate 21, but the interlayer insulating film 4 can also be formed on the diode trench electrode 21a of the diode trench gate 21. When the interlayer insulating film 4 is formed on the diode trench electrode 21a of the diode trench gate 21, it is sufficient to electrically connect the emitter electrode 6 to the diode trench electrode 21a at other cross-sections.

[0131] Alternatively, a two-layer gate structure can be applied to the diode trench electrode 21a in the diode trench gate 21, which divides the gate trench electrode into an upper layer and a lower layer.

[0132] In n ＋ A collector electrode 7 is disposed on the second main surface side of the cathode layer 26. Similar to the emitter electrode 6, the collector electrode 7 of the diode region 20 is continuously formed with the collector electrode 7 disposed in the IGBT region 10. The collector electrode 7 and n ＋ The cathode layer has a 26-ohm contact, while the n-type cathode layer has a 26-ohm contact. ＋ Type 26 cathode layer is electrically connected.

[0133] Figure 11 It is semiconductor device 100 or semiconductor device 101 Figure 9 The cross-sectional view at the dashed line DD is a cross-sectional view of diode region 20. (And...) Figure 10 The difference in the cross-sectional view shown at the dashed line CC is that no p-type anode layer 25 is placed between the p-type anode layer 25 and the barrier metal 5. ＋ The p-type anode contact layer 24 and the p-type anode layer 25 constitute the first main surface of the semiconductor substrate. That is, Figure 10 p shown ＋ The p-type anode contact layer 24 is selectively disposed on the first main surface side of the p-type anode layer 25.

[0134] like Figure 10 As shown, in diode region 20, the second dislocation 201 is also disposed at a position relative to p. ＋ The position of the type anode contact layer 24 near the second main surface. Although in p ＋ The anode contact layer 24 contains a known first dislocation 200, but it is not shown in the diagram. The second dislocation 201 is a crystal defect that extends three-dimensionally into the depth direction of the paper, and its total length L1 is longer than the mesa width W1. The total length L1 refers to the curve length when viewed in three dimensions, not the curve length when viewed from above. Although it is not easy to measure the curve length when viewed in three dimensions, it is still possible to determine the curve length when viewed in three dimensions. Figure 10In the case of a curve extending in the depth direction of the paper, it can generally be assumed that "the straight-line distance when viewed from above" < "the curve length when viewed from above" < "the curve length when viewed in three dimensions". Here, the case where "the curve length when viewed from above" = "the curve length when viewed in three dimensions" refers to the state where the dislocation does not extend in the depth direction of the paper. Conversely, the case where "the straight-line distance when viewed from above" = "the curve length when viewed from above" refers to the state where the dislocation does not extend in the depth direction of the paper and is a straight line.

[0135] The second dislocation 201 is selectively located at a different position in three-dimensional space than the first dislocation 200. The first dislocation 200 is a p-type dislocation typically formed through high-dose ion implantation. ＋ The first dislocation 200 is formed by the formation of the anode contact layer 24, a known type of dislocation. At least a portion of the semiconductor substrate is amorphized by high-dose ion implantation, followed by a heat treatment for activation, thereby forming the first dislocation 200 at high density. This is achieved by appropriately controlling the n-type dislocations, including the mesa region. － The stress in the drift layer 1 causes the first dislocation 200 to shift, selectively forming the second dislocation 201. For example... Figure 10 As shown, the position that forms the second dislocation 201 is p ＋ The anode contact layer 24 is located on the side of the second main surface. Furthermore, due to its contact with... Figure 11 The region corresponding to the cross section did not form p ＋ The anode contact layer 24 was not formed, so the first dislocation 200 was not formed.

[0136] (5) Boundary region between IGBT region 10 and diode region 20

[0137] Figure 12 It is a cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of the semiconductor device that serves as an RC-IGBT. Figure 12 yes Figure 4 The semiconductor device 100 shown or Figure 5 A cross-sectional view of the semiconductor device 101 shown at the dashed line GG.

[0138] like Figure 12 As shown, the p-type collector layer 16 disposed on the second main surface side of the IGBT region 10 is configured to extend a distance U1 from the boundary between the IGBT region 10 and the diode region 20 toward the diode region 20. In this way, by configuring the p-type collector layer 16 to extend toward the diode region 20, the n-type collector layer of the diode region 20 can be increased. ＋The distance between the cathode layer 26 and the active trench gate 11 is such that even when a gate drive voltage is applied to the gate trench electrode 11a during the operation of the freewheeling diode, current can be suppressed from flowing from the channel formed adjacent to the active trench gate 11 of the IGBT region 10 to the n-th electrode. ＋ The cathode layer 26 flows. The distance U1 can be, for example, 100 μm. Furthermore, depending on the application of the semiconductor device 100 or semiconductor device 101 as an RC-IGBT, the distance U1 can also be zero or less than 100 μm.

[0139] like Figure 12 As shown, a first dislocation 200 can also be configured at the boundary between the IGBT region 10 and the diode region 20, which includes the region corresponding to the distance U1 (the region where the p-type collector layer 16 extends from the IGBT region 10). In this case, the recovery tolerance can be increased by capturing the minority carriers (holes) when the diode is turned off. Here, the boundary between the IGBT region 10 and the diode region 20 refers to the region where the minority carriers of the diode reach when it is turned off, and its width can be wider than the distance U1. More specifically, the IGBT region 10 and the diode region 20 refer to the region ±100 μm from the end of the p-type collector layer 16.

[0140] (6) Construction of terminal region 30

[0141] Figure 13 as well as Figure 14 This is a cross-sectional view showing the structure of the terminal region of the semiconductor device, which is an RC-IGBT. Figure 13 yes Figure 4 or Figure 5 The cross-sectional view at the dashed line EE is a cross-sectional view from IGBT region 10 to terminal region 30. Additionally, Figure 14 yes Figure 4 The cross-sectional view at the dashed line FF is a cross-sectional view from diode region 20 to terminal region 30.

[0142] like Figure 13 as well as Figure 14 As shown, the terminal region 30 of the semiconductor device 100 has n regions between the first main surface and the second main surface of the semiconductor substrate. － Type Drift Layer 1. The first and second main surfaces of the terminal region 30 are the same as the first and second main surfaces of the IGBT region 10 and the diode region 20, respectively. Additionally, the n-type of the terminal region 30... － Type-type drift layer 1 is an n-type drift layer that is connected to IGBT region 10 and diode region 20. － The drift layers 1 are formed integrally with identical structures and continuously.

[0143] In n －The first main surface of the drift layer 1, i.e., the first main surface of the semiconductor substrate and n － A p-type terminal well layer 31 is disposed between the p-type drift layers 1. The p-type terminal well layer 31 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+14 / cm³. 3 ~1.0E+19 / cm 3 The p-type terminal well layer 31 is configured to surround the unit region containing the IGBT region 10 and the diode region 20. The p-type terminal well layers 31 are arranged in multiple rings, and the number of p-type terminal well layers 31 is appropriately selected according to the voltage withstand design of the semiconductor device 100 or semiconductor device 101. Furthermore, n-type terminal well layers 31 are provided on the outermost edge of the p-type terminal well layer 31. ＋ Type 32,n channel barrier layer ＋ A p-type channel barrier layer 32 surrounds a p-type terminal trap layer 31.

[0144] In the terminal region 30, a terminal dummy trench gate 35 is provided in the p-type terminal well layer 31. The terminal dummy trench gate 35 is formed by providing a terminal dummy trench electrode 35a in a trench formed in the semiconductor substrate via a terminal dummy trench insulating film 35b.

[0145] In n － A p-type terminal collector layer 16a is provided between the p-type drift layer 1 and the second main surface of the semiconductor substrate. The p-type terminal collector layer 16a is integrally formed continuously with the p-type collector layer 16 provided in the cell region. Therefore, the p-type terminal collector layer 16a can also be included and referred to as the p-type collector layer 16. In addition, in cases such as Figure 4 In the structure of the semiconductor device 100 shown, where the diode region 20 and the terminal region 30 are adjacent, such as Figure 14 As shown, the p-type terminal collector layer 16a is configured to extend a distance U2 from the end of the diode region 20 towards the diode region 20. In this way, by configuring the p-type terminal collector layer 16a to extend into the diode region 20, the n-axis of the diode region 20 can be increased. ＋ The distance between the p-type cathode layer 26 and the p-type terminal well layer 31 can suppress the p-type terminal well layer 31 from operating as the anode of the diode. The distance U2 can be, for example, 100 μm.

[0146] A collector electrode 7 is disposed on the second main surface of the semiconductor substrate. The collector electrode 7 is integrally formed continuously from the cell region including the IGBT region 10 and the diode region 20 to the terminal region 30. On the other hand, an emitter electrode 6 and a terminal electrode 6a separate from the emitter electrode 6 are disposed on the first main surface of the semiconductor substrate in the terminal region 30.

[0147] The emitter electrode 6 and the terminal electrode 6a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 can be, for example, sinSiN (semi-insulating silicon nitride). The terminal electrode 6a is connected to the p-type terminal well layer 31 and the n-type terminal well layer 32. ＋ The channel barrier layer 32 is electrically connected via contact holes formed on the interlayer insulating film 4 disposed on the first main surface of the terminal region 30. Additionally, a terminal protective film 34 covering the emitter electrode 6, the terminal electrode 6a, and the semi-insulating film 33 is provided in the terminal region 30. The terminal protective film 34 may be formed of polyimide, for example. Alternatively, the semi-insulating film 33 may be omitted, and the terminal protective film 34 may be formed without the semi-insulating film 33.

[0148] exist Figure 13 as well as Figure 14 In this configuration, the p-type terminal well layer 31 is formed up to a region closer to the second main surface than the active trench gate 11, dummy trench gate 12, or terminal dummy trench gate 35. However, the p-type terminal well layer 31 can also be formed at a position farther from the second main surface than the active trench gate 11, dummy trench gate 12, or terminal dummy trench gate 35. In other words, it can also be a p-type terminal well layer 31 that is shallower than the active trench gate 11, dummy trench gate 12, or terminal dummy trench gate 35. However, if the p-type terminal well layer 31 is shallower than the terminal dummy trench gate 35, the electric field strength on the second main surface side of the terminal dummy trench gate 35 becomes stronger. Therefore, to suppress this situation, the terminal dummy trench gate 35 can be formed to be shallower than the active trench gate 11 or dummy trench gate 12.

[0149] The number of terminal dummy trench gates 35 need not be one; there can be more than one and less than ten. When multiple terminal dummy trench gates 35 exist, in order to progressively reduce the electric field strength during disconnection, the depth of the multiple terminal dummy trench gates 35 is progressively shallowed in the outward direction (from the cell region towards the terminal region). That is, the terminal dummy trench gates 35 further out can be made shallower. Preferably, the second dislocation 201 is not configured in the terminal dummy trench gate 35 or the terminal region 30.

[0150] [Common Manufacturing Method for Implementation]

[0151] Figures 15 to 26 This is a diagram illustrating the manufacturing method of a semiconductor device as an RC-IGBT. Figures 15 to 22 This diagram illustrates the processes involved in forming the surface side of semiconductor device 100 or semiconductor device 101. Figures 23 to 26 This is a diagram showing the process of forming the back side of semiconductor device 100 or semiconductor device 101.

[0152] First, such as Figure 15 The preparation shown constitutes n － The semiconductor substrate is a type-drift layer 1. For the semiconductor substrate, for example, an FZ wafer fabricated by the FZ (Floating Zone) method or an MCZ wafer fabricated by the MCZ (Magnetic Applied Czochralki) method can be used, and it can be an n-type wafer containing n-type impurities. The concentration of n-type impurities contained in the semiconductor substrate is appropriately selected according to the breakdown voltage of the semiconductor device being fabricated. For example, in a semiconductor device with a breakdown voltage of 1200V, the concentration of n-type impurities is adjusted so that the n-type impurities constituting the semiconductor substrate... － The resistivity of drift layer 1 is approximately 40~120 Ω·cm. According to the semiconductor substrate manufacturing method, although various impurities such as phosphorus, arsenic, nitrogen, boron, oxygen, and carbon are mixed in, adjusting the resistivity is sufficient to obtain the desired breakdown voltage. Furthermore, the resistivity can also be adjusted by utilizing recombination defects with various impurity elements, intercrystalline silicon, and atomic vacancies. For example... Figure 15 As shown, in the process of preparing a semiconductor substrate, the semiconductor substrate as a whole becomes n － A p-type or n-type drift layer 1 is formed by implanting p-type or n-type impurity ions from the first main surface side or the second main surface side of such a semiconductor substrate, and then allowing them to diffuse within the semiconductor substrate through heat treatment or the like, thereby forming a p-type or n-type semiconductor layer, and manufacturing a semiconductor device 100 or semiconductor device 101.

[0153] like Figure 15 As shown, n constitutes － The semiconductor substrate of the drift layer 1 includes regions that serve as IGBT regions 10 and diode regions 20. Additionally, although not shown, regions that serve as termination regions 30 are provided around the regions that serve as IGBT regions 10 and diode regions 20. Hereinafter, the manufacturing method of the structure of the IGBT regions 10 and diode regions 20 of the semiconductor device 100 or semiconductor device 101 will be mainly described, but the termination regions 30 of the semiconductor device 100 or semiconductor device 101 can be manufactured using known manufacturing methods. For example, when the termination region 30 forms an FLR with a p-type terminal well layer 31 as a withstand voltage holding structure, it can be formed by implanting p-type impurity ions before processing the IGBT regions 10 and diode regions 20 of the semiconductor device 100 or semiconductor device 101, or it can be formed by simultaneously implanting p-type impurity ions when implanting p-type impurity ions into the IGBT regions 10 or diode regions 20 of the semiconductor device 100 or semiconductor device 101.

[0154] Next, as Figure 16As shown, an n-type carrier accumulation layer 2 is formed by implanting n-type impurities such as phosphorus (P) from the first main surface of the semiconductor substrate. Additionally, a p-type base layer 15 and a p-type anode layer 25 are formed by implanting p-type impurities such as boron (B) from the first main surface of the semiconductor substrate. The n-type carrier accumulation layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed by implanting impurity ions into the semiconductor substrate and then diffusing the impurity ions through heat treatment. Since the n-type and p-type impurities are selectively formed on the first main surface of the semiconductor substrate after ion implantation following a masking process, the n-type and p-type impurities are formed selectively on the first main surface of the semiconductor substrate. The n-type carrier accumulation layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed in the IGBT region 10 and the diode region 20, and are connected to the p-type terminal well layer 31 in the terminal region 30. In addition, masking refers to the process of coating a photoresist onto a semiconductor substrate to form a mask on the semiconductor substrate so that an opening can be formed in a predetermined area of ​​the photoresist using photolithography techniques, and ion implantation or etching can be performed on the predetermined area of ​​the semiconductor substrate through the opening.

[0155] The p-type base layer 15 and the p-type anode layer 25 can also be formed by simultaneously implanting p-type impurities with ions. In this case, the p-type base layer 15 and the p-type anode layer 25 have the same depth and p-type impurity concentration, and thus form the same structure. Alternatively, by using a mask process to implant p-type impurities into the p-type base layer 15 and the p-type anode layer 25 separately, the depth and p-type impurity concentration of the p-type base layer 15 and the p-type anode layer 25 can be made different.

[0156] Alternatively, the p-type terminal well layer 31 formed in other cross-sections can also be formed by simultaneously implanting p-type impurities into the p-type anode layer 25. In this case, the p-type terminal well layer 31 and the p-type anode layer 25 have the same depth and p-type impurity concentration, and thus form identical structures. Alternatively, p-type impurities can be implanted simultaneously to form the p-type terminal well layer 31 and the p-type anode layer 25, while setting different p-type impurity concentrations for the two layers. In this case, it is sufficient to simply set one or both masks to a mesh mask and change the aperture ratio.

[0157] Alternatively, ion implantation can be performed on the p-type terminal well layer 31 and the p-type anode layer 25 separately by using masking, thereby making the depth and p-type impurity concentration of the p-type terminal well layer 31 and the p-type anode layer 25 different.

[0158] Ion implantation can also be performed simultaneously to form a p-type terminal well layer 31, a p-type base layer 15, and a p-type anode layer 25.

[0159] Next, as Figure 17As shown, n-type impurities are selectively implanted into the first main surface of the p-type base layer 15 of the IGBT region 10 using masking to form n-type impurities. ＋ The source layer 13 is an n-type impurity. The implanted n-type impurity can be, for example, arsenic (As) or phosphorus (P). Additionally, using a mask, p-type impurities are selectively implanted into the first main surface of the p-type base layer 15 in the IGBT region 10 to form a p-type base layer. ＋ The p-type contact layer 14 is formed by selectively implanting p-type impurities into the first main surface side of the p-type anode layer 25 of the diode region 20. ＋ Type 24 anode contact layer. The injected p-type impurities can be, for example, boron (B) or aluminum (Al).

[0160] Because n ＋ Type source layer 13 or p ＋ The contact layer 14 has a high impurity concentration, so the implantation dose is usually high during ion implantation. When ion implantation is performed with a high dose, the defect density in the region through which the implanted element passes is high, and depending on the conditions, crystallinity disappears, resulting in an amorphous layer. Implanted regions or amorphous layers with high defect density are usually improved by annealing aimed at activating the implanted impurities. However, it is not necessary to return to a region with low defect density as before implantation; defects can remain as long as they do not affect the electrical properties. In the remaining defect regions, silicon atom vacancies, interlattice silicon atoms, complexes of silicon atom vacancies and interlattice silicon, and dislocations due to mismatched crystal planes are commonly present. While tiny point defects such as atomic vacancies and interlattice atoms are difficult to observe, dislocations can be easily observed using commonly used methods (e.g., scanning tunneling microscope: STM), and are known as the first dislocation 200. Although the first dislocation 200 also exists... Figures 17 to 26 n ＋ Type source layer 13, p ＋ Type contact layer 14, p ＋ Any region in the anode contact layer 24, but not shown.

[0161] Next, as Figure 18 As shown, a p-type base layer 15 and a p-type anode layer 25 are formed that penetrate from the first main surface side of the semiconductor substrate and reach the n-type anode layer. － The trench 8 of the drift layer 1. In the IGBT region 10, n... ＋ The sidewalls of the trench 8 in the source electrode layer 13 constitute n ＋ A portion of the source layer 13. The trench 8 can be formed by depositing an oxide film such as SiO2 on a semiconductor substrate, then using a mask to create openings in the portion of the oxide film where the trench 8 is to be formed, and finally etching the semiconductor substrate using the oxide film with the openings as a mask. Although in Figure 18In this design, the spacing of the trenches 8 is made the same in both the IGBT region 10 and the diode region 20, but the spacing can also be different in the two regions. Furthermore, for stress design, regions with varying trench 8 spacing can be provided in both the IGBT region 10 and the diode region 20. The depth of the trenches 8 can also be arbitrarily designed. The trench 8 spacing can be appropriately varied using a mask pattern obtained through masking. Additionally, a micro-load effect where the trench depth varies according to the mask pattern can also be utilized.

[0162] Next, as Figure 19 As shown, a semiconductor substrate is heated in an oxygen-containing atmosphere to form an oxide film 9 on the inner wall of the trench 8 and on the first main surface of the semiconductor substrate. Among the oxide films 9 formed on the inner wall of the trench 8, the oxide film 9 formed in the trench 8 of the IGBT region 10 is the gate trench insulating film 11b of the active trench gate 11 and the dummy trench insulating film 12b of the dummy trench gate 12. Additionally, the oxide film 9 formed in the trench 8 of the diode region 20 is the diode trench insulating film 21b. Furthermore, the oxide film 9 formed in the trench 8 of the terminal region 30 is the terminal dummy trench insulating film 35b. The oxide film 9 formed on the first main surface of the semiconductor substrate is removed in a subsequent process.

[0163] Next, as Figure 20 As shown, polycrystalline silicon doped with n-type or p-type impurities is deposited in a trench 8 with an oxide film 9 formed on its inner wall using methods such as CVD (chemical vapor deposition) to form a gate trench electrode 11a, a dummy trench electrode 12a, a diode trench electrode 21a, and a terminal dummy trench electrode 35a. This forms an active trench gate 11, a dummy trench gate 12, a diode trench gate 21, and a terminal dummy trench gate 35.

[0164] In the process of forming the active trench gate 11, the dummy trench gate 12, the diode trench gate 21, and the terminal dummy trench gate 35 (hereinafter collectively referred to as "trench gates"), the n including the mesa region is controlled. － Stress within the drift layer 1. To increase stress, design parameters such as those described below are effective: deepening the trench gate, narrowing the trench spacing, forming a thick oxide film 9 that will become the gate trench insulating film 11b, the dummy trench insulating film 12b, the diode trench insulating film 21b, and the terminal dummy trench insulating film 35b, setting the trench gate as a two-layer gate structure, and thickening the oxide film 9 within the two-layer gate structure. － The oxide film in contact with type drift layer 1. Includes the mesa region n. －The stress within the drift layer 1 can be easily measured using TEM analysis, convergent beam electron line diffraction (CBED), etc. The designer controls the n region containing the mesa. － The stress within the drift layer 1 is used to place the second dislocation 201 at any location.

[0165] Next, as Figure 21 As shown, after forming an interlayer insulating film 4 on the gate trench electrode 11a of the active trench gate 11 in the IGBT region 10, the oxide film 9 formed on the first main surface of the semiconductor substrate is removed. The interlayer insulating film 4 can also be, for example, SiO2. Then, contact holes are formed on the interlayer insulating film 4 deposited using a mask process. The contact holes are formed on n ＋ Above the source electrode layer 13, p ＋ Above the contact layer 14, p ＋ Above the anode contact layer 24, above the dummy trench electrode 12a, and above the diode trench electrode 21a.

[0166] Alternatively, heat treatment can be applied after the interlayer insulating film 4 is formed. Besides ensuring the thermal stability of the interlayer insulating film 4, heat treatment can also be used to control the stress level. － The drift layer 1 is configured with the power of the second dislocation 201. It can generate n... － Driven by stress and thermal energy within the drift layer 1, the first dislocation 200, formed on the first principal surface side through high-dose injection, is positioned at arbitrary locations. An arbitrary location refers to a region different from the first dislocation 200, specifically, a region different from n. ＋ Type source layer 13, p ＋ Type contact layer 14, p ＋ The anode contact layer 24 is positioned near the second main surface. The effect of arranging the second dislocation 201 within the semiconductor device is as described above. Here, the second dislocation 201 formed by this method has a total length L1 longer than the mesa width W1, is curved, and has a shape that bulges towards the second main surface. By making the total length L1 of the second dislocation 201 longer than the mesa width W1, the carrier trapping effect can be improved. Furthermore, by setting the second dislocation 201 to a shape that bulges towards the second main surface, the trapping effect is improved. － The effect of carriers in drift layer 1.

[0167] To date, no one knows how to control n － This technique utilizes stress within the drift layer 1 to position the second dislocation 201 at arbitrary locations. Compared to conventional methods of lifetime reduction such as irradiation with charged particles, this method offers the advantages of not requiring additional lifetime control steps and being able to create lifetime reduction regions at arbitrary locations by considering stress during the design phase.

[0168] Next, as Figure 22As shown, a barrier metal 5 is formed on the first main surface of the semiconductor substrate and on the interlayer insulating film 4, and an emitter electrode 6 is further formed on the barrier metal 5. The barrier metal 5 is formed by depositing titanium nitride film using PDV (physical vapor deposition) and CVD.

[0169] The emitter electrode 6 can be formed, for example, by depositing an aluminum-silicon alloy (Al-Si alloy) or a material composed mainly of copper onto the barrier metal 5 using PVD methods such as sputtering or evaporation. Alternatively, a nickel alloy (Ni alloy) can be further formed on the already formed aluminum-silicon alloy using chemical plating or electroplating to serve as the emitter electrode 6. If the emitter electrode 6 is formed by plating, a thick metal film can be easily formed as the emitter electrode 6, thereby increasing the heat capacity of the emitter electrode 6 and improving its heat resistance. Furthermore, if the emitter electrode 6 made of aluminum-silicon alloy is formed by PVD and then a nickel alloy is further formed by plating, the plating process for forming the nickel alloy can be performed after processing the second main surface side of the semiconductor substrate.

[0170] Next, as Figure 23 As shown, the second main surface of the semiconductor substrate is ground to thin the semiconductor substrate to a designed thickness. The thickness of the ground semiconductor substrate can be, for example, 60 μm to 200 μm.

[0171] Next, as Figure 24 As shown, an n-type buffer layer 3 is formed by implanting an n-type impurity from the second main surface of the semiconductor substrate. Then, a p-type collector layer 16 is formed by implanting a p-type impurity from the second main surface of the semiconductor substrate. The n-type buffer layer 3 can be formed in the IGBT region 10, the diode region 20, and the termination region 30, or it can be formed only in the IGBT region 10 or the diode region 20.

[0172] The n-type buffer layer 3 can be formed, for example, by implanting phosphorus (P) ions. Alternatively, protons (H) can also be implanted. ＋ This process is repeated. Furthermore, both protons and phosphorus can be implanted. Protons can be implanted to a deeper location from the second main surface of the semiconductor substrate with relatively low acceleration energy. Additionally, the depth of proton implantation can be easily varied by changing the acceleration energy. Therefore, when forming the n-type buffer layer 3 with protons, if multiple implantations are performed while varying the acceleration energy, an n-type buffer layer 3 with a width in the thickness direction of the semiconductor substrate can be formed that is wider than the case where it is formed with phosphorus.

[0173] Furthermore, since phosphorus can increase the activation rate of n-type impurities compared to protons, by forming the n-type buffer layer 3 from phosphorus, even in thinned semiconductor substrates, punch-through of the depletion layer can be suppressed more reliably. To achieve further thinning of the semiconductor substrate, it is preferable to implant both protons and phosphorus to form the n-type buffer layer 3, in which case protons are implanted from the second main surface to a depth greater than that of phosphorus.

[0174] The p-type collector layer 16 can be formed, for example, by implanting boron (B). The p-type collector layer 16 is also formed in the terminal region 30, and the p-type collector layer 16 in the terminal region 30 becomes the p-type terminal collector layer 16a. After ion implantation from the second main surface of the semiconductor substrate, the second main surface is irradiated with a laser for laser annealing, thereby activating the implanted boron and forming the p-type collector layer 16. At this time, phosphorus implanted from the second main surface of the semiconductor substrate to a relatively shallow position for the n-type buffer layer 3 is also activated simultaneously. On the other hand, since protons are activated at a relatively low annealing temperature of 350°C to 500°C, it is necessary to ensure that the semiconductor substrate as a whole does not reach a temperature higher than 350°C to 500°C after proton implantation, except for the proton activation process. Since laser annealing can only make the area near the second main surface of the semiconductor substrate reach a high temperature, it is possible to activate both n-type and p-type impurities even after proton implantation.

[0175] Next, as Figure 25 As shown, n is formed in diode region 20. ＋ Type 26 cathode layer. ＋ The cathode layer 26 can also be formed, for example, by implanting phosphorus (P). Figure 25 As shown, so that the p-type collector layer 16 and n ＋ The boundary of the cathode layer 26 is located at a distance U1 from the boundary between the IGBT region 10 and the diode region 20 towards the diode region 20, and phosphorus is selectively implanted from the second main surface using a mask process. This is used to form n ＋ The amount of n-type impurities implanted in the p-type cathode layer 26 is greater than the amount of p-type impurities implanted to form the p-type collector layer 16. Although in Figure 25 In the middle, the p-type collector layer 16 and n ＋ The depth of the cathode layer 26 from the second main surface is shown to be the same, but n ＋ The depth of the p-type cathode layer 26 is greater than the depth of the p-type collector layer 16. This forms an n-type collector layer. ＋ The region of the p-type cathode layer 26 becomes an n-type semiconductor because it requires the implantation of n-type impurities into the region where p-type impurities have been implanted. Therefore, the formation of n-type semiconductors... ＋ The concentration of p-type impurities implanted in the entire area of ​​the cathode layer 26 is higher than the concentration of n-type impurities.

[0176] Next, as Figure 26 As shown, a collector electrode 7 is formed on the second main surface of a semiconductor substrate. The collector electrode 7 is formed covering the entire surface of the IGBT region 10, the diode region 20, and the termination region 30 of the second main surface. Alternatively, the collector electrode 7 can be formed covering the entire surface of the second main surface of the n-type wafer, which is the semiconductor substrate. The collector electrode 7 can be formed by PVD deposition of aluminum-silicon alloy (Ai-Si alloy), titanium (Ti), etc., such as by sputtering or evaporation, or by stacking multiple metals such as aluminum-silicon alloy, titanium, nickel, or gold. Furthermore, a metal film can be further formed on a metal film formed by PVD through chemical plating or electroplating to serve as the collector electrode 7.

[0177] Semiconductor device 100 or semiconductor device 101 is manufactured through the above-described process. Since multiple semiconductor devices 100 or semiconductor devices 101 are manufactured in a matrix on a single n-type wafer, they are divided into individual semiconductor devices 100 or semiconductor devices 101 by laser cutting or blade cutting, thereby completing semiconductor device 100 or semiconductor device 101.

[0178] Although n was formed here before the trench gate was formed. ＋ Type source layer 13 and p ＋ Type contact layer 14 and p ＋ Type 24 anode contact layer, but n can also be formed after the formation of trench gate. ＋ Type source layer 13 or p ＋ Type contact layer 14 or p ＋ Type 24 anode contact layer. It is known that even after the formation of the trench gate, an n-type anode contact layer is formed. ＋ Type source layer 13 or p ＋ Type contact layer 14 or p ＋ In the case of the type anode contact layer 24, the first dislocation 200 is also formed due to high-dose implantation and annealing. However, to date, no one knows how to control n － The stress within the drift layer 1 causes the second dislocation 201 to be placed at an arbitrary location.

[0179] [Implementation Method 1]

[0180] In Embodiment 1, the second dislocation 201 is applied to the IGBT in the IGBT region 10, which is a trench-type bipolar device (bipolar semiconductor element). Although an IGBT constituting an RC-IGBT is illustrated here, the bipolar device to which the second dislocation 201 is applied can be a single IGBT or other bipolar devices. Furthermore, in the following explanation, due to the long lifespan of the semiconductor substrate, a semiconductor device made primarily of silicon is used as an example to illustrate the effect. However, as long as the same effect is achieved, semiconductor substrates made primarily of silicon carbide, gallium nitride, gallium oxide, diamond, etc., can also be used.

[0181] exist Figures 27-29 An example of the structure of the semiconductor device according to Embodiment 1 is shown. Figures 27-29 Is to make Figure 7 as well as Figure 8 The diagram shows a simplified and composite structure of the IGBT region 10.

[0182] Figure 27 It is to configure the second bit error 201 in ratio n. ＋ Type source layer 13 or p ＋ An example of a p-type base layer 15 located deep within the p-type contact layer 14 (at the location on the second main surface side). The second dislocation 201 can be bent, or it can have a shape bulging towards the second main surface side, and it can also have components of both the <110> direction and the <100> direction of the semiconductor substrate. By disposing the second dislocation 201 in an n-type contact layer... － The drift layer 1 is located near the surface, which can locally reduce carrier lifetime and improve switching losses.

[0183] Furthermore, the total length L1 of the second dislocation 201 is preferably longer than the mesa width W1 to improve the reduction of carrier lifetime. As a method to ensure the total length L1 of the second dislocation 201, the dislocation can also be bent. In this case, it is not a problem even if the second dislocation 201 has components in the <100> and <110> directions of the semiconductor substrate. Additionally, in order to reduce the carrier lifetime on the second main surface side compared to the mesa region, the second dislocation 201 can also be formed in a shape that bulges towards the second main surface side.

[0184] Figure 28 This is an example of placing the second dislocation 201 within the n-type carrier accumulation layer 2. That is, the second dislocation 201 is placed at a location deeper than the p-type base layer 15, or at a location deeper than the interface between the p-type base layer 15 and the n-type carrier accumulation layer 2.

[0185] like Figure 27Thus, when the second dislocation 201 is disposed in the p-type base layer 15, the second dislocation 201 has a different band gap and Fermi level than the perfect crystal, therefore the threshold voltage used to form the channel varies locally. Furthermore, since the second dislocation 201 is also a crystalline disorder, the channel mobility may be reduced. To avoid the above situations while forming a region with reduced carrier lifetime, such as... Figure 28 Therefore, it is preferable to place the second dislocation 201 at a position deeper than the p-type base layer 15. "Deeper than the p-type base layer 15" means that when viewed from above, it is located at a position deeper than the n-type base layer 15. ＋ In the same region as the source layer 13, the location deeper than the point where the net carrier concentration reverses from n-type to p-type in the depth direction toward the second principal surface. In other words, it refers to the end of the region on the second principal surface side of the region where the inversion layer is formed when a voltage higher than the threshold voltage is applied to the gate.

[0186] Furthermore, since the electric field strength increases when the interface between the p-type base layer 15 and the n-type carrier accumulation layer 2 is broken, the leakage current increases when the second dislocation 201 is placed at that location. Therefore, in order to suppress the increase in leakage current while forming a region with reduced carrier lifetime, it is preferable to place the second dislocation 201 at a location deeper than the interface between the p-type base layer 15 and the n-type carrier accumulation layer 2.

[0187] Figure 29 This is an example where at least a portion of the second dislocation 201 is disposed at a location deeper than the bottom of the active trench gate 11. When the second dislocation 201 is disposed at a location deeper than the active trench gate 11, in n... － The carrier lifetime reduction region can also be expanded in the deeper regions of the drift layer 1, thus increasing the effect of reducing switching losses.

[0188] [Implementation Method 2]

[0189] In embodiment 2, the second dislocation 201 is applied to the diode in diode region 20, which is a bipolar device with a trench. Although a diode constituting an RC-IGBT is illustrated here, the bipolar device to which the second dislocation 201 is applied can be a single diode or other bipolar devices.

[0190] exist Figures 30-32 An example of the structure of the semiconductor device according to Embodiment 2 is shown. Figures 30-32 Is to make Figure 10 as well as Figure 11 The diagram shows a simplified and composite structure of the diode region 20.

[0191] Figure 30 It is to configure at least a portion of the second bit fault 201 in the ratio p. ＋An example of a p-type anode layer 25 located deep within the p-type anode contact layer 24. By configuring the second dislocation 201 in the diode region 20, recovery losses can be reduced. This is achieved by configuring the second dislocation 201 closer to the n-type anode layer 25. － The region of the n-type drift layer 1 or the n-type carrier accumulation layer 2 can be expected to reduce the supply of holes during forward operation and promote the discharge of holes during disconnection, thereby reducing recovery loss.

[0192] Figure 31 This is an example where at least a portion of the second dislocation 201 is disposed in the n-type carrier accumulation layer 2. That is, at least a portion of the second dislocation 201 is disposed in a layer that is more compact than the p-type anode layer 25 and the n-type carrier accumulation layer 26. － The interface of the p-type drift layer 1 is located deeper. This is due to the p-type anode layer 25 and the n-type anode layer 25. － When the interface of the p-type drift layer 1 is disconnected, the electric field strength increases, thus increasing the leakage current when the second dislocation 201 is placed at that location. Therefore, in order to avoid increasing the leakage current while forming a region with reduced carrier lifetime, it is preferable to place the second dislocation 201 at a position greater than that of the p-type anode layer 25 and the n-type anode layer 26. － The location deep at the interface of drift layer 1.

[0193] Figure 32 This is an example where at least a portion of the second dislocation 201 is positioned deeper than the diode trench gate 21. By positioning at least a portion of the second dislocation 201 closer to the second main surface than the diode trench gate 21, thus achieving a certain effect in n... － The region on the second main surface of the drift layer 1 can also expand the carrier lifetime reduction region and reduce recovery loss.

[0194] [Implementation Method 3]

[0195] While embodiments 1 and 2 show examples of the second dislocation 201 being uniformly arranged in the left-right direction on the paper surface of the IGBT region 10, embodiment 3 shows an example of the second dislocation 201 being partially arranged. That is, embodiment 3 shows an example of the arrangement of the second dislocation 201 when viewed from above.

[0196] exist Figures 33-35 An example of the structure of the semiconductor device according to Embodiment 3 is shown. Figure 33 as well as Figure 34 Is to make Figure 7 or Figure 8 The diagram shown is a simplified and composite representation of the structure. Figure 35 Is to make Figure 13 The diagram shows a simplified and composite structure.

[0197] Figure 33 It is to allocate the second bit error 201 to n.＋ An example below source layer 13. That is, the second dislocation 201 is positioned at n when viewed from above. ＋ At least a portion of the formation region of the source layer 13. By configuring the second dislocation 201 in n ＋ Below the source layer 13, thus enabling n during turn-off. ＋ Hole discharge directly below the source layer 13 suppresses latch-up. Therefore, the cutoff tolerance of the semiconductor device is improved.

[0198] Figure 34 It is to configure the second bit error 201 in p ＋ An example below contact layer 14. That is, the second dislocation 201 is disposed on p when viewed from above. ＋ At least a portion of the formation region of the contact layer 14. By configuring the second dislocation 201 on p ＋ The contact layer 14 is positioned below the contact layer 14, thereby limiting the amount of holes injected during conduction and reducing the amount of holes discharged, thus reducing turn-off loss.

[0199] Figure 35 This is an example where the second dislocation 201 is not configured in the termination region 30. That is, the second dislocation 201 is configured in a region other than the termination region 30. The second dislocation 201 is configured at the boundary between the IGBT region 10 and the termination region 30.

[0200] Because the electric field strength increases when disconnected in the terminal region 30, the leakage current increases when the second dislocation 201 is placed in the terminal region 30. Furthermore, even if the carrier lifetime of the terminal region 30 is reduced, the impact on switching losses and breaking capacity is small. Therefore, the advantage of placing the second dislocation 201 in the terminal region 30 is small, and it is not necessary to intentionally place the second dislocation 201 in the terminal region 30; it is preferable not to place the second dislocation 201 in the terminal region 30.

[0201] In addition, Figure 35 In the terminal region 30, a plurality of terminal dummy trench gates 35 are provided, and the depth of the plurality of terminal dummy trench gates 35 gradually decreases in the outward direction (from the cell region to the terminal region). That is, the terminal dummy trench gates 35 are shallower towards the outer side. In this case, since most designs are made to increase the electric field strength on the second main surface side of the terminal dummy trench gates 35, it is more preferable not to place the second dislocation 201 in the terminal region 30.

[0202] On the other hand, it is preferable to configure the second dislocation 201 at the boundary between the IGBT region 10 and the terminal region 30. This allows for improved hole discharge during disconnection without changing the hole injection amount during conduction, thereby increasing the turn-off tolerance of the semiconductor device.

[0203] [Implementation Method 4]

[0204] exist Figure 36 as well as Figure 37 An example of the structure of the semiconductor device according to Embodiment 4 is shown. Figure 36 as well as Figure 37 Is to make Figure 12 The diagram shows a simplified and composite structure.

[0205] Figure 36 This example involves distributing at least a portion of the second dislocation 201 in the boundary region between the IGBT region 10 and the diode region 20. Furthermore, at least a portion of the diode region 20 is provided with a region where the density of the second dislocation 201 is greater than the density of the second dislocation 201 in the IGBT region 10. Additionally, in the diode region 20, when viewed from above, at p... ＋ The density of the second dislocation 201 in the formation region of the type anode contact layer 24 is greater than that in the absence of p ＋ The density of the second dislocation 201 in the region of the anode contact layer 24.

[0206] When the diode is turned off, a portion of the holes reach the IGBT region 10 and pass through p ＋ Type contact layer 14 is discharged. Therefore, in n ＋ Holes accumulate near source layer 13, potentially leading to latch-up. For example... Figure 36 In this way, by configuring the second dislocation 201 at the boundary region between the IGBT region 10 and the diode region 20, the turn-off tolerance can be increased. If it is desired to aggressively improve the recovery loss and turn-off tolerance of the diode, the second dislocation 201 can be configured at a higher density in the diode region 20 than in the IGBT region 10.

[0207] A p is configured in diode region 20. ＋ The area of ​​the type anode contact layer 24 and the unconfigured p ＋ The region of the type anode contact layer 24. Wherein, in order to suppress the anode contact layer 24... ＋ The amount of holes supplied by the anode contact layer 24 is preferably such that, when viewed from above, it is in contact with p ＋ The density of the second dislocation 201 in the overlapping region of the type anode contact layer 24 is greater than that of the dislocation 201 not associated with p when viewed from above. ＋ The density of the second dislocation 201 in the overlapping region of the type anode contact layer 24. By suppressing the dislocation from p ＋ The amount of holes supplied by the anode contact layer 24 is reduced, thereby decreasing recovery losses. Here, the density of the second dislocation 201 does not need to refer to the overall density of each region. It is conceivable to compare the density of the second dislocation 201 within a region observable in the TEM analysis section.

[0208] Figure 37 This example illustrates a region in at least a portion of the diode region 20 where the density of the second dislocation 201 is less than that in the IGBT region 10. When actively improving the turn-off loss and cut-off capacity of the IGBT, the density of the second dislocation 201 in the IGBT region 10 can be higher than that in the diode region 20. Here, the density of the second dislocation 201 does not necessarily refer to the overall density of each region. It is conceivable to compare the density of the second dislocation 201 within a region that can be observed in the TEM analysis section.

[0209] [Implementation Method 5]

[0210] exist Figure 38 An example of the structure of the semiconductor device according to Embodiment 5 is shown. Figure 38 Is to make Figure 7 as well as Figure 8 The diagram shows a simplified and composite structure.

[0211] Figure 38 This is an example where an active trench gate 11 and a dummy trench gate 12 are configured in IGBT region 10. At least a portion of the second dislocation 201 is configured to contact the dummy trench gate 12.

[0212] By utilizing the dummy trench gate 12, the drawbacks of configuring the second dislocation 201 can be suppressed. While the second dislocation 201 increases the hole ejection rate by reducing carrier lifetime, thus increasing cutoff capability and reducing switching losses, it also has the disadvantage of reducing the number of holes during turn-on and increasing the turn-on voltage. For example... Figure 38 In this way, with the second dislocation 201 arranged around the dummy trench gate 12, no channel is formed on the side of the dummy trench gate 12, and no current flows in that part. Therefore, even if the carrier lifetime is reduced, the turn-on voltage will not increase. In addition, the hole trapping effect during disconnection can be expected, thus improving the trade-off between turn-on voltage and switching losses.

[0213] Furthermore, when the second dislocation 201 contacts the active trench gate 11 with a gate potential, the electric field at the contact point where it contacts the gate trench insulating film 11b increases, raising concerns about deterioration of gate reliability. Therefore, it is preferable that the second dislocation 201 contacts the dummy trench gate 12 rather than the active trench gate 11. Here, "contact" refers to a substantial connection as determined by analytical methods such as TEM.

[0214] [Implementation Method 6]

[0215] exist Figures 39-41 An example of the structure of the semiconductor device according to Embodiment 6 is shown. Figures 39-41 Is to make Figure 7 as well as Figure 8 The diagram shows a simplified and composite structure. However, instead of the active trench gate 11, a two-layer trench gate 36 with a two-layer gate structure is provided.

[0216] Compared to the structure of implementation method 1 ( Figure 27 ), Figure 39 The structure shown replaces the active trench gate 11 with two trench gates 36. The two trench gates 36 are configured such that a lower gate trench electrode 36c is buried in the lower portion (second main surface side) of the trench formed on the semiconductor substrate via a lower gate trench insulating film 36d, and an upper gate trench electrode 36a is buried in the upper portion (first main surface side) of the trench via an upper gate trench insulating film 36b. An intermediate insulating film 36e insulates the upper gate trench electrode 36a from the upper gate trench insulating film 36b, allowing the upper gate trench electrode 36a and the upper gate trench insulating film 36b to be set to different potentials. In this embodiment, the upper gate trench electrode 36a is set to the gate potential, and the lower gate trench electrode 36c is set to the emitter potential. That is, the lower gate trench electrode 36c is electrically connected to the emitter electrode 6.

[0217] By using a two-layer trench gate 36 constructed with two gate layers, compared to an active trench gate 11 constructed with a single gate layer, n can be increased. － The stress within the drift layer 1 easily causes the second dislocation 201 to be disposed in n. － Type 1 drift layer.

[0218] In addition, in the structure of embodiment 1 ( Figure 27 In this process, the thickness of the gate trench insulating film 11b of the active trench gate 11 is changed to achieve n － Under stress control within the drift layer 1, important electrical characteristics such as the threshold voltage change. In contrast, in the structure of embodiment 6 (… Figure 39 In this process, if the lower gate trench electrode 36c is set to the emitter potential, then even if the thickness of the lower gate trench insulating film 36d of the two trench gates 36 is changed, n... － Stress control within the drift layer 1 and important electrical characteristics such as threshold voltage remain unchanged. Therefore, according to this embodiment, the thickness of the lower gate trench insulating film 36d can be designed as an independent parameter for stress control.

[0219] Figure 40This is an example where the second dislocation 201 is configured to contact the lower gate trench insulating film 36d. Furthermore, the lower gate trench insulating film 36d is thicker than the upper gate trench insulating film 36b. Additionally, the second dislocation 201 is not configured at the boundary between the upper gate trench insulating film 36b and the lower gate trench insulating film 36d (the boundary between the upper gate trench electrode 36a and the lower gate trench electrode 36c).

[0220] When the second dislocation 201 contacts the upper gate trench insulating film 36b used for potential control in forming the channel, the gate electric field locally increases at the contact point, raising concerns about reduced gate reliability. Therefore, it is preferable that the second dislocation 201 contacts the lower gate trench insulating film 36d. Furthermore, by thickening the lower gate trench insulating film 36d, it is possible to increase the n... － The stress in drift layer 1 increases.

[0221] Furthermore, by contacting the second dislocation 201 with the designed-thick lower gate trench insulating film 36d, the degradation of gate reliability can be suppressed without setting the lower gate trench electrode 36c to the emitter potential. Additionally, when the second dislocation 201 is disposed at the boundary between the upper gate trench insulating film 36b and the lower gate trench insulating film 36d, the mechanical fragility of the boundary increases, raising concerns about reliability degradation such as damage under external stress.

[0222] Figure 41 This example involves at least a portion of the second dislocation 201 contacting the boundary portion of the upper gate trench insulating film 36b and the lower gate trench insulating film 36d. The boundary portion of the upper gate trench insulating film 36b and the lower gate trench insulating film 36d is a region of high stress and thermal instability. Therefore, when external stress such as dislocation displacement is applied, the second dislocation 201 readily moves to the boundary portion of the upper gate trench insulating film 36b and the lower gate trench insulating film 36d. When the second dislocation 201 moves, the electrical characteristics may change. Therefore, by pre-positioning the second dislocation 201 at the boundary portion of the upper gate trench insulating film 36b and the lower gate trench insulating film 36d, it is possible to suppress changes in electrical characteristics when external stress is applied during thermal cycling tests, etc.

[0223] Furthermore, the various implementation methods can be freely combined or appropriately modified or omitted.

[0224] <Postscript>

[0225] The various forms disclosed herein will be recorded hereafter as appendices.

[0226] (Note 1) A semiconductor device, wherein,

[0227] The aforementioned semiconductor device includes a bipolar semiconductor element, which has the following characteristics:

[0228] A semiconductor substrate has a first main surface and a second main surface, and a drift layer of a first conductivity type is formed thereon;

[0229] Multiple trenches are formed on the first main surface of the semiconductor substrate.

[0230] The electrodes are embedded in the aforementioned trench via an insulating film;

[0231] The mesa region is the area between the trenches of the aforementioned semiconductor substrate; and

[0232] The source layer of the first conductivity type or the contact layer of the second conductivity type is formed on the surface portion of the first main surface side of the mesa region.

[0233] In the aforementioned mesa region, there are dislocations whose total length is longer than the width of the aforementioned mesa region, located on the side of the second main surface closer to the source layer or the contact layer.

[0234] (Note 2) In the semiconductor device according to Note 1, wherein,

[0235] The dislocations described above have a curved shape.

[0236] (Note 3) The semiconductor device according to Note 2, wherein,

[0237] The aforementioned dislocation bends in a manner that protrudes toward the aforementioned second principal surface.

[0238] (Appendix 4) The semiconductor device according to any one of Appendices 1 to 3, wherein,

[0239] The dislocations described above have a composition in the <110> direction and a composition in the <100> direction of the semiconductor substrate.

[0240] (Appendix 5) The semiconductor device according to any one of Appendices 1 to 4, wherein,

[0241] The main constituent element of the aforementioned semiconductor substrate is silicon.

[0242] (Appendix 6) The semiconductor device according to any one of Appendices 1 to 5, wherein,

[0243] The aforementioned bipolar semiconductor device is an IGBT (Insulated Gate Bipolar Transistor) or an RC-IGBT (Reverse Conducting IGBT) that includes an IGBT and a diode.

[0244] (Note 7) The semiconductor device according to Note 6, wherein,

[0245] The aforementioned source layer or contact layer is disposed on the surface portion of the base layer of the second conductivity type formed on the surface portion of the first main surface side of the aforementioned mesa region.

[0246] The dislocations are positioned closer to the second principal surface than the base layer.

[0247] (Note 8) The semiconductor device according to Note 7, wherein,

[0248] The aforementioned semiconductor device further comprises a carrier accumulation layer formed on the second main surface side of the aforementioned base layer.

[0249] The dislocation is positioned closer to the second main surface than the interface between the base layer and the carrier accumulation layer.

[0250] (Note 9) The semiconductor device according to Note 6, wherein,

[0251] At least a portion of the dislocation is located on the second main surface side, which is closer to the bottom of the trench.

[0252] (Note 10) The semiconductor device according to Note 6, wherein,

[0253] When viewed from above, the aforementioned dislocations overlap with at least a portion of the aforementioned source layer.

[0254] (Note 11) The semiconductor device according to Note 6, wherein,

[0255] When viewed from above, the aforementioned dislocations overlap with at least a portion of the aforementioned contact layer.

[0256] (Note 12) The semiconductor device according to Note 6, wherein,

[0257] The aforementioned semiconductor device further includes a terminal region disposed around the IGBT region where the aforementioned IGBT is configured.

[0258] The aforementioned dislocation is not configured in the aforementioned terminal region.

[0259] (Note 13) The semiconductor device according to Note 12, wherein,

[0260] Multiple terminal dummy trench gates are formed in the aforementioned terminal region, with the terminal dummy trench gates being shallower towards the outer edge.

[0261] (Note 14) The semiconductor device according to Note 6, wherein,

[0262] The aforementioned semiconductor device further includes a terminal region disposed around the IGBT region where the aforementioned IGBT is configured.

[0263] At least a portion of the aforementioned dislocations are configured in the boundary region between the aforementioned IGBT region and the aforementioned terminal region.

[0264] (Note 15) The semiconductor device according to Note 6, wherein,

[0265] A portion of the electrode embedded in the aforementioned trench is a dummy trench electrode electrically connected to the emitter electrode.

[0266] (Note 16) The semiconductor device according to Note 15, wherein,

[0267] At least a portion of the aforementioned dislocations come into contact with the aforementioned trench into which the aforementioned dummy trench electrode is embedded.

[0268] (Note 17) The semiconductor device according to Note 6, wherein,

[0269] The electrodes embedded in the trenches are separated into an upper gate trench electrode located on the first main surface side and a lower gate trench electrode located on the second main surface side.

[0270] The upper gate trench electrode and the lower gate trench electrode are insulated from each other by an intermediate insulating film.

[0271] (Note 18) The semiconductor device according to Note 17, wherein,

[0272] The insulating film within the aforementioned trench includes: an upper gate trench insulating film positioned closer to the first main surface than the intermediate insulating film; and a lower gate trench insulating film positioned closer to the second main surface than the intermediate insulating film.

[0273] At least a portion of the aforementioned dislocations are in contact with the aforementioned lower gate trench insulating film.

[0274] (Note 19) The semiconductor device according to Note 17, wherein,

[0275] The insulating film within the aforementioned trench includes: an upper gate trench insulating film positioned closer to the first main surface than the intermediate insulating film; and a lower gate trench insulating film positioned closer to the second main surface than the intermediate insulating film.

[0276] The lower gate trench insulating film is thicker than the upper gate trench insulating film.

[0277] (Note 20) The semiconductor device according to Note 19, wherein,

[0278] At least a portion of the aforementioned dislocations are in contact with the aforementioned lower gate trench insulating film.

[0279] (Note 21) The semiconductor device according to Note 17, wherein,

[0280] The insulating film within the aforementioned trench includes: an upper gate trench insulating film positioned closer to the first main surface than the intermediate insulating film; and a lower gate trench insulating film positioned closer to the second main surface than the intermediate insulating film.

[0281] The aforementioned dislocation does not contact the boundary portion of the upper gate trench insulating film and the lower gate trench insulating film.

[0282] (Note 22) The semiconductor device according to Note 17, wherein,

[0283] The insulating film within the aforementioned trench includes: an upper gate trench insulating film positioned closer to the first main surface than the intermediate insulating film; and a lower gate trench insulating film positioned closer to the second main surface than the intermediate insulating film.

[0284] At least a portion of the aforementioned dislocations are in contact with the boundary portion of the upper gate trench insulating film and the lower gate trench insulating film.

[0285] (Note 23) The semiconductor device according to any one of Notes 1 to 5, wherein,

[0286] The aforementioned bipolar semiconductor device is a diode or an RC-IGBT (Reverse Conducting IGBT) that includes both an IGBT (Insulated Gate Bipolar Transistor) and a diode.

[0287] (Note 24) The semiconductor device according to Note 23, wherein,

[0288] The aforementioned contact layer is disposed on the surface portion of the anode layer of the second conductivity type formed on the surface portion of the first main surface side of the aforementioned platform region.

[0289] At least a portion of the aforementioned dislocations are disposed in the aforementioned anode layer.

[0290] (Note 25) The semiconductor device according to Note 23, wherein,

[0291] The aforementioned contact layer is disposed on the surface portion of the anode layer of the second conductivity type formed on the surface portion of the first main surface side of the aforementioned platform region.

[0292] At least a portion of the aforementioned dislocations are disposed at a position closer to the second main surface than the interface between the aforementioned anode layer and the aforementioned drift layer.

[0293] (Note 26) The semiconductor device according to Note 23, wherein,

[0294] At least a portion of the dislocation is located on the second main surface side, which is closer to the bottom of the trench.

[0295] (Note 27) The semiconductor device according to Note 23, wherein,

[0296] The aforementioned bipolar semiconductor device is the aforementioned RC-IGBT.

[0297] At least a portion of the aforementioned dislocation is disposed at the boundary between the IGBT region where the aforementioned IGBT is disposed and the diode region where the aforementioned diode is disposed.

[0298] (Note 28) The semiconductor device according to Note 23, wherein,

[0299] The aforementioned bipolar semiconductor device is the aforementioned RC-IGBT.

[0300] The aforementioned dislocation configuration is located on both sides of the IGBT region where the aforementioned IGBT is configured and the diode region where the aforementioned diode is configured.

[0301] At least a portion of the IGBT region is provided with a region where the density of the dislocations is greater than that of the dislocations in the diode region.

[0302] (Note 29) The semiconductor device according to Note 23, wherein,

[0303] The aforementioned bipolar semiconductor device is the aforementioned RC-IGBT.

[0304] The aforementioned dislocation configuration is located on both sides of the IGBT region where the aforementioned IGBT is configured and the diode region where the aforementioned diode is configured.

[0305] At least a portion of the diode region is provided with a region where the density of the dislocations is greater than that of the IGBT region.

[0306] (Note 30) The semiconductor device according to Note 23, wherein,

[0307] When viewed from above, the density of the dislocations in the region overlapping with the contact layer is greater than the density of the dislocations in the region not overlapping with the contact layer when viewed from above.

[0308] (Appendix 31) A method for manufacturing a semiconductor device, wherein,

[0309] The method for manufacturing the above-mentioned semiconductor device includes:

[0310] A process for preparing a semiconductor substrate having a first main surface and a second main surface, and having a drift layer of a first conductivity type formed thereon;

[0311] The process of forming a source layer of the first conductivity type or a contact layer of the second conductivity type containing the first dislocation on the surface portion of the first main surface side of the semiconductor substrate; and

[0312] The process involves heat-treating the first dislocation to move it to a position closer to the second main surface than the source layer or the contact layer, thereby forming a second dislocation at a position closer to the second main surface than the source layer or the contact layer.

[0313] (Note 32) According to the method for manufacturing a semiconductor device as described in Note 31, wherein,

[0314] The manufacturing method of the aforementioned semiconductor device further includes:

[0315] The process of forming a plurality of trenches reaching the drift layer on the first main surface of the semiconductor substrate; and

[0316] The process of embedding the electrodes into the aforementioned trench via an insulating film;

[0317] In the process of forming the second dislocation, the second dislocation is formed with a total length longer than the width of the region between the trenches of the semiconductor substrate, i.e., the mesa region.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes a bipolar semiconductor element, which has: A semiconductor substrate has a first main surface and a second main surface, and a drift layer of a first conductivity type is formed thereon; Multiple trenches are formed on the first main surface of the semiconductor substrate; The electrodes are embedded in the trench via an insulating film; The mesa region is the area between the trenches of the semiconductor substrate; as well as The source layer of the first conductivity type or the contact layer of the second conductivity type is formed on the surface portion of the first main surface side of the mesa region. The mesa region has dislocations whose total length is longer than the width of the mesa region at positions on the second main surface side of the source layer or the contact layer.

2. The semiconductor device according to claim 1, characterized in that, The dislocation has a curved shape.

3. The semiconductor device according to claim 2, characterized in that, The dislocation bends in a manner that protrudes toward the second principal surface.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The dislocation has a component in the <110> direction and a component in the <100> direction of the semiconductor substrate.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The main constituent element of the semiconductor substrate is silicon.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The bipolar semiconductor element is an IGBT or an RC-IGBT that includes an IGBT and a diode.

7. The semiconductor device according to claim 6, characterized in that, The source layer or the contact layer is disposed on the surface portion of the base layer of the second conductivity type formed on the surface portion of the first main surface side of the mesa region. The dislocation is positioned closer to the second principal surface than the base layer.

8. The semiconductor device according to claim 7, characterized in that, The semiconductor device further includes a carrier accumulation layer formed on the second main surface side of the base layer. The dislocation is positioned closer to the second main surface than the interface between the base layer and the carrier accumulation layer.

9. The semiconductor device according to claim 6, characterized in that, At least a portion of the dislocation is located closer to the second principal surface than the bottom of the trench.

10. The semiconductor device according to claim 6, characterized in that, The dislocation overlaps with at least a portion of the source layer when viewed from above.

11. The semiconductor device according to claim 6, characterized in that, The dislocation overlaps with at least a portion of the contact layer when viewed from above.

12. The semiconductor device according to claim 6, characterized in that, The semiconductor device further includes a terminal region disposed around the IGBT region where the IGBT is configured. The dislocation is not configured in the terminal region.

13. The semiconductor device according to claim 12, characterized in that, Multiple terminal dummy trench gates are formed in the terminal region, with the terminal dummy trench gates being shallower towards the outer edge.

14. The semiconductor device according to claim 6, characterized in that, The semiconductor device further includes a terminal region disposed around the IGBT region where the IGBT is configured. At least a portion of the dislocation is configured in the boundary region between the IGBT region and the terminal region.

15. The semiconductor device according to claim 6, characterized in that, A portion of the electrode embedded in the trench is a dummy trench electrode electrically connected to the emitter electrode.

16. The semiconductor device according to claim 15, characterized in that, At least a portion of the dislocations are in contact with the trench into which the dummy trench electrode is embedded.

17. The semiconductor device according to claim 6, characterized in that, The electrode embedded in the trench is separated into an upper gate trench electrode located on the first main surface side and a lower gate trench electrode located on the second main surface side. The upper gate trench electrode and the lower gate trench electrode are insulated from each other by an intermediate insulating film.

18. The semiconductor device according to claim 17, characterized in that, The insulating film within the trench includes: an upper gate trench insulating film that is closer to the first main surface than the intermediate insulating film; and a lower gate trench insulating film that is closer to the second main surface than the intermediate insulating film. At least a portion of the dislocations are in contact with the underlying gate trench insulating film.

19. The semiconductor device according to claim 17, characterized in that, The insulating film within the trench includes: an upper gate trench insulating film that is closer to the first main surface than the intermediate insulating film; and a lower gate trench insulating film that is closer to the second main surface than the intermediate insulating film. The lower gate trench insulating film is thicker than the upper gate trench insulating film.

20. The semiconductor device according to claim 19, characterized in that, At least a portion of the dislocations are in contact with the underlying gate trench insulating film.

21. The semiconductor device according to claim 17, characterized in that, The insulating film within the trench includes: an upper gate trench insulating film that is closer to the first main surface than the intermediate insulating film; and a lower gate trench insulating film that is closer to the second main surface than the intermediate insulating film. The dislocation does not contact the boundary portion of the upper gate trench insulating film and the lower gate trench insulating film.

22. The semiconductor device according to claim 17, characterized in that, The insulating film within the trench includes: an upper gate trench insulating film that is closer to the first main surface than the intermediate insulating film; and a lower gate trench insulating film that is closer to the second main surface than the intermediate insulating film. At least a portion of the dislocations are in contact with the boundary portion of the upper gate trench insulating film and the lower gate trench insulating film.

23. The semiconductor device according to any one of claims 1 to 5, characterized in that, The bipolar semiconductor element is a diode or an RC-IGBT that includes an IGBT and a diode.

24. The semiconductor device according to claim 23, characterized in that, The contact layer is disposed on the surface portion of the anode layer of the second conductivity type formed on the surface portion of the first main surface side of the platform region. At least a portion of the dislocations are disposed in the anode layer.

25. The semiconductor device according to claim 23, characterized in that, The contact layer is disposed on the surface portion of the anode layer of the second conductivity type formed on the surface portion of the first main surface side of the platform region. At least a portion of the dislocation is positioned closer to the second main surface than the interface between the anode layer and the drift layer.

26. The semiconductor device according to claim 23, characterized in that, At least a portion of the dislocation is located closer to the second principal surface than the bottom of the trench.

27. The semiconductor device according to claim 23, characterized in that, The bipolar semiconductor device is the RC-IGBT. At least a portion of the dislocation is disposed at the boundary between the IGBT region where the IGBT is disposed and the diode region where the diode is disposed.

28. The semiconductor device according to claim 23, characterized in that, The bipolar semiconductor device is the RC-IGBT. The dislocation is configured on both sides of the IGBT region where the IGBT is configured and the diode region where the diode is configured. At least a portion of the IGBT region is provided with a region where the density of dislocations is greater than that of the diode region.

29. The semiconductor device according to claim 23, characterized in that, The bipolar semiconductor device is the RC-IGBT. The dislocation is configured on both sides of the IGBT region where the IGBT is configured and the diode region where the diode is configured. At least a portion of the diode region is provided with a region where the density of dislocations is greater than the density of dislocations in the IGBT region.

30. The semiconductor device according to claim 23, characterized in that, The density of dislocations in the region overlapping with the contact layer when viewed from above is greater than the density of dislocations in the region not overlapping with the contact layer when viewed from above.

31. A method for manufacturing a semiconductor device, characterized in that, The method for manufacturing the semiconductor device comprises: A process for preparing a semiconductor substrate having a first main surface and a second main surface, and having a drift layer of a first conductivity type formed thereon; The process of forming a source layer of the first conductivity type or a contact layer of the second conductivity type containing the first dislocation on the surface portion of the first main surface side of the semiconductor substrate. as well as The process of heat-treating the first dislocation to move it to a position closer to the second main surface than the source layer or the contact layer, thereby forming a second dislocation at a position closer to the second main surface than the source layer or the contact layer.

32. The method for manufacturing a semiconductor device according to claim 31, characterized in that, The method for manufacturing the semiconductor device further includes: The process of forming a plurality of trenches reaching the drift layer on the first main surface of the semiconductor substrate; and The process of embedding the electrode into the trench via an insulating film; In the process of forming the second dislocation, the second dislocation is formed with a total length longer than the width of the region between the trenches of the semiconductor substrate, i.e., the mesa region.

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