A silicon-on-insulator lateral insulated gate bipolar transistor
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-27
- Publication Date
- 2026-08-14
AI Technical Summary
[0003]传统的高压横向功率器件通常依赖大幅度增加漂移区长度提升击穿电压，这直接导致器件尺寸增大、芯片面积上升，与功率集成系统追求高功率密度、小型化的发展趋势相悖
本发明提出在LIGBT的漂移区插入多种深浅不同的沟槽结构并且在部分沟槽表面进行硅填充形成“凹凸”状多重深沟槽。这些沟槽通过与隔离沟槽同步蚀刻工艺形成，无需额外掩模或成本。在耐压过程中，深、浅沟槽侧壁氧化层分段承担电压，深沟槽内部填充的多晶硅起到垂直场板的作用，优化了电场分布，使器件击穿点出现在漂移区内部，参见图3（b），相比于单一沟槽的SOI-LIGBT只能承受17V电压，本发明在漂移区内插入多重过度不同发深浅沟槽，使其不仅缩短了漂移区长度，还可以承受308V电压。在功率器件中，漂移区的长度越长，可以实现的耐压越大，在漂移区内插入多种深浅不同的沟槽结构可以承受一部分电压，实现在相同耐压下，显著缩短漂移区的长度，从而减小功率器件的尺寸，大幅降低芯片的功率级面积。
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Figure CN122579635A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more specifically to a silicon-on-insulator lateral insulated gate bipolar transistor. Background Technology
[0002] In the field of single-chip intelligent power integrated circuits, optimizing chip area and reducing manufacturing costs remain core issues. These chips monolithically integrate various lateral power devices (power stages) with logic, control, drive, and protection circuits, with the power stages occupying more than half of the total chip area. High-voltage lateral power devices have high requirements for breakdown voltage and current carrying capacity. Therefore, a longer drift region is needed to withstand high voltage, and a larger channel width is required to carry large currents. At the same current and voltage levels, the surface area of lateral power devices is typically much larger than that of vertical power devices used in multi-chip packaging solutions. From a chip area perspective, single-chip solutions are only slightly superior to multi-chip packaging solutions at low currents. Therefore, reducing the size of high-voltage lateral power devices is of great significance for developing single-chip intelligent power integrated circuits for high current levels.
[0003] Traditional high-voltage lateral power devices typically rely on significantly increasing the drift region length to improve breakdown voltage. This directly leads to increased device size and chip area, contradicting the trend of power integrated systems pursuing high power density and miniaturization. Although existing technologies have incorporated some trench designs to assist in withstand voltage, significant shortcomings remain: firstly, a single trench has limited efficiency in electric field modulation, making it difficult to maintain high withstand voltage while significantly shortening the drift region length; secondly, traditional dielectric-filled trenches often introduce unnecessary carrier path blocking when the device is turned on, forcing current to bypass or pass through high-resistivity regions, thus limiting the device's current density. Summary of the Invention
[0004] To address the aforementioned problems, this invention proposes a silicon-on-insulator lateral insulated gate bipolar transistor that can maintain high withstand voltage even after shortening the drift region length.
[0005] The present invention adopts the following technical solution to solve the aforementioned technical problem: A silicon-on-insulator-gate lateral insulated-gate bipolar transistor (SiBMT) includes: a P-type substrate; a buried silicon dioxide layer, an N-type epitaxial layer, a gate oxide layer, and a dielectric layer sequentially disposed on the P-type substrate; a P-type well region and an N-type buffer region disposed within the N-type epitaxial layer; a P-type emitter region and an N-type emitter region disposed within the P-type well region; a P-type collector region disposed within the N-type buffer region; a gate polysilicon layer disposed on the gate oxide layer; a deep trench filled with silicon dioxide disposed within the N-type buffer region; and shallow trenches filled with silicon dioxide disposed on both sides of the deep trench. The deep trench and the shallow trench are located between the P-type well region and the N-type buffer region, and the height of the deep trench is greater than the height of the shallow trench.
[0006] Compared with the prior art, the present invention has the following beneficial effects: This invention proposes inserting multiple trench structures of varying depths into the drift region of a LIGBT and filling some trench surfaces with silicon to form a "concave-convex" multi-deep trench. These trenches are formed through a synchronous etching process with isolation trenches, requiring no additional masks or additional costs. During the withstand voltage test, the oxide layers on the sidewalls of the deep and shallow trenches segmentally bear the voltage, and the polysilicon filled inside the deep trenches acts as a vertical field plate, optimizing the electric field distribution and causing the device breakdown point to occur inside the drift region (see Figure 3(b)). Compared to a single-trench SOI-LIGBT that can only withstand 17V, this invention inserts multiple trenches of varying depths within the drift region, shortening the drift region length and enabling it to withstand 308V. In power devices, the longer the drift region, the higher the withstand voltage can be achieved. Inserting multiple trench structures of varying depths within the drift region can withstand a portion of the voltage, significantly shortening the drift region length under the same withstand voltage, thereby reducing the size of the power device and significantly reducing the power stage area of the chip.
[0007] Meanwhile, silicon is used to fill the removed silicon dioxide on the surface of the trench, forming a "concave-convex" structure on the surface of the trench. That is, slots are opened on the upper surface of the deep trench and the shallow trench and filled with silicon. This allows some charge carriers (current) to bypass the isolation area of the trench when the device is turned on and be guided to the low-resistance path on the surface of the device for transmission, thus optimizing the current path and improving the current density. Attached Figure Description
[0008] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.
[0009] Figure 1 is a schematic diagram of two 3D structures of the SOI-LIGBT device of this application. Figure 1(a) is a schematic diagram of the 3D structure of the LIGBT device proposed in this invention; Figure 1(b) is a schematic diagram of the 3D structure of the LIGBT device proposed in this invention with various deep and shallow trenches inserted in the drift region.
[0010] Figure 2These are four cross-sectional schematic diagrams of the SOI-LIGBT device of this application, wherein (a) is a cross-sectional view of the LIGBT device with silicon dioxide removed and silicon filled in the drift region trench surface; (b) is a cross-sectional view of the LIGBT device with silicon dioxide not removed in the drift region trench surface; (c) is a cross-sectional view of the LIGBT device with polysilicon filling in the drift region deep trench; and (d) is a cross-sectional view of the LIGBT device with no polysilicon in the drift region shallow trench.
[0011] Figure 3 is a schematic diagram of the off-state withstand voltage mechanism of the SOI-LIGBT device of this application. In Figure 3(a), the electric field equipotential line distribution of the LIGBT device proposed in this invention during the off-state process is shown. Figure 3(b) is a distribution diagram of the surface potential of the LIGBT with multiple deep trenches inserted in the drift region and the LIGBT with a single trench in this invention when subjected to the same voltage in the off-state as the length of the drift region is shown. Detailed Implementation
[0012] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0013] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0014] It should be understood that when a component or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers. The term "connection" in this specification, if referring to the transmission of electrical signals or data between connected circuits, modules, units, etc., should be understood as "electrical connection," "communication connection," etc. It should be understood that although the terms first, second, third, etc., may be used to describe various components, parts, areas, layers, and / or portions, these components, parts, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one component, part, area, layer, or portion from another component, part, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer or portion discussed below may be represented as a second element, component, region, layer or portion.
[0015] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0016] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be understood that “at least one” means one or more, and “a plurality” means two or more. “At least a portion of an element” means part or all of an element. It should also be understood that the terms “compose” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0017] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.
[0018] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, and P- type represents lightly doped P-type; N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type. The device is divided into emitter region, source region, channel region, drift region, and collector region.
[0019] A silicon-on-insulator-on-insulator (SiI-O) lateral insulated-gate bipolar transistor (BIP) includes: a P-type substrate 101, on which a silicon dioxide buried layer 102, an N-type epitaxial layer 103, a gate oxide layer 204, and a dielectric layer 205 are sequentially disposed; a P-type well region 104 and an N-type buffer region 108 are disposed within the N-type epitaxial layer 103; a P-type emitter region 105 and an N-type emitter region 106 are disposed within the P-type well region 104; and a P-type collector region is disposed within the N-type buffer region 108. 107. A gate polysilicon 202 is provided on the gate oxide layer 204. A deep trench 110 filled with silicon dioxide is provided in the N-type buffer zone 108. Shallow trenches 109 filled with silicon dioxide are respectively provided on both sides of the deep trench 110. The deep trench 110 and the shallow trench 109 are located between the P-type well region 104 and the N-type buffer zone 108. The height of the deep trench 110 is greater than the height of the shallow trench 109. The multiple deep trench technology of the present invention significantly reduces the area. The embodiment can further adopt the following optimization measures: The deep trench 110 is filled with polysilicon 111, and the sides and bottom of the polysilicon 111 are covered with silicon dioxide. A slot 112 is formed on the upper surface of the deep trench 110 and the shallow trench 109 respectively, and silicon is filled in the slot 112 to form a low-resistance path for charge carriers when the device is turned on. The deep trench 110 is located at the lateral center of the N-type epitaxial layer 103; the height of the deep trench 110 is 0.7 μm, and the height of the shallow trench 109 is 0.5 μm; the distance from the shallow trench 109 to the deep trench 110 on both sides of the deep trench 110 is 2 μm.
[0020] Emitter metal 201 is connected to the P-type emitter region 105 and the N-type emitter region 106; collector metal 203 is connected to the P-type collector region 107; and the gate polysilicon 202 is covered by the dielectric layer 205.
[0021] More specifically, the N-type emitter region 106 is a heavily doped N-type region, the N-type epitaxial layer 103 is a lightly doped N-type region, and the N-type buffer region 108 is a moderately doped N-type region, with the doping concentration between the N-type emitter region 106 and the N-type epitaxial layer 103; the P-type emitter region 105 and the P-type collector region 107 are heavily doped P-type regions, the P-type substrate 101 is a lightly doped P-type region, and the P-type well region 104 is a moderately doped P-type region, with the doping concentration between the P-type emitter region 105 and the P-type substrate 101.
[0022] In this embodiment, the trench structure inserted within the drift region includes a deep trench 110 filled with polysilicon 111 and a shallow trench 109 without polysilicon. The two shallow trenches 109 without polysilicon are located near the P-type well region 104 and the N-type buffer layer 108, respectively, while the deep trench 110 filled with polysilicon 111 is located at the center of the drift region. During breakdown voltage testing, the sidewall oxide layer of the trench bears the voltage, and the filled polysilicon acts as a vertical field plate, optimizing the electric field distribution and shortening the drift region length. Without the inserted trench structure, the drift region length would need to be significantly increased to achieve the same breakdown voltage.
[0023] In this embodiment, the trench surface is optimized by removing portions of silicon dioxide from both ends of the trench surface and then filling it with silicon. When the device is turned on, some charge carriers (current) can bypass the isolation area of the trench and be guided to the low-resistance path on the device surface for transmission, thus optimizing the current path. If the trench surface is not optimized, i.e., if silicon is not filled into parts of the trench surface, the charge carriers (current) can only be transmitted through the high-resistance path inside the device, reducing the current density.
[0024] The invention will now be further described with reference to the accompanying drawings: This application addresses the problem that traditional SOI-LIGBTs, in order to improve their withstand voltage capability, result in excessively long device drift regions, increased area, and reduced current density. It proposes an SOI-LIGBT device with multiple deep trenches in a "concave-convex" shape.
[0025] Figure 1(a) is a 3D structural schematic diagram of the SOI-LIGBT with multiple deep trenches in a "concave-convex" shape proposed in this application; Figure 1(b) is a 3D structural schematic diagram of the SOI-LIGBT with multiple deep trenches in a "concave-convex" shape proposed in this application. To fully demonstrate the 3D structure of the device proposed in this invention, these schematic diagrams do not show the actual device. Figure 2 The device structure proposed in this invention consists of a gate oxide layer and a dielectric layer. It is fully compatible with the fabrication processes of traditional devices. The most significant innovation of this structure is the insertion of various trench structures of different depths within the drift region, including deep trenches filled with polysilicon and shallow trenches without polysilicon. This optimizes the electric field distribution, shortens the drift region length, thereby reducing the size of the power device and significantly reducing the power stage area of the chip. Simultaneously, the trench surface is optimized by removing part of the silicon dioxide from the trench structure surface and filling it with silicon, optimizing the current path and increasing the current density.
[0026] Figure 2 (a) is a cross-sectional schematic diagram of the SOI-LIGBT with multiple deep trenches in the shape of "concave and convex" as proposed in this application, in which part of the silicon dioxide is removed from the trench surface and silicon is filled. Figure 2 (b) is a cross-sectional schematic diagram of the untreated trench surface of the SOI-LIGBT that uses multiple deep trench technology to significantly reduce the area according to the present invention. Two shallow trenches 109 without polysilicon are close to the P-type well region 104 and the N-type buffer layer 108, respectively, and the deep trench 110 filled with polysilicon 111 is located at the center of the drift region. Figure 2 (c) is a cross-sectional schematic diagram of the polysilicon-filled deep trench of the SOI-LIGBT with multiple deep trenches in the shape of "concave and convex" as proposed in this application. Figure 2 (d) is a cross-sectional schematic diagram of the shallow trench of the SOI-LIGBT with multiple deep trenches in the shape of "concave and convex" as proposed in this application.
[0027] Part of the silicon dioxide is removed from the surface of the deep trench 110 and the shallow trench 109 and filled with silicon.
[0028] Figure 3(a) is a diagram showing the electric field equipotential lines of the SOI-LIGBT with multiple deep trenches inserted in the drift region proposed in this invention during the off-state process. As shown in Figure 3(a), the SOI-LIGBT with multiple deep trenches inserted in the drift region, and the trenches filled with polysilicon as a "field plate," changes the electric field distribution, forcing the electric field equipotential lines to become denser on the oxide sidewalls of the trenches, bearing the main voltage drop. This allows for the use of a shorter drift region under the same off-state withstand voltage. Figure 3(b) is a diagram showing the surface potential distribution of the SOI-LIGBT with multiple deep trenches inserted in the drift region and the SOI-LIGBT with a single trench as a function of the drift region length when subjected to the same voltage in the off-state. As shown in Figure 3(b), the multiple deep trench structure with inserted trenches can withstand a voltage of 308V, while the SOI-LIGBT with a single trench can only withstand a voltage of 17V under the same drift region length. When both devices are subjected to a voltage of 560V, the drift region length of the SOI-LIGBT proposed in this invention is 21.5μm, while the drift region length of a single-trench SOI-LIGBT requires 47μm. The comparison shows that, under the same voltage, the SOI-LIGBT with multiple deep trenches inserted within its drift region proposed in this invention can significantly shorten the drift region length, thereby reducing the size of the power device and substantially reducing the chip power stage area.
Claims
1. A silicon-on-insulator lateral insulated gate bipolar transistor, comprising: A P-type substrate (101) is provided with a silicon dioxide buried layer (102), an N-type epitaxial layer (103), a gate oxide layer (204), and a dielectric layer (205) sequentially thereon. A P-type well region (104) and an N-type buffer region (108) are provided in the N-type epitaxial layer (103). A P-type emitter region (105) and an N-type emitter region (106) are provided in the P-type well region (104). A P-type collector region (107) is provided in the N-type buffer region (108). The gate oxide layer (204) has a gate polysilicon (202) disposed thereon. The feature is that a silicon dioxide-filled deep trench (110) is disposed in an N-type buffer zone (108), and a silicon dioxide-filled shallow trench (109) is disposed on both sides of the deep trench (110). The deep trench (110) and the shallow trench (109) are located between the P-type well region (104) and the N-type buffer zone (108). The height of the deep trench (110) is greater than the height of the shallow trench (109).
2. The silicon-on-insulator lateral insulated gate bipolar transistor according to claim 1, characterized in that, The deep trench (110) is filled with polysilicon (111) and the sides and bottom of the polysilicon (111) are covered with silicon dioxide.
3. The silicon-on-insulator lateral insulated gate bipolar transistor according to claim 1 or 2, characterized in that, A slot (112) is provided on the upper surface of the deep trench (110) and the shallow trench (109), and silicon is filled in the slot (112) to form a low-resistance path for charge carriers when the device is turned on.
4. The silicon-on-insulator lateral insulated gate bipolar transistor according to claim 1, 2, or 3, characterized in that, The deep trench (110) is located at the transverse center of the N-type epitaxial layer (103).
5. The silicon-on-insulator lateral insulated gate bipolar transistor according to claim 4, characterized in that, The height of the deep trench (110) is 0.7 μm, and the height of the shallow trench (109) is 0.5 μm.
6. The silicon-on-insulator lateral insulated gate bipolar transistor according to claim 5, characterized in that, The distance from the shallow trench (109) on both sides of the deep trench (110) to the deep trench (110) is 2 μm.