A low-conduction-loss lateral superjunction IGBT device and its fabrication method

Abstract

This invention discloses a low-conduction-loss lateral superjunction IGBT device and its fabrication method. The lateral superjunction IGBT device includes: an SOI wafer comprising a P-type substrate, a buried oxide layer, and a P-type drift layer; an N-hole region penetrating the buried oxide layer and filled with highly doped N-type silicon, the N-hole region and the P-type substrate forming a reverse-biased PN junction; an N-type drift layer formed on the P-type drift layer; an N-type buffer layer and a P-type drift layer. + The collector region is formed on the upper part of one side of the N-type drift layer; the P-type base region, P + Contact area and N + The emitter region is formed on the upper part of the N-type drift layer on the other side; the gate stack is formed above the channel region. When the device is turned on, the N-hole region and the P-type substrate block holes and electrons respectively, preventing carrier loss; when the device is turned off, when the collector voltage rises to a certain value, the reverse-biased PN junction bears a large reverse bias voltage, realizing the punch-through between the P-type drift layer and the P-type substrate, reducing turn-off loss.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit power device technology, specifically relating to a low-conduction-loss lateral superjunction IGBT device and its fabrication method. Background Technology

[0002] Lateral insulated-gate bipolar transistors (SOI-LIGBTs) based on silicon-on-insulator (SiI) technology have become highly sought-after devices in the field of high-voltage integrated circuits due to their low conduction losses, high input impedance, and fast switching capabilities. These characteristics make them suitable for applications such as power management, display drivers, and monolithic high-voltage integrated circuits. Despite their significant advantages, the physical characteristics of SOI-LIGBTs are much more complex than those of bulk silicon devices, mainly due to the presence of the buried oxide layer and the resulting floating body effect.

[0003] In LIGBT device research, optimizing the trade-off between conduction and turn-off losses is a key challenge in achieving high-performance power conversion. This balance directly affects the overall efficiency and reliability of the system, and therefore has become the core focus of current research.

[0004] Existing research primarily focuses on optimizing breakdown, conduction, or switching performance through structural improvements such as field plates, shielded base layers, and various RESURF-derived configurations. While these methods are effective, they often involve complex manufacturing processes. Among these, superjunction structures and their improved forms have garnered significant attention because they overcome the "silicon limit" inherent in traditional power devices, which restricts the breakdown voltage from the on-resistance.

[0005] Partial silicon-on-insulator (PSI) structures have been extensively studied in LDMOS, but since LIGBTs are bipolar conductive devices, directly introducing PSI will cause carrier loss and increased conduction losses during conduction. Summary of the Invention

[0006] To address the aforementioned problems, this invention discloses a low-conduction-loss lateral superjunction IGBT device, comprising: an SOI wafer including a P-type substrate, a buried oxide layer, and a P-type drift layer; an N-hole region penetrating the buried oxide layer and filled with highly doped N-type silicon, the N-hole region and the P-type substrate forming a reverse-biased PN junction; an N-type drift layer formed on the P-type drift layer; and an N-type buffer layer formed on the upper part of one side of the N-type drift layer. + A current collector region is formed on the upper part of the N-type buffer layer; a P-type base region is formed on the upper part of the other side of the N-type drift layer. + Contact area and N + The emission regions are formed adjacent to each other on the upper part of the P-type base region;

[0007] A gate stack is formed above the channel region, covering N. +Emitter region; when the device is turned on, the N-hole region and the P-type substrate block holes and electrons respectively to prevent carrier loss; when the device is turned off, when the collector voltage rises to a certain value, the reverse-biased PN junction bears a large reverse bias voltage, and its depletion layer continuously expands to both sides, realizing the penetration between the P-type drift layer and the P-type substrate, forming a hole channel to quickly export the holes stored in the drift region and reduce turn-off loss.

[0008] In the low-conduction-loss lateral superjunction IGBT device of the present invention, preferably, the doping concentration of the N-hole region is 5E15~1E17 cm⁻¹. -3 .

[0009] In the low conduction loss lateral superjunction IGBT device of the present invention, preferably, the doping concentration of the P-type substrate is 5E15~1E17 cm⁻¹. -3 .

[0010] This invention also discloses a method for fabricating a low-conduction-loss lateral superjunction IGBT device, comprising the following steps: forming an N-hole region in a buried oxide layer of an SOI wafer, wherein the SOI wafer includes a P-type substrate, a buried oxide layer, and a P-type drift layer; the N-hole region and the P-type substrate form a reverse-biased PN junction; forming an N-type drift layer on the P-type drift layer; performing ion implantation to form an N-type buffer layer on the upper part of one side of the N-type drift layer, and forming a P-type buffer layer on the upper part of the N-type buffer layer. + Collector region; perform ion implantation to form a P-type base region on the upper part of the other side of the N-type drift layer, and form adjacent P-type base regions on the upper part of the P-type base region. + Contact area and N + The emitter region is formed above the channel region with a gate stack. When the device is turned on, the N-hole region and the P-type substrate block holes and electrons respectively to prevent carrier loss. When the device is turned off, when the collector voltage rises to a certain value, the reverse-biased PN junction bears a large reverse bias voltage, and its depletion layer continues to expand to both sides, realizing the penetration between the P-type drift layer and the P-type substrate, forming a hole channel to quickly export the holes stored in the drift region and reduce turn-off loss.

[0011] In the method for fabricating a low-conduction-loss lateral superjunction IGBT device of the present invention, the preferred step of forming an N-hole region in the buried oxide layer of an SOI wafer includes: directional etching of the P-type substrate and the buried oxide layer of the SOI wafer, with the etching stopping at the P-type drift layer to form a hole; growing highly doped N-type silicon in the formed hole to form an N-hole region; and epitaxially growing P-type silicon to complete the P-type substrate.

[0012] In the method for fabricating a low-conduction-loss lateral superjunction IGBT device of the present invention, the preferred step of forming an N-hole region in the buried oxide layer of an SOI wafer includes: directional etching of the P-type drift layer and the buried oxide layer of the SOI wafer, with the etching stopping at the P-type substrate to form a hole; growing highly doped N-type silicon in the formed hole to form an N-hole region; and epitaxially growing a P-type drift layer.

[0013] In the method for fabricating a low-conduction-loss lateral superjunction IGBT device of the present invention, preferably, before the step of forming the N-type drift layer, the method further includes the following steps: annealing to repair the interface, wherein the annealing temperature is 400℃~700℃ and the time is 500min~700min.

[0014] In the method for fabricating a low-conduction-loss lateral superjunction IGBT device of the present invention, preferably, the doping concentration of the N-hole region is 5E15~1E17 cm⁻¹. -3 .

[0015] In the method for fabricating a low-conduction-loss lateral superjunction IGBT device of the present invention, preferably, the doping concentration of the P-type substrate is 5E15~1E17 cm⁻¹. -3 .

[0016] In the method for fabricating a low-conduction-loss lateral superjunction IGBT device of the present invention, preferably, during ion implantation to form P + Contact area and N + Following the emitter step, a two-step annealing process is included to fully activate the dopant and repair damage. The process involves rapid high-temperature annealing at 900-1300°C for 2-20 μs and low-temperature slow annealing at 300-400°C for 20-40 min. Attached Figure Description

[0017] Figure 1 This is a flowchart of a method for fabricating a low-conduction-loss lateral superjunction IGBT device.

[0018] Figures 2-8 This is a schematic diagram of the structure of each stage in the fabrication method of a low-conduction-loss lateral superjunction IGBT device.

[0019] Figure 9a and Figure 9b This describes the working principle of a low-conduction-loss lateral superjunction IGBT device. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining this invention and are not intended to limit this invention. The described embodiments are merely some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0021] In the description of this invention, it should be noted that the terms "upper," "lower," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0022] Furthermore, many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the device, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without adhering to these specific details. Unless specifically indicated below, various parts of the device may be made of materials known to those skilled in the art, or may employ materials with similar functionality developed in the future.

[0023] This invention is fully compatible with the existing SJ-LIGBT process, requiring only one additional photolithography step and two additional epitaxial steps. The following embodiments only list the additional process flow.

[0024] Figure 1 This is a process flow diagram for fabricating low-conduction-loss lateral superjunction IGBT devices. (Example) Figure 1 As shown, the fabrication process of a low-conduction-loss lateral superjunction IGBT device includes the following steps: Step S1: Prepare an SOI wafer with a structure comprising: a P-type substrate 100, a buried oxide layer (BOX) 101, and a P-type drift layer 102. The doping concentration of the P-type drift layer ranges from 1e¹⁴ to 3e¹⁵ cm⁻¹. -3 The thickness ranges from 2 to 8 μm. A mask 103 is formed on the back side of the P-type substrate 100, exposing only the central region of the P-type substrate 100, resulting in the structure shown below. Figure 2 As shown.

[0025] Step S2: Under mask 103, directional etching is performed on the P-type substrate 100 and the buried oxide layer 101 respectively. The etching stops at the P-type drift layer 102 to form a hole. The resulting structure is as shown in Figure 102. Figure 3 As shown.

[0026] Step S3: Using epitaxial or deposition processes, highly doped N-type silicon is grown in the formed holes to form N-hole regions 104. The doping concentration of the N-hole regions is 5E15~1E17 cm⁻¹. -3 P-type silicon was epitaxially grown, and a 100-inch P-type substrate was completed, resulting in the structure shown below. Figure 4 As shown. The N-hole region 104 and the P-type substrate 100 form a reverse-biased PN junction J1.

[0027] In another embodiment, the P-type drift layer 102 and the buried oxide layer 101 may also be etched, with the etching stopping at the P-type substrate 100 to form a hole. After the hole is filled, the P-type drift layer 102 is epitaxially completed.

[0028] Step S4: Annealing to repair the interface, with an annealing temperature of 400℃~700℃ and a time of 500min~700min. In some embodiments, this step can also be performed together with the subsequent anodic doping annealing, without the need for an additional annealing step.

[0029] Step S5: A bottom electrode 105 is formed on the back side of the P-type substrate 100 and grounded, resulting in the structure shown below. Figure 5 As shown.

[0030] Step S6: An N-type drift layer 106 is epitaxially formed on the P-type drift layer 102, resulting in the structure shown below. Figure 6 As shown. In superjunction devices, the doping concentration and thickness of the N-drift layer and the P-drift layer should be matched, with their doping concentration ranges both being 1e¹⁴~3e¹⁵ cm⁻¹. -3 The thickness range is 2~8μm.

[0031] Step S7, an N-type buffer layer 107 and a P-type buffer layer are formed through multiple ion implantations. + Collector region 108, and P-type base region 109 on the emitter side, P + Contact area 110 and N + Launch area 111, the resulting structure is as follows Figure 7 As shown.

[0032] The ion implantation dose range for the N-type buffer layer is 1E13~1e14 cm⁻¹. -2 The injection energy range is 200~800 keV. + The ion implantation dose range in the collector region is 1E14~1e15 cm⁻¹ -2The injection energy range is 30–50 keV. The injection dose range for the P-type base region is 1E13–1E14 cm⁻¹. -2 The injection energy range is 60~100 keV. + The injection dose range in the contact area is: 1E15~1e16 cm. -2 The implantation energy range was 30~50 keV; the implanted impurity was BF2. + The injection dose range in the emission zone is 3E15~3e16 cm. -2 The implantation energy range is 100~200 keV; the implanted impurity is As.

[0033] Step S8 involves a two-step annealing process: a rapid high-temperature annealing followed by a slow low-temperature annealing, to fully activate the anolyte doping and repair damage. The first rapid high-temperature annealing is performed at 900–1300°C for 2–20 μs. The second slow low-temperature annealing is performed at 300–400°C for 20–40 min.

[0034] Step S9 involves forming an isolation structure to achieve electrical isolation of the active region. For example, a bird's beak-shaped field oxide is formed on the N-type drift layer 106 using a localized silicon oxide (LOCOS) process as the isolation structure. The field oxide is approximately 2-4 μm thick and acts as a lateral field plate to improve the breakdown voltage. Alternatively, a shallow trench isolation structure can also be used.

[0035] Step S10: A gate stack is formed over the N-type drift layer 106 and the P-type base region 109. In a specific example, such as... Figure 8 As shown, the gate stack includes a gate oxide layer 113 and a polysilicon gate 114. The formation steps specifically include: A silicon dioxide layer is anisotropically deposited as the gate oxide layer under the mask in the channel region, with a thickness ranging from 80 to 120 nm. Silicon dioxide is then etched under the mask to deposit a polysilicon gate 114, with a polysilicon doping concentration ranging from 1e20 to 5e20 cm⁻¹. -3 The polysilicon gate is encapsulated by isotropically deposited silicon dioxide under the mask in the trench region, with a deposition thickness ranging from 0.3 to 0.5 μm; then it is annealed for repair at a temperature of 800 to 1100 °C for 20 to 40 min.

[0036] Step S11, at P + Collector metal is formed above collector region 108, in P + Contact areas 110 and N + Emitter metal is formed above emitter region 111, and gate electrode metal is formed above gate stack through contact holes, realizing the electrode lead-out and electrical connection of collector, emitter and gate.

[0037] like Figure 8 As shown, the low-conduction-loss lateral superjunction IGBT device includes: an SOI wafer, including a P-type substrate 100 and a buried oxide layer 101; an N-hole region penetrating the buried oxide layer 101 and filled with highly doped N-type silicon; a P-type drift layer 102 formed on the buried oxide layer 101; an N-type drift layer 106 formed on the P-type drift layer 102; and an N-type buffer layer 107 formed on the upper part of one side of the N-type drift layer 106; P + A collector region 108 is formed on the upper part of the N-type buffer layer 107; a P-type base region 109 is formed on the upper part of the other side of the N-type drift layer 106. + Contact area 110 and N + Emitter regions 111 are formed adjacent to each other on the upper part of the P-type base region 109; gate stacks are formed above the channel region.

[0038] Figure 9a and Figure 9b The diagram illustrates the working principle of a low-conduction-loss lateral superjunction IGBT device: blocking charge carriers in the on-state and extracting holes during the turn-off process. During the turn-off process, due to the increased positive voltage at the collector, electron current is conducted on the upper surface, while hole current dominates on the lower surface near the buried oxide layer.

[0039] When conduction occurs, the highly doped N-pore region and the P-type substrate block holes and electrons respectively, preventing carrier loss. At this time, the collector voltage V... C The depletion layer of the reverse-biased PN junction J1 is very narrow, insufficient to form a punch-through.

[0040] When turned off, V C The high-voltage reverse-biased PN junction J1 bears a large reverse bias voltage, and its depletion layer continuously extends to both sides, eventually achieving penetration between the P-type drift layer and the P-type substrate. This forms a hole channel to quickly export the holes stored in the drift region, thus reducing turn-off loss (E0). off The effect of ).

[0041] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A low-conduction-loss lateral superjunction IGBT device, characterized in that, include: SOI wafers include a P-type substrate, a buried oxide layer, and a P-type drift layer; The N-pore region penetrates the buried oxide layer and is filled with highly doped N-type silicon. The N-pore region and the P-type substrate form a reverse-biased PN junction. N-type drift layers are formed on top of P-type drift layers; An N-type buffer layer is formed on the upper part of one side of the N-type drift layer, P + A collector region is formed on the upper part of the N-type buffer layer; The P-type base region is formed on the upper part of the opposite side of the N-type drift layer. + Contact area and N + The emission regions are formed adjacent to each other on the upper part of the P-type base region; A gate stack is formed above the channel region; When the device is turned on, the N-hole region and the P-type substrate block holes and electrons respectively to prevent carrier loss. When the device is turned off, when the collector voltage rises to a certain value, the reverse-biased PN junction bears a large reverse bias voltage, and its depletion layer continues to expand to both sides, realizing the penetration between the P-type drift layer and the P-type substrate, forming a hole channel to quickly export the holes stored in the drift region and reduce turn-off loss.

2. The low conduction loss lateral superjunction IGBT device according to claim 1, characterized in that, The doping concentration of the N-pore region is 5E15~1E17 cm⁻¹ -3 .

3. The low conduction loss lateral superjunction IGBT device according to claim 1, characterized in that, The doping concentration of the P-type substrate is 5E15~1E17 cm⁻¹. -3 .

4. A method for fabricating a low-conduction-loss lateral superjunction IGBT device, characterized in that, Includes the following steps: An N-hole region is formed in the buried oxide layer of an SOI wafer, wherein the SOI wafer includes a P-type substrate, a buried oxide layer, and a P-type drift layer; the N-hole region and the P-type substrate form a reverse-biased PN junction; An N-type drift layer is formed on the P-type drift layer; Ion implantation is performed to form an N-type buffer layer on the upper part of one side of the N-type drift layer, and a P-type buffer layer is formed on the upper part of the N-type buffer layer. + Collection area; Ion implantation is performed to form a P-type base region on the upper part of the other side of the N-type drift layer, and adjacent P-type base regions are formed on the upper part of the P-type base region. + Contact area and N + Launch area; A gate stack is formed above the channel region; in, When the device is turned on, the N-hole region and the P-type substrate block holes and electrons respectively to prevent carrier loss. When the device is turned off, when the collector voltage rises to a certain value, the reverse-biased PN junction bears a large reverse bias voltage, and its depletion layer continues to expand to both sides, realizing the penetration between the P-type drift layer and the P-type substrate, forming a hole channel to quickly export the holes stored in the drift region and reduce turn-off loss.

5. The method for fabricating a low-conduction-loss lateral superjunction IGBT device according to claim 4, characterized in that, The steps for forming N-pore regions in the buried oxide layer of an SOI wafer include: The P-type substrate and buried oxide layer of the SOI wafer are oriented and etched, and the etching stops at the P-type drift layer to form a hole; Highly doped N-type silicon is grown in the formed pores to form N-pore regions; Epitaxial growth of P-type silicon to complete the P-type substrate.

6. The method for fabricating a low-conduction-loss lateral superjunction IGBT device according to claim 4, characterized in that, The steps for forming N-pore regions in the buried oxide layer of an SOI wafer include: The P-type drift layer and buried oxide layer of the SOI wafer are oriented and etched, with the etching stopping at the P-type substrate to form a hole; Highly doped N-type silicon is grown in the formed pores to form N-pore regions; Epitaxial growth of P-type drift layers.

7. The method for fabricating a low-conduction-loss lateral superjunction IGBT device according to claim 4, characterized in that, Before the formation of the N-type drift layer, the following steps are also included: Annealing is performed to repair the interface at a temperature of 400℃~700℃ for 500min~700min.

8. The method for fabricating a low-conduction-loss lateral superjunction IGBT device according to claim 4, characterized in that, The doping concentration of the N-pore region is 5E15~1E17 cm⁻¹ -3 .

9. The method for fabricating a low-conduction-loss lateral superjunction IGBT device according to claim 4, characterized in that, The doping concentration of the P-type substrate is 5E15~1E17 cm⁻¹. -3 .

10. The method for fabricating a low-conduction-loss lateral superjunction IGBT device according to claim 4, characterized in that, P formed by ion implantation + Contact area and N + Following the launch area steps, the following also includes: A two-step annealing process is used to fully activate the dopant and repair damage, in which... Rapid high-temperature annealing, with an annealing temperature of 900~1300℃ and an annealing time of 2~20μs; Low-temperature slow annealing, with an annealing temperature of 300~400℃ and an annealing time of 20~40min.

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