Methods for improving gate resistance uniformity in narrow pitch IGBTs and IGBT devices

Abstract

This invention discloses a method for improving the gate resistance uniformity of narrow-pitch IGBTs. The method involves fabricating the polysilicon gate of the IGBT, including a polysilicon deposition step, a polysilicon etch-back step, and a polysilicon deposition annealing step. A super-scan phosphorus implantation step is added between the polysilicon etch-back step and the polysilicon deposition annealing step. This super-scan phosphorus implantation step performs regional phosphorus compensation implantation on the center and edge regions of the wafer based on a typical map obtained from wafer VF testing. By adjusting the implantation speed at the center and edge of the wafer, the uneven phosphorus doping concentration in the polysilicon of the center and edge regions is compensated. This invention can significantly improve the on-chip uniformity of the gate resistance, reducing the resistance dispersion to less than ±10%, thereby reducing Eon fluctuations and parallel temperature rise differences.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a method for improving the gate resistance uniformity of narrow-pitch IGBTs; and an IGBT device fabricated using the method for improving the gate resistance uniformity of narrow-pitch IGBTs. Background Technology

[0002] IGBT devices typically have a gate resistor Rg connected in series at the gate to suppress gate oscillations and improve uneven current distribution when used in parallel.

[0003] Existing narrow-pitch (≤1.6um) IGBTs use polycrystalline silicon chemical mechanical polishing (PolyCMP) technology, which retains only the strip-shaped polycrystalline silicon resistors inside the trench. Its temperature coefficient is close to 0, and its resistance at 150℃ is about 1.16 times that at room temperature.

[0004] The resistance range of the gate resistor Rg directly affects the IGBT's turn-on energy (Eon): when Rg is discrete within ±20% of the mean, Eon fluctuates by ±14%; IGBTs with different Rg distributions, when packaged in parallel, exhibit significant differences in temperature rise, with the actual operating junction temperature differing by up to 7℃. To ensure consistency between Eon and temperature rise, the customer requires that the Rg range be controlled within ±20%.

[0005] In existing technologies, the morphology, linewidth / depth / angle of the trenches on the wafer surface are generally consistent. However, the large range of Rg is mainly attributed to the polysilicon deposition process: the reaction atmosphere distribution in the polysilicon deposition furnace is uneven, and the PH3 gas concentration in the center of the wafer is lower than that in the edge region. This results in a lower polysilicon doping concentration and a higher gate resistance Rg in the center of the wafer, while a higher polysilicon doping concentration and a lower gate resistance Rg at the edge of the wafer. Ultimately, this leads to poor on-wafer Rg consistency, with resistance values ​​varying by more than ±20%, which fails to meet customer requirements. Summary of the Invention

[0006] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0007] To address the problems of uneven polysilicon phosphorus doping concentration between the wafer center and edge, poor on-chip gate resistance Rg consistency, and resistance value dispersion exceeding ±20% caused by the polysilicon deposition process in existing narrow-pitch IGBTs, which in turn leads to large Eon fluctuations and significant differences in parallel temperature rise, this invention provides a method and IGBT device that can significantly improve the on-chip gate resistance consistency and meet customer control requirements for narrow-pitch IGBTs.

[0008] To solve the above technical problems, the present invention provides a method for improving the gate resistance uniformity of narrow pitch IGBTs. The method for preparing the polysilicon gate of the IGBT includes a polysilicon deposition step, a polysilicon etch-back step, and a polysilicon deposition annealing step performed sequentially. A super-scanning phosphorus implantation step is added between the polysilicon etch-back step and the polysilicon deposition annealing step. The super-scan phosphorus implantation step performs regional phosphorus compensation implantation on the central and edge regions of the wafer based on the typical map of the wafer VF test. By adjusting the implantation speed at the center and edge of the wafer, the uneven phosphorus doping concentration in the polysilicon of the center and edge regions of the wafer is compensated, and the range of gate resistance Rg is optimized.

[0009] Optionally, the method for improving the gate resistance consistency of narrow pitch IGBTs can be further improved, wherein the IGBT has a pitch ≤ 1.6µm.

[0010] Optionally, the method for improving the gate resistance consistency of narrow pitch IGBTs can be further improved by wherein, in the super-scanning phosphorus implantation step, the phosphorus implantation rate in the center region of the wafer is slower than that in the edge region, so that the phosphorus concentration in the polysilicon increases in a ring shape from the center to the edge.

[0011] Optionally, the method for improving the gate resistance consistency of narrow-pitch IGBTs can be further improved by employing a single-pitch process in the polysilicon deposition step.

[0012] Optionally, the method for improving the gate resistance consistency of narrow pitch IGBTs can be further improved, and after the super-scan phosphorus implantation step, the on-chip consistency of the gate resistance Rg is controlled within ±10%.

[0013] Optionally, the method for improving the gate resistance uniformity of narrow-pitch IGBTs can be further improved by using a super-scan phosphorus implantation dose of 2.0E16–3.0E16 atoms / cm². Optionally, the method for improving the gate resistance consistency of narrow pitch IGBTs can be further improved by using a super-scan phosphorus implantation dose of 2.33E16.

[0014] The present invention provides a narrow pitch IGBT device, wherein the polysilicon gate is prepared by any one of the methods described above for improving the gate resistance uniformity of narrow pitch IGBTs.

[0015] The working principle of the present invention is explained below based on the above scheme; This invention addresses the distribution characteristics of low phosphorus concentration and high Rg at the center of the wafer and high phosphorus concentration and low Rg at the edge caused by polysilicon deposition. After polysilicon etch-back, regional super-scan phosphorus implantation is added. Phosphorus concentration compensation is achieved through slow implantation at the center and fast implantation at the edge, so as to homogenize the polysilicon doping of the entire wafer and reduce the intra-wafer fluctuation range of gate resistor Rg.

[0016] Based on the above scheme and working principle, the present invention can achieve at least the following technical effects compared with the prior art; (1) Existing technologies cannot compensate for uneven polysilicon deposition doping through subsequent implantation. Existing technologies have an on-chip uniformity of gate resistor Rg > ±20%.

[0017] This invention can specifically correct the concentration difference between the center and the edge, and optimize the on-chip uniformity of the gate resistance Rg to within ±10% through regional compensation injection, meeting the stringent requirement of customers for a gate resistance Rg range of <20%, and achieving a significant improvement in gate resistance uniformity. (2) Existing technologies cannot achieve small-range Eon control due to large fluctuations in gate resistance Rg.

[0018] This invention reduces the gate resistance Rg fluctuation from ±20% to ±10% through regional compensation injection, corresponding to narrowing the Eon fluctuation from ±14% to within ±5%, significantly reducing the turn-on energy fluctuation and improving the consistency of device switching performance.

[0019] (3) Existing technologies cannot eliminate the parallel temperature rise difference due to the center-edge gradient distribution of the gate resistance Rg.

[0020] This invention achieves uniform distribution of gate resistance Rg through regional compensation injection, reducing the junction temperature difference of IGBTs after parallel packaging from 7°C to less than 1°C, improving the uniformity of parallel temperature rise, and enhancing the long-term reliability of the device.

[0021] (4) After adopting the regional compensation injection process provided by the present invention, the device yield is improved to over 90%, and the mass production stability is better than the baseline process without compensation injection. Attached Figure Description

[0022] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0023] Figure 1 Improved gate resistance Rgmap distribution Figure 2 Improved gate resistance Rgmap distribution Figure 3 Schematic diagram showing the relationship between phosphorus implantation rate, concentration, and resistance at the wafer center and edge. Figure 4 Comparison of Rg range under different super-scan injection doses Explanation of reference numerals in the attached figures: Rg - gate resistor, Poly - polysilicon, Trench - trench, Super scan - super scan injection. Detailed Implementation

[0024] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements.

[0025] First embodiment; The general manufacturing process of IGBTs is divided into chip manufacturing and packaging. This invention mainly relates to the chip manufacturing process.

[0026] IGBT chip manufacturing (front-end FAB) mainly includes the following steps: 1. Provide wafer substrates, high-purity single-crystal silicon wafers (N-type heavily doped substrates), polishing → cleaning → RCA cleaning to ensure atomically clean surfaces; 2. Epitaxy: An epitaxial layer with N⁻ drift region is grown on the substrate. The thickness and doping concentration are precisely controlled, which determines the breakdown voltage and on-resistance. 3. Field isolation (LOCOS / STI): Oxidation → Photolithography → Etching, forming the boundary between the active region and the isolation region; 4. Trench process (mainstream trench gate IGBT): Photolithography → dry etching to form gate trenches, with strict control over trench depth, CD, and cone angle; 5. Gate oxide layer growth: High-temperature thermal oxidation growth of gate oxide SiO2 determines gate insulation, threshold voltage, and reliability. 6. Polysilicon gate fabrication: LPCVD deposition of polysilicon → doping → photolithography → etching to form the gate electrode. Narrow pitch processes are often combined with CMP to grind the surface of the polysilicon.

[0027] 7. P-well / P-base implantation: Ion implantation (B) forms a P-type base region, and high-temperature annealing activates impurities and repairs lattice damage. 8. Emitter implantation (N⁺) and ion implantation (P / As) form the N⁺ emitter region, which together with the P base region constitutes the MOS channel. 9. Dielectric layer and contact holes: CVD deposition of ILD layer → photolithography → etching of contact holes to expose emitter region, base region and gate lead-out region; 10. Front-side metallization (Emitter): sputtering Al / AlCu alloy → photolithography → etching → alloy annealing to form the emitter electrode and gate pad; 11. Backside process (determines turn-off performance): wafer thinning (grinding + polishing), backside implantation: N⁺ field stop layer (FS) + P⁺ collector region, backside metallization: deposition of collector metal layer; 12. Passivation, testing, dicing, and deposition of passivation protective layer (SiO2 / SiN) x Wafer-level electrical testing (VF, Vth, leakage current, etc.), laser scribing → wafer cleaving → single IGBT chip.

[0028] This invention mainly relates to improvements in the sixth step of polysilicon gate fabrication.

[0029] This invention provides a method for improving the gate resistance uniformity of narrow-pitch IGBTs. The method for fabricating the polysilicon gate of the IGBT includes a polysilicon deposition step, a polysilicon etch-back step, and a polysilicon deposition annealing step performed sequentially. The method is characterized by: A super-scanning phosphorus implantation step is added between the polysilicon etch-back step and the polysilicon deposition annealing step. The super-scanning phosphorus implantation step performs regional phosphorus compensation implantation on the central and edge regions of the wafer based on the typical map of the wafer VF test. By adjusting the implantation speed at the center and edge of the wafer, the uneven phosphorus doping concentration in the polysilicon of the center and edge regions of the wafer is compensated.

[0030] For example, in the example above: Polycrystalline silicon deposition: Polycrystalline silicon deposition is performed using a single pitch. Due to the difference in atmosphere inside the furnace, the PH3 concentration in the center of the wafer is lower than that at the edge, resulting in a distribution with high Rg in the center and low Rg at the edge.

[0031] Poly Etch Back: Completes the removal of polysilicon outside the trench, retaining only the strip-shaped polysilicon structure inside the trench.

[0032] Super scan phosphorus implantation: Based on the typical map of wafer VF test, regional compensation implantation is performed on the center and edge of the wafer; the phosphorus implantation speed is slow in the center region and fast in the edge region, which compensates for the insufficient phosphorus concentration in the center region, reduces the uniformity of Rg in the center and improves the uniformity of Rg at the edge.

[0033] Polysilicon deposition anneal: activates doped ions and stabilizes the resistance of polysilicon.

[0034] Through the above process, the intra-chip consistency of Rg was optimized from baseline > ±20% to within ±10%, and the yield was >90%.

[0035] Alternatively, a comparison of different injection doses in the above embodiments can be made: Keeping other processes unchanged, the super-scan phosphorus injection dose is adjusted accordingly: Baseline: Single pitch + no injection, Rg range > ±20% Option 1: Single pitch + 1.40E16 injection dose, Rg range within ±15%.

[0036] Option 2: Single pitch + 2.33E16 injection dose, Rg range within ±10%.

[0037] Option 3: Single pitch + 3.50E16 injection dose, Rg range within ±10%.

[0038] The optimal injection dose was 2.33E16, and the Rg range was stably controlled within ±10%.

[0039] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless explicitly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.

[0040] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A method for improving the gate resistance uniformity of a narrow-pitch IGBT, comprising, during the fabrication of the IGBT polysilicon gate, a polysilicon deposition step, a polysilicon etch-back step, and a polysilicon deposition annealing step performed sequentially, characterized in that: A super-scanning phosphorus implantation step is added between the polysilicon etch-back step and the polysilicon deposition annealing step. The super-scanning phosphorus implantation step performs regional phosphorus compensation implantation on the central and edge regions of the wafer based on the typical map of the wafer VF test. By adjusting the implantation speed at the center and edge of the wafer, the uneven phosphorus doping concentration in the polysilicon of the center and edge regions of the wafer is compensated.

2. The method for improving the gate resistance uniformity of narrow pitch IGBTs according to claim 1, characterized in that: The IGBT has a pitch of ≤1.6µm.

3. The method for improving the gate resistance uniformity of narrow pitch IGBTs according to claim 1, characterized in that: In the super-scanning phosphorus implantation step, the phosphorus implantation rate in the central region of the wafer is slower than that in the edge region, causing the phosphorus concentration in the polycrystalline silicon to increase in a ring shape from the center to the edge.

4. The method for improving the gate resistance uniformity of narrow pitch IGBTs according to claim 1, characterized in that: The polysilicon deposition step employs a single-pitch process.

5. The method for improving the gate resistance uniformity of narrow pitch IGBTs according to claim 1, characterized in that: After the super-scanning phosphorus implantation step, the on-chip consistency of the gate resistor Rg is controlled within ±10%.

6. The method for improving the gate resistance uniformity of narrow pitch IGBTs according to claim 1, characterized in that: The dose of phosphorus injected by the super-scan was 2.0E16 to 3.0E16 atoms / cm².

7. The method for improving the gate resistance uniformity of narrow pitch IGBTs according to claim 6, characterized in that: The dose of phosphorus injected during the super-scan was 2.33E16.

8. A narrow-pitch IGBT device, characterized in that: Its polysilicon gate is prepared by the method for improving the gate resistance uniformity of narrow pitch IGBTs as described in any one of claims 1-7.

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