A method for manufacturing a superjunction device

Abstract

This invention discloses a method for fabricating a superjunction device. After the superjunction structure is fabricated, a thick mask layer (HM) is deposited. Exposure and etching of the HM are performed sequentially using a positive resist + active area photomask (AA Mask) and a negative resist + pillar mask. An oxide layer is then grown, forming a localized thick oxide layer at the top of the window location. The oxide layer is then photolithographically lithographically lithographically applied using the AA Mask to complete the active area windowing. Subsequent steps are consistent with the fabrication steps of conventional superjunction devices. The superjunction structure fabrication method proposed in this invention can create a localized thick oxide layer above the peak electric field position at the top of the superjunction pillar region without adding a photomask, thereby reducing the high electric field distribution within the oxide layer, reducing the mobile charge mobility during device use, and optimizing the device's reliability capabilities such as HTRB and H3TRB.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, specifically a method for manufacturing a superjunction device. Background Technology

[0002] Power semiconductor devices, as core components in power electronic systems, are used in numerous fields including power grid systems, new energy vehicles, power management systems, and consumer electronics. Before the advent of superjunction structures, there was a 2.5-fold dependence between the breakdown voltage and on-resistance of power devices. This relationship was considered the limit achievable by silicon devices for a long time, hence the term "silicon limit." Superjunction devices overcome this "silicon limit" constraint by introducing alternating P-pillars and N-pillars in the drift region. Because superjunction devices require the introduced P-pillars and N-pillars to meet charge balance conditions, in the blocking state, the P-pillars and N-pillars are completely depleted of each other. The longitudinal electric field in the drift region, modulated by the transverse electric field, forms a rectangular, uniformly distributed structure with stronger breakdown voltage. Ideally, the breakdown voltage of a superjunction device depends only on the thickness of the drift region. Therefore, for power devices meeting specific breakdown voltage requirements, superjunction design can significantly reduce the on-resistance of the device by increasing the doping concentration in the drift region.

[0003] In practical power devices, the periodic arrangement of edge cells is disrupted, so the device is divided into an active region and a termination region. The termination region surrounds the active region and extends the electric field laterally to ensure the device's breakdown voltage. However, superjunction power devices generate a high electric field peak at the top of the N-pillar during breakdown voltage testing. If this electric field peak is too high, it will enhance the mobility of mobile charges in the oxide layer, thereby affecting the device's reliability. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing a superjunction structure, comprising the following steps:

[0005] Step 1) Fabricate second conductivity type semiconductor pillars spaced apart on the first conductivity type semiconductor epitaxial layer of the semiconductor device.

[0006] Step 2) Deposit a hard mask layer HM on top.

[0007] Step 3) Expose and etch windows in the hard mask layer HM using positive photoresist and an active area photomask.

[0008] Step 4) Expose and etch the hard mask layer HM using a negative photoresist + pillar area photomask.

[0009] Step 5) Perform thermal oxide layer growth to form a localized thick oxide layer at the top of the HM window location.

[0010] Step 6) Remove the hard mask layer HM, and use positive photoresist and active area photomask to perform photolithography on the oxide layer to complete the windowing of the active area.

[0011] Step 7) Perform subsequent conventional semiconductor device processes.

[0012] Furthermore, the fabrication process for superjunction structures includes deep trenching and multi-step epitaxial processes.

[0013] Furthermore, after the second conductivity type semiconductor pillar is fabricated, photolithographic implantation of the second conductivity type main junction region is performed, or photolithographic implantation of the second conductivity type main junction region is performed simultaneously during the fabrication of the second conductivity type body region.

[0014] Furthermore, the boundary of the active region photomask is located within the range of the main junction region of the second conductivity type.

[0015] Furthermore, the impurity concentration of the epitaxial layer of the first conductivity type is on the order of [1e15cm-3, 1e18cm-3].

[0016] Furthermore, the impurity concentration of the second type of semiconductor pillar is on the order of [1e15cm-3, 1e18cm-3].

[0017] Furthermore, in the source structure, the first type of conductivity semiconductor is doped with a P-type semiconductor, and the second type of conductivity semiconductor is an N-type semiconductor. Alternatively, the first type of conductivity semiconductor is doped with an N-type semiconductor, and the second type of conductivity semiconductor is a P-type semiconductor.

[0018] A superjunction device manufactured using the method described above, wherein a first conductivity type semiconductor epitaxial layer and a second conductivity type semiconductor pillar constitute an alternating arrangement of PN pillars in the superjunction device.

[0019] A second conductivity type body region is provided above the second conductivity type semiconductor pillar in the active region.

[0020] A second conductivity type main junction region is provided above a portion of the second conductivity type semiconductor pillar in the terminal region near the active region.

[0021] Furthermore, superjunction devices are formed in MOSFET devices.

[0022] The technical effects of this invention are undeniable. This invention can create a local thick oxide layer above the peak electric field position at the top of the superjunction pillar region without adding a photomask, thereby reducing the high electric field distribution in the oxide layer, reducing the ability of mobile charges to move during device use, and optimizing the reliability of the device such as HTRB and H3TRB. Attached Figure Description

[0023] Figure 1This is a schematic diagram of a conventional superjunction MOSFET device structure in the background art of this invention.

[0024] Figure 2 This is a schematic diagram of the electric field distribution of the superjunction structure in the background art of this invention.

[0025] Figure 3 This is a key process step in the manufacturing method of a superjunction device according to the present invention.

[0026] Figure 4 This is a schematic diagram of a superjunction MOSFET device structure according to the present invention.

[0027] Figure 5 The key process 01 of this invention is the fabrication of a superjunction structure.

[0028] Figure 6 The key process 02 of this invention is the deposition of a thick mask layer HM.

[0029] Figure 7 The key process 03 of this invention is to use positive resist + active area photomask AA Mask to open windows in HM.

[0030] Figure 8 The key process 04 of this invention is: exposure using negative photoresist and a pillar mask.

[0031] Figure 9 The key process 05 of this invention is: etching HM and removing photoresist.

[0032] Figure 10 The key process 06 of this invention is: growing a thermal oxide layer to form a localized thick oxide layer.

[0033] Figure 11 The key process 07 of this invention is: using AA Mask to perform oxide layer photolithography to define the active region window of the device.

[0034] The markings in the figure are: 1-drain metal layer, 2-drain region of the first conductivity type, 3-epitaxy layer of the first conductivity type, 4-semiconductor pillar of the second conductivity type, 501-body region of the second conductivity type, 502-main junction region of the second conductivity type, 6-source region of the first conductivity type, 7-insulating dielectric layer, 8-polysilicon layer, and 9-top metal layer. Detailed Implementation

[0035] The present invention will be further described below with reference to embodiments, but it should not be construed that the scope of the present invention is limited to the following embodiments. Various substitutions and modifications made based on ordinary technical knowledge and common practices in the art without departing from the above-described technical concept of the present invention should be included within the scope of protection of the present invention.

[0036] Example 1:

[0037] A method for manufacturing a superjunction structure includes the following steps:

[0038] Step 1: Fabricate second conductivity type semiconductor pillars 4 spaced apart on the first conductivity type semiconductor epitaxial layer 3 of the semiconductor device.

[0039] Step 2: Deposit a hard mask layer HM on top.

[0040] Step 3 involves exposing and etching the hard mask layer HM using positive photoresist and an active area photomask.

[0041] Step 3 uses a negative photoresist + pillar area photomask to expose and etch the hard mask layer HM.

[0042] Step 4 involves growing a thermal oxide layer, forming a localized thick oxide layer at the top of the HM window location.

[0043] Step 5: Remove the hard mask layer HM, and use positive photoresist and active area photomask to perform photolithography on the oxide layer to complete the windowing of the active area.

[0044] Step 6 involves subsequent conventional semiconductor device processes (such as gate oxide growth, source / body region implantation, contact hole formation, and metal interconnection).

[0045] Example 2:

[0046] A method for manufacturing a superjunction structure, with the same technical content as in Example 1, further comprising a deep trench and a multi-step epitaxial process.

[0047] Example 3:

[0048] A method for manufacturing a superjunction structure, with the same technical content as any one of Embodiments 1-2, further wherein, after the second conductivity type semiconductor pillar 4 is fabricated, photolithographic implantation of the second conductivity type main junction region 502 is performed, or during the fabrication of the second conductivity type body region 501, photolithographic implantation of the second conductivity type main junction region 502 is performed simultaneously.

[0049] Specifically, the main junction region 502 and the body region 501 can be fabricated together in the subsequent processes of step 7, or 502 can be fabricated after step 1 is completed, and then step 2 and subsequent steps can be performed.

[0050] Example 4:

[0051] A method for manufacturing a superjunction structure, the technical content of which is the same as any one of Examples 1-3, wherein the boundary of the active region photomask is located within the range of the second conductivity type main junction region 502.

[0052] Example 5:

[0053] A method for manufacturing a superjunction structure, the technical content of which is the same as any one of Examples 1-4, wherein the impurity concentration of the first conductivity type epitaxial layer 3 is in the order of [1e15cm-3, 1e18cm-3].

[0054] Example 6:

[0055] A method for manufacturing a superjunction structure, the technical content of which is the same as any one of Examples 1-5, wherein the impurity concentration of the second conductivity type semiconductor pillar 4 is in the order of [1e15cm-3, 1e18cm-3].

[0056] Example 7:

[0057] A method for manufacturing a superjunction structure, with the same technical content as any one of embodiments 1-6, wherein the first type of conductivity semiconductor in the source structure is doped with a P-type semiconductor, and the second type of conductivity semiconductor is an N-type semiconductor. Alternatively, the first type of conductivity semiconductor is doped with an N-type semiconductor, and the second type of conductivity semiconductor is a P-type semiconductor.

[0058] Example 8:

[0059] A superjunction device manufactured using any one of the methods described in Examples 1-7, wherein a first conductivity type semiconductor epitaxial layer 3 and a second conductivity type semiconductor pillar 4 constitute an alternating arrangement of PN pillars in the superjunction device.

[0060] A second conductivity type body region 501 is provided above the second conductivity type semiconductor pillar 4 in the active region.

[0061] Above a portion of the second conductivity type semiconductor pillar 4 near the terminal region of the active region, a second conductivity type main junction region 502 is provided.

[0062] Example 9:

[0063] A superjunction device manufactured using the method described in any one of Examples 1-7, with the same technical content as in Example 8, further wherein the superjunction device is formed in a MOSFET device.

[0064] Example 10:

[0065] A MOSFET device structure with a superjunction includes a drain metal layer 1, a drain region of the first conductivity type 2, an epitaxial layer of the first conductivity type 3, a semiconductor pillar of the second conductivity type 4, a body region of the second conductivity type 501, a main junction region of the second conductivity type 502, a source region of the first conductivity type 6, an insulating dielectric layer 7, a polysilicon layer 8, and a top metal layer 9.

[0066] Drain metal layer 1 is formed on the lower surface of drain region 2 of the first conductivity type.

[0067] The first conductivity type epitaxial layer 3 is formed on the upper surface of the first conductivity type drain region 2.

[0068] The second conductivity type semiconductor pillar 4 is formed within the first conductivity type epitaxial layer 3.

[0069] The second conductivity type semiconductor pillar 4 and the first conductivity type epitaxial layer 3 constitute an alternating PN pillar structure for a superjunction device.

[0070] The second conductivity type body region 501 is formed above the active region second conductivity type semiconductor pillar 4.

[0071] The second conductivity type main junction region 502 is formed above the second conductivity type semiconductor pillar 4 in the terminal region portion near the active region.

[0072] The first conductivity type source region 6 is formed within the second conductivity type body region 501.

[0073] An insulating dielectric layer 7 covers the first conductivity type epitaxial layer 3, the second conductivity type semiconductor pillar 4, the second conductivity type body region 501, the second conductivity type main junction region 502, and the first conductivity type source region 6.

[0074] The polycrystalline silicon layer 8 is formed inside the insulating dielectric layer 7.

[0075] A top metal layer 9 covers the upper surface of the device.

[0076] Example 11:

[0077] A superjunction structure comprises an alternating PN pillar structure of a first conductivity type semiconductor epitaxial layer 3 and a second conductivity type semiconductor pillar 4, forming a superjunction device. A body region 501 is disposed above the active region semiconductor pillar 4, and a main junction region 502 is disposed above a portion of the semiconductor pillar 4 on the side near the terminal region of the active region.

[0078] The material of the device may be selected from any one or a combination of silicon, silicon carbide, gallium nitride, gallium arsenide, indium phosphide, gallium oxide, or germanium silicon.

[0079] Example 12:

[0080] A method for fabricating a superjunction structure, compatible with conventional superjunction device fabrication methods, adds the following key steps:

[0081] (1) After fabricating a superjunction structure on the epitaxial layer by deep trench or multi-step epitaxial process, a hard mask layer (HM) is deposited on top of it.

[0082] (2) Expose and etch windows on HM using positive photoresist + active area photomask (AA Mask);

[0083] (3) Expose and etch the HM using negative photoresist and pillar mask;

[0084] (4) Perform thermal oxide layer growth to form a local thick oxide layer at the top of the HM window position;

[0085] (5) Remove the hard mask layer HM, and use AA Mask to perform photolithography on the oxide layer to complete the windowing of the active region;

[0086] Subsequent device manufacturing processes are consistent with those for conventional superjunction devices.

[0087] Alternatively, after the superjunction structure pillar region 4 is fabricated, the main junction region 502 can be photolithographically implanted, or 501 and 502 can be implanted simultaneously during the subsequent fabrication of the body region 501.

[0088] The boundary of the active area mask is located within the main junction region 502;

[0089] The impurity concentration of the first conductivity type epitaxial layer 3 and the second conductivity type semiconductor pillar 4 is in the order of [1e15cm-3, 1e18cm-3].

[0090] The first type of conductivity semiconductor in the source structure is doped with a P-type semiconductor and the second type of conductivity semiconductor is an N-type semiconductor; or the first type of conductivity semiconductor is doped with an N-type semiconductor and the second type of conductivity semiconductor is a P-type semiconductor.

[0091] like Figure 2 As shown, when the superjunction structure is under voltage withstand, an electric field valley appears at the center of the P-pillar at the top, while an electric field peak appears at the center of the N-pillar. Therefore, in the terminal region, the high peak electric field at the top of the N-pillar can lead to an enhanced ability of mobile charges to move in the oxide layer, thereby affecting the reliability of the device.

[0092] This invention can create a local thick oxide layer above the peak electric field position at the top of the superjunction pillar region without adding a photomask, thereby reducing the high electric field distribution in the oxide layer, reducing the ability of mobile charges to move during device use, and optimizing the reliability of the device such as HTRB and H3TRB.

Claims

1. A method for manufacturing a superjunction structure, characterized in that, Includes the following steps: Step 1) Fabricate second conductivity type semiconductor pillars (4) spaced apart on the first conductivity type semiconductor epitaxial layer (3) of the semiconductor device. Step 2) Deposit a hard mask layer HM on top; Step 3) Expose and etch windows in the hard mask layer HM using positive photoresist and an active area photomask; Step 4) Expose and etch the hard mask layer HM using a negative photoresist + pillar area photomask; Step 5) Perform thermal oxide layer growth to form a localized thick oxide layer at the top of the HM window location; Step 6) Remove the hard mask layer HM, and use positive photoresist and active area photomask to perform photolithography on the oxide layer to complete the windowing of the active area; Step 7) Perform subsequent conventional semiconductor device processes.

2. The method for manufacturing a superjunction structure according to claim 1, characterized in that, The fabrication process for superjunction structures includes deep trench and multi-step epitaxial processes.

3. The method for manufacturing a superjunction structure according to claim 1, characterized in that, After the second conductivity type semiconductor pillar (4) is fabricated, photolithographic implantation of the second conductivity type main junction region (502) is performed, or photolithographic implantation of the second conductivity type main junction region (502) is performed simultaneously during the fabrication of the second conductivity type body region (501).

4. The method for manufacturing a superjunction structure according to claim 1, characterized in that, The boundary of the active region photomask is located within the range of the second conductivity type main junction region (502).

5. The method for manufacturing a superjunction structure according to claim 1, characterized in that, The impurity concentration of the epitaxial layer (3) of the first conductivity type is on the order of [1e15cm-3, 1e18cm-3].

6. The method for manufacturing a superjunction structure according to claim 1, characterized in that, The impurity concentration of the second conductivity type semiconductor pillar (4) is in the order of [1e15cm-3, 1e18cm-3].

7. The method for manufacturing a superjunction structure according to claim 1, characterized in that, The first type of conductivity semiconductor in the source structure is doped with a P-type semiconductor and the second type of conductivity semiconductor is an N-type semiconductor; or the first type of conductivity semiconductor is doped with an N-type semiconductor and the second type of conductivity semiconductor is a P-type semiconductor.

8. A superjunction device manufactured using the method described in any one of claims 1-7, characterized in that: The first conductivity type semiconductor epitaxial layer (3) and the second conductivity type semiconductor pillar (4) constitute the alternating PN pillar structure of the superjunction device; A second conductivity type body region (501) is provided above the second conductivity type semiconductor pillar (4) in the active region; Above a portion of the second conductivity type semiconductor pillar (4) near the terminal region of the active region, a second conductivity type main junction region (502) is provided.

9. The superjunction device according to claim 8, characterized in that: Superjunction devices are formed in MOSFET devices.

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