High-voltage LDMOS device fabrication methods

Abstract

This invention discloses a high-voltage LDMOS device fabrication method. By adjusting the process sequence and advancing the ion implantation process in the drift region, and then utilizing the boron absorption and phosphorus relocation oxidation effect of the high-temperature LOCOS process, phosphorus accumulation is formed at the LOCOS / Si interface. This results in a high doping concentration at the LOCOS / Si interface, with a rapid decrease in doping distribution downwards along the direction deeper into the substrate. This leads to a larger vertical doping gradient in the drift region, improving the N-type drift region resistance of the high-voltage LDMOS device and enhancing the competitiveness of the process platform. The strong LOCOS thermal process creates an excessively thick field plate dielectric layer. By selectively etching to thin the dielectric layer thickness in the LDMOS region, the device performance is further improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing processes, and in particular to a high-voltage LDMOS device manufacturing process. Background Technology

[0002] DMOS (Double-diffused MOS) is widely used in power management circuits due to its high voltage resistance, high current drive capability, and extremely low power consumption. In LDMOS (Lateral Double-Diffused MOS) devices, the breakdown voltage and on-resistance of the device are optimized by injecting 106 ohms into a laterally uniformly distributed drift region behind the field plate dielectric layer; however, this design still has considerable room for improvement.

[0003] Existing LOCOS LDMOS structures, such as Figure 1 As shown, LDMOS is a power device with a double-diffused structure. This technique involves implanting twice into the same source / drain region, with the first implantation having a higher concentration (typical implantation dose 10E15cm). -2 Arsenic (As) was injected in another dose at a lower concentration (typical dose 10E13cm). -2 Boron (B) is implanted and then subjected to a high-temperature propagation process. Because boron diffuses faster than arsenic, it diffuses further laterally below the gate boundary (P-well), forming a channel with a concentration gradient. The channel length is determined by the difference in distance between these two lateral diffusions. To increase the breakdown voltage, a drift region is established between the active and drain regions.

[0004] LOCOS is being used less and less in advanced processes with smaller linewidths due to the bird's beak effect. However, for high-voltage LDMOS devices, the bird's beak effect results in a gradually thicker field plate dielectric layer. In high-voltage LDMOS devices (breakdown voltage BV greater than 80V), the bird's beak effect still has a significant advantage in improving BV and Rsp, and is worth further optimization. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a high-voltage LDMOS device process method.

[0006] The present invention provides a high-voltage LDMOS device manufacturing process, comprising: The first step involves providing a semiconductor material layer of a first conductivity type, forming a drift region of a second conductivity type in the semiconductor material layer; then, an oxide layer and a silicon nitride layer are sequentially formed on the surface of the semiconductor material layer, and the oxide layer and silicon nitride layer are etched downwards to form a window, exposing the surface of the semiconductor material layer within the window; The second step involves performing a strong oxidation process on LOCOS to grow and form a LOCOS isolation dielectric layer on the surface of the semiconductor material layer within the window. The third step involves selectively opening the LDMOS field plate dielectric layer region using photoresist, etching the LOCOS isolation dielectric layer in the LDMOS field plate dielectric layer region, and thinning the thickness of the LOCOS isolation dielectric layer in the field plate dielectric layer region. The fourth step is to perform a thermal oxidation process to form a thermal oxidation layer on the surface of the semiconductor material layer; A polysilicon layer is deposited and etched to form a polysilicon gate; the sidewalls of the polysilicon gate are oxidized. First conductivity type ion implantation and thermal propulsion to form a body region; The fifth step involves depositing a dielectric layer and etching it on both sides of the polysilicon gate to form sidewalls; performing heavy doping implantation of the source and drain to form the source and drain regions; and performing heavy doping implantation of the first conductivity type to form the body region lead-out region. Step 6: Perform metal silicide reaction to form metal silicide; deposit insulating dielectric etching stop layer, deposit interlayer dielectric layer, planarize the interlayer dielectric layer, form contact holes and fill them to form contact leads.

[0007] Furthermore, the semiconductor material layer is a silicon substrate or an epitaxial layer, or a compound semiconductor.

[0008] Furthermore, in the first step, the oxide layer is formed by a thermal oxidation process, and the silicon nitride layer is formed by deposition.

[0009] Furthermore, in the second step, the thickness of the LOCOS isolation dielectric layer is 1500–10000 Å; during the high-temperature thermal process of forming the LOCOS isolation dielectric layer, the injected impurity ions undergo a strong boron adsorption, phosphorus repulsion, and oxidation effect at the interface between the LOCOS isolation dielectric layer and the semiconductor material layer, forming a drift region; after the strong boron adsorption, phosphorus repulsion, and oxidation effect of the LOCOS isolation dielectric layer, phosphorus aggregates are formed at the LOCOS / Si interface, and the doping distribution in the direction deeper into the semiconductor material layer has a higher concentration gradient distribution.

[0010] Furthermore, in the third step, by thinning the LOCOS isolation dielectric layer thickness in the LDMOS region, a different LOCOS isolation dielectric layer thickness is formed from that in the peripheral region, thereby improving the performance of the LDMOS device; The thickness of the thinning is 500–5000 Å.

[0011] Furthermore, the first conductivity type is P-type, and the second conductivity type is N-type; or the opposite conductivity type. The high-voltage LDMOS device fabrication method described in this invention adjusts the process sequence and utilizes the boron absorption and phosphorus removal oxidation effect of the high-temperature LOCOS process to achieve a higher concentration gradient distribution of doping in the drift region. This improves the N-type drift region resistance of the high-voltage LDMOS device and enhances the competitiveness of the process platform. The strong LOCOS thermal process results in an excessively thick field plate dielectric layer. Selective etching to thin the dielectric layer thickness in the LDMOS region further improves device performance. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the cross-sectional structure of an existing LDMOS device.

[0013] Figures 2-7 This is a schematic diagram of the process steps for the LDMOS device of the present invention.

[0014] Figure 8 These are the longitudinal distribution curves of doping concentration in the drift region of LDMOS devices using the process of this invention and existing processes.

[0015] Figure 9 This is a flowchart of the process steps of the present invention.

[0016] 101—P-type substrate / P-type epitaxial layer, 102—LDMOS field plate dielectric layer LOCOS (102-2) / LOCOS isolation (102-2) for other devices, 103—Gate insulating dielectric layer, 104—Gate polysilicon, 106—N-type drift region (LOCOS thickness 1500~10000Å) that has been diffused by the LOCOS thermal process and exhibits boron absorption and phosphorus removal effect at the LOCOS-silicon interface, 107—P-type body region, 108—Sidewall dielectric layer, 109—N-type heavily doped implantation (source / drain region), 110—P-type heavily doped implantation (body region lead-out region), 112—ILD etch stop layer (bottom silicon oxide layer 112-1, top silicon nitride layer 112-2), 114—Interlayer dielectric (ILD), 115—Contact via. Detailed Implementation

[0017] The following detailed description, in conjunction with the accompanying drawings, provides specific embodiments of the present invention and clearly and completely describes the technical solutions of the present invention. However, the present invention is not limited to the following embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise ratios, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] This invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated, and the same reference numerals denote the same elements throughout. In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0019] This invention proposes a novel process method for LDMOS devices. Taking N-LDMOS as an example, the main features of this process method are as follows: 1. Before forming the LOCOS isolation dielectric layer, ion implantation is performed to form the N-type drift region 106; 2. Then, the LOCOS process is performed to form a LOCOS isolation dielectric layer with a thickness (1500-10000 Å) greater than that of the product structure design. The N-type drift region undergoes a strong thermal process during the LOCOS process, resulting in an N-type drift region with boron adsorption and phosphorus repulsion effect at the interface between LOCOS and silicon substrate or epitaxy. 3. The high temperature of the LOCOS process results in a larger vertical distribution gradient of doping in the drift region, leading to a high doping concentration at the LOCOS / Si interface, which then decreases rapidly. 4. The intense thermal process of the LOCOS process results in an excessively thick dielectric layer in the field plate. By selectively etching to thin the dielectric layer thickness in the LDMOS region, the device performance can be further improved.

[0020] Specifically, taking the manufacturing of an NLDMOS device as an example, the process includes the following steps: The first step involves providing a P-type substrate or epitaxial layer, and performing N-type ion implantation (e.g., phosphorus ions) on the P-type substrate or P-type epitaxial layer 101 to form an N-type drift region implantation 106-1. Then, an oxide layer 201 is formed on the substrate or epitaxial layer surface, a silicon nitride layer 202 is deposited, and a window is etched to expose the substrate or epitaxial layer within the window. Figure 2 As shown.

[0021] The second step involves using a high-temperature, high-oxidation process to grow the LOCOS insulating dielectric layer 102-1, forming a layer as shown in the image. Figure 3 As shown. The thickness of the generated LOCOS isolation dielectric layer is 1500–10000 Å, which is greater than the thickness required to form the LDMOS device structure itself, that is, slightly thicker than the device structure design thickness. The ion-implanted drift region 106-1 undergoes a strong boron-absorbing and phosphorus-removing effect at the LOCOS-silicon interface due to oxidation, forming an N-type drift region 106. After the strong boron-absorbing and phosphorus-removing oxidation effect of LOCOS, phosphorus aggregates are formed at the LOCOS / Si interface, and the doping distribution along the tangential direction downwards has a higher concentration gradient distribution (compared to the existing LOCOS process where the drift region process is placed later).

[0022] The third step involves selectively opening the LDMOS field plate dielectric layer formation region, etching the LOCOS isolation dielectric layer 102-1 within the opened window region of the LDMOS region, and thinning the thickness of 102-1 to 102-2, as shown. Figure 4 As shown.

[0023] To utilize the boron absorption and phosphorus repulsion effects of the oxidation process, phosphorus aggregation and a larger concentration gradient distribution are formed at the LOCOS / Si interface. In the second step, an excessive LOCOS isolation dielectric layer is grown, exceeding the device structure design thickness. To further improve device characteristics, a thinning window is defined using photoresist 501. A specialized thinning process is then used to reduce the thickness of the LOCOS isolation dielectric layer in the LDMOS region of the thinning window by 500–5000 Å, resulting in a LOCOS isolation dielectric layer thickness different from the peripheral region.

[0024] The fourth step involves thermal oxidation to form a gate dielectric layer 103 and deposition of a polysilicon layer 104; etching of the polysilicon layer 104 and the gate dielectric layer 103 to form a gate structure; and oxidation of the polysilicon sidewalls of the gate structure, such as... Figure 5 As shown.

[0025] The fifth step involves depositing and etching a dielectric layer to form sidewalls on both sides of the gate structure; performing highly doped implantation to form the source and drain regions; and performing P-type doping to form heavily doped P-type implantation regions, such as... Figure 6 As shown. In this design, a heavily doped N-type region is formed by high-dose N-type ion implantation, serving as the source and drain regions of the LDMOS device. A heavily doped P-type implantation region is formed by P-type ion implantation, serving as the lead-out region of the body region.

[0026] Step 6: Perform a metal silicide reaction to form a metal silicide, deposit an insulating dielectric etch stop layer 112, which comprises two layers: a bottom silicon oxide layer and an upper silicon nitride layer. Deposit an interlayer dielectric layer 114, then perform a CMP process to planarize the surface of the interlayer dielectric layer 114, etch to form contact holes, and fill to form contact leads 115, as shown. Figure 7 As shown. Subsequent processes are the same as traditional CMOS processes and will not be described in detail.

[0027] This invention discloses a method for fabricating an LDMOS device. By adjusting the process sequence, the ion implantation process in the drift region is advanced. Then, utilizing the boron absorption and phosphorus relocation oxidation effect of the high-temperature process of LOCOS, phosphorus accumulation occurs at the LOCOS / Si interface, resulting in a high doping concentration at the LOCOS / Si interface. Furthermore, the doping distribution decreases rapidly downwards along the direction deeper into the substrate, leading to a larger vertical doping gradient in the drift region. Figure 8 As shown, this can improve the N-type drift region resistance of high-voltage LDMOS devices and enhance the competitiveness of the process platform. The strong LOCOS thermal process results in an excessively thick field plate dielectric layer. Selective etching to thin the dielectric layer thickness of the LDMOS region further improves device performance.

[0028] The above are merely preferred embodiments of the present invention and are not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A high-voltage LDMOS device fabrication process, characterized in that: The first step involves providing a semiconductor material layer of a first conductivity type, forming a drift region of a second conductivity type in the semiconductor material layer; then, an oxide layer and a silicon nitride layer are sequentially formed on the surface of the semiconductor material layer, and the oxide layer and silicon nitride layer are etched downwards to form a window, exposing the surface of the semiconductor material layer within the window; The second step involves performing a strong oxidation process on LOCOS to grow and form a LOCOS isolation dielectric layer on the surface of the semiconductor material layer within the window. The third step involves selectively opening the LDMOS field plate dielectric layer region using photoresist, etching the LOCOS isolation dielectric layer in the LDMOS field plate dielectric layer region, and thinning the thickness of the LOCOS isolation dielectric layer in the field plate dielectric layer region. The fourth step is to form a gate dielectric layer on the surface of the semiconductor material layer, and deposit a polysilicon layer on the surface of the gate dielectric layer. The polysilicon layer and the gate dielectric layer are etched to form the gate structure of the LDMOS device; the polysilicon sidewalls of the gate structure are oxidized. First conductivity type ion implantation and thermal propulsion to form a body region; The fifth step involves depositing a dielectric layer and etching it on both sides of the polysilicon gate to form sidewalls; performing heavy doping implantation of the source and drain to form the source and drain regions; and performing heavy doping implantation of the first conductivity type to form the body region lead-out region. The sixth step involves a metal silicide reaction to form metal silicides; An insulating dielectric etching stop layer is deposited, an interlayer dielectric layer is deposited, the interlayer dielectric layer is planarized, a contact hole is formed and filled to form a contact lead-out.

2. The high-voltage LDMOS device process method as described in claim 1, characterized in that: The semiconductor material layer is a silicon substrate or an epitaxial layer, or a compound semiconductor.

3. The high-voltage LDMOS device process method as described in claim 1, characterized in that: In the first step, the oxide layer is formed by a thermal oxidation process, and the silicon nitride layer is formed by deposition.

4. The high-voltage LDMOS device process method as described in claim 1, characterized in that: In the second step, the thickness of the LOCOS isolation dielectric layer is 1500–10000 Å. During the high-temperature thermal process of forming the LOCOS isolation dielectric layer, the injected impurity ions undergo a strong boron adsorption, phosphorus repulsion, and oxidation effect at the interface between the LOCOS isolation dielectric layer and the semiconductor material layer, forming a drift region. After the strong boron adsorption, phosphorus repulsion, and oxidation effect of the LOCOS isolation dielectric layer, phosphorus aggregates are formed at the LOCOS / Si interface, and the doping distribution in the direction of deeper layers of the semiconductor material layer has a higher concentration gradient distribution.

5. The high-voltage LDMOS device process method as described in claim 1, characterized in that: In the third step, by thinning the LOCOS isolation dielectric layer thickness in the LDMOS region, a different LOCOS isolation dielectric layer thickness is formed from the peripheral region, thereby improving the performance of the LDMOS device. The thickness of the thinning is 500–5000 Å.

6. The high-voltage LDMOS device process method as described in claim 1, characterized in that: In the fourth step, the gate dielectric layer is an oxide layer, which is formed by a thermal oxidation process.

7. The high-voltage LDMOS device fabrication method according to any one of claims 1 to 6, characterized in that: The first conductivity type is P-type, and the second conductivity type is N-type; or the conductivity type is the opposite of the above.

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