A method and structure for fabricating a depletion-mode MOSFET to improve VTH uniformity

Abstract

This invention provides a method and structure for fabricating a depletion-type MOSFET that improves VTH uniformity, relating to the field of semiconductor device manufacturing technology. The method involves constructing a sacrificial barrier layer on a semiconductor substrate based on implantation mask data to obtain an implantation opening structure. Self-aligned ion implantation is then performed based on the sacrificial barrier layer and the implantation opening structure to obtain an ion implantation region. The sacrificial barrier layer is then removed to obtain an intermediate processed surface. Threshold-adjusted implantation is performed on the intermediate processed surface based on preset threshold adjustment parameters to obtain a threshold-adjusted implantation region. The sacrificial oxide layer in the threshold-adjusted implantation region is then removed to obtain a final processed surface. Finally, a gate oxide layer covering the ion implantation region is constructed on the final processed surface to obtain a gate dielectric structure. This method enables precise control of the channel length and improves the uniformity of the threshold voltage.

Description

Technical Field

[0001] This invention relates to semiconductor device manufacturing technology, and more particularly to a method and structure for fabricating a depletion-type MOSFET that improves VTH uniformity. Background Technology

[0002] With the rapid development of power electronics technology, depletion-type metal-oxide-semiconductor field-effect transistors (MOSFETs) have shown important application value in power management, motor drive and power conversion due to their normally-on characteristics. The threshold voltage, VTH, is one of the core electrical parameters of depletion-type MOSFETs and directly affects the device's turn-on characteristics, conduction consistency and system reliability. Therefore, improving the uniformity of VTH has always been a key technical issue in the fabrication process of depletion-type MOSFETs.

[0003] Currently, the conventional fabrication method for existing depletion-type MOSFETs typically employs the following process: First, the implantation window of the Pbody region is defined using a Pbody photomask, and P-type ion implantation is performed to obtain the Pbody region. Subsequently, a gate oxide layer is grown and a polysilicon gate is deposited. Then, N-type ion implantation is performed using the gate polysilicon as a mask to obtain the NSD region. During this process, the implantation of the Pbody region and the NSD region depends on different mask boundaries, and there is an unavoidable overlay deviation between the two photolithography steps. This may lead to differences in the channel length between the Pbody region and the NSD region between different device units, resulting in poor VTH uniformity.

[0004] Therefore, how to achieve precise control of the channel length and improve the uniformity of the threshold voltage has become an urgent problem to be solved. Summary of the Invention

[0005] This invention provides a method and structure for fabricating a depletion-type MOSFET that improves VTH uniformity, enabling precise control of the channel length and improving the uniformity of the threshold voltage.

[0006] A first aspect of the present invention provides a method for fabricating a depletion-type MOSFET to improve VTH uniformity, comprising: A sacrificial barrier layer is constructed on a semiconductor substrate based on injection mask data to obtain an injection opening structure. Self-aligned ion implantation is performed based on the sacrificial barrier layer and the implantation opening structure to obtain the ion implantation region. The sacrificial barrier layer is removed to obtain an intermediate processing surface. Based on a preset threshold adjustment parameter, a threshold adjustment injection is performed on the intermediate processing surface to obtain a threshold adjustment injection region. The sacrificial oxide layer in the threshold-adjusted implantation region is removed to obtain the final processed surface, and a gate oxide layer covering the ion implantation region is constructed on the final processed surface to obtain a gate dielectric structure.

[0007] Optionally, in one possible implementation of the first aspect, the construction of a sacrificial barrier layer on the semiconductor substrate based on injection mask data to obtain an injection opening structure includes: The semiconductor substrate is subjected to thermal oxidation to obtain a sacrificial oxide layer, and polycrystalline silicon is deposited on the sacrificial oxide layer to obtain a polycrystalline silicon layer; The polysilicon layer is patterned based on the implantation mask data to obtain a sacrificial barrier layer with an implantation region, and the implantation opening structure is generated based on the sacrificial oxide layer and the implantation region.

[0008] Optionally, in one possible implementation of the first aspect, the step of patterning the polysilicon layer based on the implantation mask data to obtain a sacrificial barrier layer with implantation regions includes: The polysilicon layer is photolithographically processed based on the bulk region implantation photomask to obtain a photoresist masking layer corresponding to the implantation mask data. The polysilicon layer is dry etched using the photoresist masking layer as a mask to obtain the implantation region, thereby generating a sacrificial barrier layer with the implantation region.

[0009] Optionally, in one possible implementation of the first aspect, the self-aligned ion implantation based on the sacrificial barrier layer and the implantation opening structure to obtain the ion implantation region includes: Using the sacrificial barrier layer as a self-aligned mask, self-aligned ion implantation of the first conductivity type is performed based on the implantation opening structure to generate a hole-type body region in the semiconductor substrate; After obtaining the hole-type region, using the sacrificial barrier layer as a self-aligned mask, self-aligned ion implantation of the second conductivity type is performed based on the implantation opening structure to generate an electron-type source region within the hole-type region. The ion implantation region is formed by the hole-type region and the electron-type source region.

[0010] Optionally, in one possible implementation of the first aspect, the self-aligned ion implantation of a first conductivity type based on the implantation opening structure to generate a hole-type body region within the semiconductor substrate includes: Using the sacrificial barrier layer as the injection barrier layer, ions of the first conductivity type are injected into the injection opening structure; The semiconductor substrate after ion implantation is subjected to high-temperature push-well to obtain the hole-type body region.

[0011] Optionally, in one possible implementation of the first aspect, the self-aligned ion implantation of a second conductivity type based on the implantation opening structure to generate an electron-type source region within the hole-type body region includes: Using the sacrificial barrier layer as the injection barrier layer, ions of a second conductivity type are injected into the injection opening structure; The semiconductor substrate after ion implantation is subjected to high-temperature push-well treatment to obtain the electron source region within the hole-type body region.

[0012] Optionally, in one possible implementation of the first aspect, the removal of the sacrificial barrier layer to obtain an intermediate processed surface, and the threshold adjustment injection of the intermediate processed surface based on a preset threshold adjustment parameter to obtain a threshold-adjusted injection region, includes: The polysilicon layer constituting the sacrificial barrier layer is removed by an etching process, while the sacrificial oxide layer located on the surface of the active region of the semiconductor substrate is retained, to obtain an intermediate processed surface. Using the sacrificial oxide layer as an implantation buffer layer, ion implantation of the second conductivity type is performed on the intermediate treatment surface based on a preset implantation energy and a preset implantation dose; By controlling ions of the second conductivity type to penetrate the sacrificial oxide layer and enter the surface layer of the semiconductor substrate, a threshold-controlled implantation region is obtained.

[0013] Optionally, in one possible implementation of the first aspect, the removal of the sacrificial oxide layer in the threshold-tuned implantation region to obtain a final processed surface, and the construction of a gate oxide layer covering the ion implantation region on the final processed surface to obtain a gate dielectric structure, includes: The sacrificial oxide layer on the surface of the threshold-adjusted implantation region is removed by wet etching, and the single-crystal silicon surface of the semiconductor substrate is retained as the final processed surface. Thermal oxidation is performed on the final processed surface to obtain a gate oxide layer, which covers the ion implantation region and constitutes the gate dielectric structure.

[0014] Optionally, in one possible implementation of the first aspect, after obtaining the gate dielectric structure, the method further includes: An interlayer dielectric layer is deposited on the gate dielectric structure and the final processed surface; The interlayer dielectric layer is patterned and etched to obtain contact holes that penetrate the interlayer dielectric layer, and the contact holes expose a portion of the electron source region; A metal layer is deposited on the interlayer dielectric layer and inside the contact hole, and the metal layer is patterned to obtain a metal source electrode electrically connected to the electronic source region.

[0015] A second aspect of the present invention provides a depletion-type MOSFET structure for improving VTH uniformity, comprising: A semiconductor substrate having an active region; An ion implantation region, the ion implantation region including a hole-type region obtained within the active region and an electron-type source region obtained within the hole-type region; The lateral diffusion boundary of the hole-type body region and the lateral diffusion boundary of the electron-type source region together define the channel region within the semiconductor substrate. The gate dielectric structure consists of a gate oxide layer that directly covers the surface of the channel region and the threshold injection region; An interlayer dielectric layer covers the gate dielectric structure and the semiconductor substrate, and has contact holes inside that expose a portion of the electron source region; The metal source electrode is located above the interlayer dielectric layer and is electrically connected to the electron-type source region through the contact hole.

[0016] The beneficial effects of this invention are as follows: 1. This solution can construct a patterned sacrificial barrier layer on a semiconductor substrate and use the precise boundary obtained by a single photolithography as the common boundary for ion implantation. This can minimize the impact of alignment deviations between two photolithography steps on the channel length and improve the uniformity and consistency of the threshold voltage.

[0017] 2. This invention can utilize a pre-constructed sacrificial barrier layer as a common mask for two ion implantations. First, self-aligned implantation of the first conductivity type is performed to obtain a hole-type source region, and then self-aligned implantation of the second conductivity type is performed to obtain an electron-type source region. Since both implantations are masked by the sacrificial barrier layer, the lateral boundaries of the implantations are determined by the same sidewall of the sacrificial barrier layer. This ensures that the relative positions of the hole-type source region and the electron-type source region can be precisely fixed, and the channel length is no longer affected by photolithography offset, thereby improving the uniformity of the threshold voltage.

[0018] 3. This invention improves the quality and reliability of the gate oxide layer by arranging the ion implantation process before the growth of the gate oxide layer. During ion implantation, a sacrificial oxide layer is used as a buffer layer to protect the silicon surface. After all ion implantation processes are completed, the damaged sacrificial oxide layer is removed and the gate oxide layer is regrown on the clean silicon surface. Attached Figure Description

[0019] Figure 1 This is a schematic flowchart of a method for fabricating a depletion-type MOSFET to improve VTH uniformity according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a hole-type body region and an electron-type source region provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a threshold-adjusting injection region provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a depletion-type MOSFET that improves VTH uniformity according to an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0022] See Figure 1 This is a schematic flowchart of a method for fabricating a depletion-type MOSFET to improve VTH uniformity, provided by an embodiment of the present invention. Figure 1 The subject of the method shown can be a software and / or hardware device. The subject of this application can include, but is not limited to, at least one of the following: user equipment, network equipment, etc. User equipment can include, but is not limited to, computers, smartphones, personal digital assistants (PDAs), and the aforementioned electronic devices. Network equipment can include, but is not limited to, a single network server, a server group consisting of multiple network servers, or a cloud based on cloud computing consisting of a large number of computers or network servers. Cloud computing is a type of distributed computing, consisting of a super virtual computer composed of a group of loosely coupled computers. This embodiment does not limit this. Steps S1 to S4 are detailed as follows: S1, Based on the injection mask data, a sacrificial barrier layer is constructed on the semiconductor substrate to obtain the injection opening structure.

[0023] The implantation mask data refers to the layout design information that specifies the location and shape for ion implantation, specifically corresponding to the pattern on the P-body area photomask. The semiconductor substrate refers to the silicon wafer used to manufacture semiconductor devices, typically an N-type silicon wafer. A wafer is a circular, single-crystal silicon sheet with a very smooth surface after polishing. In power device fabrication, the original silicon wafer is usually N-type doped, resulting in very low resistivity, and serves as the drain lead. The sacrificial barrier layer is a patterned material layer temporarily constructed on the semiconductor substrate. It exists only in some process steps, and its main function is to block areas that do not need to be implanted during ion implantation, allowing ions to enter only through the opened areas. After implantation, this layer is removed and does not appear in the final device. The implantation opening structure refers to the physical structure formed by the opened areas on the sacrificial barrier layer. It provides a channel for subsequent ion implantation, through which the ion beam enters the semiconductor substrate.

[0024] In existing depletion-mode MOSFET fabrication processes, the implantation of the Pbody region and the NSD region relies on different mask boundaries. Overlapping misalignment between the two photolithography steps leads to differences in channel length between different device cells, resulting in poor VTH uniformity. This invention addresses this by constructing a patterned sacrificial barrier layer on the semiconductor substrate. Using this sacrificial barrier layer as a self-aligned mask, both the hole-type body region and the electron-type source region are self-aligned by the sidewall boundaries of the same sacrificial barrier layer. This eliminates the influence of photolithography overlapping on the channel length and improves VTH uniformity.

[0025] Understandably, in existing depletion-mode MOSFET fabrication processes, ion implantation of the Pbody region and the NSD region depends on different photolithography steps and different mask boundaries. Traditional processes first use the Pbody photomask as a mask for P-type ion implantation to obtain the Pbody region, then grow the gate oxide layer and deposit the polysilicon gate, and then use the gate polysilicon pattern as a mask for N-type ion implantation to obtain the NSD region. Since different photolithography steps are used for the two implantations, there is an inevitable registration error during the alignment process of the photolithography machine. This registration error causes the relative positional relationship between the lateral boundaries of the Pbody region and the lateral boundaries of the NSD region to differ between different device units, which directly causes inconsistency in channel length and consequently reduces the uniformity of the threshold voltage. This solution can construct a patterned sacrificial barrier layer on the semiconductor substrate and use the precise boundary obtained from one photolithography step as the common boundary for the subsequent two ion implantations, thereby minimizing the impact of the two photolithography alignment errors on the channel length.

[0026] Specifically, a sacrificial barrier layer can be constructed on the semiconductor substrate based on the pattern information determined by the implantation mask data. After construction, the sacrificial barrier layer covers a portion of the semiconductor substrate surface. At the location where subsequent ion implantation is required, the sacrificial barrier layer is opened to obtain an implantation opening structure. The position, size, and shape of the implantation opening structure are determined by the implantation mask data, and the accuracy of its sidewall boundary is guaranteed by the patterning process. Since this sidewall boundary is obtained in one patterning process, there is no alignment deviation between multiple photolithography steps, thus providing a relatively accurate and common reference boundary for the subsequent two ion implantations.

[0027] In some embodiments, step S1 can be implemented as follows: S11, the semiconductor substrate is subjected to thermal oxidation to obtain a sacrificial oxide layer, and polycrystalline silicon is deposited on the sacrificial oxide layer to obtain a polycrystalline silicon layer.

[0028] Thermal oxidation refers to a process in which a semiconductor substrate is placed in a high-temperature furnace tube and the silicon surface reacts chemically with oxygen in an oxygen-containing atmosphere to generate a layer of silicon dioxide. The sacrificial oxide layer is a layer of silicon dioxide obtained on the surface of a semiconductor substrate through thermal oxidation. This oxide layer is only used temporarily and will be removed after completing its protection and buffering functions. It will not be retained in the final device structure. The polycrystalline silicon layer is a thin silicon film layer composed of many tiny single-crystal silicon particles arranged in a disordered manner.

[0029] Before constructing the sacrificial barrier layer, a sacrificial oxide layer needs to be obtained on the surface of the semiconductor substrate, and then a polysilicon layer is deposited on it. There are two purposes for doing this. First, if polysilicon is deposited directly on the silicon surface, it is easy to damage the underlying silicon surface when removing the polysilicon. With an oxide layer as an isolation layer, the silicon surface can be protected from being affected when removing the polysilicon. Second, this sacrificial oxide layer plays a buffering role during subsequent ion implantation. High-energy ions are scattered and slowed down when passing through the oxide layer, reducing the direct impact on the silicon lattice.

[0030] Specifically, the semiconductor substrate can be placed in a high-temperature oxidation furnace, oxygen is introduced, and a thermal oxidation reaction occurs on the silicon surface under high temperature to generate a silicon dioxide layer of uniform thickness. This oxide layer is called the sacrificial oxide layer. The thickness of the sacrificial oxide layer can be determined according to the needs of the subsequent implantation process. After oxidation is completed, the semiconductor substrate is transferred to a chemical vapor deposition equipment to deposit an undoped polycrystalline silicon layer on the surface of the sacrificial oxide layer. During the deposition process, the silicon source gas decomposes at high temperature, and silicon atoms are deposited on the surface of the oxide layer to obtain a polycrystalline silicon thin film composed of tiny single crystal particles.

[0031] S12, the polysilicon layer is patterned based on the implantation mask data to obtain a sacrificial barrier layer with an implantation region, and the implantation opening structure is generated according to the sacrificial oxide layer and the implantation region.

[0032] Patterning refers to the process of creating patterns on a polysilicon layer. Specifically, it involves two steps: photolithography and etching. The pattern on the photomask is transferred to the polysilicon layer. First, photoresist is applied to the polysilicon, and then exposed and developed using a photomask to obtain the photoresist pattern. Then, etching is used to remove the polysilicon without photoresist protection. Finally, the residual photoresist is removed, and the polysilicon layer can be transformed into the desired pattern shape. The implantation region refers to the window area on the sacrificial barrier layer that is etched open. In this region, the original polysilicon is completely removed, exposing the underlying sacrificial oxide layer. The implantation region is the channel for subsequent ion implantation. The ion beam passes through the sacrificial oxide layer and enters the semiconductor substrate from here. The sidewalls of the implantation region are surrounded by the polysilicon sidewalls of the sacrificial barrier layer. This sidewall boundary is the reference boundary for subsequent self-aligned implantation.

[0033] After the polysilicon layer is deposited, it is still a complete layer without any openings. At this point, based on the implantation mask data, the polysilicon at the implantation location needs to be removed to obtain the implantation area. Meanwhile, the polysilicon at other locations is retained as a barrier layer during ion implantation. The patterning accuracy directly determines the sidewall boundary position of the implantation area. This boundary can serve as a common reference in the subsequent two implantations. Therefore, the patterning process only requires one photolithography step and one forming step, eliminating alignment deviations between multiple photolithography steps.

[0034] Specifically, the deposited polysilicon layer can be patterned based on the implantation mask data. After patterning, the polysilicon layer is no longer a single sheet, but forms a pattern with openings. The area where the polysilicon is etched away is the implantation area. The bottom of the implantation area exposes the surface of the underlying sacrificial oxide layer. The remaining polysilicon portion forms the sacrificial barrier layer. The sidewalls of the implantation area are the sidewalls of the polysilicon of the sacrificial barrier layer. These sidewalls, together with the sacrificial oxide layer exposed at the bottom of the implantation area, form the implantation opening structure. The position, size, and shape of the implantation opening structure are all determined by the implantation mask data.

[0035] In some embodiments, step S12, "patterning the polysilicon layer based on the implantation mask data to obtain a sacrificial barrier layer with implantation regions," includes the following steps: S121, the polysilicon layer is photolithographically processed based on the bulk region implantation photomask to obtain a photoresist masking layer corresponding to the implantation mask data.

[0036] The body implantation photomask refers to the photolithographic mask used to define the implantation range of the Pbody region. The photomask is a quartz glass plate etched with circuit patterns, featuring both transparent and opaque areas, resulting in a geometric shape corresponding to the implantation mask data. Ultraviolet light shines through the photomask onto the photoresist, transferring the pattern from the photomask to the photoresist. Photolithography is the process of transferring the pattern from the photomask to the photoresist layer on the wafer surface. Photoresist is a photosensitive material; the exposed areas undergo chemical changes, resulting in a different solubility rate in the developer compared to the unexposed areas. Through exposure and development, the pattern on the photomask can be copied onto the photoresist, forming a photoresist mask layer. This photoresist mask layer is a temporary mask layer formed on the wafer surface after the photolithography process and is removed after the polysilicon etching is complete.

[0037] Specifically, a layer of photoresist can be spin-coated onto the surface of the polysilicon layer. Then, a bulk injection photomask is aligned and placed above the photoresist. Ultraviolet light is used to expose the photoresist under the light-transmitting area of ​​the photomask. The photoresist is exposed, and its chemical properties change. Afterward, it can be treated with a developer to dissolve and remove the exposed photoresist. Here, a positive photoresist is used as an example, while the photoresist in the unexposed area is retained. At this point, the photoresist has been removed at the injection area position defined in the injection mask data, exposing the polysilicon underneath. In areas where polysilicon needs to be retained as a barrier layer, the photoresist is still covered. This results in a photoresist masking layer corresponding to the injection mask data.

[0038] S122, using the photoresist masking layer as a mask, the polysilicon layer is dry etched to obtain the implantation region, and a sacrificial barrier layer with the implantation region is generated.

[0039] In this process, a mask is a layer used to protect the underlying material from being etched. In this step, the resulting photoresist masking layer is the mask. The polysilicon under the area covered by the photoresist is protected, while the polysilicon under the opening area of ​​the photoresist is etched away. Dry etching is a process that uses active particles in plasma to react chemically with the material or physically bombard it to remove the material.

[0040] After photolithography, the polysilicon surface has a photoresist masking layer, exposing the polysilicon areas that need to be removed. At this point, it is necessary to completely remove the polysilicon in these areas while retaining the polysilicon in the photoresist-covered areas. Dry etching is chosen instead of wet etching because dry etching has the characteristics of good directionality and high etching precision, and can more accurately control the shape and depth of the etched sidewalls. In this step, the gas used for dry etching is selected to have a high etching rate for polysilicon and a low etching rate for the underlying sacrificial oxide layer. This way, the etching will stop naturally when it reaches the surface of the sacrificial oxide layer, without damaging the underlying silicon substrate.

[0041] Specifically, a semiconductor substrate with a photoresist masking layer can be placed in a dry etching apparatus. A gas with a high etching rate for polysilicon and a low etching rate for silicon oxide is introduced. Under the action of plasma, the gas decomposes into active particles, which react with the polysilicon exposed in the photoresist opening area, vertically removing the polysilicon. When the etching reaches the surface of the sacrificial oxide layer, the etching automatically stops because the etching rate for silicon oxide is much lower than that for polysilicon. After the etching is completed, the residual photoresist is removed. At this point, the area on the polysilicon layer that has been etched through is the implantation area, and the remaining polysilicon portion is the sacrificial barrier layer. The sidewalls of the implantation area are the polysilicon sidewalls of the sacrificial barrier layer. The boundary is precisely obtained in one photolithography and etching process.

[0042] S2, self-aligned ion implantation is performed based on the sacrificial barrier layer and the implantation opening structure to obtain the ion implantation region.

[0043] Self-aligned ion implantation refers to the process of implanting doped ions into a semiconductor substrate through an implantation opening structure using a sacrificial barrier layer as a barrier mask. The ion implantation region refers to the collection of doped regions containing two types of conductivity after two self-aligned ion implantations in the semiconductor substrate. This region contains P-type doped regions and N-type doped regions, and the channel region is obtained at the boundary between the two.

[0044] Understandably, in existing processes, the P-body region and NSD region are obtained through two separate photolithography steps. First, P-type implantation is performed using the P-body photomask as a mask to obtain the P-body region. Then, a gate oxide layer is grown and polysilicon is deposited. Next, N-type implantation is performed using the gate polysilicon pattern as a mask to obtain the NSD region. The lateral boundaries of the two implantations come from different photolithography steps, inevitably leading to alignment deviations. This results in inconsistent channel lengths between the P-body region and the NSD region across the wafer. This solution utilizes a pre-constructed sacrificial barrier layer as a common ion implantation layer for the two implantations. Using the same mask, self-aligned implantation of the first conductivity type is performed first, followed by self-aligned implantation of the second conductivity type. The first conductivity type refers to the P-type conductivity type, which is achieved by doping with acceptor impurities and uses holes as the main charge carriers. The second conductivity type refers to the N-type conductivity type, which is achieved by doping with donor impurities and uses electrons as the main charge carriers. Since both implantations are masked by the sacrificial barrier layer, the lateral boundaries of the implantations are determined by the same sidewall of the sacrificial barrier layer. The relative positions of the two doped regions can be precisely fixed, and the channel length is no longer affected by the photolithography offset, thereby improving the uniformity of the threshold voltage.

[0045] Specifically, the obtained sacrificial barrier layer can be used as a self-aligned mask to begin ion implantation. During implantation, the ion beam moves towards the surface of the semiconductor substrate. In the area covered by the sacrificial barrier layer, ions are blocked and cannot enter the semiconductor substrate. In the area corresponding to the implantation opening structure, ions pass through the implantation opening structure and can enter the interior of the semiconductor substrate. First, self-aligned ion implantation of the first conductivity type is performed. Doped ions enter the semiconductor substrate from the implantation opening structure, and a doped region of the first conductivity type is obtained below the opening. After the first implantation is completed, self-aligned ion implantation of the second conductivity type is performed. Doped ions also enter the semiconductor substrate from the same implantation opening structure, and a doped region of the second conductivity type is obtained inside the doped region obtained in the first implantation. Both implantations are masked by the sacrificial barrier layer. The lateral range of ions entering the semiconductor substrate is determined by the sidewall boundary of the sacrificial barrier layer. Since the sidewall boundary has been fixed and precise in step S1, the relative positional relationship between the doped regions obtained by the two implantations is also precisely determined. The boundary between the two is the channel region. After the two implantations are completed, an ion implantation region containing doped of two conductivity types is obtained in the semiconductor substrate.

[0046] Based on the above embodiments, step S2 can be implemented in the following ways: S21, using the sacrificial barrier layer as a self-aligned mask, self-aligned ion implantation of the first conductivity type is performed based on the implantation opening structure to generate a hole-type body region in the semiconductor substrate.

[0047] Among them, self-aligned mask refers to using the sacrificial barrier layer that already exists on the surface of the semiconductor substrate as the masking layer for subsequent ion implantation. Unlike conventional processes that require a separate photolithography to define the implantation area each time, self-aligned mask directly uses the existing patterned structure and no longer requires an additional photolithography alignment step. Hole body region refers to a P-type doped region obtained in the semiconductor substrate, also known as Pbody region. This region is doped with acceptor impurities, and the majority carriers are holes, which are P-type conductive.

[0048] Understandably, the P-type body region is essential in the structure of a MOSFET, acting as a base. The channel is formed on the surface of this base, and the N-type source region is also embedded within it. When no voltage is applied to the gate or a negative voltage is applied, the PN junction between the body region and the N-type source region is in a reverse cutoff state, and the device is turned off. When a positive voltage is applied to the gate, minority carriers on the surface of the body region are attracted to the surface, forming an inversion layer conductive channel, and the device is turned on. Therefore, the doping concentration and depth of the body region directly affect the threshold voltage and breakdown voltage characteristics of the device. In this step, self-aligned ion implantation of the first conductivity type is performed, implanting P-type impurities such as boron into the semiconductor substrate to obtain this hole-type body region. Moreover, this implantation is masked by a sacrificial barrier layer and is performed through the implantation opening structure. The lateral boundary of the implantation is determined by the sidewall of the sacrificial barrier layer, so the boundary of the body region is precisely controllable.

[0049] Specifically, a sacrificial barrier layer can be used as a self-aligned mask. Through an implantation opening structure, impurity ions of the first conductivity type are implanted into the semiconductor substrate. The ion beam passes through the opening region and enters the underlying semiconductor substrate. In the area covered by the sacrificial barrier layer, the ions are blocked from entering, and the implanted ions undergo P-type doping inside the substrate. After implantation, high-temperature annealing can be performed to activate the implanted impurity atoms and diffuse them to a suitable depth and lateral range, resulting in a stable P-type doped region within the semiconductor substrate, which is the hole-type bulk region.

[0050] Based on the above embodiments, step S21 can be implemented in the following ways: S211, using the sacrificial barrier layer as the injection barrier layer, inject ions of the first conductivity type into the injection opening structure.

[0051] The implantation barrier layer is a material layer that acts as a physical shield during ion implantation. When an ion beam strikes the surface of a semiconductor substrate, the implantation barrier layer can block the ions, preventing them from penetrating the substrate below. Only in the region corresponding to the implantation opening structure can the ion beam pass through the opening and enter the substrate. The function of the implantation barrier layer is to limit the spatial range of ion implantation.

[0052] During first-conductivity ion implantation, the ion beam covers the entire wafer surface. Without shielding, the entire semiconductor substrate will be doped with P-type impurities, making localized doping impossible. Therefore, an implantation barrier layer can be used to shield areas that do not need to be implanted, allowing ions to enter only through the implantation opening structure. The polysilicon thickness of the sacrificial barrier layer is sufficient to effectively block the implanted ions, ensuring that ions can only enter the substrate through the opening and form a hole-type body region in the designated area.

[0053] Specifically, a semiconductor substrate can be placed in an ion implanter, and an ion beam is emitted toward the substrate surface at a preset energy. In the area covered by the sacrificial barrier layer, the implanted ions are blocked by the polycrystalline silicon material and cannot enter the semiconductor substrate below. In the area corresponding to the implantation opening structure, the ions pass through the opening and the sacrificial oxide layer exposed at the bottom and enter the interior of the semiconductor substrate, resulting in a P-type impurity distribution.

[0054] S212, the semiconductor substrate after ion implantation is subjected to high-temperature push-well to obtain the hole-type body region.

[0055] High-temperature push-trap refers to placing the ion-implanted semiconductor substrate into a high-temperature furnace tube and subjecting it to long-term heat treatment under specific temperature and atmosphere conditions.

[0056] Understandably, during ion implantation, impurity atoms are forcibly driven into the silicon lattice. They remain in interstitial positions, not on lattice points, and are therefore not activated and cannot perform doping. At the same time, the implantation process damages the silicon lattice. High-temperature push-in allows impurity atoms to move from interstitial positions to lattice points, achieving electrical activation and becoming effective dopant atoms. Furthermore, it allows impurity atoms to diffuse further at high temperatures, achieving the designed depth and distribution range in both the vertical and horizontal directions. The temperature and time of push-in can be precisely controlled according to the device design requirements. The higher the temperature and the longer the time, the deeper and wider the impurity diffusion.

[0057] Specifically, the semiconductor substrate that has undergone ion implantation of the first conductivity type can be placed in a high-temperature furnace tube for high-temperature annealing. At high temperature, the implanted boron atoms gain energy and move from interstitial positions to lattice points, becoming electrically activated acceptor impurities. Simultaneously, boron atoms diffuse from high-concentration areas to low-concentration areas, expanding the doping range in both the vertical and horizontal directions. After the push-in is completed, the semiconductor substrate is removed from the furnace tube. At this point, a uniformly distributed, activated P-type doped region, i.e., the hole-type body region, has been obtained below the implantation opening structure.

[0058] S22, after obtaining the hole-type region, using the sacrificial barrier layer as a self-aligned mask, self-aligned ion implantation of the second conductivity type is performed based on the implantation opening structure to generate an electron-type source region within the hole-type region.

[0059] Among them, the electron source region refers to an N-type heavily doped region obtained inside the hole-type body region, also known as the NSD region. This region is doped with donor impurities, and the majority carriers are electrons, which are N-type conductive.

[0060] In a MOSFET structure, the source region is also essential. The source region is the entry point for current. When the device is turned on, electrons start from the source region, pass through the channel region, and flow to the drain region. The source region is a heavily doped N-type region, so that when the metal electrode contacts the source region, an ohmic contact can be obtained instead of an additional PN junction, ensuring that the current can flow in and out smoothly. In this step, after the hole-type body region is obtained, the same sacrificial barrier layer can still be used as a mask, and N-type ion implantation can be performed through the same implantation opening structure. The lateral boundary of this implantation is also determined by the sidewall of the sacrificial barrier layer. Since the position of the sidewall of the barrier layer has not changed, the boundary of the electron-type source region and the boundary of the previously obtained hole-type body region are both defined by the same sidewall. The relative position between the two regions is precisely fixed, and the boundary between the two is the channel region. The channel length is determined by the difference in lateral diffusion between the two implantations.

[0061] Specifically, after obtaining the hole-type body region, a sacrificial barrier layer can be used as a mask to inject impurity ions of the second conductivity type into the semiconductor substrate through the same injection opening structure. The injected impurity ions pass through the opening and the sacrificial oxide layer and enter the hole-type body region. After the injection is completed, a high-temperature push-well is performed to activate the injected impurities and diffuse them to a suitable range. Since the second injection is performed inside the hole-type body region, the resulting N-type heavily doped region is completely located within the P-type body region, and a PN junction is formed between the two. The boundary is the channel of the device.

[0062] Based on the above embodiments, step S22 can be implemented in the following ways: S221, using the sacrificial barrier layer as the injection barrier layer, inject ions of a second conductivity type into the injection opening structure.

[0063] Understandably, N-type ion implantation also requires limiting the implantation area. The sacrificial barrier layer was not removed after the first P-type implantation and remained on the substrate surface. Therefore, it can be directly reused for the second N-type implantation. Using the same barrier layer for both implantations can ensure the spatial self-alignment of the two implantations.

[0064] Specifically, the semiconductor substrate is placed back into the ion implanter, and impurity ions of the second conductivity type are emitted to the substrate surface with preset energy and dose. In the area covered by the sacrificial barrier layer, the implanted ions are blocked, while in the area corresponding to the implantation opening structure, the ions pass through the opening and the sacrificial oxide layer and enter the cavity region.

[0065] S222, the semiconductor substrate after ion implantation is subjected to high-temperature push-well to obtain the electron source region in the hole-type body region.

[0066] After the second implantation of phosphorus or arsenic ions into the silicon substrate, they are also located in interstitial positions and require high-temperature push-well to activate them as donor impurities. During the push-well process, N-type impurities diffuse from regions with high concentration to regions with low concentration. However, due to the high implantation dose, the concentration of N-type impurities in the electron source region is much greater than the acceptor concentration in the surrounding P-type body region. After the push-well, the N-type conductivity is still maintained. The temperature and time of the high-temperature push-well also need to be precisely controlled to ensure that the position and depth of the electron source region meet the design requirements.

[0067] Specifically, the semiconductor substrate that has undergone N-type ion implantation can be placed in a high-temperature furnace tube and annealed at high temperature under the protection of an inert gas. Under high temperature, the implanted phosphorus or arsenic atoms are electrically activated to become donor impurities, providing a large number of free electrons and obtaining an N-type conductive region. The impurities diffuse in the longitudinal and lateral directions, but since the doping is carried out inside the hole-type body region, it is surrounded by a P-type region. After the push-in is completed, an N-type heavily doped region is obtained inside the hole-type body region, which is the electron-type source region.

[0068] S23, the ion implantation region is formed based on the hole-type body region and the electron-type source region.

[0069] See Figure 2 This is a schematic diagram of a hole-type body region and an electron-type source region provided in an embodiment of the present invention, as shown below. Figure 2 As described above, the regions on both sides of the sacrificial barrier layer are the implantation regions. The implantation regions and the corresponding sacrificial oxide layers can form an implantation opening structure. The hole-type body region can be the P-type doped region obtained by self-aligned ion implantation of the first conductivity type in step S2. Figure 2 As can be seen, the hole-type region is located below the implantation opening structure. After obtaining the hole-type region, an electron-type source region can be obtained inside the hole-type region by self-aligned ion implantation of the second conductivity type. The electron-type source region is an N-type heavily doped region, which is completely surrounded by the hole-type region. The hole-type region and the electron-type source region together constitute the ion implantation region.

[0070] Through the above implementation method, the relative positions of the hole-type source region and the electron-type source region can be precisely fixed, and the channel length can no longer be affected by the photolithography offset, thereby improving the uniformity of the threshold voltage.

[0071] S3, the sacrificial barrier layer is removed to obtain an intermediate processing surface. Based on a preset threshold adjustment parameter, the intermediate processing surface is subjected to threshold adjustment injection to obtain a threshold adjustment injection region.

[0072] The removal process refers to the process of removing the sacrificial barrier layer, which has completed its blocking function, from the semiconductor substrate. The intermediate processing surface refers to the state of the semiconductor substrate surface after the sacrificial barrier layer is removed and before threshold adjustment implantation is performed. At this time, the ion implantation region is located inside the semiconductor substrate, and the surface of the semiconductor substrate is still covered with a material layer. The threshold adjustment parameters refer to the process conditions on which threshold adjustment implantation is performed, mainly including the energy and dose of implanted ions. These two parameters together determine the amount of threshold voltage adjustment. Threshold adjustment implantation refers to ion implantation performed to adjust the threshold voltage of the depletion-type MOSFET to the target value. The threshold adjustment implantation region refers to the region containing threshold adjustment impurities obtained on the surface of the semiconductor substrate after threshold adjustment implantation is completed.

[0073] After obtaining the hole-type body region and the electron-type source region, the channel length has been precisely controlled. However, the device structure at this time is still just a prototype of a common enhancement-mode MOSFET. When the gate voltage is zero, the channel is not conducting. To make the device depletion-mode, a thin layer of N-type impurities needs to be implanted on the surface of the P-type body region. This N-type impurity provides a fixed electron layer on the channel surface, so that the channel is in the conducting state under zero gate voltage conditions. In conventional processes, threshold adjustment implantation is performed after the gate oxide layer is grown. Impurity ions need to pass through the gate oxide layer to reach the silicon surface. When high-energy ions pass through the oxide layer, they will generate lattice defects and interface states inside the oxide layer, reducing the quality and reliability of the gate oxide layer.

[0074] This scheme arranges threshold adjustment implantation after the removal of the sacrificial barrier layer and before the removal of the sacrificial oxide layer. At this time, the polysilicon of the sacrificial barrier layer has been removed, and ion implantation can completely cover the entire surface of the active region. Meanwhile, the sacrificial oxide layer is still retained on the substrate surface. It can play a buffering and scattering role during the implantation process, reducing the direct impact damage of high-energy ions on the silicon lattice. The sacrificial oxide layer has been damaged after implantation and will be removed in the later steps without affecting the quality of the subsequently grown gate oxide layer.

[0075] Specifically, the sacrificial barrier layer can be removed first. An etching process with selective removal capability for polysilicon is used to remove the polysilicon material constituting the sacrificial barrier layer from the surface of the semiconductor substrate. Since the etching rate of polysilicon is much higher than that of the underlying material layer, the removal process naturally stops when it reaches the surface of the material layer, without causing damage to the material layer and the underlying silicon substrate. After the removal is completed, the substrate surface is restored to flatness, and an intermediate processed surface is obtained. At this time, the intermediate processed surface is characterized by a material layer on the surface, and the ion implantation region obtained in step S2 is below the material layer.

[0076] Then, threshold-adjusted implantation can be performed on the intermediate processing surface by adjusting the preset threshold parameters. The semiconductor substrate is placed in an ion implanter, and N-type impurity ions are implanted into the intermediate processing surface according to the preset implantation energy and implantation dose. The ion beam bombards the substrate surface, penetrates the surface material layer, and enters the surface layer of the semiconductor substrate. Due to the buffering of the material layer, the high-energy ions undergo scattering and energy attenuation before reaching the silicon surface, which reduces the impact damage to the silicon lattice. The implanted N-type impurities obtain a shallow doped layer in the surface layer of the hole-type body region. The conductivity type of this layer is N-type, which is opposite to the P-type in the lower body region. It provides a conductive channel for the channel at zero gate voltage. After implantation, a threshold-adjusted implantation region is obtained on the substrate surface, and its surface is still covered by a material layer.

[0077] Based on the above embodiments, step S3 can be implemented in the following ways: S31, the polysilicon layer constituting the sacrificial barrier layer is removed by an etching process, while the sacrificial oxide layer located on the active region surface of the semiconductor substrate is retained, to obtain an intermediate processed surface.

[0078] Etching process refers to the process technology of selectively removing unwanted material layers using chemical or physical methods. Active region surface refers to the surface of the working area on the semiconductor substrate that is surrounded by a field oxide layer and used to fabricate the core structure of transistors.

[0079] Understandably, the sacrificial barrier layer is made of polysilicon. After completing the barrier task of two ion implantations, the subsequent threshold adjustment implantation and gate oxide layer growth are required. These processes need to be carried out on a flat surface without polysilicon shielding. Therefore, the polysilicon portion of the sacrificial barrier layer needs to be completely removed while retaining the sacrificial oxide layer underneath to provide buffer protection for the subsequent threshold adjustment implantation.

[0080] Specifically, an etching process with selective removal capability for polysilicon can be used to remove the polysilicon material constituting the sacrificial barrier layer from the semiconductor substrate surface. The selective removal capability mentioned here means that the etching rate of the polysilicon is much higher than the etching rate of the underlying sacrificial oxide layer. The etching rate refers to the thickness of material removed per unit time, usually measured in angstroms per minute or nanometers per minute. Since the polysilicon is etched very quickly, while the sacrificial oxide layer is etched very slowly under the same etching conditions, when the polysilicon is completely removed and the underlying sacrificial oxide layer is exposed, the etching process will naturally stop at the surface of the sacrificial oxide layer and will not continue to etch downwards into the sacrificial oxide layer, thus avoiding damage to the sacrificial oxide layer and the silicon substrate below it. After removal, the substrate surface is restored to flatness, resulting in an intermediate processed surface. At this time, the characteristic of the substrate surface is that the sacrificial oxide layer of the active region surface is retained, and the area below the sacrificial oxide layer is the ion implantation region obtained in step S2.

[0081] S32, using the sacrificial oxide layer as an implantation buffer layer, perform second conductivity type ion implantation treatment on the intermediate treatment surface based on preset implantation energy and preset implantation dose.

[0082] The implantation buffer layer refers to a layer of material located on the surface of the silicon substrate during ion implantation. It is used to scatter and decelerate the implanted high-energy ions, reducing the direct impact damage of ions on the silicon lattice. The preset implantation energy refers to the ion acceleration energy that is preset according to the device design requirements before ion implantation. The preset implantation dose refers to the total number of ions implanted per unit area that is preset according to the target value of the depletion-type device threshold voltage before ion implantation. Ion implantation process refers to the process of accelerating impurity ions to high energy and bombarding the surface of the semiconductor substrate, causing impurity atoms to enter the interior of the substrate. The target of ion implantation process here is N-type impurity ions, and the implantation range covers the entire intermediate processing surface.

[0083] After obtaining the intermediate processed surface, the substrate surface still retains the sacrificial oxide layer. Instead of removing this oxide layer first, ion implantation is performed directly to utilize this oxide layer as a natural buffer layer. If the oxide layer is removed first before implantation, high-energy ions will directly bombard the exposed silicon surface, generating a large number of defects and dislocations in the silicon lattice, which may affect the electrical performance of the device. Utilizing the sacrificial oxide layer as a buffer can significantly reduce implantation damage.

[0084] Specifically, a semiconductor substrate can be placed in an ion implanter, with a sacrificial oxide layer as the implantation buffer layer. According to the preset implantation energy and implantation dose, ion implantation of the second conductivity type is performed on the intermediate processing surface. The ion beam enters the substrate surface, and the impurity ions first enter the sacrificial oxide layer. In the oxide layer, they undergo multiple collisions and scattering, resulting in energy attenuation and path dispersion. After passing through the oxide layer, the ions enter the surface layer of the silicon substrate and obtain a shallow doping distribution on the surface of the hole-type bulk region.

[0085] S33, control the ions of the second conductivity type to penetrate the sacrificial oxide layer and enter the surface layer of the semiconductor substrate to obtain the threshold implantation region.

[0086] During ion implantation, the implantation result needs to be precisely controlled. Impurity ions cannot remain in the sacrificial oxide layer; they must penetrate the oxide layer and enter the silicon substrate surface to achieve the doping effect. However, they cannot penetrate too deeply, otherwise they will enter the depths of the hole-type bulk region, making it impossible to obtain an effective inversion layer on the surface. Controlling the impurity ions to just penetrate the sacrificial oxide layer and remain on the silicon surface is the key to achieving the normally-on characteristic of depletion-type devices without affecting other performance characteristics of the bulk region.

[0087] Therefore, during ion implantation, the penetration depth of impurity ions can be precisely controlled by a preset implantation energy, enabling the ions to penetrate the sacrificial oxide layer and remain precisely within the surface area of ​​the semiconductor substrate. After implantation, a thin N-type doped layer is obtained on the surface of the hole-type region; this region is the threshold-tuned implantation region. (See [link to relevant documentation]). Figure 3 This is a schematic diagram of a threshold-adjusting injection region provided in an embodiment of the present invention, as shown below. Figure 3 As shown, Figure 3 As shown, the threshold injection region is located on the surface layer of the hole-type region and is very shallow. Its conductivity type is N-type. At this time, the surface of the threshold injection region is still covered with a sacrificial oxide layer, which will be removed in subsequent steps.

[0088] S4, the sacrificial oxide layer in the threshold-adjusted implantation region is removed to obtain the final processed surface, and a gate oxide layer covering the ion implantation region is constructed on the final processed surface to obtain the gate dielectric structure.

[0089] The final processed surface refers to the clean single-crystal silicon surface exposed after the sacrificial oxide layer is removed. The gate oxide layer refers to an insulating dielectric layer obtained on the final processed surface. The gate dielectric structure refers to the gate dielectric structure composed of the gate oxide layer, which covers the ion implantation region and includes the hole-type body region, the electron-type source region, and the channel region between them.

[0090] After threshold-adjusted implantation is completed and the threshold-adjusted implantation region is obtained, the sacrificial oxide layer covering the substrate surface has undergone the first implantation, the second implantation, and the threshold-adjusted implantation in steps S2 and S3, a total of three high-energy ion implantations. A large amount of lattice damage, interface trap charges, and impurity contamination have accumulated inside this oxide layer. If this damaged oxide layer is used directly as the gate dielectric layer, the gate leakage current of the device will be very large, the breakdown voltage will be reduced, and the long-term reliability may be poor.

[0091] Therefore, after all ion implantation processes are completed, the damaged sacrificial oxide layer can be removed first, and then a brand new gate oxide layer can be reconstructed on a clean silicon surface that has not been damaged by implantation. This ensures that the newly constructed gate oxide layer has never been bombarded by high-energy ions, and its interior is dense and uniform with low interface state density and high intrinsic breakdown strength, which significantly improves the quality and reliability of the device.

[0092] Specifically, the sacrificial oxide layer in the threshold-tuned implantation region can be removed first. The sacrificial oxide layer covering the surface of the threshold-tuned implantation region can be completely removed to expose the clean single-crystal silicon surface underneath, resulting in the final processed surface. The final processed surface has not undergone direct bombardment by ion implantation and has an intact crystal structure. Then, a gate oxide layer can be constructed on the final processed surface to cover the ion implantation region, that is, to cover the hole-type body region, the electron-type source region, and the channel region at the junction of the two. The constructed gate oxide layer constitutes the gate dielectric structure.

[0093] Based on the above embodiments, step S4 can be implemented in the following ways: S41, the sacrificial oxide layer on the surface of the threshold implantation region is removed by wet etching process, and the single-crystal silicon surface of the semiconductor substrate is retained as the final processed surface.

[0094] Wet etching process refers to the process of removing materials using liquid chemical etching solution, and single crystal silicon surface refers to the surface of the semiconductor substrate itself with silicon atoms arranged in a uniform lattice.

[0095] After undergoing multiple ion implantation penetrations, the sacrificial oxide layer has accumulated lattice damage and impurity contamination, which needs to be completely removed. Removing this oxide layer requires a process with a high etching rate for silicon oxide and an extremely low etching rate for monocrystalline silicon. This way, after the oxide layer is completely removed, the etching process will automatically stop on the silicon surface without damaging the intact silicon surface underneath. Wet etching process meets this requirement perfectly, and by selecting an appropriate etchant, extremely high selectivity can be achieved.

[0096] Specifically, a wet etching process can be used, in which a chemical solution with high selective etching ability for silicon oxide is used to treat the surface of the semiconductor substrate covered with a sacrificial oxide layer. The solution reacts chemically with the sacrificial oxide layer, gradually dissolving and removing the silicon oxide. Since the etching rate of the etchant on silicon oxide is much higher than that on single-crystal silicon, the etching process automatically stops on the silicon surface after the oxide layer is completely removed, and will not continue to etch downwards into the silicon substrate. After removal, the clean and flat single-crystal silicon surface underneath is exposed, which is the final processed surface.

[0097] S42, thermal oxidation is performed on the final processed surface to obtain a gate oxide layer, which covers the ion implantation region and constitutes the gate dielectric structure.

[0098] The gate oxide layer refers to a high-quality silicon dioxide layer that is regrown on the final processed surface.

[0099] After removing the damaged sacrificial oxide layer, a clean single-crystal silicon surface is exposed. At this point, a high-quality oxide layer can be reconstructed on the silicon surface as the gate dielectric. This is the first time an oxide layer has been grown on a clean silicon surface in the entire device manufacturing process. The previous sacrificial oxide layer was a temporary protective layer, and the one constructed here is the gate oxide layer that will ultimately remain in the device. The quality of the gate oxide layer directly determines the gate reliability of the device and needs to be grown on the cleanest surface. Specifically, a thermal oxide layer can be reconstructed on the final processing surface so that this oxide layer covers the ion implantation region, that is, it covers the hole-type region, the electron-type source region, and the channel region at the junction of the two. This oxide layer is the gate oxide layer, which is directly bonded to the final processing surface below to form the gate dielectric structure.

[0100] The above-described implementation methods can effectively improve the quality and reliability of the gate oxide layer.

[0101] Based on the above steps, after obtaining the gate dielectric structure, this solution also includes the following embodiments: A1, depositing an interlayer dielectric layer on the gate dielectric structure and the final processed surface.

[0102] The interlayer dielectric layer refers to an insulating material layer deposited on the gate dielectric structure and the semiconductor substrate surface. Its function is to isolate different conductive layers such as the gate and source to prevent short circuits between them. The interlayer dielectric layer is usually made of insulating materials such as borosilicate glass and is obtained through chemical vapor deposition. This dielectric layer will cover the entire device surface, including the area above the gate dielectric structure and the surface of the active region that is not covered by the gate.

[0103] After obtaining the gate dielectric structure, metal electrodes need to be fabricated on the device surface to bring out the gate and source. There must be an insulating material between the metal electrodes, otherwise a short circuit will occur. Therefore, an interlayer dielectric layer can be deposited on the entire device surface to cover the obtained gate dielectric structure and semiconductor substrate surface, providing an insulating substrate for subsequent metal wiring. Specifically, an interlayer dielectric layer can be deposited on the gate dielectric structure and the final processing surface, so that this insulating material covers the entire device surface, including the top of the gate dielectric structure and the surrounding final processing surface that is not covered by the gate.

[0104] A2, patterning etching is performed on the interlayer dielectric layer to obtain contact holes that penetrate the interlayer dielectric layer, and the contact holes expose a portion of the electron source region.

[0105] Patterning etching refers to the process of first coating photoresist on the interlayer dielectric layer, creating a pattern through photolithography, and then using the photoresist as a mask for etching to open holes at specific locations on the interlayer dielectric layer. Contact holes are small holes etched into the interlayer dielectric layer that penetrate the entire thickness of the dielectric layer. The function of contact holes is to allow metal electrodes to pass through the insulating dielectric layer and make contact with the underlying semiconductor region.

[0106] After the interlayer dielectric layer covers the entire device surface, the metal source and the electronic source region are separated by the insulating dielectric layer, making electrical connection impossible. Therefore, it is necessary to make holes in the interlayer dielectric layer above the electronic source region so that the metal source can contact the electronic source region through these holes. The position of the contact hole must be precisely aligned with the electronic source region, and the size of the hole must also be appropriate to ensure sufficient contact area without exceeding the range of the electronic source region.

[0107] Specifically, the interlayer dielectric layer can be patterned and etched to obtain a contact hole that penetrates the dielectric layer at the position corresponding to the electron source region on the dielectric layer. The bottom of the contact hole exposes part of the surface of the electron source region, providing a channel for the subsequent electrical connection between the metal source and the electron source region.

[0108] A3. A metal layer is deposited on the interlayer dielectric layer and inside the contact hole, and the metal layer is patterned to obtain a metal source electrode electrically connected to the electronic source region.

[0109] The metal layer refers to the conductive metal material layer deposited on the interlayer dielectric layer and filled into the contact hole, and the metal source refers to the metal electrode obtained after patterning and electrically connected to the electronic source region.

[0110] After the contact hole is opened, metal electrodes need to be fabricated to achieve electrical connection of the device. After the metal layer is deposited, it covers the upper surface of the dielectric layer and the inside of the contact hole, and makes direct contact with the electron source region exposed at the bottom of the contact hole. The metal layer is patterned to make the metal layer into the required electrode pattern to obtain an independent metal source electrode and avoid short circuit with other electrodes.

[0111] Specifically, a metal layer can be deposited on the interlayer dielectric layer and inside the contact hole. The metal material simultaneously covers the upper surface of the dielectric layer and fills the inside of the contact hole, making direct contact with the electron source region exposed at the bottom of the contact hole. Then, the metal layer is patterned to create an electrode pattern, resulting in a metal source electrode electrically connected to the electron source region.

[0112] See Figure 4 This is a schematic diagram of a depletion-type MOSFET structure for improving VTH uniformity provided in an embodiment of the present invention, as shown below. Figure 4As described, the depletion-type MOSFET structure based on improving VTH uniformity includes a semiconductor substrate, which has an active region and an ion-implanted region. The ion-implanted region includes a hole-type body region formed within the active region and an electron-type source region formed within the hole-type body region. The lateral diffusion boundary of the hole-type body region and the lateral diffusion boundary of the electron-type source region together define a channel region within the semiconductor substrate. Figure 4 The JEFT region in the semiconductor consists of a gate dielectric structure, which is composed of a gate oxide layer that directly covers the surface of the channel region and the threshold injection region. The interlayer dielectric layer covers the gate dielectric structure and the semiconductor substrate and has contact holes that expose part of the electron source region. The metal layer is a conductive metal material layer deposited on the interlayer dielectric layer and filled into the contact holes. The metal source is located on the interlayer dielectric layer and is electrically connected to the electron source region through the contact holes.

[0113] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a depletion-mode MOSFET to improve VTH uniformity, characterized in that, include: A sacrificial barrier layer is constructed on a semiconductor substrate based on injection mask data to obtain an injection opening structure. Self-aligned ion implantation is performed based on the sacrificial barrier layer and the implantation opening structure to obtain the ion implantation region. The sacrificial barrier layer is removed to obtain an intermediate processing surface. Based on a preset threshold adjustment parameter, a threshold adjustment injection is performed on the intermediate processing surface to obtain a threshold adjustment injection region. The sacrificial oxide layer in the threshold-adjusted implantation region is removed to obtain the final processed surface, and a gate oxide layer covering the ion implantation region is constructed on the final processed surface to obtain a gate dielectric structure.

2. The method according to claim 1, characterized in that, The construction of a sacrificial barrier layer on a semiconductor substrate based on injection mask data to obtain an injection opening structure includes: The semiconductor substrate is subjected to thermal oxidation to obtain a sacrificial oxide layer, and polycrystalline silicon is deposited on the sacrificial oxide layer to obtain a polycrystalline silicon layer; The polysilicon layer is patterned based on the implantation mask data to obtain a sacrificial barrier layer with an implantation region, and the implantation opening structure is generated based on the sacrificial oxide layer and the implantation region.

3. The method according to claim 2, characterized in that, The step of patterning the polysilicon layer based on the implantation mask data to obtain a sacrificial barrier layer with implantation regions includes: The polysilicon layer is photolithographically processed based on the bulk region implantation photomask to obtain a photoresist masking layer corresponding to the implantation mask data. The polysilicon layer is dry etched using the photoresist masking layer as a mask to obtain the implantation region, thereby generating a sacrificial barrier layer with the implantation region.

4. The method according to claim 1, characterized in that, The self-aligned ion implantation based on the sacrificial barrier layer and the implantation opening structure to obtain the ion implantation region includes: Using the sacrificial barrier layer as a self-aligned mask, self-aligned ion implantation of the first conductivity type is performed based on the implantation opening structure to generate a hole-type body region in the semiconductor substrate; After obtaining the hole-type region, using the sacrificial barrier layer as a self-aligned mask, self-aligned ion implantation of the second conductivity type is performed based on the implantation opening structure to generate an electron-type source region within the hole-type region. The ion implantation region is formed by the hole-type region and the electron-type source region.

5. The method according to claim 4, characterized in that, The self-aligned ion implantation of the first conductivity type based on the implantation opening structure, generating a hole-type body region within the semiconductor substrate, includes: Using the sacrificial barrier layer as the injection barrier layer, ions of the first conductivity type are injected into the injection opening structure; The semiconductor substrate after ion implantation is subjected to high-temperature push-well to obtain the hole-type body region.

6. The method according to claim 4, characterized in that, The self-aligned ion implantation of the second conductivity type based on the implantation opening structure, generating an electron source region within the hole-type body region, includes: Using the sacrificial barrier layer as the injection barrier layer, ions of a second conductivity type are injected into the injection opening structure; The semiconductor substrate after ion implantation is subjected to high-temperature push-well treatment to obtain the electron source region within the hole-type body region.

7. The method according to claim 1, characterized in that, The sacrificial barrier layer is removed to obtain an intermediate processed surface. A threshold adjustment injection is then performed on the intermediate processed surface based on a preset threshold adjustment parameter to obtain a threshold-adjusted injection region, including: The polysilicon layer constituting the sacrificial barrier layer is removed by an etching process, while the sacrificial oxide layer located on the surface of the active region of the semiconductor substrate is retained, to obtain an intermediate processed surface. Using the sacrificial oxide layer as an implantation buffer layer, ion implantation of the second conductivity type is performed on the intermediate treatment surface based on a preset implantation energy and a preset implantation dose; By controlling ions of the second conductivity type to penetrate the sacrificial oxide layer and enter the surface layer of the semiconductor substrate, a threshold-controlled implantation region is obtained.

8. The method according to claim 1, characterized in that, The process involves removing the sacrificial oxide layer in the threshold-adjusted implantation region to obtain a final processed surface, and then constructing a gate oxide layer covering the ion implantation region on the final processed surface to obtain a gate dielectric structure, including: The sacrificial oxide layer on the surface of the threshold-adjusted implantation region is removed by wet etching, and the single-crystal silicon surface of the semiconductor substrate is retained as the final processed surface. Thermal oxidation is performed on the final processed surface to obtain a gate oxide layer, which covers the ion implantation region and constitutes the gate dielectric structure.

9. The method according to claim 1, characterized in that, After obtaining the gate dielectric structure, the following is also included: An interlayer dielectric layer is deposited on the gate dielectric structure and the final processed surface; The interlayer dielectric layer is patterned and etched to obtain contact holes that penetrate the interlayer dielectric layer, and the contact holes expose a portion of the electron source region; A metal layer is deposited on the interlayer dielectric layer and inside the contact hole, and the metal layer is patterned to obtain a metal source electrode electrically connected to the electronic source region.

10. A depletion-mode MOSFET structure for improving VTH uniformity, characterized in that, include: A semiconductor substrate having an active region; An ion implantation region, the ion implantation region including a hole-type region obtained within the active region and an electron-type source region obtained within the hole-type region; The lateral diffusion boundary of the hole-type body region and the lateral diffusion boundary of the electron-type source region together define the channel region within the semiconductor substrate. The gate dielectric structure consists of a gate oxide layer that directly covers the surface of the channel region and the threshold injection region; An interlayer dielectric layer covers the gate dielectric structure and the semiconductor substrate, and has contact holes inside that expose a portion of the electron source region; The metal source electrode is located above the interlayer dielectric layer and is electrically connected to the electron-type source region through the contact hole.

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