A method for constructing a clean interface field-effect transistor and the transistor itself.

Abstract

This invention belongs to the technical field of two-dimensional semiconductor device fabrication. It discloses a method for constructing a clean interface field-effect transistor and the transistor itself. The method includes: depositing a dielectric layer on the surface of a two-dimensional semiconductor material; coating a photoresist layer on the surface of the dielectric layer and patterning the photoresist layer with corresponding predetermined source and drain regions through exposure and development; etching the corresponding regions of the dielectric layer with the predetermined source and drain regions using an etching process in an etching gas environment to remove the dielectric layer at the corresponding locations; depositing a metal material in the etched areas of the dielectric layer to form source and drain electrodes; and then removing the photoresist layer to obtain the transistor device. This invention, through optimization of process steps and the combination of gas etching, avoids the process step of coating photoresist on the surface of the two-dimensional material, significantly reducing organic residues at the interface and achieving clean interface fabrication between the two-dimensional semiconductor material and the metal source and drain electrodes.

Description

Technical Field

[0001] This invention belongs to the technical field of two-dimensional semiconductor device fabrication, and more specifically, relates to a method for constructing a clean interface field-effect transistor and the transistor itself. Background Technology

[0002] Moore's Law states that the number of components that can be placed on an integrated circuit doubles every 18-24 months, and performance also doubles, placing higher demands on the size and performance of electronic devices. As the size of electronic devices continues to shrink, scaling traditional transistors becomes increasingly difficult. When the thickness of three-dimensional materials drops below 5 nm, short-channel effects may occur, leading to problems such as increased drain current and lower threshold voltage, severely affecting the normal operation of the device. Graphene, as the first discovered two-dimensional (2D) material, opened up a new field of two-dimensional field-effect transistors (2D FETs) with its unique electrical, optical, mechanical, and thermal properties. Subsequently, various two-dimensional materials, such as transition metal dihalides (TMDs), black phosphorus (BP), and hexagonal boron nitride (hBN), have been extensively studied due to their inherent properties. Two-dimensional materials are formed by out-of-plane van der Waals forces and can be mechanically exfoliated into monolayers with a typical thickness of less than 1 nm. Compared to traditional bulk materials, two-dimensional materials have thinner atomic structures and naturally uniform, dangling-bond-free surfaces, offering promising prospects for transistor scaling and demonstrating performance that surpasses traditional silicon-based FETs, such as higher switching speeds, lower power consumption, and better integration potential.

[0003] The high surface area to volume ratio of two-dimensional materials makes the interfacial properties between them and the electrodes / gates significantly impact device performance. Environmental effects, such as the adsorption of gases and water molecules, also affect interfacial properties. Dangling bonds, impurities, and defects at the interface can lead to additional scattering and trapping centers, thereby reducing carrier mobility and the device's on / off ratio. Well-known two-dimensional semiconductor device fabrication processes involve multiple steps, including substrate preparation and cleaning, two-dimensional material stripping and transfer, photolithography and patterning, electrode fabrication, gate dielectric deposition, annealing, and performance tuning. In photolithography, PMMA residue generated by electron beam exposure negatively impacts subsequent electrode metal deposition steps, severely degrading the interfacial properties between the two-dimensional material and the electrodes. Furthermore, in the micro / nano fabrication of two-dimensional semiconductor devices, dielectric layer removal or patterning typically requires dry etching methods such as plasma etching. However, existing two-dimensional semiconductor materials generally have poor tolerance to etching processes, easily leading to lattice damage, defect introduction, and channel performance degradation during etching.

[0004] Therefore, existing technologies for fabricating two-dimensional field-effect transistors (FETs) inevitably introduce organic residues and reduce interface cleanliness due to reliance on photolithography for structural definition. Thus, developing an effective technique for constructing clean interfaces is a crucial step in realizing high-performance two-dimensional FETs. Summary of the Invention

[0005] In view of the above-mentioned defects or improvement needs of the prior art, the present invention provides a method for constructing a clean interface field-effect transistor and a transistor, which solves the problem that the existing technology relies on photolithography process for structural definition, which inevitably introduces organic residues and reduces the cleanliness of the interface.

[0006] To achieve the above objectives, according to one aspect of the present invention, a method for constructing a clean interface field-effect transistor is provided, comprising: A dielectric layer is formed on the surface of a two-dimensional semiconductor material through a deposition process; A photoresist layer is coated on the surface of the dielectric layer, and the photoresist layer is patterned with respect to the pre-defined source and drain regions by exposure and development. The dielectric layer is etched in an etching gas environment to remove the dielectric layer at the corresponding locations of the preset source and drain regions using an etching process. Metal material is deposited in the etched region of the dielectric layer to form source and drain electrodes, and then the photoresist layer is removed to obtain a transistor device.

[0007] The method for constructing a clean interface field-effect transistor according to the present invention further includes, before coating the dielectric layer with a photoresist layer: A top gate electrode is fabricated on the dielectric layer; Accordingly, coating the dielectric layer with a photoresist layer specifically involves coating the dielectric layer and the top gate electrode with photoresist.

[0008] According to the method for constructing a clean interface field-effect transistor provided by the present invention, the two-dimensional semiconductor material is selected as a two-dimensional indium-based semiconductor material; the etching gas is selected as a fluorine-based etching gas.

[0009] According to the method for constructing a clean interface field-effect transistor provided by the present invention, the two-dimensional indium-based semiconductor material is InSe; the fluorine-based etching gas includes SF6.

[0010] According to the method for constructing a clean interface field-effect transistor provided by the present invention, the dielectric layer is selected from at least one of HfO2 layer, Sb2O3 layer and hBN layer.

[0011] According to the method for constructing a clean interface field-effect transistor provided by the present invention, the dielectric layer is an HfO2 / Sb2O3 composite dielectric layer, including an Sb2O3 layer disposed in contact with a two-dimensional semiconductor material and an HfO2 layer located on the side of the Sb2O3 layer away from the two-dimensional semiconductor material; the Sb2O3 layer serves as an interface buffer layer, and the HfO2 layer serves as a high-k gate dielectric layer.

[0012] According to the clean interface field-effect transistor construction method provided by the present invention, inductively coupled plasma-reactive ion etching is used as the etching process. The plasma density of the etching process is controlled by the ICP power, and the ion bombardment energy is controlled by the RF bias power. By controlling the ICP power, RF bias power, etching gas flow rate and etching chamber pressure parameters, the etching depth and morphology of the dielectric layer can be precisely controlled.

[0013] According to the method for constructing a clean interface field-effect transistor provided by the present invention, the etching process specifically uses a mixture of SF6 and Ar as the etching gas; the gas flow rates of SF6 and Ar are 30 sccm and 5 sccm, respectively.

[0014] According to the method for constructing a clean interface field-effect transistor provided by the present invention, the ICP power is set to 300 W and the RF bias power is set to 50 W.

[0015] According to another aspect of the present invention, a clean interface field-effect transistor is provided, which is prepared by the method for constructing a clean interface field-effect transistor as described in any of the preceding claims.

[0016] In summary, compared with the prior art, the clean interface field-effect transistor construction method and transistor provided by this invention offer the following advantages: 1. By optimizing the process steps and combining gas etching, the source and drain electrode materials are directly prepared based on the two-dimensional material itself during the preparation process, avoiding the process step of coating photoresist on the surface of the two-dimensional material, significantly reducing organic residues at the interface, and realizing the preparation of a clean interface between the two-dimensional semiconductor material and the metal source and drain electrodes, which is beneficial to improving the electrical performance stability and device consistency of the field-effect transistor. 2. Taking advantage of the etching resistance of two-dimensional indium-based semiconductor materials to fluorine-based etching gases (such as SF6), it is proposed to select two-dimensional indium-based semiconductor materials and fluorine-based etching gases. This allows the patterned dielectric layer to be etched to expose the predetermined source and drain electrode regions without causing etching damage to the underlying two-dimensional semiconductor channel material, further avoiding the formation of interface defects and improving device performance. 3. The dielectric layer preparation technology (such as thermal evaporation and atomic layer deposition) and subsequent dry etching process used in this invention are all mature standard semiconductor manufacturing processes, which are easy to realize large-scale preparation and device integration. This feature makes the method of this invention not only suitable for laboratory research, but also able to support large-scale, wafer-level device array preparation, and easy to integrate with other functional modules on chip. 4. The device fabrication method is applicable to a variety of different dielectric layers, and the type and thickness of the dielectric layer can be adjusted as needed, providing high flexibility; the etching process adopts inductively coupled plasma-reactive ion etching technology. The advantage of this technology is that its plasma density is controlled by ICP power and ion bombardment energy is controlled by RF bias power, so they can be independently and precisely controlled. By optimizing the combination of process parameters (such as power, gas ratio, and pressure) and controlling the etching time, precise control of the etching depth of the dielectric layer can be achieved, ensuring efficient removal of the dielectric layer while minimizing damage to the two-dimensional channel material. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the construction method of a clean interface field-effect transistor in an embodiment of the present invention.

[0018] Figure 2 This is a schematic diagram illustrating the effect of the selective etching step in an embodiment of the present invention.

[0019] Figure 3 This is an AFM characterization of the HfO2 / Sb2O3 dielectric layer before and after deposition on the InSe surface in this embodiment of the invention.

[0020] Figure 4 This is the back gate transfer characteristic curve of the clean interface device after annealing in this embodiment of the invention, with an on / off ratio of up to 10. 9 The migration rate is approximately 56 cm. 2 ·V -1 · s -1 .

[0021] Figure 5 This is the back gate output characteristic curve of the clean interface device after annealing in this embodiment of the invention. The contact effect of the device has been significantly improved, showing a better ohmic contact.

[0022] Figure 6 This is the top gate transfer characteristic curve of the clean interface device after annealing in this embodiment of the invention. The highest on / off ratio of the device is 10. 9 The subthreshold swing amplitude (SS) can reach as low as approximately 60 mV·dec. -1 .

[0023] Figure 7This is a cross-sectional STEM image of the channel position of the clean interface device after annealing in an embodiment of the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0025] Please see Figure 1 This embodiment provides a method for constructing a clean interface field-effect transistor, the method comprising: A dielectric layer is formed on the surface of a two-dimensional semiconductor material through a deposition process; A photoresist layer is coated on the surface of the dielectric layer, and the photoresist layer is patterned with respect to the pre-defined source and drain regions by exposure and development. The dielectric layer is etched in an etching gas environment to remove the dielectric layer at the corresponding locations of the preset source and drain regions using an etching process. Metal material is deposited in the etched region of the dielectric layer to form source and drain electrodes, and then the photoresist layer is removed to obtain a transistor device.

[0026] In this embodiment, by optimizing the process steps and combining them with gas etching, a dielectric layer is first deposited on the surface of a two-dimensional material. Then, photoresist is used to pattern the corresponding source and drain regions on the dielectric layer surface. Gas etching is then used to remove the corresponding portions of the dielectric layer and source / drain regions, exposing the pre-defined source / drain regions on the two-dimensional material. Finally, source and drain electrodes are fabricated by depositing metal material. In this fabrication process, the source and drain electrode materials are directly fabricated based on the two-dimensional material itself, avoiding the process of coating the two-dimensional material surface with photoresist. This significantly reduces organic residues at the interface, achieving a clean interface between the two-dimensional semiconductor material and the metal source / drain electrodes. This is beneficial for improving the electrical performance stability and device consistency of the field-effect transistor. Furthermore, the dielectric layer deposition (e.g., atomic layer deposition) and etching processes involved in the fabrication are compatible with mainstream semiconductor manufacturing processes, possessing good process inheritance and scalability, which is beneficial for industrial applications.

[0027] In some embodiments, the process further includes, prior to coating the photoresist layer onto the dielectric layer surface: A top gate electrode is fabricated on the dielectric layer; Accordingly, coating the dielectric layer with a photoresist layer specifically involves coating the dielectric layer and the top gate electrode with photoresist.

[0028] In this embodiment, the top gate electrode can be fabricated based on photolithography patterning and metal deposition processes. That is, photoresist is first coated on the surface of the dielectric layer, then the top gate electrode area is patterned to expose it, and then the top gate electrode is fabricated by depositing metal in the exposed area.

[0029] In some embodiments, further considering that etching processes are unavoidable in the process of device structure construction and pattern definition, and that two-dimensional materials themselves are highly sensitive to the etching process and are prone to device performance degradation due to etching damage, how to complete the device structure construction without damaging the two-dimensional semiconductor material and at the same time achieve a high-cleanliness interface remains a technical problem that urgently needs to be solved in this field.

[0030] To address the above issues, this embodiment proposes using a two-dimensional indium-based semiconductor material and a fluorine-based etching gas. This embodiment leverages the etching resistance of the two-dimensional indium-based semiconductor material to fluorine-based etching gases (e.g., SF6) to innovate the device fabrication process: first, a dielectric layer is completely deposited on the surface of the two-dimensional material; then, selective etching is used to pattern the dielectric layer to expose predetermined source and drain electrode regions without causing etching damage to the underlying two-dimensional semiconductor channel material. Figure 2 As shown, metal is finally deposited in this region to form an electrode. Furthermore, based on the etching resistance of indium-based materials to the fluorine-based etching gas SF6, polymer non-contact was achieved on the surface of the two-dimensional material during device fabrication. No polymer residue remains at the contact site between the two-dimensional material and the metal electrode. The surface properties of the two-dimensional material are preserved, allowing the fabricated device to exhibit its intrinsic characteristics.

[0031] The principle behind the etching resistance of two-dimensional indium-based semiconductor materials to fluorine-based etching gases (such as SF6) is as follows: In gas etching processes, the chemical etching rate depends on the reaction efficiency between active free radicals and the material to be etched. When the reaction products are gaseous, they can be promptly discharged from the chamber, ensuring continuous etching. For example, a mixed plasma of SF6 and N2 can etch transition metal chalcogenides (TMDs) such as MoS2, with reaction products including gaseous substances such as MoF3 and F2, effectively driving the etching process. However, when SF6 is used to etch indium (In)-based materials, the etching rate is significantly reduced. The main reason for this phenomenon is that the indium trifluoride (InF3) generated in the etching reaction is solid in the etching chamber environment, making it difficult to effectively remove from the reaction system, thus hindering further contact and reaction between SF6 and the surface of the material to be etched.

[0032] In some embodiments, the two-dimensional indium-based semiconductor material is InSe; the fluorine-based etching gas includes SF6. The two-dimensional indium-based semiconductor material used in this embodiment is InSe, whose effective electron mass (m) is... eThe extremely low electron transport properties (m0 = 0.143) of InSe, which are less affected by the number of layers, allow InSe to maintain high electron mobility even over thicker layers. Therefore, research on InSe in the fabrication of high-mobility, low-power field-effect transistors has attracted considerable attention, making it suitable for verifying the feasibility of this embodiment. Using the high-mobility two-dimensional semiconductor InSe as the channel to construct a field-effect transistor further demonstrates the advantages of this transistor fabrication method. It should be noted that InSe is only the experimental material used from the perspective of field-effect transistor performance; the principle of the scheme adopted in this embodiment can also be applied to the fabrication of other two-dimensional indium-based transistor devices.

[0033] In some embodiments, the dielectric layer is selected from at least one of an HfO2 layer, a Sb2O3 layer, and an hBN layer. Optionally, the dielectric layer is an HfO2 / Sb2O3 composite dielectric layer, comprising an Sb2O3 layer disposed in contact with the two-dimensional semiconductor material and an HfO2 layer located on the side of the Sb2O3 layer away from the two-dimensional semiconductor material; the Sb2O3 layer serves as an interface buffer layer, and the HfO2 layer serves as a high-k gate dielectric layer. The combination of the two ensures a high dielectric constant while forming a good interface with the two-dimensional indium-based semiconductor material, synergistically demonstrating the performance advantages of clean interface devices. The material-selective etching approach adopted in this method can be extrapolated to various dielectric layer material systems.

[0034] In some embodiments, inductively coupled plasma-reactive ion etching (ICP-RIE) is used as the etching process. ICP-RIE is a dry etching technique that achieves high etching rates, high anisotropy, and high selectivity by separating plasma generation and ion energy control, and is suitable for the fabrication of two-dimensional field-effect transistors. The plasma density of the etching process is controlled by the ICP power, and the ion bombardment energy is controlled by the RF bias power. By controlling the ICP power, RF bias power, etching gas flow rate, and etching chamber pressure parameters, precise control of the etching depth and morphology of the dielectric layer is achieved.

[0035] In some embodiments, the etching process specifically uses a mixed gas of SF6 and Ar as the etching gas; the etching gas is mainly SF6, taking advantage of the fact that the etching rate of SF6 on the two-dimensional indium-based semiconductor channel layer is significantly lower than that on the composite dielectric layer. This allows for selective etching while completely removing the dielectric layer and maintaining the integrity of the channel material's crystal structure and good electrical properties. This mixed gas system is suitable for etching various dielectric materials such as HfO2 / Sb2O3 and hBN. By precisely adjusting the gas flow rates of SF6 and Ar and the reaction chamber pressure, the desired etching rate and selectivity can be obtained based on the material composition and thickness of the dielectric layer.

[0036] Optionally, the gas flow rates of SF6 and Ar are 30 sccm and 5 sccm, respectively. Under these parameters, the etching process is dominated by the chemical etching reaction of the dielectric layer by the fluorine-based active material generated by SF6, supplemented by the moderate physical bombardment of Ar ions to maintain anisotropic etching morphology and promote the desorption of byproducts. This gas ratio maximizes the etching selectivity between the dielectric layer and the InSe channel, efficiently and thoroughly removing the dielectric layer while reducing physicochemical damage to the InSe surface. The ICP power is set to 300 W and the RF power is set to 50 W, where the ICP module is responsible for plasma generation and the RF module controls the ion bombardment intensity. This power ratio can increase the proportion of chemical etching and further enhance etching selectivity.

[0037] Preferably, the etching process is equipped with a high-precision mass flow controller and an in-situ film thickness monitoring system (such as a crystal oscillator). By monitoring and adjusting the etching gas flow rate in real time and with feedback, the uniformity of gas conditions in each process cycle can be ensured. The etching process uses a cluster of equipment with independent sample inlet chambers and high-vacuum etching chambers. This design allows the sample to be pre-vacuumed in the sample inlet chamber before being transferred into the etching chamber, significantly shortening the time from the atmospheric environment to the working chamber, thereby reducing the contact between InSe and air. During sample injection in the etching process, a small amount of silicone oil is evenly applied to the back of the sample to be etched, which serves both as sample fixation and heat transfer, preventing sample displacement and excessively high local temperatures during the etching process.

[0038] Preferably, the sample is immediately sent into a high-vacuum coating instrument after etching to reduce the time the InSe surface is exposed to air, avoid oxidation or adsorption contamination of the fresh InSe surface after etching due to exposure to air, and ensure atomic-level cleanliness and chemical stability of the metal-semiconductor interface.

[0039] In some embodiments, the method for constructing a clean interface field-effect transistor further includes, between depositing a dielectric layer on the surface of a two-dimensional semiconductor material: preparing a two-dimensional semiconductor material on a SiO2 / Si substrate by mechanical exfoliation; and after removing the photoresist layer, further including: performing an annealing process.

[0040] This embodiment addresses the common problem that two-dimensional materials are generally poorly resistant to plasma etching processes in the fabrication of existing two-dimensional semiconductor devices. During the removal or patterning of the dielectric layer in the source / drain regions, the etching process easily damages the two-dimensional semiconductor channel material, introducing defects and contamination at the interface, leading to device performance degradation and reduced consistency. To avoid etching damage, traditional processes typically rely on photolithography techniques such as electron beam lithography to define the pattern. However, these processes inevitably introduce photoresist and its residues, thereby reducing the cleanliness of the interface between the two-dimensional material and the metal electrodes and dielectric layer. To address these issues, this embodiment proposes a device fabrication method that achieves a clean interface while avoiding etching damage to the two-dimensional material. The method includes the following steps: forming a dielectric layer (e.g., HfO2) on the surface of an indium-based two-dimensional material through a deposition process, and fabricating a top gate electrode on the dielectric layer; subsequently, selectively etching the dielectric layer in a fluorine-based etching gas environment (e.g., SF6) by utilizing the etching selectivity of the indium-based two-dimensional semiconductor material relative to the dielectric material, thereby removing only the dielectric layer above the source and drain regions without causing etching damage to the underlying two-dimensional semiconductor channel material; further depositing metal material in the etched exposed areas to form source and drain electrodes. Through the above fabrication method, the formation process of the source and drain electrodes does not require the introduction of organic materials such as photoresist, significantly reducing organic residues and defect density at the interface, thereby effectively reducing charge scattering and interface traps, and improving the electrical performance stability and device consistency of the field-effect transistor.

[0041] In some embodiments, a clean interface field-effect transistor is also provided, which is prepared by the method for constructing a clean interface field-effect transistor as described in any of the preceding embodiments.

[0042] Specific examples Figure 1 This is a schematic diagram of the method for constructing a clean interface field-effect transistor using selective etching, as described in this specific example. On a 300 nm SiO2 / Si substrate, the two-dimensional semiconductor material InSe is mechanically exfoliated as the channel material. HfO2 / Sb2O3 is used as the dielectric layer. First, 3 nm of Sb2O3 is deposited on the InSe surface by thermal evaporation. Then, 7 nm of HfO2 is prepared on top of the Sb2O3 using atomic layer deposition to form a composite dielectric layer. The HfO2 / Sb2O3 dielectric layer exhibits good compatibility with the two-dimensional material. Its AFM characterization before and after deposition on the InSe surface is as follows: Figure 3As shown, the InSe surfaces after Sb₂O₃ deposition and HfO₂ deposition are highly uniform, with roughness less than 0.5 nm, meeting the conditions for further fabrication of two-dimensional field-effect transistors. Subsequently, the top gate electrode of the device was fabricated. The source and drain electrode regions were patterned using electron beam lithography (EBL), and the dielectric layer in these regions was removed using selective etching. Specific etching parameters were: SF₆ / Ar gas flow rate 30 / 5 sccm, ICP power 300 W, RF power 50 W, and etching time 130 s. A schematic diagram of the etching steps is shown below. Figure 2 As shown, source and drain electrode metals were subsequently deposited, followed by a lift-off process in acetone at 55 °C for 2 h. The device was then annealed at 150 °C for 0.5 h in an environment with an Ar / H2 gas flow rate of 90 / 10 sccm. The back-gate transfer characteristic curve, back-gate output curve, and top-gate transfer characteristic curve of the device were then tested, as shown in the figures below. Figure 4 , Figure 5 and Figure 6 As shown. After the device fabrication was completed, a cross-sectional STEM test was performed on the channel location, and the resulting image is shown below. Figure 7 As shown.

[0043] Figure 1 This is a schematic diagram illustrating the method for constructing a clean interface field-effect transistor using selective etching in an example. An Sb₂O₃ / HfO₂ dielectric layer is prepared on the surface of a mechanically stripped indium-based two-dimensional semiconductor material via thermal evaporation and atomic layer deposition. First, the top gate electrode is prepared. Then, based on the etching resistance of the indium-based material to the fluorine-based etching gas SF₆, the dielectric layer at the source and drain electrodes is etched away without damaging the two-dimensional material. Finally, metal is deposited as the source and drain electrodes.

[0044] Figure 2 This is a schematic diagram illustrating the effect of the selective etching step. During the etching process, the dielectric layer reacts with the etching gas to generate volatile gases, which drive the etching reaction. However, due to the non-volatility of the etching reaction product InF3, the etching of indium-based two-dimensional materials is stopped, thus achieving the effect of selective etching.

[0045] Figure 3AFM characterization of the HfO2 / Sb2O3 dielectric layer before and after deposition on the InSe surface in this example shows that the HfO2 / Sb2O3 dielectric layer prepared on the InSe surface has high uniformity. A 3 nm Sb2O3 film deposited on the InSe surface exhibits a uniform and continuous fine-grained morphology, with no obvious interdomain gaps or pore defects. The surface smoothness is excellent, and it achieves complete and dense coverage of the InSe surface, providing an ideal interface substrate for subsequent HfO2 deposition and meeting the structural requirements of the buffer layer. A 7 nm HfO2 layer was prepared on the 3 nm Sb2O3 buffer layer via atomic layer deposition. It can be seen that the composite dielectric layer still maintains a uniform and continuous surface morphology, without obvious pores, wrinkles, or local protrusions, and its roughness is comparable to that of the Sb2O3 buffer layer. This indicates that HfO2 achieved uniform and defect-free growth on the Sb2O3 surface without introducing additional interface defects.

[0046] Figure 4 This is the back-gate transfer characteristic curve of the clean interface device after annealing in the example. After annealing, the device performance is improved, and the on / off ratio can reach 10. 9 The migration rate is approximately 56 cm. 2 ·V -1 ·s -1 .

[0047] Figure 5 This is the back-gate output characteristic curve of the clean interface device after annealing in the example, where the current varies with V. ds The linear growth and the intersection point approaching the origin further confirm that the source / drain electrodes and the InSe channel interface form an ohmic contact with low contact resistance, which greatly improves the carrier injection efficiency and the transport process is no longer hindered by the interface barrier.

[0048] Figure 6 This is the top-gate transfer characteristic curve of the clean interface device after annealing in the example. The results show that the highest switching ratio of the device is 10 under different back-gate voltages. 9 The subthreshold swing amplitude (SS) can reach as low as approximately 60 mV·dec. -1 The Boltzmann limit further demonstrates the device's excellent gate control efficiency, fully verifying the superiority of the composite dielectric layer structure and the clean interface process based on selective etching, and realizing the construction of high-performance InSe top-gate transistors.

[0049] Figure 7 This is a cross-sectional STEM image of the channel location of the clean interface device after annealing in the example. The interface between HfO2 / Sb2O3 and InSe is clearly visible with no polymer residue, and Sb2O3 exhibits atomic-level homogeneity on the InSe surface.

[0050] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for constructing a clean interface field-effect transistor, characterized in that, include: A dielectric layer is formed on the surface of a two-dimensional semiconductor material through a deposition process; A photoresist layer is coated on the surface of the dielectric layer, and the photoresist layer is patterned with respect to the pre-defined source and drain regions by exposure and development. The dielectric layer is etched in an etching gas environment to remove the dielectric layer at the corresponding locations of the preset source and drain regions using an etching process. Metal material is deposited in the etched region of the dielectric layer to form source and drain electrodes, and then the photoresist layer is removed to obtain a transistor device.

2. The method for constructing a clean interface field-effect transistor as described in claim 1, characterized in that, Before coating the photoresist layer on the dielectric layer surface, the following steps are also included: A top gate electrode is fabricated on the dielectric layer; Accordingly, coating the dielectric layer with a photoresist layer specifically involves coating the dielectric layer and the top gate electrode with photoresist.

3. The method for constructing a clean interface field-effect transistor as described in claim 1, characterized in that, Two-dimensional indium-based semiconductor material was selected as the two-dimensional semiconductor material; fluorine-based etching gas was selected as the etching gas.

4. The method for constructing a clean interface field-effect transistor as described in claim 3, characterized in that, The two-dimensional indium-based semiconductor material is InSe; the fluorine-based etching gas includes SF6.

5. The method for constructing a clean interface field-effect transistor as described in claim 1, characterized in that, The dielectric layer is selected from at least one of HfO2 layer, Sb2O3 layer and hBN layer.

6. The method for constructing a clean interface field-effect transistor as described in claim 5, characterized in that, The dielectric layer is an HfO2 / Sb2O3 composite dielectric layer, including an Sb2O3 layer disposed in contact with the two-dimensional semiconductor material and an HfO2 layer located on the side of the Sb2O3 layer away from the two-dimensional semiconductor material; the Sb2O3 layer serves as an interface buffer layer and the HfO2 layer serves as a high-k gate dielectric layer.

7. The method for constructing a clean interface field-effect transistor as described in claim 1, characterized in that, Inductively coupled plasma-reactive ion etching (ICP-REI) is used as the etching process. The plasma density of the etching process is controlled by the ICP power, and the ion bombardment energy is controlled by the RF bias power. By controlling the ICP power, RF bias power, etching gas flow rate, and etching chamber pressure parameters, the etching depth and morphology of the dielectric layer can be precisely controlled.

8. The method for constructing a clean interface field-effect transistor as described in claim 7, characterized in that, The etching process specifically uses a mixture of SF6 and Ar as the etching gas; the gas flow rates of SF6 and Ar are 30 sccm and 5 sccm, respectively.

9. The method for constructing a clean interface field-effect transistor as described in claim 7, characterized in that, The ICP power is set to 300 W and the RF bias power is set to 50 W.

10. A clean interface field-effect transistor, characterized in that, It is prepared by the method for constructing a clean interface field-effect transistor according to any one of claims 1-9.

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