Fabrication method and NMOS structure

Abstract

This application provides a method for fabricating an NMOS structure and the NMOS structure itself. The method includes: providing a substrate; forming a gate structure and sidewalls on both sides of the gate structure on one side of the substrate, wherein the substrate regions on the outer sides of the gate structure are source / drain regions; forming a silicide barrier layer on one side of the substrate, such that the silicide barrier layer covers the gate structure, sidewalls, and source / drain regions of the substrate; patterning the silicide barrier layer; removing the silicide barrier layer corresponding to the source / drain regions of the substrate, thereby exposing the source / drain regions of the substrate; performing a silicon epitaxial process on the exposed source / drain regions of the substrate to form an epitaxial layer; and filling an interlayer dielectric trench defined by the silicide barrier layer and the epitaxial layer to form an interlayer dielectric layer. This application significantly reduces the trench depth-to-width ratio of conventional interlayer dielectric trenches, thereby reducing the difficulty of filling the interlayer dielectric layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a method for fabricating an NMOS structure and the NMOS structure itself. Background Technology

[0002] As semiconductor process nodes continue to evolve towards advanced nodes such as 28nm, 14nm, 7nm, and 3nm, transistor feature sizes continue to shrink, and the aspect ratio of trenches and gaps within devices continues to increase. In the fabrication of CMOS (Complementary Metal Oxide Semiconductor) devices, ILD0 (Zero Inter-Layer Dielectric) is used to isolate the transistor gate and source / drain regions, and is an indispensable insulating structure in advanced processes. Currently, HARP (High Aspect Ratio Process) is commonly used for dielectric filling of ILD0 trenches at 40nm and below process nodes. This process has excellent high aspect ratio gap filling capabilities, but it has stringent requirements on the morphology and aspect ratio of the ILD0 trenches. Typically, the trenches are required to be V-shaped structures with continuous sidewalls and a slope of no more than 86°; otherwise, voids or gap defects are easily formed inside the trenches after filling.

[0003] The ILD0 trenches of NMOS transistors are relatively deep, with aspect ratios reaching 3.5:1, exceeding the stable fill window of the HARP process. This excessive aspect ratio causes premature closure of the trench top during HARP deposition, preventing the dielectric from fully filling the trench bottom and resulting in voids or gaps. These defects can lead to metal bridging and short circuits in subsequent contact hole and interconnect fabrication processes, significantly reducing chip yield and device reliability.

[0004] To address the aforementioned void problem, existing technologies primarily adjust the ILD0 trench sidewall angle through dry etching morphology modification and silicon nitride pullback, or employ a composite filling process involving multiple HARP deposition (DEP) and etching (ETCH). However, these improvements only slightly optimize the trench morphology and cannot fundamentally reduce the aspect ratio of the NMOS ILD0 trench, leaving voids and seam defects. Furthermore, multiple deposition and etching processes increase process complexity, raise production costs, and further introduce process deviations, compressing the process window. Summary of the Invention

[0005] To address the problems in the prior art, the purpose of this application is to provide a method for fabricating an NMOS structure and an NMOS structure that significantly reduces the trench depth-to-width ratio of conventional interlayer dielectric trenches, thereby reducing the difficulty of filling the interlayer dielectric layer.

[0006] This application provides a method for fabricating an NMOS structure, including: A substrate is provided, on one side of the substrate a gate structure and sidewalls respectively disposed on both sides of the gate structure, the substrate regions on the outer sides of the gate structure are source and drain regions; A silicide barrier layer is formed on one side of the substrate, such that the silicide barrier layer covers the gate structure, the sidewall, and the source / drain regions of the substrate; The silicide barrier layer is patterned to remove the silicide barrier layer corresponding to the source / drain regions of the substrate, thereby exposing the source / drain regions of the substrate. Silicon epitaxy is performed on the exposed source and drain regions of the substrate to form an epitaxial layer; An interlayer dielectric layer is formed by filling the interlayer dielectric trench defined by the silicide barrier layer and the epitaxial layer.

[0007] In some embodiments, a silicon epitaxial process is performed on the exposed source / drain regions of the substrate, including a selective monocrystalline silicon epitaxial process is performed on the exposed source / drain regions of the substrate to form a monocrystalline silicon epitaxial layer.

[0008] In some embodiments, when performing selective single-crystal silicon epitaxy on the exposed source / drain regions of the substrate, a low-pressure chemical vapor deposition process is used, the reaction gas source is silane and borane, the epitaxy temperature is 500°C to 580°C, and the epitaxy pressure is controlled at 10 to 20 Torr.

[0009] In some embodiments, after performing a silicon epitaxial process on the exposed source / drain regions of the substrate to form an epitaxial layer, and before filling the interlayer dielectric trench defined by the silicide barrier layer and the epitaxial layer, the following steps are further included: Remove the silicide oxide layer and sidewalls located on top of the gate structure.

[0010] In some embodiments, the trench depth-to-width ratio of the interlayer medium trench is 1:1 to 2:1.

[0011] In some embodiments, dielectric filling is performed in the interlayer dielectric trench defined by the silicide barrier layer and the epitaxial layer, including: A high aspect ratio filling process is used to fill the dielectric in the interlayer dielectric trench defined by the silicide barrier layer and the epitaxial layer.

[0012] In some embodiments, the silicide barrier layer is patterned, including: The photolithography process and the dry etching process are performed sequentially. The photoresist mask formed by the photolithography process exposes only the source and drain regions of the substrate, and the silicide barrier layer corresponding to the source and drain regions of the substrate is removed by the dry etching process.

[0013] In some embodiments, the silicide barrier layer is patterned, and the silicide barrier layer corresponding to the source / drain regions of the substrate is removed to expose the source / drain regions of the substrate. Before forming the epitaxial layer, a silicon epitaxial process is performed on the exposed source / drain regions of the substrate, and the following steps are further included: The exposed source and drain areas of the substrate are wet-cleaned.

[0014] In some embodiments, the substrate is a single-crystal silicon substrate, a silicon carbide substrate, a gallium nitride substrate, or a diamond substrate.

[0015] This application also provides an NMOS structure, including: A substrate, wherein a gate structure and sidewalls are respectively disposed on both sides of the gate structure, and the substrate regions on the outer sides of the gate structure are source and drain regions; A silicide barrier layer covers the outer side of the sidewall; An epitaxial layer is formed in the source / drain region of the substrate, and the sidewalls and the epitaxial layer together define an interlayer dielectric trench; An interlayer dielectric layer is filled inside the interlayer dielectric trench.

[0016] The fabrication method and NMOS structure provided in this application have the following advantages: This application grows an epitaxial layer after removing the silicide barrier layer in the source / drain region. The epitaxial layer can raise the bottom of the interlayer dielectric trench from bottom to top, effectively reducing the effective depth of the interlayer dielectric trench, reducing the overall aspect ratio of the trench, optimizing the trench morphology, adapting to the filling window of the interlayer dielectric, and significantly widening the process window for void-free filling of the zero-layer interlayer dielectric trench of NMOS devices. During the filling process, the top of the trench will not close prematurely, and the dielectric can completely fill the bottom of the trench, fundamentally avoiding the generation of voids and seam defects inside the trench, preventing metal bridging and device short circuits in subsequent contact hole preparation and metal wiring processes, and significantly improving chip yield and long-term transistor reliability. Attached Figure Description

[0017] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0018] Figure 1 This is a method for fabricating an NMOS structure according to an embodiment of this application; Figure 2These are transmission electron microscope (TEM) comparison images of the interlayer dielectric trench portion of existing 28nm PMOS and NMOS structures; Figures 3-6 This is a flowchart of a method for fabricating an NMOS structure according to an embodiment of this application; Figure 7 These are transmission electron microscope (TEM) comparison images of the interlayer dielectric trench portion of the NMOS structure obtained using the fabrication method of this application and the existing PMOS structure. Figure 8 This is a transmission electron microscope image of an NMOS structure according to an embodiment of this application.

[0019] Figure label: 100 - Substrate; 110 - Source / drain region; 200 - Gate structure; 300 - Sidewall; 400 - Silicate barrier layer; 500 - Epitaxial layer; 600 - Interlayer dielectric trench; 700 - Interlayer dielectric layer. Detailed Implementation

[0020] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Although the terms “upper,” “lower,” “between,” etc., may be used in this specification to describe different exemplary features and elements of this application, these terms are used herein only for convenience, such as the orientation of the examples described in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of this application. Although “first” or “second,” etc., are used in this specification to denote certain features, they are merely indicative of function and not as a limitation on the number or importance of specific features.

[0021] like Figure 1 As shown in the figure, this application provides a method for fabricating an NMOS structure, including: S100: A substrate is provided, on one side of which a gate structure and sidewalls are respectively disposed on both sides of the gate structure, and the substrate regions on the outer sides of the gate structure are source and drain regions. In this embodiment, the substrate is a single-crystal silicon substrate, a silicon carbide substrate, a gallium nitride substrate, or a diamond substrate; the gate structure includes, for example, an interface oxide layer, a dielectric layer, a work function regulating metal layer, a metal barrier layer, a tungsten conductive gate layer, and a gate top hard mask layer; the initially formed sidewalls wrap around the outer sides and top of the left and right sidewalls of the gate structure. S200: A silicide barrier layer is formed on one side of the substrate, so that the silicide barrier layer covers the gate structure, sidewalls and source / drain regions of the substrate; In this embodiment, the silicide barrier layer is a self-aligned silicide barrier layer; the silicide barrier layer covers the entire area of ​​one side of the substrate; S300: Pattern the silicide barrier layer and remove the silicide barrier layer corresponding to the source and drain regions of the substrate to expose the source and drain regions of the substrate. After step S300, the silicide barrier layer on the sidewalls and top of the gate structure remains intact; S400: Perform silicon epitaxy on the exposed source and drain regions of the substrate to form an epitaxial layer; In this embodiment, the epitaxial layer can lift the bottom of the interlayer dielectric trench from bottom to top; S500: Dielectric filling is performed in the interlayer dielectric trench defined by the silicide barrier layer and the epitaxial layer to form an interlayer dielectric layer; In this embodiment, the interlayer dielectric trench is an ILD0 trench; step S500: dielectric filling is performed in the interlayer dielectric trench defined by the silicide barrier layer and the epitaxial layer, including: A high aspect ratio process (HARP) is used to fill the interlayer dielectric trench defined by a silicide barrier layer and an epitaxial layer, wherein the material of the interlayer dielectric layer formed by the filling is silicon dioxide.

[0022] The method for fabricating the NMOS structure in this application involves growing an epitaxial layer after removing the silicide barrier layer in the source and drain regions. The epitaxial layer can raise the bottom of the interlayer dielectric trench from bottom to top, effectively reducing the effective depth of the interlayer dielectric trench, lowering the overall aspect ratio of the trench, optimizing the trench morphology, adapting to the filling window of the interlayer dielectric, and significantly widening the process window for void-free filling of the zero-layer interlayer dielectric trench of the NMOS device. During the filling process, the top of the trench will not close prematurely, and the dielectric can completely fill the bottom of the trench, fundamentally avoiding the generation of voids and seams inside the trench. This prevents metal bridging and device short circuits in subsequent contact hole fabrication and metal wiring processes, significantly improving chip yield and long-term transistor reliability.

[0023] The process solution proposed in this application can not only be applied to the HARP filling process of ILD0 trenches of NMOS devices at the 28nm process node, but also adapt to the high aspect ratio dielectric filling scenarios of ILD0 trenches at other advanced process nodes such as 14nm, 7nm, and 3nm. It has strong versatility and wide applicability.

[0024] In conventional 28nm CMOS device fabrication processes, after the gate structure and sidewalls of transistors are fabricated, ion implantation is commonly used to heavily dope the source and drain regions. Arsenic and phosphorus ions, among other dopants, form conductive source and drain electrodes. This is followed by RTA (Rapid Thermal Annealing) to repair silicon lattice damage caused by ion implantation and activate dopants. Simultaneously, the industry deposits a global SAB (Self-Aligned Silicide Block) to define the formation area for subsequent salicide deposition, preventing the formation of low-resistivity silicides in non-target areas that could cause device malfunctions.

[0025] For PMOS (Positive Metal Oxide Semiconductor) transistors, existing processes fabricate SiGe (Silicon Germanium) epitaxial layers in the source and drain regions. These epitaxial layers can raise the bottom of the ILD0 trench, keeping the aspect ratio of the ILD0 trench corresponding to the PMOS at a low level. The HARP process can stably achieve complete filling without voids or seams. Figure 2 These are transmission electron microscope (TEM) comparison images of the interlayer dielectric trench portion of existing 28nm PMOS and NMOS structures. Figure 2 As shown, taking the 28nm device structure as an example, the ILD0 trench depth-to-width ratio AR of the PMOS structure is 1.7:1, the bottom of the trench is flat and wide, and there are no defects after the dielectric is filled; while the ILD0 trench depth-to-width ratio AR of the NMOS structure reaches 3.5:1, the bottom of the trench is narrow and sharp, and obvious voids and seam defects will be generated at the bottom of the trench after filling.

[0026] In this embodiment, the trench depth-to-width ratio of the interlayer dielectric trench is 1:1 to 2:1 (including the two endpoint values). When the trench depth-to-width ratio is less than 1:1, the trench is too shallow overall, limiting the size of the active region of the device and potentially affecting the transistor drive current and conduction performance. When the trench depth-to-width ratio exceeds 2:1, the trench depth is too large, and the top of the trench is prone to premature closure during dielectric deposition, still posing a risk of voids and seam defects, making it impossible to achieve defect-free complete filling. Further, the trench depth-to-width ratio of the interlayer dielectric trench is 1.5:1 to 1.8:1 (including the two endpoint values). This application raises the trench substrate by in-situ doping the epitaxial layer in the source and drain regions, reducing the trench depth-to-width ratio of traditional NMOS, which is as high as 3.5:1, to the range of 1:1 to 2:1 without changing the lateral width of the trench defined by the silicide barrier layer, thus fundamentally solving the filling defect problem of existing processes.

[0027] Traditional NMOS relies on ion implantation to achieve heavy doping of the source and drain. High-energy ion bombardment will destroy the silicon substrate lattice, which not only requires a high-temperature RTA process, but also easily introduces problems such as device leakage and performance degradation.

[0028] In this embodiment, step S400 involves performing a silicon epitaxial process on the exposed source / drain regions of the substrate, including a selective single-crystal silicon epitaxial process on the exposed source / drain regions of the substrate to form a single-crystal silicon epitaxial layer. By fabricating the source / drain electrodes through in-situ epitaxial doping, the traditional ion implantation and associated RTA annealing processes can be eliminated, avoiding problems such as device leakage and performance degradation caused by traditional methods.

[0029] In this embodiment, in step S400, when performing selective single-crystal silicon epitaxial processing on the exposed source and drain regions of the substrate, a low-pressure chemical vapor deposition (LPCVD) process is used. The reaction gas sources are silane and borane. Silane is used as a silicon source to deposit and grow the single-crystal silicon body, and borane is used as a p-type heavy doping gas source to complete in-situ doping simultaneously with the growth of the epitaxial film. This allows the generated single-crystal silicon epitaxial layer to directly possess the high conductivity required for the source and drain electrodes, without the need for additional ion implantation and rapid thermal annealing processes.

[0030] In this embodiment, during step S400, when performing selective single-crystal silicon epitaxy on the exposed source and drain regions of the substrate, the epitaxial temperature is 500℃~580℃ (inclusive of both endpoints), and the epitaxial pressure is controlled at 10~20 Torr (inclusive of both endpoints). By matching the above-mentioned LPCVD process temperature, pressure, and gas source composition, a heavily doped single-crystal silicon epitaxial layer with uniform thickness and stable doping concentration can be selectively grown in the source and drain regions. On the one hand, this raises the bottom of the interlayer dielectric trench to reduce the trench aspect ratio; on the other hand, it forms source and drain electrodes with low resistance conductivity, simultaneously solving the dual defects of dielectric filling voids and ion implantation lattice damage in existing NMOS processes.

[0031] In this embodiment, step S300: patterning the silicide barrier layer, including: The photolithography process and the dry etching process are performed sequentially. The photoresist mask formed by the photolithography process only exposes the source and drain regions of the substrate. The silicide barrier layer corresponding to the source and drain regions of the substrate is removed by the dry etching process, while the silicide barrier layer on the gate structure and sidewall surface is still completely preserved.

[0032] In this embodiment, step S300: patterning the silicide barrier layer, removing the silicide barrier layer corresponding to the source / drain regions of the substrate, and exposing the source / drain regions of the substrate, step S400: performing silicon epitaxial processing on the exposed source / drain regions of the substrate, before forming the epitaxial layer, further includes the following steps: Wet cleaning is performed on the exposed source / drain regions of the substrate to remove etching residues and the native oxide layer on the surface, ensuring the quality of epitaxial crystal growth. After dry etching removes the silicide barrier layer in the source / drain regions, polymer residues and etching byproduct particles generated during dry etching remain on the silicon substrate surface. At the same time, a thin native oxide layer will rapidly form when the silicon substrate is exposed to air and the process chamber atmosphere. This oxide layer and impurity residues will hinder the uniform adsorption of silicon source gas on the silicon substrate surface, disrupting the subsequent nucleation process of selective single-crystal silicon epitaxy, and easily causing problems such as lattice defects, uneven thickness, and localized abnormal doping concentration in the epitaxial layer. The corrosive action of wet cleaning solutions can gently and controllably peel off the natural oxide layer on the surface of the silicon substrate in the source and drain regions. At the same time, it dissolves and rinses away residual polymers and particulate impurities from the etching process, resulting in a clean, oxide-free, and impurity-free fresh silicon surface. This is beneficial for improving the crystallization quality of thin films in selective epitaxy processes, ensuring the uniformity of epitaxial layer thickness and doping concentration across the entire wafer, and enabling heavily doped epitaxial layers to stably and completely raise the bottom of the interlayer dielectric trenches. It also allows for stable control of the trench aspect ratio, avoiding adverse phenomena such as filling defects and device electrical performance drift caused by substrate surface contamination from the process source.

[0033] In this embodiment, after performing silicon epitaxy on the exposed source / drain regions of the substrate to form an epitaxial layer in step S400, and before filling the interlayer dielectric trench defined by the silicide barrier layer and the epitaxial layer in step S500, the following steps are further included: Self-aligned etching (SAE) is used to remove the sidewalls and silicide barrier layer located on top of the gate structure. This ensures that the sidewalls only cover the sidewalls of the gate structure and do not extend to the top of the gate structure. Simultaneously, the silicide barrier layer only covers the outer sides of the sidewalls and no longer covers the sidewalls or the top of the gate structure. In this step, a self-aligned etching process is used, relying on the contour of the gate structure itself to achieve directional etching. No additional photoresist mask is required. Differential removal is achieved by relying on the etching selectivity between different film layers. Only the dielectric film stacked on the top surface of the gate structure is etched vertically downwards. The sidewalls attached to the outer sides of the left and right sidewalls of the gate, and the silicide barrier layer covering the outer sides of the sidewalls, are completely preserved and not damaged by etching.

[0034] The following combination Figures 3-6 The various processes of the fabrication method of the NMOS structure in a specific embodiment are described in detail.

[0035] like Figure 3As shown, corresponding to step S100, a substrate 100 is provided, and a gate structure 200 and sidewalls 300 respectively disposed on both sides of the gate structure 200 are formed on one side of the substrate 100. The substrate regions on the outer sides of the gate structure 200 are source and drain regions 110. In this embodiment, the substrate 100 is a single-crystal silicon substrate, a silicon carbide substrate, a gallium nitride substrate, or a diamond substrate. The gate structure 200 adopts a 28nm HKMG (High-K Metal Gate) structure, including an interface oxide layer, a dielectric layer, a work function adjustment metal layer, a metal barrier layer, a tungsten conductive gate layer, and a gate top hard mask layer. The initially formed sidewalls wrap around the outer sides and top of the left and right sidewalls of the gate structure.

[0036] like Figure 3 As shown, corresponding to step S200, a silicide barrier layer 400 is formed on one side of the substrate 100. The silicide barrier layer 400 is a SAB (Self-aligned silicide barrier layer, Salicide Block), so that the silicide barrier layer 400 completely covers the top surface of the gate structure 200, the outer surface of the sidewall 300, and the source / drain region 110 of the substrate 100; the silicide barrier layer 400 covers the entire area of ​​one side of the substrate 100.

[0037] like Figure 4 As shown, corresponding to step S300, the silicide barrier layer 400 is patterned, and the silicide barrier layer 400 corresponding to the source / drain region 110 of the substrate 100 is removed, so that the source / drain region 110 of the substrate 100 is exposed.

[0038] like Figure 5 As shown, corresponding to step S400, after wet cleaning to remove impurities and the native oxide layer from the substrate surface, a silicon epitaxial process is performed on the exposed source / drain regions 110 of the substrate 100 to form an epitaxial layer 500. The silicide barrier layer 400 and the epitaxial layer 500 together define the interlayer dielectric trench 600, and the epitaxial layer 500 can lift the bottom of the interlayer dielectric trench 600 from bottom to top, effectively reducing the effective depth of the interlayer dielectric trench 600 and lowering the overall aspect ratio of the trench.

[0039] like Figure 6 As shown, corresponding to step S500, dielectric filling is performed in the interlayer dielectric trench 600 defined by the silicide barrier layer 400 and the epitaxial layer 500 to form an interlayer dielectric layer 700. During the dielectric filling process, the top of the trench does not close prematurely, and the dielectric can completely fill the bottom of the trench, fundamentally avoiding the generation of voids and seam defects inside the trench. This prevents metal bridging and device short circuits in subsequent contact hole fabrication and metal wiring processes, significantly improving chip yield and long-term transistor reliability.

[0040] Figure 7These are transmission electron microscope (TEM) comparison images of the interlayer dielectric trench portion of the NMOS structure obtained using the fabrication method of this application and the existing PMOS structure. Figure 8 This is a transmission electron microscope (TEM) image of an NMOS structure according to an embodiment of this application. (Combined with...) Figure 7 and Figure 8 It can be seen that the source and drain regions of the NMOS device prepared using the process of this application form a raised epitaxial layer. The bottom of the ILD0 trench is raised from bottom to top by the epitaxial layer, and the trench depth-to-width ratio is reduced to 1.8:1, which is basically consistent with the trench outline and depth-to-width ratio of existing mature PMOS devices. Moreover, the bottom of the trench is wide and flat.

[0041] Compared to existing 28nm NMOS fabrication processes, this application, after completing the SAB oxide deposition process, opens the source and drain regions of the NMOS substrate through photolithography and dry etching patterning processes, exposing the silicon substrate at the source and drain locations. Following wet cleaning to remove surface impurities and the native oxide layer, a selective single-crystal silicon epitaxial process is performed, growing a single-crystal silicon epitaxial layer only on the exposed silicon substrate surface, thus raising the ILD0 trench substrate of the NMOS device from bottom to top. Based on this epitaxial lifting structure, the aspect ratio of the ILD0 trench in traditional NMOS devices can be optimized from 3.5:1 to 1:1~2:1. Compared to existing processes, this application only requires a single HARP deposition process to complete defect-free dielectric filling, significantly reducing the difficulty of the ILD0 dielectric filling process, widening the stable process window of the HARP process, and improving the yield of chip mass production.

[0042] like Figure 6 As shown in the illustration, this application also provides an NMOS structure, including: A substrate 100 has a gate structure 200 and sidewalls 300 respectively disposed on both sides of the gate structure 200. The substrate regions on the outer sides of the gate structure 200 are source / drain regions 110. In this embodiment, the substrate 100 is a single-crystal silicon substrate, a silicon carbide substrate, a gallium nitride substrate, or a diamond substrate. The gate structure 200 is, for example, a 28nm HKMG (High-K Metal Gate) structure, including an interface oxide layer, a dielectric layer, a work function adjustment metal layer, a metal barrier layer, a tungsten conductive gate layer, and a gate top hard mask layer. The sidewalls 300 surround the outer sides of the left and right sidewalls of the gate structure 200. A silicide barrier layer 400 covers the outer side of the sidewall 300; in this embodiment, the silicide barrier layer 400 is a (Salicide Block, self-aligned silicide barrier layer); the silicide barrier layer 400 covers the entire area of ​​one side of the substrate; An epitaxial layer 500 is formed in the source / drain region 110 of the substrate 100. The silicide barrier layer 400 and the epitaxial layer 500 together define an interlayer dielectric trench 600. The epitaxial layer 500 can lift the bottom of the interlayer dielectric trench from bottom to top. In this embodiment, the interlayer dielectric trench is an ILD0 trench, and the trench depth-to-width ratio of the interlayer dielectric trench is 1:1 to 2:1 (including the two endpoint values). Further, the trench depth-to-width ratio of the interlayer dielectric trench is 1.5:1 to 1.8:1 (including the two endpoint values). An interlayer dielectric layer 700 is filled inside the interlayer dielectric trench 600. In this embodiment, a high aspect ratio filling process is used to fill the dielectric in the interlayer dielectric trench defined by the silicide barrier layer and the epitaxial layer, wherein the material of the interlayer dielectric layer formed by filling is silicon dioxide.

[0043] The NMOS structure in this application is, for example, an NMOS device structure with a 28nm process node, or an NMOS device structure with other advanced process nodes such as 14nm, 7nm, and 3nm.

[0044] The NMOS structure of this application grows an epitaxial layer 500 after removing the silicide barrier layer 400 in the source / drain region 110. The epitaxial layer 500 can lift the bottom of the interlayer dielectric trench 600 from bottom to top, effectively reducing the effective depth of the interlayer dielectric trench 600, reducing the overall aspect ratio of the trench, optimizing the trench morphology, adapting to the filling window of the interlayer dielectric, and significantly widening the process window for void-free filling of the zero-layer interlayer dielectric trench of the NMOS device. During the filling process, the top of the trench will not close prematurely, and the dielectric can completely fill the bottom of the trench, fundamentally avoiding the generation of voids and seam defects inside the trench, preventing metal bridging and device short circuits in subsequent contact hole preparation and metal wiring processes, and significantly improving chip yield and long-term transistor reliability.

[0045] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A method for fabricating an NMOS structure, characterized in that, include: A substrate is provided, on one side of the substrate a gate structure and sidewalls respectively disposed on both sides of the gate structure, the substrate regions on the outer sides of the gate structure are source and drain regions; A silicide barrier layer is formed on one side of the substrate, such that the silicide barrier layer covers the gate structure, the sidewall, and the source / drain regions of the substrate; The silicide barrier layer is patterned to remove the silicide barrier layer corresponding to the source / drain regions of the substrate, thereby exposing the source / drain regions of the substrate. Silicon epitaxy is performed on the exposed source and drain regions of the substrate to form an epitaxial layer; An interlayer dielectric layer is formed by filling the interlayer dielectric trench defined by the silicide barrier layer and the epitaxial layer.

2. The method for fabricating an NMOS structure according to claim 1, characterized in that, Perform silicon epitaxial processing on the exposed source / drain regions of the substrate, including performing selective single-crystal silicon epitaxial processing on the exposed source / drain regions of the substrate to form a single-crystal silicon epitaxial layer.

3. The method for fabricating an NMOS structure according to claim 2, characterized in that, When performing selective single-crystal silicon epitaxy on the exposed source and drain regions of the substrate, a low-pressure chemical vapor deposition process is used, the reaction gas source is silane and borane, the epitaxy temperature is 500℃~580℃, and the epitaxy pressure is controlled at 10~20 Torr.

4. The method for fabricating an NMOS structure according to claim 1, characterized in that, After performing silicon epitaxy on the exposed source / drain regions of the substrate to form an epitaxial layer, and before filling the interlayer dielectric trench defined by the silicide barrier layer and the epitaxial layer, the following steps are also included: Remove the silicide oxide layer and sidewalls located on top of the gate structure.

5. The method for fabricating an NMOS structure according to claim 1, characterized in that, The trench depth-to-width ratio of the interlayer medium trench is 1:1 to 2:

1.

6. The method for fabricating an NMOS structure according to claim 1, characterized in that, Dielectric filling is performed in the interlayer dielectric trench defined by the silicide barrier layer and the epitaxial layer, including: A high aspect ratio filling process is used to fill the dielectric in the interlayer dielectric trench defined by the silicide barrier layer and the epitaxial layer.

7. The method for fabricating an NMOS structure according to claim 1, characterized in that, The silicide barrier layer is patterned, including: The photolithography process and the dry etching process are performed sequentially. The photoresist mask formed by the photolithography process exposes only the source and drain regions of the substrate, and the silicide barrier layer corresponding to the source and drain regions of the substrate is removed by the dry etching process.

8. The method for fabricating an NMOS structure according to claim 1, characterized in that, The silicide barrier layer is patterned, and the silicide barrier layer corresponding to the source / drain regions of the substrate is removed to expose the source / drain regions of the substrate. Before forming the epitaxial layer, a silicon epitaxial process is performed on the exposed source / drain regions of the substrate, and the following steps are also included: The exposed source and drain areas of the substrate are wet-cleaned.

9. The method for fabricating an NMOS structure according to claim 1, characterized in that, The substrate is a single-crystal silicon substrate, a silicon carbide substrate, a gallium nitride substrate, or a diamond substrate.

10. An NMOS structure, characterized in that, include: A substrate, wherein a gate structure and sidewalls are respectively disposed on both sides of the gate structure, and the substrate regions on the outer sides of the gate structure are source and drain regions; A silicide barrier layer covers the outer side of the sidewall; An epitaxial layer is formed in the source / drain region of the substrate, and the sidewalls and the epitaxial layer together define an interlayer dielectric trench; An interlayer dielectric layer is filled inside the interlayer dielectric trench.

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