A gallium nitride-based device and its fabrication method

Abstract

This invention relates to the field of third-generation semiconductor device manufacturing technology, and provides a gallium nitride-based device and its fabrication method. The method includes: forming a substrate comprising a silicon substrate, an undoped GaN layer and an AlGaN layer formed on the silicon substrate, wherein an ohmic contact region is defined on the AlGaN layer; performing multi-step Si ion implantation under low-temperature implantation conditions to form an initial Si-doped region in the ohmic contact region, wherein the energy-dose gradient of the multi-step Si ion implantation increases progressively; performing laser annealing and low-temperature rapid thermal annealing processes on the initial Si-doped region to form a target Si-doped region; and forming a composite electrode comprising a transparent conductive layer and a metal stack on the AlGaN layer, wherein the transparent conductive layer is in contact with the target Si-doped region. This invention overcomes the limitations of traditional high-temperature processes by using low-temperature, gradient Si ion implantation, combined with laser and thermal annealing synergistic technology and electrode optimization, thereby reducing lattice damage rate and ohmic contact resistance.

Description

Technical Field

[0001] This invention relates to the field of third-generation semiconductor device manufacturing technology, and in particular to a gallium nitride-based device and its fabrication method. Background Technology

[0002] Gallium nitride (GaN) high electron mobility transistors (HEMTs) represent wide-bandgap power semiconductor devices and have great potential in high-frequency power applications. Compared to silicon (Si) and silicon carbide (SiC), gallium nitride (GaN) materials have higher electron mobility, higher saturation electron velocity, and higher breakdown electric field. GaN power devices can achieve lower on-resistance and gate charge.

[0003] However, the n-type doping of existing AlGaN / GaN heterojunctions relies on high-temperature (greater than 1000℃) epitaxial growth, leading to thermal decomposition of the AlGaN layer (surface roughness greater than 2nm) and a decrease in the mobility of the two-dimensional electron gas (2DEG) (less than 1200cm). 2 / V·s); Existing thermal annealing cannot simultaneously repair AlGaN surface defects, and the metal-semiconductor interface barrier height (Φ) B A voltage greater than 0.5 eV limits current transport efficiency. When conventional Ti / Al / Ni / Au electrodes are in contact with AlGaN, the surface state density is too high (greater than 10⁻⁶ eV), limiting current transport efficiency. 13 cm -2 ·eV -1 This induces a strong Fermi pinning effect, increasing the ohmic contact resistivity (ρ). c It's difficult to break through 10. -5 Ω·cm 2 The contact resistance remains high, reaching significant levels. Furthermore, direct Si ion implantation into AlGaN requires high-temperature annealing (above 800°C) to activate charge carriers, leading to an increase in nitrogen vacancies (V0.05) at the AlGaN / GaN interface. N Density surge (greater than 10) 17 cm -3 The reverse leakage current of the device will increase significantly, and the ion implantation damage will be irreversible.

[0004] Therefore, there is an urgent need for a method to achieve high-concentration n-type doping in AlGaN / GaN heterojunctions and significantly reduce ohmic contact resistance, in order to solve the technical problems of existing high-temperature doping process defects, high contact resistance, and irreversible ion implantation damage. Summary of the Invention

[0005] The purpose of this invention is to provide a gallium nitride-based device and its fabrication method, which breaks through the limitations of traditional high-temperature processes and reduces lattice damage rate and ohmic contact resistance.

[0006] To achieve the above objectives, the present invention provides a method for fabricating a gallium nitride-based device, the method comprising the following steps: forming a substrate, the substrate comprising a silicon substrate, an undoped GaN layer and an AlGaN layer formed on the silicon substrate, wherein an ohmic contact region is defined on the AlGaN layer; performing multi-step Si ion implantation under low-temperature implantation conditions to form an initial Si-doped region in the ohmic contact region, wherein the energy-dose gradient of the multi-step Si ion implantation increases progressively; performing laser annealing and low-temperature rapid thermal annealing processes on the initial Si-doped region to form a target Si-doped region; and forming a composite electrode comprising a transparent conductive layer and a metal stack on the AlGaN layer, wherein the transparent conductive layer is in contact with the target Si-doped region.

[0007] In some embodiments, the step of performing multi-step Si ion implantation under low-temperature implantation conditions to form an initial Si-doped region in the ohmic contact region specifically includes: adjusting the ion implantation temperature to a first temperature to complete the low-temperature implantation condition setting, adjusting the ion implantation vacuum to a first vacuum level, and adjusting the ion implantation tilt angle to a first implantation tilt angle; controlling the ion implantation energy to a first ion implantation energy and the ion implantation dose to a first ion implantation dose to perform the first Si ion implantation step; controlling the ion implantation energy to a second ion implantation energy and the ion implantation dose to a second ion implantation dose to perform the second Si ion implantation step, wherein the second ion implantation energy is greater than the first ion implantation energy and the second ion implantation dose is greater than the first ion implantation dose; and controlling the ion implantation energy to a third ion implantation energy and the ion implantation dose to a third ion implantation dose to perform the third Si ion implantation step to form the initial Si-doped region in the ohmic contact region; wherein the third ion implantation energy is greater than the second ion implantation energy and the third ion implantation dose is greater than the second ion implantation dose.

[0008] In some embodiments, the steps of performing laser annealing and low-temperature rapid thermal annealing on the initial Si doped region to form the target Si doped region specifically include: performing laser annealing by scanning with a preset wavelength ultraviolet pulsed laser; and performing low-temperature rapid thermal annealing in a nitrogen atmosphere at a preset heating rate to a second temperature for a preset duration to obtain the target Si doped region.

[0009] To achieve the above objectives, the present invention also provides a gallium nitride-based device, comprising: a substrate, the substrate including a silicon substrate, a GaN layer and an AlGaN layer stacked on the silicon substrate, wherein an ohmic contact region is defined on the AlGaN layer; a target Si-doped region formed in the ohmic contact region, the target Si-doped region being formed by performing multi-step Si ion implantation under low-temperature implantation conditions, followed by laser annealing and low-temperature rapid thermal annealing processes; and a composite electrode disposed on the AlGaN layer, the composite electrode comprising a transparent conductive layer and a metal stack, wherein the transparent conductive layer is in contact with the target Si-doped region.

[0010] The above technical solution, by performing multi-step Si ion implantation under low-temperature implantation conditions, can form a Si doped region with a high peak concentration within the AlGaN layer and reduce the lattice damage rate. It employs a synergistic technology of laser annealing and low-temperature rapid thermal annealing. Laser annealing achieves selectivity and reduces thermal damage through localized rapid heating, while low-temperature rapid thermal annealing can repair deep-level defects, improve carrier mobility, overcome the limitations of traditional high-temperature processes, and suppress reverse leakage current. Interface layer optimization is achieved through a transparent conductive layer in the composite electrode, weakening the Fermi pinning effect and reducing the metal-semiconductor interface barrier height. The metal stack design in the composite electrode effectively reduces contact interface roughness. This significantly reduces ohmic contact resistivity and device on-resistance, improves device breakdown voltage, and is suitable for the millimeter-wave band requirements of 5G communication. The maximum temperature throughout the process is less than or equal to 500°C, making it compatible with 8-inch CMOS production line equipment. Laser selective annealing supports localized doping control and is suitable for the development of multifunctional integrated devices. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic flowchart of a method for fabricating a gallium nitride-based device according to an embodiment of the present invention; Figures 2A-2C This is a schematic diagram of the structure of the substrate according to an embodiment of the present invention; Figures 3A-3B This is a schematic diagram of a structure for performing multi-step Si ion implantation according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure for forming a target Si doped region according to an embodiment of the present invention; Figures 5A-5CThis is a schematic diagram of the structure for forming a composite electrode according to an embodiment of the present invention.

[0013] Explanation of reference numerals in the attached figures: 20. Silicon-based substrate; 21. GaN layer; 22. AlGaN layer; 220. Ohmic contact area; 30. Initial Si-doped region; 40. Target Si-doped region; 50. Composite electrode; 510. Transparent conductive material layer; 51. Transparent conductive layer; 520. Multilayer metal material layers; 52. Metal stacking. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] Please refer to the following: Figures 1-5C ,in, Figure 1 This is a schematic flowchart of a method for fabricating a gallium nitride-based device according to an embodiment of the present invention; Figures 2A-2C This is a schematic diagram of the structure of the substrate according to an embodiment of the present invention; Figures 3A-3B This is a schematic diagram of a structure for performing multi-step Si ion implantation according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure after forming the target Si doped region according to an embodiment of the present invention; Figures 5A-5C This is a schematic diagram of the structure for forming a composite electrode according to an embodiment of the present invention.

[0016] like Figure 1As shown, the method for fabricating the gallium nitride-based device includes the following steps: S1, forming a substrate, the substrate including a silicon substrate, an undoped GaN layer and an AlGaN layer formed on the silicon substrate, wherein an ohmic contact region is defined on the AlGaN layer; S2, performing multi-step Si ion implantation under low-temperature implantation conditions to form an initial Si doped region in the ohmic contact region, wherein the energy-dose gradient of the multi-step Si ion implantation increases progressively; S3, performing laser annealing and low-temperature rapid thermal annealing processes on the initial Si doped region to form a target Si doped region; and S4, forming a composite electrode including a transparent conductive layer and a metal stack on the AlGaN layer, wherein the transparent conductive layer is in contact with the target Si doped region.

[0017] Please refer to steps S1 and... Figure 2C A substrate is formed, the substrate including a silicon substrate 20, an undoped GaN layer 21 and an AlGaN layer 22 formed on the silicon substrate 20, and an ohmic contact region 220 is defined on the AlGaN layer 22.

[0018] In some embodiments, the formation of the substrate in step S1 can be achieved by the following steps: (11) providing a silicon substrate 20, such as... Figure 2A As shown; (12) An undoped GaN layer 21 and an AlGaN layer 22 are epitaxially grown on the silicon substrate 20, as follows: Figure 2B As shown; and (13) performing a photolithography / hard mask process to determine the ohmic contact region 220 on the AlGaN layer 22, as shown. Figure 2C As shown, by opening windows through photolithography / hard mask, subsequent ion implantation is performed only in the area that needs to be doped (the area corresponding to the ohmic contact region 220).

[0019] In some embodiments, the silicon substrate 20 includes a SiC substrate. The GaN layer 21 has a film thickness of 0.5 μm to 1.5 μm, for example, 0.5 μm, 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, etc. The AlGaN layer 22 has a film thickness of 15 nm to 25 nm, for example, 15 nm, 18 nm, 20 nm, 22 nm, 25 nm, etc. The two-dimensional electron gas (2DEG) density of the AlGaN layer 22 is 9 × 10⁻⁶. 12 cm -2 The two-dimensional electron gas (2DEG) is formed when electrons are confined near the interface of a heterojunction (such as AlGaN / GaN), and can only move freely along the interface and are quantized in the vertical direction.

[0020] In some embodiments, the substrate formation step further includes: (121) depositing and growing a protective layer (not shown) on the surface of the AlGaN layer. Specifically, the protective layer can be deposited and grown on the surface of the AlGaN layer using atomic layer deposition (ALD) at a growth temperature of 200°C to 300°C. That is, an additional 5nm to 10nm amorphous SiNx protective layer can be deposited on the surface of the AlGaN layer using ALD, with a thickness deviation of ≤ ±0.5nm. The refractive index of the protective layer is 1.8 to 2.0 at 633nm, meaning that the refractive index of the protective layer ranges from 1.8 to 2.0 under incident light at a wavelength of 633nm. This protective layer can block impurity ions from directly bombarding the AlGaN layer during subsequent ion implantation, preventing damage to the AlGaN layer surface from implanted ions, and does not change the ion implantation doping dose in the ohmic contact region, effectively improving the ohmic contact performance of the subsequently fabricated device.

[0021] Please refer to step S2 and... Figures 3A-3B Multi-step Si ion implantation is performed under low-temperature implantation conditions to form an initial Si doped region 30 in the ohmic contact region 220, and the energy-dose gradient of the multi-step Si ion implantation increases progressively.

[0022] By performing multi-step Si ion implantation under low-temperature implantation conditions, Si ions are implanted into the AlGaN / GaN heterostructure. This locally increases n-type doping in the AlGaN / GaN heterostructure beneath the subsequently formed composite electrode, significantly reducing the depletion layer width and thus effectively lowering the resistance of the ohmic contact. Multi-step Si ion implantation under low-temperature conditions can form a Si-doped region with a high peak concentration within the AlGaN layer and reduce the lattice damage rate. Furthermore, optimizing the implantation tilt angle can suppress channeling effects and ensure doping uniformity.

[0023] In some embodiments, the step of performing multi-step Si ion implantation under low-temperature implantation conditions to form an initial Si-doped region in the ohmic contact region specifically includes: (21) adjusting the ion implantation temperature to a first temperature to complete the low-temperature implantation condition setting, adjusting the ion implantation vacuum to a first vacuum, and adjusting the ion implantation tilt angle to a first implantation tilt angle; (22) controlling the ion implantation energy to a first ion implantation energy and the ion implantation dose to a first ion implantation dose to perform the first Si ion implantation step; (23) controlling the ion implantation energy to a second ion implantation energy and the ion implantation dose to a second ion implantation dose to perform the second Si ion implantation step, wherein the second ion implantation energy is greater than the first ion implantation energy and the second ion implantation dose is greater than the first ion implantation dose; and (24) controlling the ion implantation energy to a third ion implantation energy and the ion implantation dose to a third ion implantation dose to perform the third Si ion implantation step to form the initial Si-doped region in the ohmic contact region; wherein the third ion implantation energy is greater than the second ion implantation energy and the third ion implantation dose is greater than the second ion implantation dose. A schematic diagram of performing multi-step Si ion implantation is shown below. Figure 3A As shown, the arrows indicate Si ion implantation. By combining low-temperature implantation with energy-dose gradient coupling design, a high-peak-concentration Si-doped region can be formed within the AlGaN layer, while reducing lattice damage rate and avoiding defects in high-temperature doping processes. The structure formed after multi-step Si ion implantation is shown below. Figure 3B As shown.

[0024] In some embodiments, the first temperature is -70°C to -50°C; for example, -70°C, -65°C, -60°C, -55°C, -50°C, etc. The first vacuum degree is less than or equal to 5 × 10⁻⁶. -6 Torr. The first injection tilt angle is 5° to 9°; for example, 5°, 6°, 7°, 8°, 9°, etc.

[0025] In some embodiments, the first ion implantation energy is 8keV to 12keV; for example, 8keV, 9keV, 10keV, 11keV, 12keV, etc. The second ion implantation energy is 25keV to 35keV; for example, 25keV, 28keV, 30keV, 32keV, 35keV, etc. The third ion implantation energy is 45keV to 55keV; for example, 45keV, 48keV, 50keV, 52keV, 55keV, etc.

[0026] In some embodiments, the first ion implantation dose is 0.5 × 10⁻⁶. 13 cm -2 ~1.5×10 13 cm -2For example, 0.5 × 10 13 cm -2 0.8×10 13 cm -2 1.0×10 13 cm -2 1.2×10 13 cm -2 1.5×10 13 cm -2 The second ion implantation dose is 4 × 10⁻⁶. 13 cm -2 ~6×10 13 cm -2 For example, 4×10 13 cm -2 4.5×10 13 cm -2 5×10 13 cm -2 5.5×10 13 cm -2 6×10 13 cm -2 The third ion implantation dose is 0.5 × 10⁻⁶. 14 cm -2 ~1.5×10 14 cm -2 For example, 0.5 × 10 14 cm -2 0.8×10 14 cm -2 1.0×10 14 cm -2 1.2×10 14 cm -2 1.5×10 14 cm -2 wait.

[0027] In other embodiments, Si ion implantation can also be performed using different energy gradients within the device, ranging from 10 keV to 50 keV, with a total ion implantation dose ranging from 1 × 10⁻⁶. 14 cm -2 ~5×10 14 cm -2 To achieve a peak concentration greater than or equal to 2 × 10⁻⁶ within the AlGaN layer. 19 cm -3 The Si-doped region.

[0028] By performing multi-step Si ion implantation with increasing energy-dose gradient under low-temperature implantation conditions, it is possible to form a high peak concentration (peak concentration greater than or equal to 2 × 10⁻⁶) within the AlGaN layer. 19 cm-3 The Si-doped region can be reduced to below 12%, far lower than the lattice damage rate of more than 30% in existing processes. By optimizing the implantation tilt angle, the channel effect is suppressed, ensuring doping uniformity and making the deviation less than ±8%.

[0029] Please refer to step S3 and... Figure 4 Laser annealing and low-temperature rapid thermal annealing processes are performed on the initial Si-doped region 30 to form the target Si-doped region 40. The photolithography / hard mask structure used to determine the ohmic contact region 220 is removed after annealing.

[0030] In some embodiments, the steps of performing laser annealing and low-temperature rapid thermal annealing on the initial Si doped region to form the target Si doped region specifically include: (31) using a preset wavelength ultraviolet pulsed laser to scan and complete laser annealing, so as to activate the Si doping in the initial Si doped region and improve the Si doping activation rate; (32) heating to a second temperature at a preset heating rate in a nitrogen atmosphere for a preset duration of low-temperature rapid thermal annealing, so as to repair deep level defects, improve carrier mobility, and obtain the target Si doped region. That is, this embodiment uses a combination of laser annealing and low-temperature rapid thermal annealing technology. Laser annealing achieves selectivity, reduces thermal damage, and improves the Si doping activation rate through local rapid heating, while low-temperature rapid thermal annealing can repair deep level defects and improve carrier mobility.

[0031] In some embodiments, the step of scanning with a preset wavelength ultraviolet pulsed laser to complete laser annealing specifically includes: using a KrF excimer laser to generate a wavelength including but not limited to 248nm (e.g., 93nm, 248nm, 308nm, etc.), a pulse width of 20ns~30ns (e.g., 20ns, 22ns, 25ns, 28ns, 30ns, etc.), and an energy density of 0.4J / cm². 2 ~0.5J / cm 2 (For example, 0.4 J / cm) 2 0.42J / cm 2 0.45J / cm 2 0.48J / cm 2 0.5J / cm 2Ultraviolet pulsed lasers with scanning speeds of 8 mm / s to 12 mm / s (e.g., 8 mm / s, 9 mm / s, 10 mm / s, 11 mm / s, 12 mm / s, etc.) and overlap rates of 15% to 25% (e.g., 15%, 18%, 20%, 22%, 25%, etc.) are used. The high absorption rate of ultraviolet pulsed lasers ensures that energy is concentrated in the surface layer (i.e., 0–50 nm), avoiding damage to the underlying two-dimensional electron gas (2DEG). The pulse width of the ultraviolet pulsed laser balances thermal diffusion and instantaneous melting repair, achieving a Si doping activation rate greater than 90%.

[0032] In some embodiments, the nitrogen flow rate in the nitrogen atmosphere is 4 L / min to 6 L / min (e.g., 4 L / min, 4.5 L / min, 5 L / min, 5.5 L / min, 6 L / min, etc.), the preset heating rate is 45℃ / s to 55℃ / s (e.g., 45℃ / s, 48℃ / s, 50℃ / s, 52℃ / s, 55℃ / s, etc.), the first temperature is 400℃ to 500℃ (e.g., 400℃, 420℃, 450℃, 480℃, 500℃, etc.), and the preset duration is 55s to 65s (e.g., 55s, 58s, 60s, 62s, 65s, etc.). By implementing this in a nitrogen atmosphere, deep-level defects (such as interfacial nitrogen vacancies V) can be repaired. N (Ga vacancies) restore carrier mobility to 1350 cm² / V·s.

[0033] Please refer to step S4 and... Figure 5C A composite electrode 50 comprising a transparent conductive layer 51 and a metal stack 52 is formed on the AlGaN layer 22, wherein the transparent conductive layer 51 is in contact with the target Si doped region 40.

[0034] In some embodiments, the step of forming a composite electrode 50 comprising a transparent conductive layer 51 and a metal stack 52 on the AlGaN layer 22 specifically includes: (41) forming a transparent conductive material layer 510 on the AlGaN layer using a magnetron sputtering process, wherein the transparent conductive material layer is in contact with the target Si doped region, such as... Figure 5A As shown; (42) A multilayer metal material layer 520 is formed on the transparent conductive material layer using an electron beam evaporation process. The multilayer metal material layer includes at least an Al material layer and a TiN material layer, such as Figure 5B As shown; and (43) performing photolithography / hard mask process, the remaining transparent conductive material layer forms a transparent conductive layer 51 in contact with the target Si doped region 40, and the remaining multilayer metal material layers form a metal stack 52 covering the transparent conductive layer 51, the transparent conductive layer 51 and the metal stack 52 together constitute the composite electrode 50, as shown. Figure 5CAs shown. Interface layer optimization is achieved through transparent conductive layer 51, weakening the Fermi pinning effect and reducing the metal-semiconductor interface barrier height (Φ). B Through metal stacking design, the TiN layer acts as a diffusion barrier layer, which can suppress the migration of A atoms in the Al layer, thereby reducing the roughness of the contact interface.

[0035] In some embodiments, an ITO layer with a thickness of 1 nm to 3 nm is formed on the AlGaN layer using magnetron sputtering for subsequent formation of the transparent conductive layer 51. In the magnetron sputtering process, the sputtering power can be 200 W, and the Ar / O2 ratio is 20:1. The carrier concentration of the ITO layer is greater than or equal to 10⁻⁶. 21 cm -3 The sheet resistance is less than or equal to 50Ω / □; the high work function (4.7eV) of this ITO layer is used to weaken the Fermi pinning effect, thus reducing the metal-semiconductor interface barrier height (Φ B It dropped to 0.28 eV.

[0036] In some embodiments, the metal stack 52 comprises Ti / Al / TiN / Au; in the electron beam evaporation process, the vacuum degree is less than or equal to 2 × 10⁻⁶. -7 Torr. Specifically, using electron beam evaporation, a four-layer metal stack structure is sequentially formed, consisting of a Ti layer with a thickness of 8nm~12nm, an Al layer with a thickness of 140nm~160nm, a TiN layer with a thickness of 18nm~22nm, and an Au layer with a thickness of 80nm~120nm. By using the TiN layer as a diffusion barrier to suppress Al atom migration, the contact interface roughness can be reduced to less than or equal to 0.3nm, which is far lower than the contact interface roughness of more than 1.2nm in existing processes.

[0037] In some embodiments, when performing a photolithography / hard mask process to peel off excess material to form a composite electrode, the edge steepness of the composite electrode is close to vertical (greater than or equal to 85°), which makes the electrode sheet resistance stable, the contact resistance low, and improves the interface and contact performance as well as the device performance.

[0038] By optimizing the electrodes and mitigating the Fermi pinning effect, the metal-semiconductor interface barrier height was reduced to below 0.28 eV. Furthermore, by suppressing Al atom migration through a TiN layer, the contact interface roughness was reduced to 0.3 nm, significantly lower than the 1.2 nm of existing processes. The ohmic contact resistivity is approximately 3.2 × 10⁻⁶. -6 The voltage is reduced by 2 orders of magnitude compared to existing processes; the carrier activation rate is greater than 90%, and the on-resistance of the device is reduced to 1.2Ω·mm, which is suitable for the millimeter-wave frequency band requirements of 5G communication; the device breakdown voltage is increased to 1200V, which is higher than 800V of existing processes.

[0039] Based on the same inventive concept, an embodiment of the present invention also provides a gallium nitride-based device, which can be fabricated using the method described above.

[0040] Please see Figure 5C This is a schematic diagram of the structure of a gallium nitride-based device provided in an embodiment of the present invention. Specifically, the gallium nitride-based device provided in this embodiment can be fabricated using the method described above in the present invention, and includes: a silicon substrate 20, a GaN layer 21, an AlGaN layer 22, a target Si doped region 40, and a composite electrode 50.

[0041] Specifically, a silicon substrate 20, a GaN layer 21, and an AlGaN layer 22 are included within the substrate. The GaN layer 21 and the AlGaN layer 22 are stacked on the silicon substrate 20, and an ohmic contact region 220 (shown in Figure 22) is defined on the AlGaN layer 22. Figure 2C middle).

[0042] In some embodiments, the silicon substrate 20 comprises a SiC substrate. The GaN layer 21 has a film thickness of 0.5 μm to 1.5 μm; the AlGaN layer 22 has a film thickness of 15 nm to 25 nm. The two-dimensional electron gas (2DEG) density of the AlGaN layer 22 is 9 × 10⁻⁶. 12 cm -2 .

[0043] In some embodiments, a protective layer (not shown) is also grown on the surface of the AlGaN layer 22. This protective layer can block impurity ions from directly bombarding the AlGaN layer during subsequent ion implantation, preventing damage to the AlGaN layer surface from implanted ions, and does not change the ion implantation doping dose in the ohmic contact region, thus effectively improving the ohmic contact performance of the subsequently fabricated device.

[0044] Specifically, the target Si-doped region 40 is formed in the ohmic contact region. The target Si-doped region 40 is formed by performing multi-step Si ion implantation under low-temperature implantation conditions, followed by laser annealing and low-temperature rapid thermal annealing. In one embodiment, the peak concentration of the target Si-doped region is greater than or equal to 2 × 10⁻⁶. 19 cm -3 The lattice damage rate is less than 12%.

[0045] By performing multi-step Si ion implantation with increasing energy-dose gradient under low-temperature implantation conditions, it is possible to form a high peak concentration (peak concentration greater than or equal to 2 × 10⁻⁶) within the AlGaN layer. 19 cm -3The Si-doped region is optimized, and the lattice damage rate can be reduced to below 12%, far lower than the lattice damage rate of more than 30% in existing processes. By optimizing the injection tilt angle, the channel effect is suppressed, ensuring doping uniformity and making the deviation less than ±8%. A synergistic technology of laser annealing and low-temperature rapid thermal annealing is adopted. Laser annealing achieves selectivity, reduces thermal damage, and improves Si doping activation rate through local rapid heating, while low-temperature rapid thermal annealing can repair deep-level defects and improve carrier mobility.

[0046] Specifically, the composite electrode 50 is disposed on the AlGaN layer 22, and the composite electrode 50 includes a transparent conductive layer 51 and a metal stack 52, wherein the transparent conductive layer 51 is in contact with the target Si doped region 40.

[0047] In some embodiments, the metal stack 52 includes at least an Al layer and a TiN layer. The thickness of the transparent conductive layer 51 is 1 nm to 3 nm, and the thickness of the TiN layer is 15 nm to 25 nm.

[0048] In some embodiments, the transparent conductive layer 51 includes an ITO layer with a thickness of 1 nm to 3 nm, wherein the carrier concentration of the ITO layer is greater than or equal to 10. 21 cm -3 The sheet resistance is less than or equal to 50 Ω / □ (ohms per square); the high work function (4.7 eV) of this ITO layer is used to weaken the Fermi pinning effect, thus reducing the metal-semiconductor interface barrier height (Φ B It dropped to 0.28 eV.

[0049] In some embodiments, the metal stack 52 comprises Ti / Al / TiN / Au. By using the TiN layer as a diffusion barrier to suppress Al atom migration, the contact interface roughness can be reduced to less than or equal to 0.3 nm, which is far lower than the contact interface roughness of more than 1.2 nm in existing processes.

[0050] In some embodiments, the edge steepness of the composite electrode is close to vertical (greater than or equal to 85°), which makes the electrode sheet resistance stable, the contact resistance low, and improves the interface and contact performance as well as the device performance.

[0051] The above embodiments achieve ultra-low contact resistance in AlGaN / GaN heterojunctions below 500°C through low-damage, low-temperature, gradient Si ion implantation combined with laser and thermal annealing synergistic techniques, overcoming the limitations of traditional high-temperature processes and suppressing reverse leakage current. By optimizing the electrodes and mitigating the Fermi pinning effect, the metal-semiconductor interface barrier height is reduced to below 0.28 eV. Furthermore, by suppressing Al atom migration through the TiN layer, the contact interface roughness is reduced to 0.3 nm, far lower than the 1.2 nm of existing processes. The ohmic contact resistivity is approximately 3.2 × 10⁻⁶. -6The efficiency is reduced by two orders of magnitude compared to existing processes; the carrier activation rate is greater than 90%, and the device on-resistance is reduced to 1.2 Ω·cm², meeting the requirements of 5G millimeter-wave communication; the maximum temperature throughout the process is less than or equal to 500°C, compatible with 8-inch CMOS production line equipment; laser selective annealing supports local doping control, suitable for the development of multifunctional integrated devices; the device breakdown voltage is increased to 1200V, higher than the 800V of existing processes. This embodiment solves the problems of existing AlGaN / GaN heterojunctions where n-type doping depends on high-temperature epitaxial growth exceeding 1000°C, leading to thermal decomposition of the AlGaN layer, surface roughness greater than 2nm, and 2D electron gas (2DEG) mobility decay to less than 1200cm² / V·s; and direct Si ion implantation of AlGaN requires high-temperature annealing above 800°C to activate carriers, resulting in a surge in nitrogen vacancy density at the AlGaN / GaN interface to greater than 10. 17 cm -3 The reverse leakage current of the device increases significantly, and existing thermal annealing cannot simultaneously repair AlGaN surface defects. The metal-semiconductor interface barrier height is greater than 0.5 eV, limiting current transport efficiency. When conventional electrodes are in contact with AlGaN, the surface state density is too high (above 10^6 eV). 13 cm -2 ·eV -1 This triggers a strong Fermi pinning effect, making it difficult for the resistivity of ohmic contacts to exceed 10. -5 Ω·cm 2 The issue is of magnitude.

[0052] In the above description, descriptions of well-known components and technologies have been omitted to avoid unnecessarily obscuring the concept of the present invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar or identical parts between embodiments can be referred to mutually.

[0053] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising a…" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element. Additionally, embodiments and features thereof in this invention can be combined with each other without conflict.

[0054] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a gallium nitride-based device, characterized in that, The method includes the following steps: A substrate is formed, the substrate comprising a silicon substrate, an undoped GaN layer and an AlGaN layer formed on the silicon substrate, wherein an ohmic contact region is defined on the AlGaN layer; Multi-step Si ion implantation is performed under low-temperature implantation conditions to form an initial Si doped region in the ohmic contact region, and the energy-dose gradient of the multi-step Si ion implantation increases progressively. Laser annealing and low-temperature rapid thermal annealing processes are performed on the initial Si doped region to form the target Si doped region; as well as A composite electrode comprising a transparent conductive layer and a metal stack is formed on the AlGaN layer, wherein the transparent conductive layer is in contact with the target Si doped region.

2. The method according to claim 1, characterized in that, The specific steps involved in forming the substrate include: Provide a silicon-based substrate; Undoped GaN and AlGaN layers are epitaxially grown on the silicon substrate. A photolithography / hard mask process is performed to determine the ohmic contact region on the AlGaN layer.

3. The method according to claim 1, characterized in that, The substrate formation step also includes depositing and growing a protective layer on the surface of the AlGaN layer.

4. The method according to claim 3, characterized in that, The protective layer is deposited and grown on the surface of the AlGaN layer using atomic layer deposition (ALD) at a growth temperature of 200°C to 300°C.

5. The method according to claim 1, characterized in that, The steps of performing multi-step Si ion implantation under low-temperature implantation conditions to form an initial Si-doped region in the ohmic contact region specifically include: The ion implantation temperature is adjusted to the first temperature to complete the low-temperature implantation condition setting, and the ion implantation vacuum degree is adjusted to the first vacuum degree and the ion implantation tilt angle is adjusted to the first implantation tilt angle; Control the ion implantation energy to the first ion implantation energy and the ion implantation dose to the first ion implantation dose, and perform the first step of Si ion implantation; The second step of Si ion implantation is performed by controlling the ion implantation energy to a second ion implantation energy and the ion implantation dose to a second ion implantation dose, wherein the second ion implantation energy is greater than the first ion implantation energy and the second ion implantation dose is greater than the first ion implantation dose; and The ion implantation energy and the ion implantation dose are controlled to be the third ion implantation energy and the third ion implantation dose, respectively, and the third step of Si ion implantation is performed to form the initial Si doped region in the ohmic contact region; wherein the third ion implantation energy is greater than the second ion implantation energy and the third ion implantation dose is greater than the second ion implantation dose.

6. The method according to claim 5, characterized in that, The first temperature is -70℃ to -50℃, and the first vacuum degree is less than or equal to 5×10⁻⁶. -6 Torr, the first injection tilt angle is 5° to 9°; The first ion implantation energy is 8keV~12keV, the second ion implantation energy is 25keV~35keV, and the third ion implantation energy is 45keV~55keV; the first ion implantation dose is 0.5×10⁻⁶. 13 cm -2 ~1.5×10 13 cm -2 The second ion implantation dose is 4 × 10⁻⁶. 13 cm -2 ~6×10 13 cm -2 The third ion implantation dose is 0.5 × 10⁻⁶. 14 cm -2 ~1.5×10 14 cm -2 .

7. The method according to claim 1, characterized in that, The steps of performing laser annealing and low-temperature rapid thermal annealing on the initial Si doped region to form the target Si doped region specifically include: laser annealing by scanning with a preset wavelength ultraviolet pulsed laser; and low-temperature rapid thermal annealing in a nitrogen atmosphere at a preset heating rate to a second temperature for a preset duration to obtain the target Si doped region.

8. The method according to claim 7, characterized in that, The laser annealing process, which involves scanning with a pre-set wavelength ultraviolet pulsed laser, specifically includes: using a KrF excimer laser to generate a laser with a wavelength of 248 nm, a pulse width of 20 ns to 30 ns, and an energy density of 0.4 J / cm². 2 ~0.5J / cm 2 Ultraviolet pulsed laser with a scanning speed of 8mm / s to 12mm / s and an overlap rate of 15% to 25%.

9. The method according to claim 7, characterized in that, The nitrogen flow rate in the nitrogen atmosphere is 4L / min to 6L / min, the preset heating rate is 45℃ / s to 55℃ / s, the first temperature is 400℃ to 500℃, and the preset duration is 55s to 65s.

10. The method according to claim 1, characterized in that, The step of forming a composite electrode comprising a transparent conductive layer and a metal stack on the AlGaN layer specifically includes: forming a transparent conductive material layer on the AlGaN layer using a magnetron sputtering process, wherein the transparent conductive material layer is in contact with the target Si doped region; forming multiple metal material layers on the transparent conductive material layer using an electron beam evaporation process, wherein the multiple metal material layers include at least an Al material layer and a TiN material layer; and performing a photolithography / hard mask process, wherein the remaining transparent conductive material layer forms a transparent conductive layer in contact with the target Si doped region, and the remaining multiple metal material layers form a metal stack covering the transparent conductive layer, wherein the transparent conductive layer and the metal stack together constitute the composite electrode.

11. A gallium nitride-based device, characterized in that, include: The substrate includes a silicon substrate, a GaN layer and an AlGaN layer stacked on the silicon substrate, wherein an ohmic contact region is defined on the AlGaN layer; The target Si-doped region is formed in the ohmic contact region by performing multi-step Si ion implantation under low-temperature implantation conditions, followed by laser annealing and low-temperature rapid thermal annealing. as well as A composite electrode is disposed on the AlGaN layer. The composite electrode includes a transparent conductive layer and a metal stack, and the transparent conductive layer is in contact with the target Si doped region.

12. The gallium nitride-based device according to claim 11, characterized in that, The silicon-based substrate includes a SiC substrate, the GaN layer has a film thickness of 0.5 micrometers to 1.5 micrometers, and the AlGaN layer has a film thickness of 15nm to 25nm.

13. The gallium nitride-based device according to claim 11, characterized in that, The peak concentration of the target Si-doped region is greater than or equal to 2 × 10⁻⁶. 19 cm -3 The lattice damage rate is less than 12%.

14. The gallium nitride-based device according to claim 11, characterized in that, The metal stack includes at least an Al layer and a TiN layer, the thickness of the transparent conductive layer is 1 nm to 3 nm, and the thickness of the TiN layer is 15 nm to 25 nm.

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