Semiconductor devices and their manufacturing methods

Abstract

This application relates to a semiconductor device and a method for manufacturing the same, comprising: providing a wafer, the wafer including a substrate, a gate structure formed on the substrate, and a barrier layer covering the top and sidewalls of the gate structure; forming a first ion implantation region in the substrate on both sides of the gate structure; immersing the wafer in a mixed solution and continuously irradiating the wafer with visible light to form a reduction layer on the exposed surface of the substrate, the reduction layer covering the first ion implantation region; and annealing the wafer to form a metal silicide layer in the first ion implantation region. This application, by forming a reduction layer covering the first ion implantation region, helps to reduce or even avoid the probability of damage to the metal silicide layer while forming the metal silicide layer, solving the problem of metal residue on the metal silicide layer, and simultaneously reducing the environmental pollution caused by the mixed solution.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Self-aligned silicides are a key process in semiconductor manufacturing. The typical preparation process involves: first, depositing a nickel-platinum alloy layer on the exposed silicon surfaces of the source and drain electrodes of the semiconductor device; then, generating a nickel-silicon compound through rapid thermal annealing, and removing the unreacted nickel-platinum alloy layer using a wet etching process; subsequently, performing rapid thermal annealing again to convert the nickel-silicon compound into a low-resistivity metallic silicide (NiSi). The wet etching process for nickel-platinum alloys has high process requirements, typically using aqua regia or high-temperature sulfuric acid-hydrogen peroxide solutions as etchants.

[0003] However, as mentioned above, the etchant can easily damage the generated nickel-silicon compound, and the etchant causes significant environmental pollution. Reducing the dosage of the etchant may result in unreacted nickel-platinum alloys not being cleaned properly, thereby affecting the yield and stability of semiconductor devices. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor device and a method for manufacturing the same, so as to reduce the probability of damage to the metal silicide layer and reduce or avoid the problem of metal residue on the metal silicide layer.

[0005] This application provides a method for manufacturing a semiconductor device, comprising:

[0006] A wafer is provided, the wafer including a substrate on which a gate structure is formed, and the top and sidewalls of the gate structure are covered with a barrier layer;

[0007] A first ion implantation region is formed in the substrate on both sides of the gate structure;

[0008] The wafer is immersed in a mixed solution and continuously irradiated with visible light to form a reduction layer on the exposed surface of the substrate, the reduction layer covering the first ion implantation region;

[0009] The wafer is annealed to form a metal silicide layer in the first ion implantation region.

[0010] In one embodiment, the mixed solution includes a reducing agent, a sacrificial agent, and a modifier, wherein the reducing agent includes nickel chloride and chloroplatinic acid, the sacrificial agent includes methanol, and the modifier includes one of ammonium fluoride and hydrofluoric acid.

[0011] In one embodiment, the material of the reduction layer includes a nickel-platinum alloy, the material of the metal silicide layer includes a nickel-silicon compound, and the platinum content in the reduction layer is less than or equal to 10%.

[0012] In one embodiment, the process of forming a first ion implantation region in the substrate on both sides of the gate structure includes:

[0013] An ion implantation process is used to implant impurity ions into the substrate to form the first ion implantation region, and a second ion implantation region is formed on the side of the barrier layer away from the gate structure.

[0014] Remove the second ion implantation region.

[0015] In one embodiment, the impurity ions implanted in the first ion implantation region and the second ion implantation region include metal elements, said metal elements including one of metallic nickel and metallic iron.

[0016] In one embodiment, a wet etching process is used to remove the second ion implantation region, and when the material of the barrier layer includes silicon nitride, the etchant of the wet etching process includes phosphoric acid.

[0017] In one embodiment, during the annealing process of the wafer, the process temperature range of the annealing process includes 400°C to 600°C.

[0018] In one embodiment, after the first ion implantation region is formed and before the wafer is immersed in a mixed solution, a protective layer is applied to the surface of the substrate on the side of the first ion implantation region away from the gate structure.

[0019] In one embodiment, the protective layer is made of silicon nitride.

[0020] Accordingly, this application also provides a semiconductor device manufactured using the semiconductor device manufacturing method described above.

[0021] The unexpected effect of this application is that by forming a barrier layer covering the gate structure on the substrate within the wafer and forming a first ion implantation region in the substrate on both sides of the gate structure, damage to the gate structure in subsequent process steps can be reduced or avoided. By immersing the wafer in a mixed solution and continuously irradiating the wafer with visible light, a reduction layer covering the first ion implantation region is formed on the exposed surface of the substrate. Then, by annealing, a metal silicide layer is formed on the substrate on both sides of the gate structure, reducing or even avoiding the probability of damage to the metal silicide layer, solving the problem of metal residue on the metal silicide layer, and reducing the environmental pollution caused by the mixed solution. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of this application.

[0024] Figure 2 This is a schematic diagram of the structure corresponding to the step of providing a wafer in the manufacturing method of a semiconductor device provided in one embodiment of this application.

[0025] Figure 3 This is a schematic diagram of the structure corresponding to the step of implanting impurity ions into a substrate using an ion implantation process in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0026] Figure 4 This is a schematic diagram of the structure corresponding to the step of removing the second ion implantation region in the manufacturing method of a semiconductor device provided in one embodiment of this application.

[0027] Figure 5 This is a schematic diagram of the structure corresponding to the step of immersing a wafer in a mixed solution and continuously irradiating it with visible light in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0028] Figure 6 This is a schematic diagram of the structure corresponding to the step of forming a reduction layer on the exposed surface of a substrate in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0029] Figure 7 This is a schematic diagram of the structure corresponding to the step of annealing a wafer and forming a metal silicide layer in a first ion implantation region in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0030] The reference numerals in the figures include: 100-substrate; 101-first ion implantation region; 110-gate structure; 111-gate; 112-gate sidewall; 120-barrier layer; 121-second ion implantation region; 130-reduction layer; 140-metal silicide layer; W-wafer; A-reaction tank; a-mixed solution; L-visible light. Detailed Implementation

[0031] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0033] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0034] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as “below,” “below,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0035] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0036] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of this application. See also... Figure 1 One embodiment of this application provides a method for manufacturing a semiconductor device, which includes the following steps S01 to S04.

[0037] Step S01: Provide a wafer, the wafer including a substrate, on which a gate structure is formed, and the top and sidewalls of the gate structure are covered with a barrier layer.

[0038] It should be noted that by forming a barrier layer and covering the sidewalls and top of the gate structure, the barrier layer can be used to protect the gate structure in subsequent process steps, thereby reducing or even avoiding damage to the gate structure in subsequent process steps, which helps to improve the yield and stability of semiconductor devices.

[0039] Step S02: Form a first ion implantation region in the substrate on both sides of the gate structure.

[0040] Step S03: Immerse the wafer in a mixed solution and continuously irradiate the wafer with visible light to form a reduction layer on the exposed surface of the substrate, the reduction layer covering the first ion implantation region.

[0041] It should be noted that since silicon materials at the nanoscale exhibit good photocatalytic ability, the photocatalytic ability of wafers can be used to achieve metal deposition, thereby forming a reduction layer on the exposed surface of the substrate, which in turn helps to provide a foundation for the subsequent steps of forming metal silicide layers.

[0042] Step S04: Anneal the wafer to form a metal silicide layer in the first ion implantation region.

[0043] The semiconductor device manufacturing method described above reduces or avoids damage to the gate structure in subsequent processes by forming a barrier layer covering the gate structure on a substrate within a wafer and forming first ion implantation regions in the substrate on both sides of the gate structure. By immersing the wafer in a mixed solution and continuously irradiating the wafer with visible light, a reduction layer covering the first ion implantation region is formed on the exposed surface of the substrate. Then, a metal silicide layer is formed on the substrate on both sides of the gate structure through annealing. This reduces or even avoids the probability of damage to the metal silicide layer, solves the problem of metal residue on the metal silicide layer, and reduces the environmental pollution caused by the mixed solution.

[0044] Figures 2 to 7 This is a schematic diagram of the structure corresponding to some steps in the manufacturing method of a semiconductor device provided in one embodiment of this application. The following is in conjunction with... Figures 2 to 7 This application provides a detailed description of a method for manufacturing a semiconductor device according to one embodiment.

[0045] First, refer to Figure 2 The process in step S01 includes: providing a wafer W, the wafer W including a substrate 100, a gate structure 110 formed on the substrate 100, and a barrier layer 120 covering the top and sidewalls of the gate structure 110. Optionally, the material of the substrate 100 includes silicon (Si). Optionally, the material of the barrier layer 120 includes silicon nitride (SiN), and the barrier layer 120 covering the gate structure 110 is formed using a chemical vapor deposition (CVD) process.

[0046] Continue reading Figure 2 In one embodiment of this application, the gate structure 110 includes a gate 111 and a gate sidewall 112, wherein the gate 111 is formed on the substrate 100, and the gate sidewall 112 covers the sidewalls and top of the gate 111. Optionally, the material of the gate 111 includes polysilicon, and the material of the gate sidewall 112 includes at least one of silicon oxide and silicon nitride.

[0047] It should be noted that in other embodiments of this application, the relevant parameters (such as materials and thicknesses) of the substrate, gate structure, and barrier layer can be adjusted according to actual process requirements, and this application does not impose any limitations on this. Furthermore, the specific manufacturing process of the gate structure is common knowledge well-known to those skilled in the art, and therefore will not be described in detail here.

[0048] Next, refer to Figure 3 and Figure 4 Step S02 includes forming a first ion implantation region 101 within the substrate 100 on both sides of the gate structure 110. Exemplarily, in one embodiment, the process of forming the first ion implantation region 101 within the substrate 100 on both sides of the gate structure 110 includes: firstly, referring to… Figure 3 An ion implantation process is used to implant impurity ions into the substrate 100 to form a first ion implantation region 101, and a second ion implantation region 121 is formed on the side of the barrier layer 120 away from the gate structure 110; then, refer to Figure 4 The second ion implantation region 121 is removed. Optionally, the implantation voltage range of the ion implantation process includes 200 eV to 1000 eV, and the implantation dose is, for example, 1 × 10⁻⁶. 18 atom / cm 2 .

[0049] Continue reading Figure 3 In one embodiment, the impurity ions implanted in the first ion implantation region 101 and the second ion implantation region 121 include metal elements, specifically nickel (Ni) and iron (Fe). It should be noted that the implanted metal elements can form a reduction layer in subsequent process steps. Therefore, those skilled in the art can select appropriate metal elements for impurity ion implantation based on the specific type of reduction layer to be formed, and this application does not impose any limitations in this regard.

[0050] Continue reading Figure 4 In one embodiment, a wet etching process is used to remove the second ion implantation region 121, and when the material of the barrier layer 120 includes silicon nitride, the etchant of the wet etching process includes phosphoric acid.

[0051] In one embodiment, after forming the first ion implantation region and before immersing the wafer in a mixed solution, the method for manufacturing the semiconductor device further includes forming a protective layer on the substrate surface on the side of the first ion implantation region away from the gate structure, to protect other areas of the substrate surface from damage in subsequent steps. Optionally, the material of the protective layer includes silicon nitride.

[0052] Then refer to Figure 5 and Figure 6Step S03 includes immersing the wafer W in a mixed solution a and continuously irradiating the wafer W with visible light L to form a reduction layer 130 on the exposed surface of the substrate 100, wherein the reduction layer 130 covers the first ion implantation region 101. In one embodiment, the wavelength range of the visible light includes 300 nm to 800 nm.

[0053] Continue reading Figure 5 In one embodiment, the reaction tank A contains a mixed solution a, and a light source (not shown in the figure) is placed directly above the reaction tank A. During the formation of the reduction layer, the wafer W is completely immersed in the mixed solution a, and the visible light emitted by the light source continuously irradiates the wafer W, causing electrons and holes to be generated on the surface of the wafer W. At this time, the generated holes are consumed by the sacrificial agent in the mixed solution, and the generated electrons combine with the reducing agent in the mixed solution and undergo a metal reduction reaction. The reduced metal is deposited on the wafer surface and forms a reduction layer.

[0054] In one embodiment, the mixed solution includes a reducing agent, a sacrificial agent, and a modifier, wherein the reducing agent includes nickel chloride and chloroplatinic acid, the sacrificial agent includes methanol, and the modifier includes one of ammonium fluoride and hydrofluoric acid. Optionally, the material of the reduction layer includes a nickel-platinum alloy (NiPt), and the content of platinum (Pt) in the reduction layer is less than or equal to 10%.

[0055] Table 1. Examples of relationships between the components of the mixed solution, illumination parameters, and reduction layer parameters.

[0056]

[0057] For example, the relationship between the components of the mixed solution, the relevant parameters of illumination, and the parameters of the formed reduction layer is shown in Table 1. In other embodiments of this application, those skilled in the art can adjust the composition and content of the mixed solution, illumination parameters, etc., according to actual process requirements to obtain a reduction layer that meets the process requirements. This is something that those skilled in the art can reasonably infer from common knowledge in the field, and this application does not impose any limitations on it.

[0058] It should be noted that during the formation of the reduction layer as described above, the wafer surface is gradually covered by the reduction layer as the reaction proceeds. When the wafer surface is completely covered by the reduction layer, the wafer can no longer absorb visible light, and the reduction reaction stops. Furthermore, when the substrate includes silicon and the protective layer includes silicon nitride, since the band gap of silicon is only 1.21 eV while that of silicon nitride reaches 6 eV, the protective layer has no photocatalytic activity during the reduction process described above, and no metal deposition occurs on the portion of the substrate surface covered by the protective layer. In other words, the portion of the substrate surface covered by the protective layer does not form a reduction layer.

[0059] Then refer to Figure 7 Step S04 includes annealing the wafer W to form a metal silicide layer 140 within the first ion implantation region 101. In one embodiment, if the material of the reduction layer 130 includes a nickel-platinum alloy (NiPt), the material of the metal silicide layer 140 includes a nickel-silicon compound (NiSi).

[0060] Continue reading Figure 7 In one embodiment, the annealing process for wafer W is carried out at a temperature range of 400°C to 600°C. In other embodiments of this application, the specific process parameters for annealing can be adjusted according to actual process requirements, and this application does not impose any limitations on this.

[0061] Accordingly, this application also provides a semiconductor device manufactured using the semiconductor device manufacturing method described above. In other embodiments of this application, other identical or similar semiconductor structures can also be manufactured using the semiconductor device manufacturing method described above to solve the problem of metal residues easily generated during the preparation of silicide layers, while also helping to reduce environmental pollution caused by the mixed solutions used in the manufacturing process.

[0062] See Figure 7 In one embodiment, the semiconductor device includes a substrate 100, a gate structure 110, a barrier layer 120, and a metal silicide layer 140; wherein the gate structure 110 is disposed on the substrate 100, the barrier layer 120 is located on the gate structure 110 and covers the sidewalls of the gate structure 110, and the metal silicide layer 140 is located on the substrate 100 on both sides of the gate structure 110. Optionally, the material of the substrate 100 includes silicon (Si), the material of the barrier layer 120 includes silicon nitride (SiN), and the material of the metal silicide layer 140 includes nickel silicon compound (NiSi).

[0063] In one embodiment of this application, the gate structure 110 includes a gate 111 and a gate sidewall 112, wherein the gate 111 is formed on the substrate 100, and the gate sidewall 112 covers the sidewalls and top of the gate 111. Optionally, the material of the gate 111 includes polysilicon, and the material of the gate sidewall 112 includes at least one of silicon oxide and silicon nitride.

[0064] The unexpected effect of this application is that by forming a barrier layer covering the gate structure on the substrate within the wafer and forming a first ion implantation region in the substrate on both sides of the gate structure, damage to the gate structure in subsequent process steps can be reduced or avoided. By immersing the wafer in a mixed solution and continuously irradiating the wafer with visible light, a reduction layer covering the first ion implantation region is formed on the exposed surface of the substrate. Then, by annealing, a metal silicide layer is formed on the substrate on both sides of the gate structure, reducing or even avoiding the probability of damage to the metal silicide layer, solving the problem of metal residue on the metal silicide layer, and reducing the environmental pollution caused by the mixed solution.

[0065] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0066] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0067] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A wafer is provided, the wafer including a substrate on which a gate structure is formed, and the top and sidewalls of the gate structure are covered with a barrier layer; A first ion implantation region is formed in the substrate on both sides of the gate structure; The wafer is immersed in a mixed solution and continuously irradiated with visible light to form a reduction layer on the exposed surface of the substrate, the reduction layer covering the first ion implantation region; The wafer is annealed to form a metal silicide layer in the first ion implantation region.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The mixed solution includes a reducing agent, a sacrificial agent, and a modifier, wherein the reducing agent includes nickel chloride and chloroplatinic acid, the sacrificial agent includes methanol, and the modifier includes one of ammonium fluoride and hydrofluoric acid.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The material of the reduction layer includes a nickel-platinum alloy, the material of the metal silicide layer includes a nickel-silicon compound, and the content of platinum in the reduction layer is less than or equal to 10%.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The process of forming a first ion implantation region in the substrate on both sides of the gate structure includes: An ion implantation process is used to implant impurity ions into the substrate to form the first ion implantation region, and a second ion implantation region is formed on the side of the barrier layer away from the gate structure. Remove the second ion implantation region.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that, The impurity ions implanted in the first ion implantation region and the second ion implantation region include metal elements, and the metal elements include one of metallic nickel and metallic iron.

6. The method for manufacturing a semiconductor device according to claim 4, characterized in that, The second ion implantation region is removed using a wet etching process, and when the material of the barrier layer includes silicon nitride, the etchant used in the wet etching process includes phosphoric acid.

7. The method for manufacturing a semiconductor device according to claim 1, characterized in that, During the annealing process of the wafer, the annealing temperature range includes 400℃ to 600℃.

8. The method for manufacturing a semiconductor device according to claim 1, characterized in that, After the first ion implantation region is formed and before the wafer is immersed in a mixed solution, a protective layer is applied to the surface of the substrate on the side of the first ion implantation region away from the gate structure.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The material of the protective layer includes silicon nitride.

10. A semiconductor device, characterized in that, It is manufactured using the manufacturing method of any one of claims 1 to 9.

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