A silicon carbide power device and chip

Abstract

This application belongs to the field of semiconductor technology and provides a silicon carbide power device and chip. By forming a P-type heavily doped region on an N-type drift layer and setting the lower surface height of the P-type well region to gradually increase from the side closer to the P-type heavily doped region to the side farther away from the P-type heavily doped region, a P-type well region with a tilted interface is formed. Combined with the gate dielectric layer and the gate polysilicon layer of the planar gate structure, the tilted interface of the P-type well region bears the electric field, reducing the peak electric field of the gate dielectric layer and the device, and improving the reliability of the device. Furthermore, the second electrode on its gate dielectric is set as a shallow trench structure, which reduces the specific on-resistance of the device. While optimizing the current spread capability of the device, it reduces its on-resistance at high temperature, enhances the saturation current clamping capability of the device, and improves the short-circuit withstand capability of the device.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a silicon carbide power device and chip. Background Technology

[0002] Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have become core devices in high-voltage power electronic systems due to their excellent material properties (such as high critical breakdown electric field, high thermal conductivity, and high saturated electron drift velocity). Currently, mainstream commercial SiC MOSFET structures are mainly divided into two categories: traditional planar gate structures and trench gate structures. While traditional planar gate SiC MOSFETs have good gate oxide reliability, they suffer from a decrease in channel mobility and threshold voltage drift with increasing temperature, leading to a significant increase in on-resistance at high temperatures and increased system losses.

[0003] While trench gate MOSFET power devices reduce on-resistance, they typically have high current saturation capability, leading to excessively high short-circuit current peaks, severe device heating, and reduced short-circuit withstand time. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a silicon carbide power device and chip, aiming to provide a silicon carbide power device that simultaneously achieves low on-resistance and strong short-circuit withstand capability.

[0005] A first aspect of this application provides a silicon carbide power device, the silicon carbide power device comprising: silicon carbide substrate; An N-type drift layer formed on the front side of the silicon carbide substrate; A P-type heavily doped region is formed on the N-type drift layer; a P-type well region is formed on the current extension region; the height of the lower surface of the P-type well region gradually increases from the side closer to the P-type heavily doped region to the side farther away from the P-type heavily doped region; An N-type heavily doped region formed on the P-type well region; A gate dielectric layer and a gate polysilicon layer are formed on the current extension region, the P-type well region, and the N-type heavily doped region, wherein the gate dielectric layer and the interlayer dielectric layer form a cavity structure to enclose the gate polysilicon layer, and the gate polysilicon layer is disposed opposite to at least a portion of the N-type drift layer, the P-type well region, and the N-type heavily doped region to form a planar gate structure. A first electrode formed on the back side of the silicon carbide substrate; A second electrode is formed on the interlayer dielectric layer and the P-type heavily doped region. The second electrode extends along the side above the gate dielectric layer to the P-type heavily doped region and contacts the N-type heavily doped region.

[0006] In some embodiments, the upper part of the N-type drift layer is a current spreading region, the lower part of the N-type drift layer is a drift region, and the doping concentration of the current spreading region is greater than the doping concentration of the drift region; The P-type well region is formed between the current-spreading region and the heavily doped P-type region; wherein the thickness of the current-spreading region gradually decreases from the side away from the heavily doped P-type region to the side closer to the heavily doped P-type region.

[0007] In some embodiments, the upper surface of the N-type heavily doped region is higher than the upper surface of the P-type heavily doped region, the gate dielectric layer covers a portion of the N-type heavily doped region, the vertical portion of the second electrode has a stepped structure, and the second electrode extends stepwise from the upper surface of the gate dielectric layer and the upper surface of the N-type heavily doped region to the P-type heavily doped region.

[0008] In some embodiments, the P-type well region is located between the vertical portion of the current extension region and the heavily doped P-type region. The P-type well region includes a plurality of sub-well regions, and the doping concentration of the plurality of sub-well regions gradually increases from the current extension region to the heavily doped P-type region.

[0009] In some embodiments, the P-type well region is located between the vertical portion of the current extension region and the heavily doped P-type region, and the doping concentration of the P-type well region gradually decreases from the drift region toward the heavily doped N-type region.

[0010] In some embodiments, the interface between the P-type well region and the current extension region is any one of an arc surface, a linear inclined surface, a continuous curved surface, or a continuous irregular curved surface.

[0011] In some embodiments, the thickness of the P-type well region is less than the thickness of the current spreading region, and the interface depth between the heavily doped P-type region and the current spreading region is greater than half the thickness of the heavily doped P-type region; and / or The thickness of the P-type heavily doped region is greater than 2.5 μm.

[0012] In some embodiments, the silicon carbide power device further includes: A P-type floating region is formed between the drift region and the current expansion region.

[0013] In some embodiments, the second electrode is an emitter, the first electrode is a collector, and the silicon carbide substrate is P-type doped.

[0014] A second aspect of this application also provides a chip including a silicon carbide power device as described in any of the preceding embodiments.

[0015] The beneficial effects of this application embodiment compared with the prior art are as follows: By forming a heavily doped P-type region on the N-type drift layer and setting the lower surface height of the P-type well region to gradually increase from the side closer to the heavily doped P-type region to the side farther away from the heavily doped P-type region, a P-type well region with a tilted interface is formed. Combined with the planar gate dielectric layer and the gate polysilicon layer, the tilted interface of the P-type well region bears the electric field, reducing the overall electric field peak of the gate dielectric layer and the device, and improving the reliability of the device. Furthermore, setting the second electrode on the gate dielectric layer to a shallow trench structure reduces the specific on-resistance of the device. While optimizing the current spread capability of the device, it reduces its on-resistance at high temperature, enhances the saturation current clamping capability of the device, and improves the short-circuit withstand capability of the device. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of a silicon carbide power device provided in one embodiment of this application. Figure 1 ; Figure 2 This is a schematic diagram of the structure of a silicon carbide power device provided in one embodiment of this application. Figure 2 ; Figure 3 This is a schematic diagram of the structure of a silicon carbide power device provided in one embodiment of this application. Figure 3 ; Figure 4 This is a schematic diagram of the structure of a silicon carbide power device provided in one embodiment of this application. Figure 4 ; Figure 5 This is a schematic diagram of the structure of a silicon carbide power device provided in one embodiment of this application. Figure 5 ; Figure 6 This is a schematic diagram of the structure of a silicon carbide power device provided in one embodiment of this application. Figure 6 ; Figure 7 This is a schematic diagram of the structure of a silicon carbide power device provided in one embodiment of this application. Figure 7 ; Figure 8 This is a schematic diagram of the structure of a silicon carbide power device provided in one embodiment of this application. Figure 8 ; Figure 9 This is a schematic diagram of the structure of a silicon carbide power device provided in one embodiment of this application. Figure 9 ; Figure 10 This is a schematic diagram of the structure of a silicon carbide power device provided in one embodiment of this application. Figure 10 ; Figure 11 This is a schematic diagram of the doping concentration distribution of a silicon carbide power device with a P-type well region formed by tilted implantation and a P-type well region formed by planar implantation, according to an embodiment of this application. Figure 12 This is a schematic diagram of the electric field distribution of a silicon carbide power device with a P-type well region formed by tilted injection and a P-type well region formed by planar injection, according to an embodiment of this application. Figure 13 This is a schematic diagram of the breakdown voltage curves of a silicon carbide power device with a P-type well region formed by tilted injection and a P-type well region formed by planar injection, according to an embodiment of this application. Figure 14a This is a schematic diagram of the electric field peak of the gate dielectric layer of a silicon carbide power device with a P-type well region formed by planar implantation according to an embodiment of this application; Figure 14b This is a schematic diagram of the electric field peak of the gate dielectric layer of a silicon carbide power device with a P-type well region formed by tilted injection, provided in one embodiment of this application. Detailed Implementation

[0017] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0018] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0019] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means one or more, unless otherwise explicitly specified.

[0021] In this application specification, references to "one embodiment," "some embodiments," or "embodiment" mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," "in a particular embodiment," "in a particular application," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, specific features, structures, or characteristics may be combined in any suitable manner.

[0022] While traditional trench MOSFET devices reduce on-resistance, they introduce more severe reliability challenges. For example, the electric field strength at the corner of the trench bottom is much higher than that of the planar gate, causing the gate oxide to be subjected to extremely high voltage stress. To alleviate this problem, a double trench structure is usually required. Although the double trench structure alleviates the gate oxide electric field, it increases the process complexity, and the source trench is deeper, which can easily introduce new leakage current channels.

[0023] On the other hand, trench gate structures also present significant manufacturing challenges. Anisotropic etching of SiC is difficult, controlling the roughness of the trench sidewalls is challenging, and the rounding of the trench bottom places extremely high demands on the process window. Trench gate structures typically exhibit high current saturation capability, leading to excessively high short-circuit current peaks, severe device heating, and reduced short-circuit withstand time. In summary, current technology has not yet provided a SiC MOSFET structure that simultaneously achieves low on-resistance and strong short-circuit withstand capability without significantly increasing process complexity.

[0024] To provide a silicon carbide power device that simultaneously achieves at least two of the following: low on-resistance and strong short-circuit withstand capability, see [link to relevant documentation]. Figure 1 As shown, the silicon carbide power device in this embodiment includes: a silicon carbide substrate 110, an N-type drift layer 200, a P-type heavily doped region 310, a P-type well region 410, an N-type heavily doped region 510, a gate dielectric layer 611, an interlayer dielectric layer 612, a gate polysilicon layer 620, a second electrode 720, and a first electrode 710.

[0025] An N-type drift layer 200 is formed on the front side of a silicon carbide substrate 110. A P-type well region 410 and a P-type heavily doped region 310 are formed on the N-type drift layer 200. The P-type heavily doped region 310 and the P-type well region 410 are arranged adjacent to each other, and the P-type well region 410 is located between the N-type drift layer 200 and the P-type heavily doped region 310. The height of the lower surface of the P-type well region 410 gradually increases from the side closer to the P-type heavily doped region 310 to the side farther away from the P-type heavily doped region 310.

[0026] An N-type heavily doped region 510 is formed on a P-type well region 410. A gate dielectric layer 611 and a gate polysilicon layer 620 are formed on the P-type well region 410, the N-type heavily doped region 510, and the N-type drift layer 200. The gate dielectric layer 611 encapsulates the gate polysilicon layer 620. The gate polysilicon layer 620 is disposed opposite to the N-type drift layer 200 and the P-type well region 410, and is also disposed opposite to at least a portion of the N-type heavily doped region 510 to form a planar gate structure.

[0027] The second electrode 720 is formed on the interlayer dielectric layer 612 and the P-type heavily doped region 310, extending along the upper surface and side surface of the interlayer dielectric layer 612 to the P-type heavily doped region 310, and contacting the side surface of the N-type heavily doped region 510 to form a shallow trench structure.

[0028] In this embodiment, the planar gate structure combined with the sloped P-type well region 410 and the shallow trench electrode utilizes the sloped P-type well region 410 as an "electric field drainage channel" for the entire device structure. Since the second electrode 720 extends along the upper and side surfaces of the interlayer dielectric layer 612 to the heavily doped P-type region 310 and contacts the heavily doped N-type region 510, when a blocking voltage is applied, the high potential of the first electrode 710 splits and shunts the current in both the up and down directions along the slope, completely changing the slope of the equipotential line and cutting off the risk of electric field breakdown at the sharp corner of the gate dielectric layer from the source.

[0029] In some embodiments, see Figure 2 As shown, the N-type drift layer 200 includes a drift region 210 and a current spreading region 220. The upper part of the N-type drift layer 200 is the current spreading region 220, and the lower part of the N-type drift layer 200 is the drift region 210. That is, the current spreading region 220 is in contact with the gate dielectric layer 611, and the drift region 210 is in contact with the front side of the silicon carbide substrate 110.

[0030] In some embodiments, the doping concentration of the current extension region 220 is greater than the doping concentration of the drift region 210. The current extension region 220 and the P-type heavily doped region 310 are formed on the drift region 210. The P-type heavily doped region 310 is disposed adjacent to the current extension region 220, and the P-type well region is located between the current extension region 220 and the P-type heavily doped region 310.

[0031] In some embodiments, see Figure 2 As shown, the current extension region 220 includes a vertical portion and an inclined portion. The thickness of the inclined portion gradually decreases from the side away from the heavily doped P-type region 310 to the side closer to the heavily doped P-type region 310. The lower surface of the vertical portion contacts the drift region 210, and the upper surface of the vertical portion contacts the gate dielectric layer 611. The contact surface between the inclined portion and the P-type well region 410 is an inclined plane (which is the lower surface of the P-type well region 410). By setting the P-type well region 410 containing this inclined plane, it serves as an "electric field venting channel" for the entire device structure. When a blocking voltage is applied, the high potential of the first electrode 710 splits and shunts the current in both the vertical and horizontal directions along the inclined plane, completely changing the slope of the equipotential line and cutting off the risk of electric field breakdown at the sharp corner of the dielectric layer from the source.

[0032] In some embodiments, the second electrode 720 is the source, the first electrode 710 is the drain, and the gate dielectric layer 611 is a silicon oxide layer. The electric field is mainly concentrated at the corner of the P-type well region 410. In this embodiment, by forming a contact surface with an inclined angle at the interface between the P-type well region 410 and the N-type drift layer 200, the vertical blocking wall is essentially transformed into a gentle slope. When a blocking voltage is applied, the high potential of the drain is bifurcated along the inclined surface in both the up and down directions, reducing the risk of electric field breakdown at the sharp corner of the gate dielectric layer 611.

[0033] In some embodiments, a P-type well region 410 is formed on the current extension region 220, and an N-type heavily doped region 510 is formed on the P-type well region 410. In this embodiment, the N-type heavily doped region 510 can be formed by implanting N-type dopant ions into the side of the P-type well region 410 closest to the P-type heavily doped region 310, and the concentration of N-type dopant ions in the N-type heavily doped region 510 is greater than the concentration of P-type dopant ions in the P-type well region 410. The gate polysilicon layer 620 is disposed opposite to the P-type well region 410.

[0034] In some embodiments, the second electrode 720 is formed on the interlayer dielectric layer 612 and the P-type heavily doped region 310, and the second electrode 720 has an L-shaped structure. The first electrode 710 is formed on the back side of the silicon carbide substrate 110.

[0035] In this embodiment, the second electrode 720 has an L-shaped structure. The horizontal portion of the second electrode 720 covers the interlayer dielectric layer 612, and the vertical portion of the second electrode 720 extends to the side of the interlayer dielectric layer 612 and contacts the P-type heavily doped region 310. The N-type heavily doped region 510 is located in the space formed by the P-type well region 410, the second electrode 720, and the gate dielectric layer 611. By forming adjacent current extension regions 220 and P-type heavily doped regions 310 on the drift region 210, and setting the thickness of the current extension region 220 to gradually decrease from the side away from the P-type heavily doped region 310 to the side closer to the P-type heavily doped region 310, a P-type well region 410 is formed on the current extension region 220, thereby forming a P-type well region 410 with a tilted interface. This allows the tilted interface of the P-type well region 410 to bear the electric field, reducing the peak electric field of the gate dielectric layer 611 and the device, and improving the reliability of the device. Furthermore, by setting the second electrode 720 on its interlayer dielectric layer 612 to an L-shaped structure, the specific on-resistance of the device is reduced. While optimizing the current extension capability of the device, its on-resistance at high temperature is reduced, enhancing the saturation current clamping capability of the device and improving the short-circuit withstand capability of the device.

[0036] In some embodiments, such as Figure 2 As shown, the thickness of the gate dielectric layer 611 between the gate polysilicon layer 620 and the current extension region 220 is less than the thickness of the interlayer dielectric layer 612 between the gate polysilicon layer 620 and the second electrode 720.

[0037] In this embodiment, the second electrode 720 extends into the heavily doped P-type region 310 via a channel. The width of the vertical portion of the second electrode 720 is the same as the width of the heavily doped P-type region 310, but smaller than the width of the P-type well region 410. Since the trench depth is strictly limited to less than 1 μm, the planar area required for a single cell is significantly reduced while ensuring good ohmic contact. This directly results in an extremely narrow cell pitch of ≤5 μm. Within this confined space, the JFET spacing of the device is reduced to <1.5 μm, greatly reducing the overall specific on-resistance of the device.

[0038] In some embodiments, the depth of the vertical portion of the second electrode 720 is less than 1 μm, and its depth range can be set to 0.2-0.8 μm.

[0039] In some embodiments, see Figure 2As shown, the upper surface of the N-type heavily doped region 510 is higher than the upper surface of the P-type heavily doped region 310. The gate dielectric layer 611 covers a portion of the N-type heavily doped region 510. The vertical portion of the second electrode 720 has a stepped structure, and the horizontal portion of the second electrode 720 covers the interlayer dielectric layer 612. The second electrode 720 extends stepwise from the upper surface of the gate dielectric layer 611 and the upper surface of the N-type heavily doped region 510 to the P-type heavily doped region 310.

[0040] In this embodiment, combined with Figure 2 As shown, the vertical portion of the second electrode 720 has a stepped structure, and the width of the gate dielectric layer 611 is smaller than the width of the current extension region 220.

[0041] In some embodiments, the lower surface of the P-type well region 410 is inclined at an angle between 1° and 30°, the total depth of the P-type well region 410 is 1.2–2.5 μm, and the doping concentration of the P-type well region 410 exhibits a gradient distribution, with the doping concentration near the channel being lower than the high concentration at the bottom. Thus, the geometry of the PN junction can be altered using the inclined structure, transforming the traditional vertical electric field distribution into an oblique electric field distributed along the inclined surface.

[0042] In some embodiments, see Figure 3 As shown, the P-type well region 410 is located between the vertical portion of the current extension region 220 and the P-type heavily doped region 310. The P-type well region 410 includes multiple sub-well regions, and the doping concentration of the multiple sub-well regions gradually increases from the current extension region 220 to the P-type heavily doped region 310.

[0043] In this embodiment, combined with Figure 3 As shown, the P-type well region 410 includes a first sub-well region 411 and a second sub-well region 412, with the doping concentration of the second sub-well region 412 being lower than that of the first sub-well region 411. The second sub-well region 412 is located near the vertical portion of the current extension region 220, while the first sub-well region 411 is located near the heavily doped P-type region 310. The first sub-well region 411 can serve as the main discharge channel, and during high-voltage blocking, it is the first sub-well region 411 that is depleted first, undertaking the main longitudinal withstand voltage task. In this way, the high electric field region can be transferred from the sensitive channel region to the depth of the device, protecting the channel from high field stress. The deep P-well structure provides a larger avalanche current distribution volume, improving the device's UIS (unclamped inductive load switch) capability.

[0044] In some embodiments, the doping concentration of the portion of the first sub-well region 411 closer to the current extension region 220 is greater than the doping concentration of the portion of the first sub-well region 411 farther from the current extension region 220.

[0045] In some embodiments, the doping concentration of the portion of the second sub-well region 412 closer to the current extension region 220 is greater than the doping concentration of the portion of the second sub-well region 412 farther from the current extension region 220.

[0046] In some embodiments, the P-type well region 410 is located between the vertical portion of the current extension region 220 and the P-type heavily doped region 310, and the doping concentration of the P-type well region 410 gradually decreases from the drift region 210 toward the N-type heavily doped region 510.

[0047] In some embodiments, the depth of the P-type heavily doped region 310 is greater than the depth of the P-type well region 410, and the doping concentration of the P-type well region 410 gradually decreases from the drift region 210 to the N-type heavily doped region 510. Its doping concentration is non-uniformly doped, which realizes a smooth transition of the electric field from the high-voltage region to the low-voltage region, so as to prevent electric field spikes caused by abrupt changes in depth and realize the balanced management of the electric field. Moreover, gradient doping reduces interface states and reduces reverse leakage current at high temperatures.

[0048] In some embodiments, the lower surface of the P-type well region 410 is an arc surface or a linear slope.

[0049] In some embodiments, the lower surface of the P-type well region 410 is a continuous curved surface, which can be a regular curved surface or an irregular curved surface.

[0050] In this embodiment, by setting the lower surface of the P-type well region 410 as an arc surface or a linear slope, a buffered slope structure can be formed. The lower surface of the P-type well region 410 extends slowly from the lower left corner of the heavily doped P-type region 310 to the vertical part of the current extension region 220. The continuously inclined interface of the P-type well region 410 can reduce the interface electric field spikes, so that the electric field transitions smoothly from the high-voltage region to the low-voltage region.

[0051] In some embodiments, see Figure 4 As shown, the lower surface of the P-type well region 410 is an arc surface. The thickness of the P-type well region 410 is the same as the thickness of the current extension region 220. The height of the arc surface between the P-type well region 410 and the current extension region 220 is greater than half the thickness of the current extension region 220.

[0052] In this embodiment, combined with Figure 4 As shown, the lower surface of the P-type well region 410 is an arc surface. The arc-shaped interface of the P-type well region 410 extends from the lower surface of the heavily doped P-type region 310 to the vertical part of the current extension region 220. The interface between the vertical part of the current extension region 220 and the P-type well region 410 is linear. In this way, the continuously tilted interface of the P-type well region 410 can reduce the interface electric field peaks and make the electric field transition smoothly from the high voltage region to the low voltage region.

[0053] In some embodiments, see Figure 5As shown, the lower surface of the P-type well region 410 is a series of continuous arc surfaces connected together, extending from the lower surface of the heavily doped P-type region 310 to the vertical part of the current extension region 220. The interface between the vertical part of the current extension region 220 and the P-type well region 410 is linear. Thus, the lower surface of the P-type well region 410 is a stepped, continuously inclined arc-shaped interface, which can reduce the electric field peaks at the interface, balance the distribution of the internal electric field, and achieve a smooth transition of the electric field from the high-voltage region to the low-voltage region.

[0054] In some embodiments, see Figure 6 As shown, the thickness of the P-type well region 410 is less than the thickness of the current extension region 220, and the interface depth between the heavily doped P-type region 310 and the current extension region 220 is greater than half the thickness of the heavily doped P-type region 310.

[0055] In this embodiment, the thickness of the P-type well region 410 is less than the thickness of the current extension region 220. The P-type well region 410 and the current extension region 220 are at an inclined interface. The inclined interface extends from a region at a depth higher than half the depth of the heavily doped P-type region 310 to the vertical part of the current extension region 220. Through gradient doping, the distribution of the internal electric field can be balanced, so that the electric field can smoothly transition from the high-voltage region to the low-voltage region.

[0056] In some embodiments, the thickness of the P-type heavily doped region 310 is greater than 2.5 μm.

[0057] In some embodiments, see Figure 7 As shown, in Figure 6 Based on the structure, the vertical portion of the second electrode 720 can also be set to extend downward to contact a portion of the side surface of the P-type well region 410.

[0058] In some embodiments, the second electrode 720 is a source electrode, and the depth of the source electrode trench is greater than 1 μm.

[0059] In some embodiments, see Figure 8As shown, both the current extension region 220 and the drift region 210 are N-type doped and integrally formed. The heavily P-type doped region 310 extends from the silicon carbide substrate 110 to the second electrode 720. The first sub-well region 411 and the second sub-well region 412 of the P-type well region 410 form a lateral trapezoidal structure and a superjunction structure. The upper surface of the first sub-well region 411 is in contact with the gate dielectric layer 611, and the upper surface of the second sub-well region 412 is in contact with the heavily N-type doped region 510. The interface between the P-type well region 410 and the current extension region 220 is a continuous linear slope with steps, thus forming a buffered slope structure. The interface between the P-type well region 410 and the current extension region 220 extends stepwise from the lower surface of the gate dielectric layer 611 to the silicon carbide substrate 110. The continuously inclined P-type interface can reduce the interface electric field spikes, making the electric field transition smoothly from the high-voltage region to the low-voltage region.

[0060] In some embodiments, see Figure 9 As shown, the silicon carbide power device also includes a P-type floating region 810 formed between the drift region and the current extension region 220.

[0061] In some embodiments, see Figure 10 As shown, the second electrode 720 is the emitter, the first electrode 710 is the collector, and the silicon carbide substrate 110 is P-type doped.

[0062] In some embodiments, Figure 11 This is a schematic diagram showing the doping concentration distribution of a silicon carbide power device with a P-type well region formed by tilted implantation (schematic structure (b)) and a silicon carbide power device with a P-type well region formed by planar implantation (schematic structure (a)) according to an embodiment of this application. Figure 11 As shown in the schematic structure (b), the lower surface of the P-type well region 410 formed by the tilted injection angle is tilted, and the doping concentration of the P-type well region 410 is gradient-distributed, with the doping concentration near the channel being lower than the high concentration at the bottom.

[0063] In some embodiments, Figure 12 This application provides a silicon carbide power device with a planar implanted P-type well region as one embodiment of the present application. Figure 12 The schematic structure (a) and the silicon carbide power device with a P-type well region formed by tilted injection ( Figure 12 The schematic diagram of the electric field distribution of the schematic structure (b) is shown in the figure. Figure 13 This is a schematic diagram of the breakdown voltage curves of a silicon carbide power device with a P-type well region formed by tilted implantation and a P-type well region formed by planar implantation, provided in one embodiment of this application. Figure 12 and Figure 13As shown, the silicon carbide power device in this embodiment has a tilted P-type well region 410. According to simulation results, under the same cell size, in the schematic structure (a), the breakdown voltage (BVDSS) is 1551V, the threshold voltage is 2.85V, and the specific on-resistance is 2.598 mΩ·cm², achieved through the P-type well region and the heavily doped P-type region. In this embodiment, the breakdown voltage (BVDSS) is 1647V, the threshold voltage is 2.795V, and the specific on-resistance is 2.3892 mΩ·cm², achieved through the tilted surface of the P-type well region 410. Compared with the silicon carbide power device with a P-type well region formed by planar implantation, the breakdown voltage and specific on-resistance of the device are slightly improved after tilted implantation.

[0064] Figure 14a This is a schematic diagram of the electric field peak of the gate dielectric layer of a silicon carbide power device with a P-type well region formed by planar implantation according to an embodiment of this application. Figure 14b This is a schematic diagram of the peak electric field of the gate dielectric layer in a silicon carbide power device with a P-type well region formed by tilted injection. The vertical axis X represents the vertical direction, and the horizontal axis Y represents the horizontal direction, with units in micrometers. Figure 14a and Figure 14b Simulation results show that the peak electric field of the gate dielectric layer of the silicon carbide power device with P-type well region formed by planar injection is 2.97MV / cm, while the peak electric field of the gate dielectric layer of the silicon carbide power device with P-type well region formed by tilted injection is 2.36MV / cm.

[0065] This application also provides a chip, including the silicon carbide power device as described in any of the above embodiments.

[0066] In some embodiments, the chip includes a chip substrate on which one or more silicon carbide device structures are disposed, the silicon carbide device structures including the silicon carbide device structures of any of the above embodiments.

[0067] In one specific application embodiment, when the silicon carbide substrate 110 is N-type doped, the silicon carbide device structure can be a MOS structure, with the second electrode 720 as the source and the first electrode 710 as the drain. When the silicon carbide substrate 110 is P-type doped, the silicon carbide device structure can be an IGBT structure, with the second electrode 720 as the emitter and the first electrode 710 as the collector.

[0068] Other related semiconductor devices, as well as MOSFETs, can be integrated on the chip substrate to form an integrated circuit.

[0069] In one specific application embodiment, the chip can be a switch chip or a driver chip.

[0070] In this embodiment, a P-type heavily doped region is formed on the N-type drift layer, and the lower surface height of the P-type well region is set to gradually increase from the side closer to the P-type heavily doped region to the side farther away from the P-type heavily doped region, thereby forming a P-type well region with a tilted interface. Combined with the planar gate dielectric layer and the gate polysilicon layer, the tilted interface of the P-type well region bears the electric field, reducing the overall electric field peak of the gate dielectric layer and the device, and improving the reliability of the device. Furthermore, the second electrode located on the gate dielectric layer is set as a shallow trench structure, which reduces the specific on-resistance of the device. While optimizing the current spread capability of the device, it reduces its on-resistance at high temperature, enhances the saturation current clamping capability of the device, and improves the short-circuit withstand capability of the device.

[0071] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0072] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A silicon carbide power device, characterized in that, The silicon carbide power device includes: silicon carbide substrate; An N-type drift layer is formed on the front side of the silicon carbide substrate; A P-type well region and a P-type heavily doped region are formed on the N-type drift layer; the P-type well region is located between the N-type drift layer and the P-type heavily doped region; the height of the lower surface of the P-type well region gradually increases from the side closer to the P-type heavily doped region to the side farther away from the P-type heavily doped region. An N-type heavily doped region formed on the P-type well region; A gate dielectric layer, a gate polysilicon layer, and an interlayer dielectric layer are formed on the P-type well region, the N-type heavily doped region, and the N-type drift layer, wherein the gate dielectric layer and the interlayer dielectric layer form a cavity structure to enclose the gate polysilicon layer, the gate polysilicon layer is disposed opposite to the N-type drift layer and the P-type well region, and is disposed opposite to at least a portion of the N-type heavily doped region to form a planar gate structure; A first electrode formed on the back side of the silicon carbide substrate; A second electrode is formed on the interlayer dielectric layer and the P-type heavily doped region. The second electrode extends along the upper surface and side surface of the interlayer dielectric layer to the P-type heavily doped region and contacts the N-type heavily doped region.

2. The silicon carbide power device as described in claim 1, characterized in that, The N-type drift layer includes a current extension region and a drift region, the current extension region being in contact with the gate dielectric layer; the doping concentration of the current extension region is greater than the doping concentration of the drift region; the P-type well region is formed between the current extension region and the heavily doped P-type region.

3. The silicon carbide power device as described in claim 1, characterized in that, The upper surface of the N-type heavily doped region is higher than the upper surface of the P-type heavily doped region; the gate dielectric layer partially covers the N-type heavily doped region; the vertical portion of the second electrode has a stepped structure, and the second electrode extends stepwise from the upper surface of the gate dielectric layer and the upper surface of the N-type heavily doped region to the P-type heavily doped region.

4. The silicon carbide power device as described in claim 2, characterized in that, The P-type well region is located between the vertical portion of the current extension region and the heavily doped P-type region. The P-type well region includes multiple sub-well regions, and the doping concentration of the multiple sub-well regions gradually increases from the current extension region to the heavily doped P-type region.

5. The silicon carbide power device as described in claim 2, characterized in that, The P-type well region is located between the vertical portion of the current extension region and the heavily doped P-type region, and the doping concentration of the P-type well region gradually decreases from the drift region toward the heavily doped N-type region.

6. The silicon carbide power device as described in claim 2, characterized in that, The interface between the P-type well region and the current extension region is an arc surface or a linear slope.

7. The silicon carbide power device as described in claim 2, characterized in that, The thickness of the P-type well region is less than the thickness of the current spreading region, and the depth of the contact surface between the heavily doped P-type region and the current spreading region is greater than half the thickness of the heavily doped P-type region; and / or The thickness of the P-type heavily doped region is greater than 2.5 μm.

8. The silicon carbide power device as described in claim 2, characterized in that, The silicon carbide power device also includes: A P-type floating region is formed between the drift region and the current expansion region.

9. The silicon carbide power device according to any one of claims 1-8, characterized in that, The second electrode is the emitter, the first electrode is the collector, and the silicon carbide substrate is P-type doped.

10. A chip, characterized in that, Including the silicon carbide power device as described in any one of claims 1-9.

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