A self-aligned fabrication method for silicon carbide power devices, and a chip.

Abstract

This application belongs to the field of semiconductor technology and provides a self-aligned process fabrication method and chip for silicon carbide power devices. The method involves multiple implantation of P-type dopant ions into a region of a first P-type well region using a self-aligned process to form a sloping P-type well region. The interface between the sloping P-type well region and the top epitaxial region is a continuous sloping surface. The implantation energy of the multiple P-type dopant ion implantation processes gradually decreases. Combined with a planar gate structure, the sloping interface of the P-type well region bears the electric field, reducing the peak electric field of the gate dielectric layer and the device, thus improving the reliability of the device. Furthermore, the second electrode on the gate dielectric is configured as a shallow trench structure, reducing the specific on-resistance of the device. While optimizing the current spread capability of the device, the on-resistance at high temperatures is reduced, enhancing the saturation current clamping capability and improving the short-circuit withstand capability of the device.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a self-aligned process fabrication method and chip for silicon carbide power devices. Background Technology

[0002] Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) are mainly divided into two categories: planar gate and trench gate. Traditional planar gate SiC MOSFETs have a mature structure, but their high JFET region resistance leads to a high specific on-resistance. Simultaneously, under high-voltage blocking conditions, electric field spikes easily form at the edge of the P-well beneath the gate oxide layer, affecting the long-term reliability of the device, especially under high temperature and high dV / dt conditions, where the threshold voltage is prone to drift. To overcome the shortcomings of planar gates, the industry has developed trench gate SiC MOSFETs. This structure eliminates the junction field-effect region (JFET region) by etching trenches within the P-well and burying the gate within them, thereby achieving lower on-resistance and higher cell density.

[0003] However, the bottom corners of traditional trench gate structures are also areas of concentrated electric field, which can easily lead to premature breakdown of the gate oxide layer. Furthermore, their manufacturing process is more complex and costly. Existing trench-assisted planar gate structures still require improvement in terms of electric field uniformity optimization, temperature stability of on-resistance, and manufacturability. For example, how to precisely control the doping profile of the P-well to form an optimal gradually varying electric field structure without adding extra photolithography steps, and how to ensure reliable source ohmic contacts while reducing cell size, remain pressing technical challenges in this field. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a self-aligned process fabrication method and chip for silicon carbide power devices, aiming to form silicon carbide power devices with sloping P-type well regions without adjusting the position of the wafer substrate.

[0005] The first aspect of this application provides a self-aligned fabrication method for silicon carbide power devices, the self-aligned fabrication method comprising: An N-type drift region and a top epitaxial region are sequentially formed on the front side of a silicon carbide substrate; A first hard mask is formed in a first predetermined area of ​​the top epitaxial region, and a first trench is formed by etching the top epitaxial region under the protection of the first hard mask; Polycrystalline silicon material is deposited to form a polycrystalline silicon mask, and P-type doped ions are implanted into the top epitaxial region under the coverage of the polycrystalline silicon mask to form a first P-type well region. A first self-aligned sidewall is formed on the surface of the polysilicon mask and the first P-type well region. By repeatedly etching the first self-aligned sidewall, P-type doped ions are implanted into the region of the first P-type well region multiple times using the thickness difference of the self-aligned sidewall to form a sloping P-type well region. The interface between the sloping P-type well region and the top epitaxial region is a continuous sloping surface, and the implantation energy of the multiple P-type doped ion implantation process gradually decreases. After removing the self-aligned sidewalls, a channel masking layer is formed by oxidizing the polysilicon mask, and a second hard mask is formed in the first trench. N-type doped ions are injected into the sloping P-type well region using the masking effect of the channel masking layer and the second hard mask to form an N-type heavily doped region; wherein, the doping depth of the N-type heavily doped region is less than the doping depth of the sloping P-type well region. Remove the channel masking layer and the second hard mask, form a third hard mask on the top epitaxial region, the sloping P-type well region and the N-type heavily doped region, and implant P-type dopant ions along the first trench under the coverage of the third hard mask to form a P-type heavily doped region that extends into the N-type drift region. Remove the hard mask from the previous step to form a fourth hard mask covering the sloping P-type well region, the N-type heavily doped region, and the P-type heavily doped region. Under the coverage of the fourth hard mask, N-type dopant ions are injected into the top epitaxial region to form a current spread region. After removing the fourth hard mask, a gate dielectric layer is formed by an oxidation process. After depositing the gate polysilicon material, the gate polysilicon material is etched using a gate mask to form a gate polysilicon layer. After removing the gate mask, an interlayer dielectric material is deposited to form an interlayer dielectric layer. The gate dielectric layer and the interlayer dielectric layer form a cavity structure to enclose the gate polysilicon layer. A planar gate stack structure is formed on the channel region within the sloping P-type well region. The interlayer dielectric layer is etched to form electrode trenches to expose the P-type heavily doped region; A first electrode is formed on the back side of the silicon carbide substrate, and a second electrode is formed along the surface of the interlayer dielectric layer and the electrode trench; wherein the N-type heavily doped region and the P-type heavily doped region are in ohmic contact with the second electrode.

[0006] In some embodiments, forming a first self-aligned sidewall on the surface of the polysilicon mask and the first P-type well region includes: The first self-aligned sidewall is formed by isotropic deposition of silicon oxide material.

[0007] In some embodiments, the step of repeatedly implanting P-type doped ions into the region of the first P-type well region by repeatedly etching the first self-aligned sidewall and utilizing the thickness difference of the self-aligned sidewall includes: The first self-aligned sidewall is etched to form an arc-shaped sidewall, and P-type doped ions are implanted into the first P-type well region in a vertical direction.

[0008] In some embodiments, the step of repeatedly implanting P-type doped ions into the region of the first P-type well region by repeatedly etching the first self-aligned sidewall and utilizing the thickness difference of the self-aligned sidewall further includes: Under the cover of the arc-shaped sidewall, P-type doped ions are implanted into the first P-type well region multiple times in a vertical direction, wherein the implantation energy of the multiple ion implantation processes decreases sequentially.

[0009] In some embodiments, the implantation dose of the ion implantation process decreases sequentially in multiple iterations.

[0010] In some embodiments, the implantation of P-type doped ions along the first trench under the coverage of the third hard mask to form a heavily doped P-type region extending into the N-type drift region includes: Under the cover of the third hard mask, within an implantation depth of 1.0 μm-1.5 μm, a multiple ion implantation process with progressively decreasing implantation energy is used to implant P-type doped ions along the first trench to form the heavily doped P-type region; the doping concentration of the heavily doped P-type region is greater than 1E19 cm⁻¹. -3 .

[0011] In some embodiments, the implantation of N-type doped ions into the top epitaxial region under the coverage of the fourth hard mask to form a current-spreading region includes: Under the cover of the fourth hard mask, N-type doped ions are injected into the top epitaxial region in an implantation depth range of 1 μm-4 μm, in order of gradually decreasing implantation energy.

[0012] In some embodiments, the interface between the inclined P-type well region and the current extension region is any one of a linear inclined plane, a continuous inclined plane, a continuous curved inclined plane, or a continuous irregular inclined plane.

[0013] The first aspect of this application also provides a self-aligned fabrication method for silicon carbide power devices, the self-aligned fabrication method comprising: An N-type drift region and a top epitaxial region are sequentially formed on the front side of a silicon carbide substrate; A polysilicon mask is formed in a first predetermined region of the top epitaxial region, and P-type doped ions are implanted into the top epitaxial region under the coverage of the polysilicon mask to form a first P-type well region. A first self-aligned sidewall is formed on the surface of the polysilicon mask and the first P-type well region by depositing polysilicon material. The first self-aligned sidewall is then etched multiple times, and P-type doped ions are implanted into the region of the first P-type well region multiple times by utilizing the thickness difference of the self-aligned sidewall to form a sloping P-type well region. The interface between the sloping P-type well region and the top epitaxial region is a continuous sloping surface, and the implantation energy of the multiple P-type doped ion implantation process gradually decreases. After removing the self-aligned sidewalls, a channel masking layer is formed by oxidizing the polysilicon mask. N-type dopant ions are then injected into the sloping P-type well region using the masking layer to form an N-type heavily doped region. The doping depth of the N-type heavily doped region is less than the doping depth of the sloping P-type well region. Remove the channel masking layer and the polysilicon mask to form a third hard mask, and etch the N-type heavily doped region under the protection of the third hard mask to form a first trench; Under the protection of the third hard mask, P-type doped ions are injected along the first trench to form a heavily doped P-type region that extends into the N-type drift region; Remove the hard mask from the previous step to form a fourth hard mask covering the sloping P-type well region, the N-type heavily doped region, and the P-type heavily doped region. Under the coverage of the fourth hard mask, N-type dopant ions are injected into the top epitaxial region to form a current spread region. After removing the fourth hard mask, a gate dielectric layer is formed by an oxidation process. After depositing the gate polysilicon material, the gate polysilicon material is etched using a gate mask to form a gate polysilicon layer. After removing the gate mask, an interlayer dielectric material is deposited to form an interlayer dielectric layer. The gate dielectric layer and the interlayer dielectric layer form a cavity structure to enclose the gate polysilicon layer. A planar gate stack structure is formed on the channel region within the sloping P-type well region. The interlayer dielectric layer is etched to form electrode trenches to expose the P-type heavily doped region; A first electrode is formed on the back side of the silicon carbide substrate, and a second electrode is formed along the surface of the interlayer dielectric layer and the electrode trench; wherein the N-type heavily doped region and the P-type heavily doped region are in ohmic contact with the second electrode.

[0014] A second aspect of this application also provides a silicon carbide power device, which is fabricated using a self-aligned process fabrication method as described in any of the preceding embodiments.

[0015] A third aspect of this application also provides a chip, including a silicon carbide power device fabricated by the self-aligned process fabrication method described in any of the preceding claims.

[0016] The beneficial effects of this application embodiment compared with the prior art are as follows: P-type doped ions are implanted multiple times into the region of the first P-type well region through a self-aligned process to form a sloping P-type well region. The interface between the sloping P-type well region and the top epitaxial region is a continuous sloping surface. The implantation energy of the multiple P-type doped ion implantation processes gradually decreases. Combined with the planar gate structure, the sloping interface of the P-type well region bears the electric field, reducing the overall electric field peak of the gate dielectric layer and the device, and improving the reliability of the device. Furthermore, the second electrode on its gate dielectric is set as a shallow trench structure, which reduces the specific on-resistance of the device. While optimizing the current spread capability of the device, it reduces its on-resistance at high temperature, enhances the saturation current clamping capability of the device, and improves the short-circuit withstand capability of the device. Attached Figure Description

[0017] Figure 1 This is a schematic flowchart of a first self-aligned process fabrication method for silicon carbide power devices provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure after forming the N-type drift region 210 and the top extension region 220 according to an embodiment of this application; Figure 3a This is a schematic diagram of the structure after the first hard mask 101 is formed in the first self-aligned process fabrication method; Figure 3b This is a schematic diagram of the structure after forming the polycrystalline silicon mask 201 and the first P-type well region 411 in the first self-aligned process fabrication method; Figure 3c This is a schematic diagram of the structure after the first self-aligned sidewall 401 is formed in the first self-aligned process preparation method; Figure 3d This is a schematic diagram of the structure after the formation of the second self-aligned sidewall 402 in the first self-aligned process preparation method; Figure 3e This is a schematic diagram of the structure after forming the N-type heavily doped region 510 in the first self-aligned process preparation method; Figure 4a This is a schematic diagram of the structure after forming the polysilicon mask 201 and the first P-type well region 411 in the second self-aligned process fabrication method; Figure 4b This is a schematic diagram of the structure after the first self-aligned sidewall 401 is formed in the second self-aligned process preparation method; Figure 4c This is a schematic diagram of the structure after the second self-aligned sidewall 402 is formed in the second self-aligned process preparation method; Figure 4d This is a schematic diagram of the structure after forming the N-type heavily doped region 510 in the second self-aligned process preparation method; Figure 4eThis is a schematic diagram of the structure after the third hard mask 103 and the first trench are formed in the second self-aligned process fabrication method; Figure 4f This is a schematic diagram of the process for the second self-aligned fabrication method; Figure 5 This is a schematic diagram of the structure after the P-type heavily doped region 310 is provided in one embodiment of this application; Figure 6 This is a schematic diagram of the structure after forming the current extension region 230 according to one embodiment of this application; Figure 7 This is a schematic diagram of the structure after forming the gate dielectric layer 611, the interlayer dielectric layer 612, and the gate polysilicon layer 620 according to an embodiment of this application; Figure 8 This is a schematic diagram of the structure after etching the interlayer dielectric layer 612 according to one embodiment of this application; Figure 9 This is a schematic diagram of the structure after forming the first electrode 710 and the second electrode 720 according to an embodiment of this application; Figure 10 This is a schematic diagram of a silicon carbide power device with a grid-like cell inclined P-type well region fabricated using a self-aligned process according to an embodiment of this application; Figure 11 This is a schematic diagram of the doping concentration distribution of a silicon carbide power device with a P-type well region formed by tilted implantation and a P-type well region formed by planar implantation, according to an embodiment of this application. Figure 12 This is a schematic diagram of the electric field distribution of a silicon carbide power device with a P-type well region formed by tilted injection and a P-type well region formed by planar injection, according to an embodiment of this application. Figure 13 This is a schematic diagram of the breakdown voltage curves of a silicon carbide power device with a P-type well region formed by tilted injection and a P-type well region formed by planar injection, according to an embodiment of this application. Figure 14a This is a schematic diagram of the electric field peak of the gate dielectric layer of a silicon carbide power device with a planar P-type well region provided in one embodiment of this application; Figure 14b This is a schematic diagram of the electric field peak of the gate dielectric layer of a silicon carbide power device with a tilted P-type well region provided in one embodiment of this application. Detailed Implementation

[0018] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0019] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0020] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means one or more, unless otherwise explicitly specified.

[0022] In this application specification, references to "one embodiment," "some embodiments," or "embodiment" mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," "in a particular embodiment," "in a particular application," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, specific features, structures, or characteristics may be combined in any suitable manner.

[0023] While traditional trench MOSFETs reduce on-resistance, they introduce more severe reliability challenges. For example, the electric field strength at the corners of the trench bottom is much higher than that of a planar gate, causing the gate oxide to experience significant voltage stress. To alleviate this problem, a double-trench structure is usually required. Although the double-trench structure alleviates the gate oxide electric field, it increases the process complexity, and the deeper source trench can easily introduce new leakage paths. However, regardless of the form factor, when the device is off-state, significant electric field concentration occurs near the gate oxide / semiconductor interface and at the edges and corners of the PN junction between the P-well and N-drift regions.

[0024] To address the aforementioned technical problems, this application provides a self-aligned fabrication method for silicon carbide power devices. (See attached document.) Figure 1 As shown, the self-aligned process preparation method in this embodiment includes steps S100 to S910.

[0025] In step S100, an N-type drift region 210 and a top epitaxial region 220 are sequentially formed on the front side of the silicon carbide substrate 110, such as... Figure 2 As shown.

[0026] In this embodiment, see Figure 2 As shown, an N-type drift region 210 is formed on the front side of the silicon carbide substrate 110, and a top epitaxial region 220 is formed on the N-type drift region 210.

[0027] In some embodiments, when the silicon carbide power device is a MOS device, the silicon carbide substrate 110 is N-type doped; when the silicon carbide power device is an IGBT device, the silicon carbide substrate 110 is P-type doped.

[0028] In some embodiments, the N-type drift region 210 and the top epitaxial region 220 are both N-type doped.

[0029] In some embodiments, the doping concentration of N-type dopants in the silicon carbide substrate 110 is greater than the doping concentration of N-type dopants in the N-type drift region 210 and the top epitaxial region 220.

[0030] In some embodiments, the doping concentration of the top epitaxial region 220 is 1.0E16 cm⁻¹. -3 -4E16 cm -3 The thickness of the top epitaxial region 220 is 1-4 μm, and the doping concentration of the N-type drift region 210 is 3E15cm. -3 -2E16 cm -3 The thickness and concentration of the N-type drift region 210 and the top epitaxial region 220 depend on the device's voltage rating.

[0031] In step S200, a first hard mask 101 is formed in a first preset region of the top epitaxial region 220, and a first trench is formed in the top epitaxial region 220 under the protection of the first hard mask 101, such as... Figure 3a As shown.

[0032] In this embodiment, combined with Figure 3aAs shown, the front side of the top epitaxial region 220 includes a first preset region and a second pre-driven region. The first hard mask 101 covers the first preset region of the top epitaxial region 220. Under the coverage of the first hard mask 101, the top epitaxial region 220 is etched, and a first trench can be formed in the edge region of the top epitaxial region 220. Through the first trench, the top epitaxial region 220 can have different thicknesses in different regions.

[0033] In some embodiments, the first trench can serve as a source trench, the first hard mask 101 can be a conventional hard mask, and the source trench is formed by dry etching, with a depth of 0.2μm-0.8μm.

[0034] In step S300, polysilicon material is deposited to form a polysilicon mask 201, and under the coverage of the polysilicon mask 201, multiple ion implantation processes are performed on the top epitaxial region 220 to implant P-type doped ions to form a first P-type well region 411.

[0035] In this embodiment, combined with Figure 3b As shown, after removing the first hard mask 101, since the top epitaxial region 220 has different thicknesses in different regions, after multiple ion implantation processes to implant P-type doped ions, the interface between the first P-type well region 411 and the top epitaxial region 220 is an inclined interface.

[0036] In some embodiments, the implantation depth of the first P-type well region 411 formed by implanting P-type doped ions in a multiple ion implantation process ranges from 0.6 μm to 1.1 μm, and the number of implantation cycles is 3 to 5. The energy of the multiple ion implantation processes decreases sequentially, and the doping concentration of the first P-type well region 411 is 1E16cm⁻¹. -3 -2E18cm -3 The overall distribution is in the shape of a box.

[0037] In step S400, a first self-aligned sidewall 401 is formed on the surface of the polysilicon mask 201 and the first P-type well region 411. By repeatedly etching the first self-aligned sidewall 401, P-type doped ions are repeatedly implanted into the region of the first P-type well region 411 using the thickness difference of the self-aligned sidewall, forming a sloped P-type well region 410.

[0038] In this embodiment, combined with Figure 3c As shown, by depositing self-aligned materials, first self-aligned sidewalls 401 with different thicknesses in different regions can be formed on the surfaces of the polysilicon mask 201 and the first P-type well region 411. Combined with... Figure 3dAs shown, by etching the first self-aligned sidewall 401 to adjust the thickness difference of each region of the self-aligned sidewall, the second self-aligned sidewall 402 is obtained. Under the coverage of the polysilicon mask 201 and the second self-aligned sidewall 402, P-type doped ions are implanted using their thickness difference to form a sloped P-type well region 410.

[0039] In some embodiments, combined with Figure 3d As shown, the interface between the sloping P-type well region 410 and the top extension region 220 is a continuous sloping surface.

[0040] In some embodiments, the energy of the multiple P-type doped ion implantation processes decreases sequentially, making the P-type well region a sloping P-type well region 410 with a sloping structure. The depth of the sloping P-type well region 410 increases from 0.2 μm to 0.8 μm.

[0041] In some embodiments, the tilt angle of the interface between the sloping P-type well region 410 and the top epitaxial region 220 ranges from 1 to 30°, depending on the process hard mask thickness and the pattern critical dimension (CD).

[0042] In some embodiments, step S400, forming a first self-aligned sidewall 401 on the surface of the polysilicon mask 201 and the first P-type well region 411, includes forming the first self-aligned sidewall 401 by isotropically depositing silicon oxide material.

[0043] In this embodiment, isotropic CVD is used to deposit silicon oxide material. The deposition rate is uniform in three-dimensional space. Instead of "direct" deposition from a certain direction, it is deposited using a wrap-around method combined with isotropic filling. The effective thickness of silicon oxide at the edge of the masked area / bottom of the window is locked by the masked area width (critical dimension, CD) itself, and its deposition thickness is determined by the deposition time. In this way, the position of the first self-aligned sidewall 401 (i.e., silicon oxide sidewall) is automatically defined by the trench, saving one photolithography process. Furthermore, the alignment tolerance is reduced to zero. As the trench size of the current stage decreases, the upper limit of the allowable deposition thickness also decreases. The process opening automatically shrinks with the node, eliminating the need for redesign.

[0044] In some embodiments, step S400 involves repeatedly etching the first self-aligned sidewall 401 and repeatedly implanting P-type doped ions into the region of the first P-type well region 411 using the thickness difference of the self-aligned sidewall, including: etching the first self-aligned sidewall 401 to form an arc-shaped sidewall and implanting P-type doped ions into the first P-type well region 411 in a vertical direction.

[0045] In this embodiment, combined with Figure 3dAs shown, the second self-aligned sidewall 402 is an arc-shaped sidewall. Under the coverage of the arc-shaped sidewall, P-type doped ions are implanted 3-5 times using a vertical ion implantation process, with the implantation energy decreasing sequentially. The thickness difference of the sidewall mask is used to form a sloping structure in the P-type well region, increasing the depth by 0.8μm-3.0μm, depending on the thickness of the process hard mask and the critical dimension CD of the pattern.

[0046] In some embodiments, if the silicon carbide power device is a silicon carbide power device with a sloping P-type well region having grid-like cells, since the implantation angle of the P-type doped ions in step S400 is vertical, even if the device has four cells, the sloping P-type well region 410 can still have a sloping interface structure by utilizing the thickness difference of the sidewall mask, which greatly improves the accuracy and stability of the process. If the ion implantation angle in this step is 0-45°, then after completing the P-type ion implantation process in each direction, the wafer needs to be rotated 90°, and then the sloping angle P-type ion implantation process is performed again. In this way, the wafer needs to be rotated four times in the horizontal direction, and the wafer is rotated 90° each time. The rotation direction can be clockwise or counterclockwise, thus forming a sloping P-type well region 410 with a wide top and narrow bottom structure. Therefore, errors may be introduced in each rotation process, reducing the accuracy of the process.

[0047] In some embodiments, step S400 involves repeatedly etching the first self-aligned sidewall 401 and repeatedly implanting P-type doped ions into the region of the first P-type well region 411 using the thickness difference of the self-aligned sidewall, including: performing an ion implantation process multiple times in the vertical direction under the cover of the arc-shaped sidewall to implant P-type doped ions into the first P-type well region 411.

[0048] In this embodiment, the implantation direction of the multiple ion implantation process is vertical, and the implantation energy of the multiple ion implantation processes decreases sequentially. Thus, the sequential decrease in implantation energy, combined with the thickness difference of the arc-shaped oxide sidewall, makes the implantation depth smoothly transition from shallow to deep. In the area where the arc-shaped sidewall is thicker, the implantation depth of P-type doped ions is shallower, and in the area where the arc-shaped sidewall is thinner, the implantation depth of P-type doped ions is deeper.

[0049] In some embodiments, the implantation dose decreases sequentially in multiple ion implantation processes.

[0050] In this embodiment, the implantation dose decreases sequentially in the multiple ion implantation processes. Combined with the thickness difference of the arc-shaped oxide sidewalls, the implantation depth smoothly transitions from shallow to deep. Furthermore, the doping concentration is highest in the region with the greatest implantation depth, i.e., the doping concentration is higher at the interface between the sloping P-type well region 410 and the top epitaxial region 220 and the N-type drift region 210, or in the region close to the top epitaxial region 220 and the N-type drift region 210. Then, the doping concentration gradually decreases in the region away from the top epitaxial region 220 and the N-type drift region 210. In this way, the geometry of the PN junction is changed by using the smoothly transitioning sloping structure, transforming the traditional vertical electric field distribution into an oblique electric field distributed along the sloping surface.

[0051] In some embodiments, in step S400, the first self-aligned sidewall 401 is etched multiple times. Each etching operation implants P-type doped ions once using a vertical ion implantation process. Thus, the coverage area and thickness of the second self-aligned sidewall 402 gradually decrease, resulting in a higher doping concentration in the sloped P-type well region 410 closer to the top epitaxial region 220 and the N-type drift region 210. Furthermore, the contact surface between the sloped P-type well region 410 and the top epitaxial region 220 and the N-type drift region 210 is sloped. This reduces the doping concentration near the channel compared to the high concentration at the bottom, allowing the sloped structure to alter the geometry of the PN junction and transform the traditional vertical electric field distribution into an oblique electric field distributed along the slope.

[0052] In step S500, combined Figure 3e As shown, after removing the self-aligned sidewalls, a channel masking layer 301 is formed by an oxide polysilicon mask 201, and a second hard mask 102 is formed in the first trench. Using the cover of the channel masking layer 301 and the second hard mask 102, N-type doped ions are injected into the inclined P-type well region 410 to form an N-type heavily doped region 510.

[0053] In this embodiment, after the sidewall is removed, the polysilicon mask 201 forms a channel masking layer 301, which masks the channel. At the same time, the second hard mask 102 is used to perform hard masking on the top of the first trench. Ion implantation forms an N-type heavily doped region 510. The doping depth of the N-type heavily doped region 510 is less than the doping depth of the sloping P-type well region 410.

[0054] In step S600, the channel masking layer 301 and the second hard mask 102 are removed, and a third hard mask 103 is formed on the top epitaxial region 220, the sloping P-type well region 410, and the N-type heavily doped region 510. Under the coverage of the third hard mask 103, P-type dopant ions are implanted along the first trench to form a P-type heavily doped region 310 extending into the N-type drift region 210. Figure 5 As shown.

[0055] In some embodiments, step S600, implanting P-type dopant ions along the first trench under the coverage of the third hard mask 103 to form a heavily doped P-type region 310 extending into the N-type drift region 210, includes: under the coverage of the third hard mask 103, implanting P-type dopant ions along the first trench using a multiple ion implantation process with progressively decreasing implantation energy to form the heavily doped P-type region 310 within an implantation depth range of 1.0 μm-1.5 μm.

[0056] In this embodiment, the doping concentration of the heavily doped p-type region 310 is greater than 1E19cm. -3 .

[0057] In some embodiments, during the process of implanting P-type dopant ions along a portion of the N-type heavily doped region 510 to form a P-type heavily doped region 310 extending into the N-type drift region 210, the implantation depth of the P-type dopant ions is 1.0 μm-1.5 μm, the number of P-type dopant ion implantations is 3-5 times, the implantation energy of the P-type dopant ions decreases sequentially, and the doping concentration of the P-type dopant ions is greater than 1E19 cm⁻¹. -3 The doping concentration of the P-type heavily doped region 310 exhibits a BOX distribution.

[0058] In this embodiment, the doping concentration of the well region near the heavily doped P-type region 310 is greater than that of the well region farther away from the heavily doped P-type region 310. Thus, the well region near the heavily doped P-type region 310 can serve as the main discharge channel. During high-voltage blocking, the well region near the heavily doped P-type region 310 is depleted first, undertaking the main longitudinal withstand voltage task. This allows the high electric field region to be transferred from the sensitive channel region to the depths of the device, protecting the channel from high field stress. The deep P-well structure provides a larger avalanche current distribution volume, improving the device's UIS (unclamped inductive load switch) capability.

[0059] In some embodiments, the depth of the heavily doped P-type region 310 is greater than the depth of the sloping P-type well region 410. The doping concentration of the sloping P-type well region 410 gradually decreases from the N-type drift region 210 to the N-type heavily doped region 510. Its doping concentration is non-uniformly doped, which realizes a smooth transition of the electric field from the high-voltage region to the low-voltage region, so as to prevent electric field spikes caused by abrupt changes in depth and realize the balanced management of the electric field. Moreover, gradient doping reduces interface states and reduces reverse leakage current at high temperatures.

[0060] In some embodiments, such as Figure 4f As shown, this embodiment proposes another self-aligned process fabrication method for silicon carbide power devices. This self-aligned process fabrication method replaces steps S200 to S600 in the above embodiment with steps S210 to S610.

[0061] In step S210, a polysilicon mask 201 is formed in the first preset region of the top epitaxial region 220, and under the coverage of the polysilicon mask 201, multiple ion implantation processes are performed on the top epitaxial region 220 to implant P-type doped ions to form a first P-type well region 411, as shown below. Figure 4a As shown.

[0062] In this embodiment, combined with Figure 4a As shown, under the coverage of the polysilicon mask 201, multiple ion implantation processes are performed to implant P-type doped ions into the top epitaxial region 220. The implantation depth of the multiple ion implantation processes is 0.6 μm-1.1 μm, and the number of implantation times is 3-5. The energy of the multiple ion implantation processes decreases sequentially. The doping concentration of the first P-type well region 411 is 1E16 cm⁻¹. -3 -2E18cm -3 Its doping concentration exhibits a BOX distribution overall.

[0063] In step S310, a first self-aligned sidewall 401 is formed on the surface of the polysilicon mask 201 and the first P-type well region 411 by depositing polysilicon material, as shown below. Figure 4b As shown. By repeatedly etching the first self-aligned sidewall 401, P-type doped ions are repeatedly implanted into the region of the first P-type well region 411 using the thickness difference of the self-aligned sidewall, forming a sloped P-type well region 410, as shown. Figure 4c As shown.

[0064] In this embodiment, a second self-aligned sidewall 402 is formed by etching the first self-aligned sidewall 401 multiple times. Under the cover of the second self-aligned sidewall 402, P-type doped ions are implanted using its thickness difference to form a sloping P-type well region 410. The thickness of the second self-aligned sidewall 402 is negatively correlated with the implantation depth. The thicker the second self-aligned sidewall 402, the shallower the implantation of P-type doped ions. Thus, by adjusting the surface arc shape of the second self-aligned sidewall 402 through the etching process, the interface shape between the sloping P-type well region 410 and the top epitaxial region 220 can be adjusted.

[0065] In some embodiments, when the self-aligned sidewalls are etched in successive stages, the implantation energy is gradually reduced in combination with multiple P-type doped ion implantation processes, so that the interface between the sloping P-type well region 410 and the top epitaxial region 220 is a continuous sloping surface.

[0066] In some embodiments, an arc-shaped sidewall can be formed by etching the first self-aligned sidewall 401 of the previous step through multiple etching processes. After each etching process, the coverage area of ​​the arc-shaped sidewall is reduced and its thickness is decreased. Then, after each etching process, P-type doped ions are implanted 3-5 times using a vertical ion implantation process, with the implantation energy decreasing sequentially. Thus, without rotating the wafer or adjusting the ion implantation direction, a sloped P-type well region 410 with a sloped structure is formed by utilizing the thickness difference of the sidewall mask. Its depth is increased by 0.8 μm-3.0 μm, depending on the thickness of the process hard mask and the critical dimension CD of the pattern.

[0067] In step S410, combined Figure 4d As shown, after removing the self-aligned sidewalls, a channel masking layer 301 is formed by an oxide polysilicon mask 201. Using the masking effect of the channel masking layer 301, N-type dopant ions are injected into the inclined P-type well region 410 to form an N-type heavily doped region 510.

[0068] In this embodiment, after the sidewalls are removed and the polysilicon mask 201 is oxidized, silicon oxide is formed on its surface as a channel masking layer 301, thus achieving channel masking. Ion implantation forms an N-type heavily doped region 510, and the doping depth of the N-type heavily doped region 510 is less than the doping depth of the sloping P-type well region 410.

[0069] In step S510, the channel masking layer 301 and the polysilicon mask 201 are removed to form a third hard mask 103, and the N-type heavily doped region 510 is etched under the protection of the third hard mask 103 to form the first trench.

[0070] In this embodiment, combined with Figure 4e As shown, the third hard mask 103 is a conventional hard mask mask, and the first trench is formed by dry etching. The first trench serves as a shallow source trench with a depth of 0.2μm-0.8μm.

[0071] In some embodiments, the pattern shape of the third hard mask 103 is the same as that of the first hard mask 101.

[0072] In step S610, under the protection of the third hard mask 103, P-type doped ions are implanted along the first trench to form a heavily doped P-type region 310 extending into the N-type drift region 210, as shown below. Figure 5 As shown.

[0073] In this embodiment, a heavily doped P-type region 310 can be formed by multiple P-type ion implantations. The implantation depth of the P-type ions is 1.0 μm-1.5 μm, the number of implantations is 3-5, and the implantation energy of the P-type ions decreases sequentially. The doping concentration of the heavily doped P-type region 310 is greater than 1E19cm. -3 The overall distribution is in the shape of a box.

[0074] In step S700, the hard mask from the previous step (e.g., the third hard mask 103) is removed to form a fourth hard mask 104 covering the sloping P-type well region 410, the heavily doped N-type region 510, and the heavily doped P-type region 310. Under the coverage of the fourth hard mask 104, N-type dopant ions are implanted into the top epitaxial region 220 to form a current extension region 230. Figure 6 As shown.

[0075] In this embodiment, the fourth hard mask 104 is a conventional hard mask, which is used to mask the N-type doping of the top epitaxial region 220 to improve conductivity and form a current extension region 230. The N-type doping implantation depth is 1.0 μm-1.4 μm, the number of N-type doping implantations is 4-6 times, and the N-type doping implantation energy decreases sequentially. The doping concentration of the current extension region 230 is 2E16cm. -3 -2E17cm -3 The overall distribution is in the shape of a box.

[0076] In some embodiments, step S700, under the coverage of the fourth hard mask 104, injecting N-type dopant ions into the top epitaxial region 220 to form a current extension region 230, includes: under the coverage of the fourth hard mask 104, injecting N-type dopant ions into the top epitaxial region 220 in a gradually decreasing order of injection energy within an injection depth range of 1 μm-4 μm.

[0077] In step S800, the fourth hard mask 104 is removed, the gate dielectric layer 611 is formed by oxidation process, and the gate polysilicon material is deposited. Then, the gate polysilicon material is etched under the cover of the gate mask to form the gate polysilicon layer 620. After the gate mask is removed, the interlayer dielectric material is deposited to form the interlayer dielectric layer 612.

[0078] In this embodiment, a gate dielectric layer 611 can be formed by oxidizing the device surface. For example, by removing the fourth hard mask 104, taking boron ion doping as an example, through dry oxidation of the material on the front side of the device, the silicon on its surface is oxidized to form silicon oxide. The silicon is consumed, the interface is pushed inward, and the original boron profile is scooped into a narrower subsurface silicon material. After depositing the gate polysilicon material, the gate position is defined by the gate mask. Under the cover of the gate mask, the gate polysilicon material is etched to form a gate polysilicon layer 620. The interlayer dielectric layer 612 and the gate dielectric layer 611 wrap the gate polysilicon layer 620, forming a planar gate stack structure on the channel region within the inclined P-type well region 410, such as... Figure 7 As shown.

[0079] In some embodiments, after the ion implantation process is completed, the device is annealed and activated at an environment of 1600-1800°C. A gate dielectric layer 611 is formed by a sacrificial oxidation process. Then, a polysilicon material is deposited to form a gate polysilicon layer 620. The gate polysilicon layer 620 is then etched under the cover of a gate mask to define the gate position. An interlayer dielectric material is then deposited to form an interlayer dielectric layer 612 to isolate the gate source, thus forming a planar gate structure.

[0080] In step S900, the interlayer dielectric layer 612 on the heavily doped p-type region 310 is etched to form electrode trenches, thereby exposing the heavily doped p-type region 310, such as... Figure 8 As shown.

[0081] In step S910, a first electrode 710 is formed on the back side of the silicon carbide substrate 110, and a second electrode 720 is formed along the surface of the interlayer dielectric layer 612 and the electrode trench.

[0082] In this embodiment, the N-type heavily doped region 510 and the P-type heavily doped region 310 are in ohmic contact with the second electrode 720. The planar gate structure, combined with the sloping P-type well region 410 and the shallow trench electrode, utilizes the sloping P-type well region 410 as an "electric field drainage channel" for the entire device structure. Since the second electrode 720 extends along the upper and side surfaces of the interlayer dielectric layer 612 to the P-type heavily doped region 310 and contacts the N-type heavily doped region 510, when a blocking voltage is applied, the high potential of the first electrode 710 splits and shunts the current in both the vertical and horizontal directions along the sloping surface, completely changing the slope of the equipotential line and eliminating the risk of electric field breakdown at the sharp corners of the gate dielectric layer from the source.

[0083] In some embodiments, the interface between the inclined P-type well region 410 and the current extension region 230 is any one of a linear inclined surface, a continuous inclined surface, a continuous curved inclined surface, or a continuous irregular inclined surface.

[0084] In this embodiment, P-type doped ions are implanted multiple times into the region of the first P-type well region through a self-aligned process to form a sloping P-type well region. The interface between the sloping P-type well region and the top epitaxial region is a continuous sloping surface. The implantation energy of the multiple P-type doped ion implantation processes gradually decreases. Combined with the planar gate structure, the sloping interface of the P-type well region bears the electric field, reducing the overall electric field peak of the gate dielectric layer and the device, and improving the reliability of the device. Furthermore, the second electrode on its gate dielectric is set as a shallow trench structure to reduce the specific on-resistance of the device. While optimizing the current spread capability of the device, its on-resistance at high temperature is reduced, enhancing the saturation current clamping capability of the device and improving the short-circuit withstand capability of the device.

[0085] In some embodiments, if the silicon carbide power device is an IGBT, then the second electrode 720 is the emitter, the first electrode 710 is the collector, and the silicon carbide substrate 110 is P-type doped.

[0086] In some embodiments, see Figure 10 As shown, the current extension region 230 may include a first current extension region 221 and a second current extension region 222. Multiple first current extension regions 221 are arranged sequentially along a first direction, and multiple second current extension regions 222 are arranged sequentially along a second direction. The first direction is perpendicular to the second direction, thus the interface between the inclined P-type well region 410 and the second current extension region 222 is a continuous inclined surface, forming a grid-like cell inclined P-type well region 410. This makes the edge of the inclined P-type well region no longer a single-depth straight-wall corner, but presents an effective large radius of curvature transition with spatial expansion. The electric field is borne by its inclined interface. In contrast, under the stepped P-well structure, a severe electric field concentration occurs at the corner position under the blocking voltage, which reduces the device breakdown voltage. Furthermore, under short-circuit and UIS avalanche conditions, the stepped P-well structure leads to corner-concentrated collision ionization and heat. Compared to the stepped P-well structure, the grid-like cell inclined P-type well region 410 in this embodiment helps reduce the overall electric field peak of the gate dielectric layer and the device, improving the device reliability.

[0087] Prepared using the self-aligned process method described in the above embodiments Figure 10 The silicon carbide power device with a grid-like cell sloping P-type well region shown has a first preset angle for its ion implantation process. This first preset angle is fixed, for example, 90°. In this way, P-type doped ions can be implanted vertically into the second self-aligned sidewall 402. The arc-shaped sidewall of the previous step is etched using multiple etching processes. After each etching process, the coverage area of ​​the arc-shaped sidewall is reduced and its thickness is reduced. Then, after each etching process, P-type doped ions are implanted 3-5 times using a vertical ion implantation process, with the implantation energy decreasing sequentially. Thus, without rotating the wafer or adjusting the ion implantation direction, the sloping P-type well region 410 with a sloping structure is formed by utilizing the thickness difference of the sidewall mask. Its depth is increased by 0.8μm-3.0μm, and its specific size depends on the thickness of the process hard mask and the critical dimension CD of the pattern.

[0088] In some embodiments, Figure 11 This application provides a silicon carbide power device with a planar implanted P-type well region as one embodiment of the present application. Figure 11 (a) and silicon carbide power devices with P-type well regions formed by tilted injection ( Figure 11 The schematic diagram of doping concentration distribution in (b) is shown in the figure. Figure 11 As shown, Figure 11In (b), the lower surface of the inclined P-type well region 410 formed by the inclined injection angle is inclined, and the doping concentration of the inclined P-type well region 410 is gradient distributed, with the doping concentration near the channel being lower than the high concentration at the bottom.

[0089] In some embodiments, Figure 12 This application provides a silicon carbide power device with a planar implanted P-type well region as one embodiment of the present application. Figure 12 (a) and silicon carbide power devices with P-type well regions formed by tilted injection ( Figure 12 The schematic diagram of the electric field distribution in (b) is shown in the figure. Figure 13 This is a schematic diagram of the breakdown voltage curves of a silicon carbide power device with a P-type well region formed by tilted implantation and a P-type well region formed by planar implantation, provided in one embodiment of this application. Figure 12 and Figure 13 As shown, the silicon carbide power device in this embodiment has a sloping P-type well region 410 with an inclined shape. According to simulation results, under the same cell size, Figure 11 The schematic structure in (a) is voltage-bearing through the P-type well region and the heavily doped P-type region, and its breakdown voltage (BVDSS) is 1551V. Figure 13 Curve a) in the figure has a threshold voltage of 2.85V and a specific on-resistance of 2.3892 milliohms per square centimeter (mΩ·cm²). In this embodiment, through the inclined surface of the P-type well region 410, its breakdown voltage (BVDSS) is 1647V. Figure 13 Curve b in the figure shows that the threshold voltage is 2.795V and the specific on-resistance is 2.2748 milliohms per square centimeter (mΩ·cm²). Compared with silicon carbide power devices with P-type well regions formed by planar implantation, the breakdown voltage and specific on-resistance of the device are slightly improved after tilted implantation.

[0090] Combination Figure 14a and Figure 14b Simulation results show that the peak electric field of the gate dielectric layer of the silicon carbide power device with P-type well region formed by planar injection is 2.97MV / cm, while the peak electric field of the gate dielectric layer of the silicon carbide power device with P-type well region formed by tilted injection is 2.36MV / cm.

[0091] This application also provides a chip, including a silicon carbide power device fabricated by any of the self-aligned process methods described above.

[0092] In some embodiments, the chip includes a chip substrate on which one or more silicon carbide device structures are disposed, the silicon carbide device structures including the silicon carbide device structures of any of the above embodiments.

[0093] In one specific application embodiment, when the silicon carbide substrate 110 is N-type doped, the silicon carbide device structure can be a MOS structure, with the second electrode 720 as the source and the first electrode 710 as the drain. When the silicon carbide substrate 110 is P-type doped, the silicon carbide device structure can be an IGBT structure, with the second electrode 720 as the emitter and the first electrode 710 as the collector.

[0094] Other related semiconductor devices, as well as MOSFETs, can be integrated on the chip substrate to form an integrated circuit.

[0095] In one specific application embodiment, the chip can be a switch chip or a driver chip.

[0096] In this embodiment, the silicon carbide power device includes a grid-like cell inclined P-type well region within the chip. Multiple first current extension regions and second current extension regions are formed on the N-type drift region. The multiple first current extension regions are arranged sequentially according to a first direction, and the multiple second current extension regions are arranged sequentially according to a second direction. The first direction is perpendicular to the second direction, thus the interface between the inclined P-type well region and the second current extension region is a continuous inclined surface, forming a grid-like cell inclined P-type well region. This makes the edge of the inclined P-type well region no longer a single-depth straight-wall corner, but presents an effective large radius of curvature transition with spatial expansion. The inclined interface bears the electric field, reducing the overall electric field peak of the gate dielectric layer and the device, and improving the reliability of the device.

[0097] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0098] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A self-aligned fabrication method for silicon carbide power devices, characterized in that, The self-aligned process preparation method includes: An N-type drift region and a top epitaxial region are sequentially formed on the front side of a silicon carbide substrate; A first hard mask is formed in a first predetermined area of ​​the top epitaxial region, and a first trench is formed by etching the top epitaxial region under the protection of the first hard mask; Polycrystalline silicon material is deposited to form a polycrystalline silicon mask, and P-type doped ions are implanted into the top epitaxial region under the coverage of the polycrystalline silicon mask to form a first P-type well region. A first self-aligned sidewall is formed on the surface of the polysilicon mask and the first P-type well region. By repeatedly etching the first self-aligned sidewall, P-type doped ions are implanted into the region of the first P-type well region multiple times using the thickness difference of the self-aligned sidewall to form a sloping P-type well region. The interface between the sloping P-type well region and the top epitaxial region is a continuous sloping surface, and the implantation energy of the multiple P-type doped ion implantation process gradually decreases. After removing the self-aligned sidewalls, a channel masking layer is formed by oxidizing the polysilicon mask, and a second hard mask is formed in the first trench. N-type doped ions are injected into the sloping P-type well region using the masking effect of the channel masking layer and the second hard mask to form an N-type heavily doped region; wherein, the doping depth of the N-type heavily doped region is less than the doping depth of the sloping P-type well region. Remove the channel masking layer and the second hard mask, form a third hard mask on the top epitaxial region, the sloping P-type well region and the N-type heavily doped region, and implant P-type dopant ions along the first trench under the coverage of the third hard mask to form a P-type heavily doped region that extends into the N-type drift region. Remove the hard mask from the previous step to form a fourth hard mask covering the sloping P-type well region, the N-type heavily doped region, and the P-type heavily doped region. Under the coverage of the fourth hard mask, N-type dopant ions are injected into the top epitaxial region to form a current spread region. After removing the fourth hard mask, a gate dielectric layer is formed by an oxidation process. After depositing the gate polysilicon material, the gate polysilicon material is etched using a gate mask to form a gate polysilicon layer. After removing the gate mask, an interlayer dielectric material is deposited to form an interlayer dielectric layer. The gate dielectric layer and the interlayer dielectric layer form a cavity structure to enclose the gate polysilicon layer. A planar gate stack structure is formed on the channel region within the sloping P-type well region. The interlayer dielectric layer is etched to form electrode trenches to expose the P-type heavily doped region; A first electrode is formed on the back side of the silicon carbide substrate, and a second electrode is formed along the surface of the interlayer dielectric layer and the electrode trench; wherein the N-type heavily doped region and the P-type heavily doped region are in ohmic contact with the second electrode.

2. The self-aligned process preparation method according to claim 1, characterized in that, The formation of a first self-aligned sidewall on the surface of the polysilicon mask and the first P-type well region includes: The first self-aligned sidewall is formed by isotropic deposition of silicon oxide material.

3. The self-aligned process preparation method according to claim 1, characterized in that, The step of repeatedly etching the first self-aligned sidewall and implanting P-type doped ions into the region of the first P-type well region by utilizing the thickness difference of the self-aligned sidewall includes: The first self-aligned sidewall is etched to form an arc-shaped sidewall, and P-type doped ions are implanted into the first P-type well region in a vertical direction.

4. The self-aligned process preparation method according to claim 3, characterized in that, The method of repeatedly implanting P-type doped ions into the region of the first P-type well region by repeatedly etching the first self-aligned sidewall and utilizing the thickness difference of the self-aligned sidewall further includes: Under the cover of the arc-shaped sidewall, P-type doped ions are implanted into the first P-type well region multiple times in a vertical direction, wherein the implantation energy of the multiple ion implantation processes decreases sequentially.

5. The self-aligned process preparation method according to claim 4, characterized in that, The implantation dose decreases sequentially in each of the ion implantation processes described.

6. The self-aligned process preparation method according to any one of claims 1-5, characterized in that, The process of implanting P-type doped ions along the first trench under the coverage of the third hard mask to form a heavily doped P-type region extending into the N-type drift region includes: Under the cover of the third hard mask, within an implantation depth of 1.0 μm-1.5 μm, a multiple ion implantation process with progressively decreasing implantation energy is used to implant P-type doped ions along the first trench to form the heavily doped P-type region; the doping concentration of the heavily doped P-type region is greater than 1E19 cm⁻¹. -3 .

7. The self-aligned process preparation method according to any one of claims 1-5, characterized in that, The step of implanting N-type doped ions into the top epitaxial region under the cover of the fourth hard mask to form a current-spreading region includes: Under the cover of the fourth hard mask, N-type doped ions are injected into the top epitaxial region in an implantation depth range of 1 μm-4 μm, in order of gradually decreasing implantation energy.

8. The self-aligned process preparation method according to any one of claims 1-5, characterized in that, The interface between the inclined P-type well region and the current extension region can be any one of a linear inclined plane, a continuous inclined plane, a continuous curved inclined plane, or a continuous irregular inclined plane.

9. A self-aligned fabrication method for silicon carbide power devices, characterized in that, The self-aligned process preparation method includes: An N-type drift region and a top epitaxial region are sequentially formed on the front side of a silicon carbide substrate; A polysilicon mask is formed in a first predetermined region of the top epitaxial region, and P-type doped ions are implanted into the top epitaxial region under the coverage of the polysilicon mask to form a first P-type well region. A first self-aligned sidewall is formed on the surface of the polysilicon mask and the first P-type well region by depositing polysilicon material. The first self-aligned sidewall is then etched multiple times, and P-type doped ions are implanted into the region of the first P-type well region multiple times by utilizing the thickness difference of the self-aligned sidewall to form a sloping P-type well region. The interface between the sloping P-type well region and the top epitaxial region is a continuous sloping surface, and the implantation energy of the multiple P-type doped ion implantation process gradually decreases. After removing the self-aligned sidewalls, a channel masking layer is formed by oxidizing the polysilicon mask. N-type dopant ions are then injected into the sloping P-type well region using the masking layer to form an N-type heavily doped region. The doping depth of the N-type heavily doped region is less than the doping depth of the sloping P-type well region. Remove the channel masking layer and the polysilicon mask to form a third hard mask, and etch the N-type heavily doped region under the protection of the third hard mask to form a first trench; Under the protection of the third hard mask, P-type doped ions are injected along the first trench to form a heavily doped P-type region that extends into the N-type drift region; Remove the hard mask from the previous step to form a fourth hard mask covering the sloping P-type well region, the N-type heavily doped region, and the P-type heavily doped region. Under the coverage of the fourth hard mask, N-type dopant ions are injected into the top epitaxial region to form a current spread region. After removing the fourth hard mask, a gate dielectric layer is formed by an oxidation process. After depositing the gate polysilicon material, the gate polysilicon material is etched using a gate mask to form a gate polysilicon layer. After removing the gate mask, an interlayer dielectric material is deposited to form an interlayer dielectric layer. The gate dielectric layer and the interlayer dielectric layer form a cavity structure to enclose the gate polysilicon layer. A planar gate stack structure is formed on the channel region within the sloping P-type well region. The interlayer dielectric layer is etched to form electrode trenches to expose the P-type heavily doped region; A first electrode is formed on the back side of the silicon carbide substrate, and a second electrode is formed along the surface of the interlayer dielectric layer and the electrode trench; wherein the N-type heavily doped region and the P-type heavily doped region are in ohmic contact with the second electrode.

10. A chip, characterized in that, Including silicon carbide power devices prepared by the self-aligned process fabrication method as described in any one of claims 1-9.

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