Vertical gallium nitride gold oxide half-high electron mobility transistor with improved performance structure

Abstract

An integrated circuit includes electrodes of a vertical gallium nitride (GaN) gold-oxide-semiconductor (HOS) transistor and a gallium nitride super barrier rectifier (GaN Super Barrier Rectifier) ​​disposed in a gate trench of a unit. A first channel region of the GaN transistor is formed along a first sidewall of the gate trench, while a second channel region of the GaN Super Barrier Rectifier is formed along a first portion of a second sidewall opposite to the first sidewall of the gate trench. A source metal is connected via a source contact trench to a heterojunction surface, the body regions of the GaN transistor and the GaN Super Barrier Rectifier, and the gate electrode of the GaN Super Barrier Rectifier. Furthermore, a grounded P-type region is formed along a second portion of the second sidewall of the gate trench and connected to a P-type shielding region below the gate trench.

Description

Technical Field

[0001] This case relates to a nitride semiconductor device with an improved performance structure, and more specifically, to a gallium nitride gold oxide semiconductor (GOS) high electron mobility transistor that embeds a super barrier rectifier in the gate trench of the cell in a bypass parasitic diode manner, thereby reducing turn-off losses without reducing the channel density of the gallium nitride gold oxide semiconductor high electron mobility transistor. Background Technology

[0002] By utilizing heterojunction interfaces to generate two-dimensional electron gases (2DEG) with high electron mobility, lower on-resistance than silicon and silicon carbide (SiC) can be achieved. When vertical aluminum gallium nitride / gallium nitride (AlGaN / GaN) structures are used as switching components in converters or inverters, parasitic PN diodes exist within the components. Furthermore, due to the high reverse conduction voltage, this results in significant energy consumption during reverse conduction mode. Therefore, a common practice is to externally connect a freewheeling diode in parallel to reduce switching losses. However, the added freewheeling diode increases cost and parasitic inductance.

[0003] Furthermore, because the area of ​​gallium nitride (GaN) devices is much smaller than that of silicon-based MOSFETs (Si-MOSFETs), short-circuit failure remains the most serious reliability issue for GaN devices, and it also leads to higher junction temperatures. During the instantaneous short circuit, the device will withstand high DC voltage and large saturation current. If the device does not have good short-circuit withstand capability, it will lead to a decrease in device performance or even severe burnout failure.

[0004] Therefore, the design and fabrication of gallium nitride gold oxide semi-high electron mobility transistors still require a novel cell structure, component structure, and process technology to enable vertical gallium nitride gold oxide semi-high electron mobility transistors to have a lower electric field strength in the gate oxide layer, thereby achieving lower on-resistance and lower saturation current, and improving the short-circuit withstand capability of the component. Summary of the Invention

[0005] This invention relates to a nitride semiconductor device comprising at least three epitaxial layers grown on a substrate, including a top epitaxial layer, an intermediate epitaxial layer, and a bottom epitaxial layer; the bandgap of the top epitaxial layer is greater than or less than that of the intermediate epitaxial layer, and a heterojunction surface is formed between the top and intermediate epitaxial layers; a body region is formed at the top of the bottom epitaxial layer. A gate trench extends through the top, intermediate, and body regions and terminates at the bottom epitaxial layer. A source contact trench extends through the top, intermediate, and body regions and terminates at the bottom epitaxial layer. A metal contact plug is filled in the source contact trench and connected to the heterojunction surface and body region by a source metal. When the component is turned on, the drain-source current will flow from the back metal, which serves as the drain metal, to the front metal, which serves as the source metal, and will pass through the drift region of the bottom epitaxial layer, the channel region along the sidewall of the gate trench in the body region, the metal contact plug in the heterojunction interface and the source contact trench.

[0006] The nitride semiconductor device of the present invention further includes at least one pair of P-shields (PS) formed of a second conductivity type, the P-shields surrounding the bottom region of the source contact trench and connected to the body contact region; at least one junction field-effect transistor (JFET) formed of a first conductivity type is sandwiched between the pair of P-shields, wherein the doping concentration of the junction field-effect transistor is higher than that of the bottom epitaxial layer, thereby limiting the saturation current during the forward conduction phase and improving short-circuit withstand capability. Due to the presence of the pair of P-shields, the electric field strength of the gate oxide layer is reduced when the region of high electric field strength shifts from the channel region to the pair of P-shields.

[0007] The nitride semiconductor device of the present invention further includes a gate trench having at least one single stepped gate trench structure, comprising a first type gate trench and a second type gate trench, wherein the first type gate trench is located above the second type gate trench and has a wider trench width than the second type gate trench; a first gate electrode is disposed in the first type gate trench and is surrounded by a first insulating layer on the bottom of the first type gate trench and by a first gate oxide layer on the sidewall of the first type gate trench; the first insulating layer has a thicker thickness than the first gate oxide layer; the second type gate trench is surrounded by a P-type shielding region formed by a second conductivity type and is filled with the first insulating layer; and at least one grounded P-type region (grounded P,GP) formed by the second conductivity type surrounds the sidewall of the first type gate trench and is connected to the body region and the P-type shielding region.

[0008] This invention also discloses an integrated circuit comprising a vertical gallium nitride gold-oxide half-wave high electron mobility transistor (hereinafter referred to as GaN MOSHEMT or GaN HEMT) and a gallium nitride super barrier rectifier (hereinafter referred to as GaN SBR), and each cell having two gate electrodes arranged side-by-side in a gate trench. The first channel region of the GaN MOSHEMT is formed along the first sidewall of the gate trench, while the second channel region of the GaN SBR is formed along the first portion of the second sidewall of the gate trench opposite to the first sidewall. The source metal is connected to the heterojunction interface, the body region of the GaN MOSHEMT, the body region of the GaN SBR, and the gate electrode of the GaN SBR via a source metal contact plug filled in the source contact trench, and is connected to a P-type shielding region located below the gate trench via a grounded P-type region (GP) along the second portion of the second sidewall of the gate trench.

[0009] According to another aspect of this invention, the present invention further includes an integrated circuit comprising a first gate electrode of a GaN MOSHEMT disposed in the upper portion of a gate trench, a shielding gate electrode disposed below the first gate electrode, which is connected to the source metal and grounded, and serves as a second gate electrode of a GaN SBR, and an interpolysilicon oxide (IPO) layer isolating the second gate electrode from the first gate electrode; the first gate electrode is laterally isolated from the adjacent epitaxial layer by the first gate oxide layer on the sidewall of the gate trench in the GaN MOSHEMT, and the second gate electrode is vertically isolated from the adjacent epitaxial layer by the second gate oxide layer in the bottom region of the gate trench in the GaN SBR, wherein the thickness of the second gate oxide layer is thinner than that of the first gate oxide layer; the first channel region of the GaN MOSHEMT is formed along the first sidewall of the gate trench, while the second channel region of the GaN SBR is formed along the bottom region of the gate trench.

[0010] After reading the following detailed description of preferred embodiments, the objects and advantages of the present invention will undoubtedly become apparent to those skilled in the art, wherein the preferred embodiments are described in conjunction with the accompanying drawings. Attached Figure Description

[0011] Figure 1A A cross-sectional view of a preferred embodiment of a nitride semiconductor device of the present invention is shown, wherein the device includes three epitaxial layers, namely a top epitaxial layer, a middle epitaxial layer and a bottom epitaxial layer.

[0012] Figure 1BA cross-sectional view of another preferred embodiment of the nitride semiconductor device of the present invention is shown, wherein the device includes three epitaxial layers, namely a top epitaxial layer, a middle epitaxial layer and a bottom epitaxial layer, and the materials of the top epitaxial layer and the middle epitaxial layer are interchangeable.

[0013] Figure 1C A cross-sectional view of another preferred embodiment of the nitride semiconductor device of the present invention is shown, wherein the device includes three epitaxial layers, the gate oxide layer being an atomic layer deposition of SiO2, Al2O3 or HfO2, and an intermediate layer formed of aluminum nitride or unintentionally doped gallium nitride filling the sidewalls of the gate trench to enhance channel mobility.

[0014] Figure 1D A cross-sectional view of another preferred embodiment of the nitride semiconductor device of the present invention is shown, wherein the device includes three epitaxial layers and an N-type source is disposed on top of the top epitaxial layer.

[0015] Figure 2 A cross-sectional view of another preferred embodiment of the nitride semiconductor device of the present invention is shown, wherein the device includes three epitaxial layers having two heterojunction surfaces formed on the body region.

[0016] Figure 3 A cross-sectional view of another preferred embodiment of the nitride semiconductor device of the present invention is shown, wherein the device includes three epitaxial layers and shows the vertical doping concentration variation of the P-type shielding region (from the PS1t region to the PS1b region) and the N-type region (from the JFET1t region to the N+ GaN substrate).

[0017] Figure 4 A cross-sectional view of another preferred embodiment of the nitride semiconductor device of the present invention is shown, wherein the device includes three epitaxial layers and has a shielded gate electrode disposed below the gate electrode in a gate trench.

[0018] Figure 5 A cross-sectional view of another preferred embodiment of the nitride semiconductor device of the present invention is shown, wherein the device includes three epitaxial layers, an additional N-type buffer layer sandwiched between an N+ type substrate and a P-type pillar region, and a junction field-effect transistor region formed between two adjacent sidewall P-type shielded regions (SPS).

[0019] Figure 6A A cross-sectional view of another preferred embodiment of the nitride semiconductor device of the present invention is shown, illustrating an insulated gate bipolar transistor (IGBT) structure applied to a P+ type substrate.

[0020] Figure 6BA cross-sectional view of another preferred embodiment of the nitride semiconductor device of the present invention is shown, illustrating an insulated-gate bipolar transistor structure applied to a P+ type substrate having multiple alternating P+ and N+ regions.

[0021] Figure 7 A cross-sectional view of another preferred embodiment of the nitride semiconductor device of the present invention is shown, wherein the device includes three epitaxial layers having an L-shaped P-type shielding region (LPS) disposed below the gate trench and beside the sidewall, and adjacent to the lower surface of the body region.

[0022] Figure 8 A cross-sectional view of another preferred embodiment of the nitride semiconductor device of the present invention is shown, wherein the device includes three epitaxial layers having a single stepped gate trench structure and an additional second P-type shielding region (PS2) having a second conductivity type.

[0023] Figure 9A A cross-sectional view of another preferred embodiment of the nitride semiconductor device of the present invention is shown, wherein the device includes three epitaxial layers and two gate electrodes disposed side by side in a gate trench.

[0024] Figure 9B A cross-sectional view of another preferred embodiment of the nitride semiconductor device of the present invention is shown, wherein the device includes three epitaxial layers, two gate electrodes arranged side by side in a gate trench, and an N-type source region is provided on top of the top epitaxial layer.

[0025] Figure 10A A top view of a preferred embodiment of the trench semiconductor power component of the present invention is shown, wherein the component has a strip cell layout.

[0026] Figure 10B A top view of another preferred embodiment of the trench semiconductor power component of the present invention is shown, wherein the component has a strip cell layout.

[0027] Figure 10C It shows according to Figure 10A In a preferred embodiment, a cross-sectional view along A1-A1' is provided, wherein the component includes three epitaxial layers, has a single stepped gate trench structure, and an additional second P-type shielding region having a second conductivity type.

[0028] Figure 10D It shows according to Figure 10A In a preferred embodiment, a cross-sectional view along B1-B1' shows that the component includes three epitaxial layers and has a grounded P-type region (GP) disposed along the second sidewall of the first type gate trench.

[0029] Figure 10E It shows according to Figure 10AIn a preferred embodiment, a cross-sectional view along C1-C1' shows the gate electrode contact region of the GaN SBR.

[0030] Figure 10F It shows according to Figure 10A In a preferred embodiment, a cross-sectional view along D1-D1' shows the gate electrode contact region of the GaN MOSFET.

[0031] Figure 10G It shows according to Figure 10A Another preferred embodiment of the A1-A1' cross-sectional view, wherein the component has an N-type source region disposed on top of the top epitaxial layer.

[0032] Figure 11A It shows according to Figure 10A Another preferred embodiment of the cross-sectional view of A1-A1', wherein the component has a P+ type substrate.

[0033] Figure 11B It shows according to Figure 10A Another preferred embodiment of the cross-sectional view A1-A1' shows an IGBT structure paired with a P+ type substrate having multiple staggered P+ and N+ regions.

[0034] Figure 12A A top view of a preferred embodiment of the trench semiconductor power component of the present invention is shown, wherein the component has a strip cell layout.

[0035] Figure 12B It shows according to Figure 12A In a preferred embodiment, a cross-sectional view along A2-A2' shows that the component has a second P-type body region and a first N-type source region, and surrounds the second sidewall of the gate trench.

[0036] Figure 12C It shows according to Figure 12A In a preferred embodiment, a cross-sectional view along B2-B2' shows the contact area of ​​the shielded gate electrode.

[0037] Figure 12D It shows according to Figure 12A Another preferred embodiment of the A2-A2' cross-sectional view, wherein the component has a second N-type source region disposed on top of the top epitaxial layer.

[0038] List of reference numerals

[0039] 101, 101', 101'', 101''', 201, 301, 401, 501, 701, 801, 901, 901', 1001'', 1001''', 1001''', 1001'''', 1001'''', 1201', 1201'', 1201'': N+ type GaN substrate

[0040] 601, 601', 1101, 1101': P+ type GaN substrate

[0041] 102, 102', 102'', 102''', 202, 302, 402, 502, 602, 602', 702, 902, 902', 1002, 1002', 1202, 1202', 1202'', 1202''': Gate trench

[0042] 802, 1002'', 1002''', 1002'''', 1002'''', 1002''''', 1102, 1102': Type I gate trench

[0043] 803, 1003'', 1003''', 1003'''', 1003'''', 1003''''', 1103, 1103': Type II gate trench

[0044] 104, 104', 104'', 104''', 204, 304, 404, 504, 604, 604', 704, 804, 904, 904', 1004'', 1004''', 1004''', 1004'''', 1004'''', 1104, 1104', 1204', 1204'', 1204'': Source contact trench

[0045] 105, 105', 105'', 105''', 205, 305, 405, 505, 605, 605', 705, 805: Gate electrode

[0046] 106, 106''', 206, 306, 406, 606, 606', 706, 806: First insulating layer

[0047] 107, 107', 107'', 107''', 207, 307, 407, 507, 607, 607', 707, 807, 907, 907', ​​1007, 1007'', 1007''', 1007''', 1007'''', 1007'''', 1107, 1107', 1207, 1207', 1207'', 1207'': Source metal contact plug

[0048] 408, 1008'', 1008''', 1008'''', 1008'''', 1008''''', 1108, 1108', 1208', 1208'', 1208'': Current spreading layer

[0049] 109, 109', 109'', 109''', 209, 309, 409, 509, 609, 609', 709, 809, 909, 909', 1009'', 1009''', 1009''', 1009'''', 1009'''', 1109, 1109', 1209', 1209'', 1209'': Intermediate dielectric layer

[0050] 110, 110', 110'', 210, 310, 410, 510, 610, 610', 710, 810, 910, 910', 1010'', 1110, 1110': Body contact area

[0051] 111'''、911'、1011'''''': n+ type source region

[0052] 112, 112', 112'', 112''', 212, 312, 412, 512, 612, 612', 712, 812, 912, 912', 1012'', 1012''', 1012''', 1012'''', 1112, 1112', 1212, 1212', 1212'', 1212'': Source metal

[0053] 113, 113', 113'', 113''', 213, 313, 413, 513, 613, 613', 713, 813, 913, 913', 1013'', 1013''', 1013''', 1013'''', 1013''''', 1113, 1113', 1213', 1213'', 1213'': Bottom epitaxial layer

[0054] 114, 114', 114'', 114''', 214, 314, 414, 514, 614, 614', 714, 814, 914, 914', 1014'', 1014''', 1014''', 1014'''', 1114, 1114', 1214', 1214'', 1214'': Body area

[0055] 915, 915', 1015''''': First gate electrode

[0056] 916, 916', 1016'', 1016''', 1016'''', 1016''''', 1116, 1116': First insulating layer

[0057] 117, 117', 117'', 117''', 217, 617, 617', 717, 917, 917': Junction field-effect transistor region

[0058] 317: Top junction field-effect transistor region

[0059] 118, 118', 118'', 118''', 218, 418, 618, 618', 718, 818, 918, 918', 1018, 1018', 1018'', 1018''', 1018''', 1018'''', 1018''''', 1118, 1118', 1218', 1218'', 1218'': First P-type shielding zone

[0060] 318: Top First P-type Shielding Zone

[0061] 119, 119', 119'', 119''', 219, 319, 419, 519, 619, 619', 719, 819, 919, 919', 1019'', 1019''', 1019'''', 1119, 1119', 1219', 1219''': First gate oxide layer

[0062] 120, 120', 120'', 120''', 220, 320, 420, 520, 620, 620', 720, 820, 920, 920', 1020'', 1020''', 1020''', 1020'''', 1120, 1120', 1220', 1220'', 1220'': Back metal

[0063] 1221', 1221'', 1221''': First source region

[0064] 522, 622, 622', 1122, 1122': N-type buffer layer

[0065] 123, 123', 123'', 123''', 223, 323, 423, 523, 623, 623', 723, 823, 923, 923', 1023'', 1023''', 1023''', 1023'''', 1023''''', 1123, 1123', 1223', 1223'', 1223'': Intermediate epitaxial layer

[0066] 924, 924', 1024'', 1024''', 1024'''', 1024'''', 1124, 1124', 1224, 1224', 1224'', 1224'': Second Body Region

[0067] 925, 925', 1025''': Second gate electrode

[0068] 426: Intermediate polysilicon oxide layer

[0069] 926, 926', 1026'', 1026''', 1026''''', 1126, 1126', 1226', 1226''': Second insulating layer

[0070] 327: Bottom junction field-effect transistor region

[0071] 728: L-shaped P-type shielding area

[0072] 328: Bottom first P-type shielding area

[0073] 129'', 529: Intermediate layer

[0074] 929, 929', 1029'', 1029''', 1029''', 1029'''', 1029''''', 1129, 1129', 1229'': Second gate oxide layer

[0075] 1029''': Grounding P-type area

[0076] 1231''': Second n+ type source region

[0077] 1032, 1032', 1032''', 1232, 1232'': Second gate metal contact plugs

[0078] 133, 133', 133'', 133''', 233, 333, 433, 533, 633, 633', 733, 833, 933, 933', 1033'', 1033''', 1033''', 1033'''', 1033''''', 1133, 1133', 1233', 1233'', 1233'': Top epitaxial layer

[0079] 435, 1235', 1235'', 1235''': Shielded gate electrode

[0080] 936, 936', 1036'', 1036''', 1036''''', 1136, 1136': Intermediate polysilicon oxide layer

[0081] 537: Junction Field-Effect Transistor Region

[0082] 538: Sidewall P-type shielding area

[0083] 1239'': Third gate oxide layer

[0084] 540: P-type column zone

[0085] 1042, 1042', 1042''''', 1242: First gate metal contact plugs

[0086] 143, 143', 143'', 143''', 243, 343, 443, 543, 943, 943', 1043'', 1043''', 1043''', 1043'''', 1143, 1143', 1243', 1243'', 1243'': Heterojunction surface

[0087] 947, 947', 1047'', 1047''', 1047'''', 1147, 1147', 1247', 1247'', 1247'': N-type short channel injection region

[0088] 848, GP: Grounded P-type area

[0089] 1052, 1052', 1052''''', 1252: Gate metal rails

[0090] 253: Epitaxial layer

[0091] 858, 1058, 1058', 1058'', 1058''', 1058''', 1058'''', 1058'''', 1158, 1158': Second P-type shielding zone

[0092] 859, 1059'', 1159, 1159': Top second P-type shielding area

[0093] 860, 1060'', 1160, 1160': Bottom second P-type shielding area

[0094] 662', 1062': High-concentration N+ type doped regions

[0095] 263: Heterogeneous junction

[0096] 971, 971', 1071, 1071', 1071'', 1071''', 1071''', 1071'''', 1071'''', 1171, 1171', 1271, 1271', 1272'', 1271''': First Passage Area

[0097] 972, 972', 1072, 1072'', 1072''', 1072'''', 1072'''', 1072''''', 1172, 1172', 1272', 1272'', 1272'': Second Passage Area

[0098] 990, 990', 1090', 1090'', 1090''', 1290': GaN SBR

[0099] 900, 900', 1000'', 1000''', 1200': GaN MOSHEMT

[0100] GOX1: First gate oxide layer

[0101] GOX2: Second gate oxide layer

[0102] G1: First gate electrode

[0103] G2: Second gate electrode

[0104] PS2t: Top Second P-type Shielding Area

[0105] PS2b: Bottom second P-type shielding area

[0106] G: Gate electrode

[0107] SG: Shielded Gate Electrode

[0108] 1202'-S1, 1202''-S1, 1202'''-S1: First sidewall

[0109] 1202'-S2, 1202''-S2, 1202'''-S2: Second sidewall Detailed Implementation

[0110] In the following detailed description, reference will be made to the accompanying drawings, which form a part of the description and illustrate specific embodiments in which the present invention may be implemented. Therefore, directional terms such as “upper,” “lower,” “front,” and “rear” are used to describe various directions in the drawings, and since the components and structures shown in the embodiments can be applied in various directions, such directional terms are for illustrative purposes and do not constitute any limitation. It should be understood that other embodiments may be used, with structural or logical modifications, without departing from the scope of the invention. Therefore, the following detailed description should not be considered a limitation of the invention, the scope of which is determined by the statement of the appended claims. It should be understood that, unless otherwise specifically stated, various features of the various exemplary embodiments described herein can be combined with each other.

[0111] Please refer to Figure 1A The preferred embodiment of the present invention is shown. This preferred embodiment includes a nitride semiconductor device formed on an N+ type GaN substrate 101 (as shown in the figure, N+ GaN), on which a low-doped N-type GaN (as shown in the figure, N-GaN) bottom epitaxial layer 113 (as shown in the figure, BEL) extends. A back metal 120 is deposited on the back side of the N+ type GaN substrate 101 as a drain. A gallium nitride aluminum layer (Al) X Ga YA top epitaxial layer 133 (as shown in the figure, TEL) and an N-type GaN layer 123 (as shown in the figure, MEL) are formed on top of the bottom N-type GaN epitaxial layer 113. The top epitaxial layer 133 has a higher bandgap than the intermediate epitaxial layer 123, thus forming a heterojunction surface 143 between the top epitaxial layer 133 and the intermediate epitaxial layer 123. A P-type GaN (P GaN) body region 114 is formed on the top of the bottom epitaxial layer 113 and is connected to a p+ type body contact region 110 that is also disposed on the top of the bottom epitaxial layer 113. In the N-type epitaxial layer, a plurality of gate trenches 102 and source contact trenches 104 are formed vertically downward from the top surface of the top epitaxial layer 133. The trenches penetrate the top epitaxial layer 133, the middle epitaxial layer 123 and the body region 114, and terminate at the bottom epitaxial layer 113. In each gate trench 102, a gate electrode 105 (as shown in Figure G) is disposed in the upper portion and is laterally isolated from the adjacent epitaxial layer by a gate oxide layer (GOX1) 119, and is vertically isolated from the adjacent epitaxial layer by a first insulating layer 106 located in the bottom region of the gate trench 102. The thickness of the first insulating layer 106 is greater than the thickness of the gate oxide layer 119, wherein the gate oxide layer 119 is an atomic layer deposition of silicon dioxide (SiO2), aluminum oxide (Al2O3) or hafnium dioxide (HfO2). In the bottom epitaxial layer 113, a pair of first P-type shielding regions 118 (as shown in the figure PS1) with a second conductivity type are formed and separated by an N-type junction field-effect transistor region 117 (as shown in the figure JFET, hereinafter also referred to as such), wherein the doping concentration of the junction field-effect transistor region 117 is higher than that of the bottom epitaxial layer 113. Each of the first P-type shielding regions 118 in each pair is arranged around the bottom region of the source contact trench 104 and connected to the p+ type body contact region 110 and a metal contact plug 107 filled in the source contact trench 104. The metal contact plug 107 is connected to the heterojunction junction 143 and the p-type body region 114 by the source metal 112. In addition, an intermediate dielectric layer 109 is stacked above the epitaxial layer, and the source metal 112 is disposed on the intermediate dielectric layer 109.

[0112] Please refer to Figure 1BThe following is another preferred embodiment of the present invention, wherein a novel improved component structure is employed. The gallium nitride component of this embodiment is similar in structure to the embodiment shown in Figure 1A, the difference being the interchangeability of the materials of the top epitaxial layer and the intermediate epitaxial layer. In this embodiment, an N-type gallium nitride layer serves as the top epitaxial layer 123', and an N-type aluminum gallium nitride layer serves as the intermediate epitaxial layer 133' and is formed on the N-type GaN bottom epitaxial layer 113'. Furthermore, a gate oxide layer 119' is deposited on the sidewalls and bottom region of the gate trench 102'.

[0113] Please refer to Figure 1C The invention shown in another preferred embodiment employs a novel improved component structure. The gallium nitride component of this embodiment is... Figure 1A The structures of the embodiments shown are similar, except that, in addition to the gate oxide layer 119" being an atomic layer deposition of SiO2, Al2O3 or HfO2, the two sidewalls of the gate trench 102'' are filled with an intermediate layer 129'' formed of aluminum nitride (AlN) or unintentionally doped (UID) GaN to improve channel mobility.

[0114] Please refer to Figure 1D The invention shown in another preferred embodiment employs a novel improved component structure. The gallium nitride component of this embodiment is... Figure 1A The structure of the illustrated embodiment is similar, except that it further includes an n+ type source region 111''' formed on top of the top epitaxial layer 133'''. This n+ type source region 111''' is connected to the gate trench 102''' and the source contact trench 104''' to reduce the on-resistance. The n+ type source region 111''' is formed by depositing a highly doped N-type nitride semiconductor layer or by implanting silicon ions into the top epitaxial layer 133'''.

[0115] Please refer to Figure 2 The invention shown in another preferred embodiment employs a novel improved component structure. The gallium nitride component of this embodiment is... Figure 1A The structure of the illustrated embodiment is similar, except that it further includes three epitaxial layers disposed above the P-type body region 214, and these three epitaxial layers are Al... X Ga Y N-layer 253, GaN-layer 233 and Al X Ga YN layer 223, and two junctions between the three epitaxial layers above the P-type body region 214 form heterojunction junctions 243 and 263 respectively, where Y = 1 when X = 1, or Y = 1 – X when 0 < X ​​< 1.

[0116] Please refer to Figure 3 Another preferred embodiment of the present invention is shown, wherein this embodiment employs a novel improved component structure, and the doping concentration variations of the first P-type shielding region PS1 (from the top first P-type shielding region PS1t to the bottom first P-type shielding region PS1b) and the N-type region (from the top first junction field-effect transistor region JFET1t to the N+ type substrate) are depicted along the vertical direction. The gallium nitride component of this embodiment is similar in structure to the embodiment shown in Figure 1A, except that it includes multiple stepped P-type shielding regions (MSPS as shown), wherein the stepped P-type shielding regions are disposed in the bottom epitaxial layer 313, and include a pair of bottom first P-type shielding regions 328 (as shown in the figure PS1b) and a pair of top first P-type shielding regions 318 (as shown in the figure PS1t). The top first P-type shielding regions 318 are disposed above the bottom first P-type shielding regions 328, and the bottom first P-type shielding regions 328 have a doping concentration D. PS1b Furthermore, the top first P-type shielding region 318 has a doping concentration D. PS1t And the doping concentration D PS1t < Doping concentration D PS1b Furthermore, two first-junction field-effect transistor regions are formed, including a bottom-junction field-effect transistor region 327 (as shown in Figure JFET1b) and a top-junction field-effect transistor region 317 (as shown in Figure JFET1t). The bottom-junction field-effect transistor region 327 has a width W. J1b and doping concentration D JFET1b Furthermore, the top junction field-effect transistor region 317 has a width W J1t and doping concentration D JFET1t , where the width W J1b < Width W J1t And the doping concentration D JFET1b > Doping concentration D JFET1t However, the doping concentration D JFET1b The doping concentration D is lower than that of the N+ type GaN substrate 301. N+ Doping concentration D JFET1t The doping concentration D is higher than that of the bottom epitaxial layer 313 of N-type GaN. N Therefore, the doping concentration in the N-type region has the following relationship: Doping concentration D N < Doping concentration D JFET1t < Doping concentration D JFET1b <Doping concentration DN+ The doping concentration distribution curves in the first P-type shielding region (the top first P-type shielding region PS1t and the bottom first P-type shielding region PS1b) are consistent with those in the first junction field-effect transistor region JFET1 (the top first junction field-effect transistor region JFET1t and the bottom first junction field-effect transistor region JFET1b). The bottom first junction field-effect transistor region JFET1b 327 and the top first junction field-effect transistor region JFET1t 317 are respectively formed between a pair of bottom first P-type shielding regions PS1b 328 and a pair of top first P-type shielding regions PS1t 318. Additionally, the first saturation current pinching structure (as shown in Figure 1) is also present. st The SCP includes a top first junction field-effect transistor region JFET1t 317, sandwiched between two top first P-type shielded regions PS1t 318. The second saturation current clamping structure (as shown in Figure 2) nd The SCP includes a bottom first junction field-effect transistor region JFET1b 327 sandwiched between two bottom first P-type shielded regions PS1b 328. A first saturation current clamping structure and a second saturation current clamping structure are used to clamp the voltage, thereby limiting the saturation current during the forward conduction phase and improving short-circuit withstand capability.

[0117] Please refer to Figure 4 The invention shown in another preferred embodiment employs a novel improved component structure. The gallium nitride component of this embodiment is... Figure 1AThe illustrated embodiments have similar structures, differing only in that they include a different shielding gate structure in the gate trench 402, and further include an additional N-type current spreading layer 408 (current spreading layer, as shown in the figure, CSL), formed above the bottom epitaxial layer 413 and below the P-type body region 414, and having a higher doping concentration than the bottom epitaxial layer 413. In this structure, in each gate trench 402, a shielding gate electrode 435 (as shown in the figure, SG) is disposed in the lower portion of the gate trench 402 and below the gate electrode 405 (as shown in the figure, G). The gate electrode 405 is disposed in the upper portion of the gate trench 402. The gate electrode 405 is laterally isolated from the adjacent epitaxial layer by a gate oxide layer 419 on the sidewall of the gate trench 402, and the shielding gate electrode 435 is vertically isolated from the adjacent epitaxial layer by an insulating layer 406, wherein the thickness of the insulating layer 406 is greater than the thickness of the gate oxide layer 419. Furthermore, the shielded gate electrode 435 and the gate electrode 405 are insulated from each other by another insulating layer 426, which may be an inter-poly oxide (IPO) layer.

[0118] Please refer to Figure 5 The invention shown in another preferred embodiment employs a novel improved component structure. The gallium nitride component of this embodiment is... Figure 1C The structures of the embodiments shown are similar, the difference being that... Figure 1C The first P-type shielding region PS1 in the illustrated embodiment is omitted, and this embodiment further includes a P-type pillar region 540 (as shown in the figure PC), wherein the P-type pillar region 540 has a second conductivity type, is formed above the N+ type substrate 501 and adjacent to the bottom surface of the P-type body region 514. The N-type bottom epitaxial layer 513 thus forms a super junction (as shown in the figure SJ) with the P-type pillar region 540. In addition, the added N-type buffer layer 522 (as shown in the figure Nb) has a resistance value Rb and is sandwiched between the N+ type substrate 501 and the P-type pillar region 540, wherein the resistance value Rb of the N-type buffer layer 522 is greater than the resistance value of the N-type bottom epitaxial layer 513. In addition, the two sidewall P-type shielding regions 538 (as shown in the figure SPS) each have a second conductivity type, are opposite each other and horizontally adjacent to the corresponding P-type pillar region 540, the two sidewall P-type shielding regions 538 are separated from the P-type body region 514, and the doping concentration of the two sidewall P-type shielding regions 538 is higher than the doping concentration of the P-type pillar region 540. A junction field-effect transistor region (as shown in the figure JFET) with a first conductivity type is formed between the two sidewall P-type shielding regions 538, and the doping concentration of the two sidewall P-type shielding regions 538 is higher than the doping concentration of the N-type bottom epitaxial layer 513.

[0119] Please refer to Figure 6A The invention shown in another preferred embodiment employs a novel improved component structure. The gallium nitride component of this embodiment is... Figure 1A The structures of the embodiments shown are similar, the difference being the use of different substrates and the addition of a buffer layer. In this embodiment, the GaN component is formed on a P+ type GaN substrate 601, and an N-type GaN buffer layer 622 (as shown in the figure, Nb) is sandwiched between the P+ type GaN substrate 601 and the bottom epitaxial layer 613. The resistance value Rb of the buffer layer 622 is less than the resistance value R of the bottom epitaxial layer 613.

[0120] Please refer to Figure 6B The invention shown in another preferred embodiment employs a novel improved component structure. The gallium nitride component of this embodiment is... Figure 6A The structures of the embodiments shown are similar, the difference being that... Figure 6B The gallium nitride device shown further includes multiple highly doped N+ type GaN regions 662' in a P+ type substrate 601' to form multiple alternating P+ and N+ regions in the substrate.

[0121] Please refer to Figure 7 The invention shown in another preferred embodiment employs a novel improved component structure. The gallium nitride component of this embodiment is... Figure 1A The structures of the embodiments shown are similar, except that this embodiment further includes an L-shaped P-type shielding region 728 (as shown in the figure, LPS), which has a second conductivity type and is disposed below the gate trench 702 and next to the sidewall, and adjacent to the bottom surface of the P-type body region 714.

[0122] Please refer to Figure 8 The invention shown in another preferred embodiment employs a novel improved component structure. The gallium nitride component of this embodiment is... Figure 1A The structures of the embodiments shown are similar, the difference being that... Figure 1A In the embodiment shown, the junction field-effect transistor region (JFET) is omitted, and the gate trench has a step.

[0123] The gate trench structure includes a first-type gate trench 802 and a second-type gate trench 803, wherein the first-type gate trench 802 is located above the second-type gate trench 803 and has a wider gate width than the second-type gate trench 803. A gate electrode 805 (as shown in Figure G) is disposed in the first-type gate trench 802. The bottom region of the first-type gate trench 802 is surrounded by a thick oxide layer as a first insulating layer 806, and the sidewalls of the first-type gate trench 802 are surrounded by a gate oxide layer 819, wherein the thickness of the gate oxide layer 819 is thinner than the thickness of the first insulating layer 806, and the second-type gate trench 803 is filled with the first insulating layer 806. The GaN device shown in Figure 8 also includes a second P-type shielding region 858 (as shown in Figure PS2), having a second conductivity type, to reduce the electric field of the gate oxide layer surrounding the bottom and sidewalls of the second-type gate trench 803. The second P-type shielding region 858 further includes two sub-regions: a top second P-type shielding region 859 (as shown in the figure PS2t) and a bottom second P-type shielding region 860 (as shown in the figure PS2b). The bottom second P-type shielding region 860 is located below the top second P-type shielding region 859 and has a lower doping concentration than the top second P-type shielding region 859. Additionally, a grounded P-type region 848 (as shown in the figure GP) has a second conductivity type and is wound around the sidewall of the first type gate trench 802, connecting the second P-type shielding region 858 and the P-type body region 814.

[0124] Please refer to Figure 9AAnother preferred embodiment of the present invention is shown, wherein this embodiment employs a novel improved component structure, wherein a GaN MOSHEMT 900 and a GaN SBR 990 are integrated into a single unit, which is formed on a bottom epitaxial layer 913 on an N+ type GaN substrate 901 (as shown in the figure, N+ GaN), wherein the bottom epitaxial layer 913 has a lower doping concentration than the N+ type GaN substrate 901, and the back side of the N+ type GaN substrate 901 is plated with a back metal 920 as a drain metal. An N-type AlGaN layer as a top epitaxial layer 933 and an N-type GaN layer as an intermediate epitaxial layer 923 are formed on the N-type GaN bottom epitaxial layer 913, wherein the top epitaxial layer 933 has a different bandgap than the intermediate epitaxial layer 923, thereby forming a heterojunction interface 943 between the interface of the top epitaxial layer 933 and the intermediate epitaxial layer 923. A first P-type body region 914 (as shown in p1) of GaNMOSHEMT 900 and a second P-type body region 924 (as shown in p2) of GaN SBR 990 are formed on the top of the bottom epitaxial layer 913. The first P-type body region 914 and the second P-type body region 924 are respectively connected to a p+ type body contact region 910, which is also disposed on the top of the bottom epitaxial layer 913. In the N-type epitaxial layer, a plurality of gate trenches 902 and source contact trenches 904 are formed vertically downward from the upper surface of the top epitaxial layer 933. The gate trenches 902 and source contact trenches 904 penetrate the intermediate epitaxial layer 923, the body region 914, the body region 924, and the p+ type body contact region 910, and terminate at the bottom epitaxial layer 913. In each gate trench 902, a first gate electrode 915 of the GaN MOSHEMT 900 (as shown in G1) and a second gate electrode 925 of the GaN SBR 900 (as shown in G2) are formed side by side. A first gate oxide layer (GOX1) 919 on the sidewall of the gate trench of the GaN MOSHEMT 900 laterally isolates the first gate electrode 915 from the adjacent epitaxial layer, and a first insulating layer 916 located in the bottom region of the gate trench 902 vertically isolates it from the adjacent epitaxial layer, wherein the thickness of the first insulating layer 916 is greater than the thickness of the first gate oxide layer 919.The second gate electrode 925 is vertically isolated from the adjacent epitaxial layer by a second insulating layer 926 at the bottom of the gate trench 902 of the GaN SBR 990, and laterally isolated from the adjacent first gate electrode 915 and epitaxial layer by an inter polysilicon oxide (IPO) 936 and a second gate oxide (GOX2) 929 on the sidewall of the gate trench 902 of the GaN SBR 990. The thickness of the second gate oxide 929 is thinner than the thicknesses of the first gate oxide 919 and the second insulating layer 926, and the sidewall of the second gate trench is opposite to the sidewall of the first gate trench. In body region 914, a channel region 971 of the GaN MOSHEMT is formed along the first sidewall of the gate trench 902, serving as the first channel region. In body region 924, a channel region 972 of the GaN SBR is formed along the second sidewall of the gate trench 902, serving as the second channel region, wherein the second channel region 972 has a shorter channel length than the first channel region 971. In GaNSBR 990, an N-type short-channel implantation region 947 (as shown in the icon Nsci) is formed along the second sidewall of the gate trench 902 and surrounds the second gate electrode 925, and the N-type short-channel implantation region 947 has a higher doping concentration than the bottom epitaxial layer 913, and the second gate electrode 925 is short-circuited to the source metal 912. In the bottom epitaxial layer 913, a pair of first P-type shielding regions 918 (as shown in the figure, PS1) have a second conductivity type and are horizontally separated by an N-type junction field-effect transistor region 917 (as shown in the figure, JFET), wherein the doping concentration of the N-type junction field-effect transistor 917 is higher than that of the bottom epitaxial layer 913. Each of the first P-type shielding regions 918 surrounds the bottom region of the source contact trench 904 and is connected to the p+ type body contact region 910 and a metal contact plug 907 filled in the source contact trench 904. The metal contact plug 907 is connected to the heterojunction junction 943 and the p+ type body contact region 910 by a source metal 912. In addition, an intermediate dielectric layer 909 is stacked above the epitaxial layer, and the source metal 912 is disposed above the intermediate dielectric layer 909.

[0125] Please refer to Figure 9B The invention shown in another preferred embodiment employs a novel improved component structure. The gallium nitride component of this embodiment is... Figure 9AThe structure of the illustrated embodiment is similar, except that it further includes an n+ type source region 911' disposed on the top of the top epitaxial layer 933', connected to the gate trench 902' and the source contact trench 904', to reduce the on-resistance. The n+ type source region 911' is formed by a highly doped N-type nitride semiconductor layer or by silicon ion implantation in the top epitaxial layer 933'.

[0126] Please refer to Figure 10A The preferred embodiment shown is a top view of a GaN power device with a strip-shaped cell layout and an asymmetrical gate trench structure. In each cell, a strip-shaped gate trench 1002 surrounds a second P-type shielding region (PS2) 1058, and a trench-shaped source contact plug 1007 is disposed between adjacent gate trenches 1002. Furthermore, the second P-type shielding region 1058 is grounded to the source metal 1012 via a grounded P-type region (as shown in the icon GP) and the trench-shaped source contact plug 1007, while the trench-shaped source contact plug 1007 is surrounded by a first P-type shielding region 1018 (PS1). According to the present invention, a first channel region 1071 of the MOSFET is formed along a first sidewall of a gate trench 1002 having a first gate oxide layer GOX1, and a second channel region 1072 of the SBR is formed along a second sidewall of a gate trench 1002 having a second gate oxide layer GOX2, and is formed between two grounded P-type regions, wherein the first gate oxide layer GOX1 has a thicker thickness than the second gate oxide layer GOX2. Two gate electrodes are formed in the gate trench 1002, wherein the first gate electrode is shorted to a gate metal rail 1052 through a first gate contact plug 1042 of the GaNMOSHEMT (as shown in Figure G1), and the second gate electrode is shorted to the source metal 1012 through a second gate contact 1032 of the GaN SBR (as shown in Figure G2).

[0127] Please refer to Figure 10B This figure shows another top view of a GaN power device with a strip-shaped cell layout and an asymmetrical gate trench structure. The structure of the GaN power device in this embodiment is similar to that of the embodiment shown in Figure 10A, except that the ground P-type region GP and the SBR region 1090' are alternately formed along the second sidewall of the gate trench 1002' in this embodiment.

[0128] Please refer to Figure 10C It is a display Figure 10A A cross-sectional view along A1-A1' is shown in the preferred embodiment, where a new improved component structure is employed. The structure of the GaN component in this embodiment is similar to... Figure 9A The structures of the embodiments shown are similar, the difference being that... Figure 9AThe junction field-effect transistor (JFET) region is omitted in this embodiment, and the gate trench in this embodiment has a stepped gate trench structure, which includes a first type gate trench 1002'' and a second type gate trench 1003'', wherein the first type gate trench 1002'' is located above the second type gate trench 1003'' and has a wider gate width than the second type gate trench 1003'', and a first insulating layer 1016'' is filled in the second type gate trench 1003''. The GaN component shown in Figure 10C also includes a second P-type shielding region 1058'' (PS2) with a second conductivity type to reduce the electric field of the gate oxide layer at the bottom and sidewalls of the second type gate trench 1003'', wherein the second type gate trench 1003'' is filled in the first insulating layer 1016''. The second P-type shielding region 1058'' also includes two sub-regions, which include a top second P-type shielding region 1059'' (as shown in the figure PS2t) and a bottom second P-type shielding region 1060'' (as shown in the figure PS2b), wherein the bottom second P-type shielding region 1060'' is located below the top second P-type shielding region 1059'' and has a lower doping concentration than the top second P-type shielding region 1059''.

[0129] Please refer to Figure 10D It is a display Figure 10A A cross-sectional view along B1-B1' is shown in the preferred embodiment, where a new improved component structure is employed. The structure of the GaN component in this embodiment is similar to... Figure 10C The structures of the embodiments shown are similar, except that the N-type short channel injection region (as shown in the figure Nsci) is omitted, and this embodiment further includes a grounded P region 1029''' (as shown in the figure GP), which is formed along the second portion of the second sidewall of the first type gate trench 1002''', and grounds the second P-type shielding region 1058''' and the source metal 1012''' through the body region 1024''' and the metal contact plug 1007''', so as to reduce the electric field on the gate oxide layer.

[0130] Please refer to Figure 10E , it is Figure 10AThe preferred embodiment shows a cross-sectional view of the gate electrode contact region of the GaN SBR along section C1-C1'. In this embodiment, a second gate electrode 1025'''' (as shown in G2) is disposed on the upper portion of each first-type gate trench 1002'''', and the second gate electrode 1025'''' is separated from the N-type epitaxial layer by a second gate oxide layer 1029'''' (GOX2) formed along the trench sidewall and a second insulating layer 1026'''' at the bottom of the gate trench. The second gate oxide layer 1029'''' has a thinner thickness than the second insulating layer 1026''''. In addition, the second gate electrode 1025'''' is connected to the source metal 1012'''' via a trench-shaped metal contact plug 1032''''.

[0131] Please refer to Figure 10F , it is Figure 10A The preferred embodiment shows a cross-sectional view of the gate electrode contact region of the GaN MOSHEMT along section D1-D1'. In this embodiment, a first gate electrode 1015'''' (as shown in the figure G1) is disposed on the upper portion of each first type gate trench 1002''''', and the first gate electrode 1015''''' is separated from the N-type epitaxial layer by a first gate oxide layer 1019''''' (GOX1) formed along the trench sidewall and a first insulating layer 1016''''' at the bottom of the gate trench. The first gate oxide layer 1019'''' has a thinner thickness than the first insulating layer 1016''''. In addition, the first gate electrode 1015''''' is connected to the gate metal rail 1052''''' via a trench-shaped metal contact plug 1042'''''.

[0132] Please refer to Figure 10G It is a display Figure 10A The preferred embodiment is a cross-sectional view along A1-A1', wherein this embodiment employs a new improved component structure. The structure of the GaN component in this embodiment is similar to that of the embodiment shown in Figure 10C, except that this embodiment further includes an n+ type source region 1011'''''', formed on top of the top epitaxial layer 1033'''''', connected to the gate trench 1002'''''' and the source contact trench 1004'''''', to reduce on-resistance. The n+ type source region 1011'''''' is formed by a highly doped N-type nitride semiconductor layer or by silicon ion implantation in the top epitaxial layer 1033''''''.

[0133] Please refer to Figure 11A As shown Figure 10AAnother preferred embodiment is shown in the cross-sectional view along A1-A1', wherein this embodiment employs a novel improved component structure. The structure of the GaN component in this embodiment is similar to... Figure 10C The structures of the embodiments shown are similar, differing only in the use of different substrates and additional buffer layers. In this embodiment, the GaN component is formed on a P+ type GaN substrate 1101, and an N-type GaN buffer layer 1122 (as shown in the figure, Nb) is sandwiched between the P+ type GaN substrate 1101 and the bottom epitaxial layer 1113, and the resistance value Rb of the buffer layer 1122 is less than the resistance value R of the bottom epitaxial layer 1113.

[0134] Please refer to Figure 11B As shown Figure 10A Another preferred embodiment is shown in the cross-sectional view along A1-A1', wherein this embodiment employs a novel improved component structure. The structure of the GaN component in this embodiment is similar to... Figure 11A The structure of the illustrated embodiment is similar, except that it further includes multiple highly doped N+ type GaN regions 1162' in the P+ type substrate 1101' to form multiple alternating P+ and N+ regions.

[0135] Please refer to Figure 12A The preferred embodiment shown is a top view of another GaN power device with a strip-shaped unit layout and an asymmetrical gate trench structure. Trench-shaped source metal contact plugs 1207 are disposed between adjacent gate trenches 1202, and a second P-type body region 1224 (p2) grounds the source metal 1212 via the trench-shaped source metal contact plugs 1207. According to the invention, the channel region 1271 of the MOSHEMT is formed along the first sidewall of the gate trench 1202, and a first gate oxide layer (GOX1) and two electrodes, including a gate electrode and a shielding gate electrode, are formed in the gate trench 1202. The gate electrode serves as the first gate electrode and is short-circuited to the gate metal rail 1252 via a first gate metal contact plug 1242 (as shown in Figure G); the shielding gate electrode serves as the second gate electrode and is short-circuited to the source metal 1212 via a shielding gate metal contact plug 1232 (as shown in Figure SG).

[0136] Please refer to Figure 12B As shown Figure 12A Another preferred embodiment is shown in the cross-sectional view along A2-A2', where this embodiment employs a novel improved component structure. The structure of the GaN component in this embodiment is similar to... Figure 4The structures of the illustrated embodiments are similar, except that the GaN SBR 1290' in this embodiment further includes a short channel injection region 1247' (as shown in the figure Nsci), formed along a portion of the bottom region of the gate trench 1202' and located below the shielded gate electrode 1235'; and a second p-type body region 1224' (as shown in the figure p2) and a first source region 1221' (as shown in the figure n+1) surrounding the second sidewall 1202'-S2 of the gate trench 1202' to be formed with a portion of the bottom region of the gate trench 1202', wherein this portion of the bottom region is adjacent to the second sidewall 1202'-S2, and the second sidewall 1202'-S2 is opposite to the first sidewall 1202'-S1. In the body region 1224', a second channel region 1272' is formed along the bottom region of the gate trench 1202', wherein the second channel region 1272' has a shorter channel length than the first channel region 1271'.

[0137] Please refer to Figure 12C , it is Figure 12A Another preferred embodiment along B2-B2' shows a cross-sectional view of the contact region of the shielded gate electrode, wherein this embodiment employs a novel improved component structure. The structure of the GaN power component in this embodiment is similar to that of the embodiment shown in Figure 12B, the difference being that different gate structures exist in the gate trenches 1202''. In this embodiment, shielded gate electrodes 1235'' (as shown in Figure SG) are formed in each gate trench 1202'' and are vertically isolated from the N-type epitaxial layer by a second gate oxide layer 1229'' (GOX2) located at the bottom of the gate trench, and horizontally isolated from the epitaxial layer by a third gate oxide layer 1239'' (GOX3) located on the sidewall of the gate trench, wherein the second gate oxide layer 1229'' has a thinner thickness than the third gate oxide layer 1239''. Furthermore, the shielded gate electrodes 1235'' are connected to the source metal 1212'' via shielded gate contacts 1232''.

[0138] Please refer to Figure 12D As shown Figure 12A Another preferred embodiment is shown in the cross-sectional view along A2-A2', where this embodiment employs a novel improved component structure. The structure of the GaN component in this embodiment is similar to... Figure 12AThe structures of the embodiments shown are similar, except that this embodiment further includes a second n+ type source region 1231''' (as shown in n+2), which is disposed on top of the top epitaxial layer 1233''' and connected to the first source region 1221''' (as shown in n+1) to reduce the on-resistance. The second n+ type source region 1231''' is formed by a nitride semiconductor layer doped with a high concentration of the first conductivity type or by silicon ion implantation on the top epitaxial layer 1233'''.

[0139] While the present invention has been described with reference to preferred embodiments, it should be understood that the above description is not intended to limit the invention. Those skilled in the art will undoubtedly have many ideas or modifications after reading the above description. Therefore, the appended claims should be interpreted as encompassing all ideas and modifications within the spirit of the invention.

Claims

1. A nitride semiconductor component, characterized in that, include: At least three epitaxial layers, including a top epitaxial layer, an intermediate epitaxial layer and a bottom epitaxial layer, each having a first conductivity type, and grown on a substrate; The bandgap of the top epitaxial layer is different from that of the intermediate epitaxial layer having the first conductivity type; At least one heterojunction surface is formed at a contact surface between the top epitaxial layer and the middle epitaxial layer, thereby forming a two-dimensional electron gas and allowing current to flow. An integral region having a second conductivity type is formed on a top of the bottom epitaxial layer and is connected to an integral contact region having the second conductivity type; A gate trench extends through the top epitaxial layer, the middle epitaxial layer, and the body region, and terminates at the bottom epitaxial layer; A source contact trench extends through the top epitaxial layer, the middle epitaxial layer, and the body contact area, and terminates at the bottom epitaxial layer. A gate electrode is disposed in the gate trench and is horizontally isolated from the at least three epitaxial layers by a gate oxide layer located on the sidewall of the gate trench. At least one pair of first P-type shielding regions, having the second conductivity type, are formed in the bottom epitaxial layer having the first conductivity type, and the pair of first P-type shielding regions are horizontally separated by a junction field-effect transistor region having the first conductivity type, the junction field-effect transistor region having a higher doping concentration than the bottom epitaxial layer, wherein each of the pair of first P-type shielding regions surrounds a bottom region of the source contact trench and is connected to the body contact region; as well as A metal contact plug is inserted into the source contact trench, and a source metal connects the heterojunction surface to the body contact area.

2. The nitride semiconductor device of claim 1, wherein the gate electrode is surrounded by a first insulating layer located in a bottom region of the gate trench, and the first insulating layer has a thickness greater than that of the gate oxide layer.

3. The nitride semiconductor device of claim 1, wherein the gate oxide layer is an atomically deposited silicon dioxide layer, aluminum oxide layer or hafnium dioxide layer, and an intermediate layer of aluminum nitride or unintentionally doped gallium nitride is filled on the sidewall of the gate trench to improve channel mobility.

4. The nitride semiconductor device according to claim 1, wherein the top epitaxial layer and the intermediate epitaxial layer are GaN / Al X Ga Y N layer or Al X Ga Y N / GaN layer, where when X = 1, Y = 1, or when 0 < X < 1, Y = 1 - X.

5. The nitride semiconductor component according to claim 1, further comprising three epitaxial layers Al X Ga Y N / GaN / Al X GaYN is disposed above the body region, and two heterojunction interfaces are formed in the three epitaxial layers Al X Ga Y N / GaN / Al X GaYN above the body region, wherein when X = 1, Y = 1, or when 0 < X < 1, Y = 1 - X.

6. The nitride semiconductor assembly of claim 1 further includes a source region having the first conductivity type, disposed on a top of the top epitaxial layer, and connected to the gate trench and the metal contact plug to reduce on-resistance, wherein the source region is formed by a heavily doped nitride semiconductor layer having the first conductivity type or by silicon ions implanted in the top epitaxial layer.

7. The nitride semiconductor device of claim 1, wherein the at least one pair of first P-type shielding regions includes a pair of top first P-type shielding regions separated by a top first junction field-effect transistor region; and a pair of bottom first P-type shielding regions separated by a bottom first junction field-effect transistor region, wherein each of the top first P-type shielding regions surrounds the bottom region of the source contact trench, and the bottom first P-type shielding region is located below the top first P-type shielding region; a doping concentration of the bottom first P-type shielding region is higher than a doping concentration of the top first P-type shielding region; a doping concentration of the bottom first junction field-effect transistor region is higher than a doping concentration of the top first junction field-effect transistor region; and a width of the bottom first junction field-effect transistor region is narrower than a width of the top first junction field-effect transistor region.

8. The nitride semiconductor device of claim 1 further includes a shielded gate electrode disposed within the gate trench and below the gate electrode.

9. The nitride semiconductor device of claim 1, further comprising a superjunction structure having a P-type pillar region of the second conductivity type disposed on a buffer layer having the first conductivity type, the buffer layer having a resistance value Rb and sandwiched between the substrate and the bottom epitaxial layer, the P-type pillar region being connected to the body contact region.

10. The nitride semiconductor device of claim 9, wherein the substrate has the first conductivity type, and the epitaxial layer comprises a single epitaxial layer having a uniform doping concentration and a resistance value R, wherein the resistance value R < the resistance value Rb.

11. The nitride semiconductor assembly of claim 10, further comprising at least two sidewall P-type shielding regions having the second conductivity type, adjacent to each other, adjacent to the P-type pillar region and spaced apart from the body region, wherein the sidewall P-type shielding regions have a higher doping concentration than the P-type pillar region, and the at least two sidewall P-type shielding regions are separated by a first junction field-effect transistor region having the first conductivity type, the first junction field-effect transistor region having a higher doping concentration than the bottom epitaxial layer.

12. The nitride semiconductor device of claim 1, further comprising a buffer layer having the first conductivity type, disposed between the bottom epitaxial layer and the substrate, and having a resistance value Rb, wherein the bottom epitaxial layer has a resistance value R, and the resistance value R > the resistance value Rb; the substrate has a second conductivity type, or includes a plurality of highly doped regions having the first conductivity type and a plurality of highly doped regions having the second conductivity type, to form a plurality of alternating P+ regions and N+ regions on the substrate.

13. The nitride semiconductor assembly of claim 1 further includes an L-shaped P-type shielding region having the second conductivity type, disposed below the gate trench and next to one side wall of the gate trench, and connected to a lower surface of the body region.

14. The nitride semiconductor device of claim 1, wherein the gate trench has at least one stepped trench structure, the at least one stepped trench structure including a first type gate trench and a second type gate trench, the first type gate trench being disposed above the second type gate trench; the first type gate trench having a trench width wider than the second type gate trench. The gate electrode is disposed in the first type of gate trench and is surrounded by a first insulating layer located in a bottom region of the first type of gate trench and a gate oxide layer located on the sidewall of the first type of gate trench, wherein the first insulating layer has a thickness greater than the gate oxide layer. as well as A second P-type shielding region having the second conductivity type and disposed around a bottom and sidewall of the second type gate trench, wherein the first insulating layer is filled into the second type gate trench; The second P-type shielding region further includes at least two sub-regions, each sub-region comprising a top second P-type shielding region and a bottom second P-type shielding region, wherein the bottom second P-type shielding region is located below the top second P-type shielding region and has a lower doping concentration than the top second P-type shielding region; and At least one grounded P-type region, having the second conductivity type, is disposed around one sidewall of the first type gate trench and connects the body region and the second P-type shielding region.

15. An integrated circuit, characterized in that, include: A gallium nitride gold oxide half-cell high electron mobility transistor and a gallium nitride super barrier rectifier are integrated in each unit; At least three epitaxial layers, including a top epitaxial layer, an intermediate epitaxial layer and a bottom epitaxial layer, each having a first conductivity type, and grown on a substrate; The bandgap of the top epitaxial layer is different from that of the intermediate epitaxial layer having the first conductivity type; At least one heterojunction surface is formed at a contact surface between the top epitaxial layer and the middle epitaxial layer, thereby forming a two-dimensional electron gas and allowing current to flow. The first body region of the gallium nitride gold-oxide half-cell high electron mobility transistor and the second body region of the gallium nitride super barrier rectifier each have a second conductivity type and are formed on the top of the bottom epitaxial layer; a gate trench penetrates the top epitaxial layer, the middle epitaxial layer, the first body region and the second body region, and terminates at the bottom epitaxial layer. A source contact trench extends through the top epitaxial layer, the middle epitaxial layer, and a plurality of body contact regions having the second conductivity type, and terminates at the bottom epitaxial layer. A metal contact plug is inserted into the source contact trench, and a source metal connects the heterojunction surface to the plurality of body contact areas. The gallium nitride gold oxide half-arm high electron mobility transistor further includes: A first gate electrode is disposed in the gate trench and is horizontally isolated from the at least three epitaxial layers by a first gate oxide layer located on a first sidewall of the gate trench; The first gate electrode is surrounded by a first insulating layer located at the bottom of the gate trench, wherein the first insulating layer has a thickness that is thicker than the first gate oxide layer. A first channel region is formed in the first body region and disposed along the first sidewall of the gate trench; This gallium nitride super barrier rectifier further includes: A second gate electrode is disposed in the gate trench, parallel to the first gate electrode, and isolated from the first gate electrode by an intermediate polysilicon inter-oxide layer; The second gate electrode is laterally isolated by a second gate oxide layer and the at least three epitaxial layers, wherein the second gate oxide layer is located on a second sidewall of the gate trench and has an oxide layer thickness that is thinner than that of the first gate oxide layer; The second gate electrode is surrounded by a second insulating layer located in a bottom region of the gate trench, wherein the second insulating layer has a thickness greater than the second gate oxide layer, and the first insulating layer has a thickness greater than the second insulating layer. A second channel region is formed in the second body region along the second sidewall of the gate trench, relative to the first sidewall, wherein the second channel region has a channel length shorter than the first channel region; A short-channel injection region having the first conductivity type is formed along the second sidewall and surrounding the second gate electrode; The second gate electrode is short-circuited to the source metal through a gate contact of the gallium nitride super barrier rectifier; A current spreading layer, having the first conductivity type, is formed on top of the bottom epitaxial layer and below the first body region and the second body region, wherein the current spreading layer has a higher doping concentration than the bottom epitaxial layer; and A first P-type shielding region, having the second conductivity type, surrounds a bottom region of the source contact trench and is connected to the plurality of body contact regions.

16. The integrated circuit of claim 15, wherein the gate trench has at least one stepped trench structure, the at least one stepped trench structure including a first type gate trench and a second type gate trench, the first type gate trench being located above the second type gate trench; the first type gate trench having a trench width wider than the second type gate trench. The first gate electrode is disposed in the first type gate trench and is surrounded by the first insulating layer located at a bottom of the first type gate trench and the first gate oxide layer located on the first sidewall of the first type gate trench; the second gate electrode is disposed in the first type gate trench and is surrounded by the second insulating layer located at a bottom region of the first type gate trench and the second gate oxide layer located on the second sidewall of the first type gate trench. as well as A second P-type shielding region, having the second conductivity type, surrounds a bottom and sidewall of the second type gate trench, wherein the first insulating layer is filled into the second type gate trench; The second P-type shielding region includes at least two sub-regions, each sub-region comprising a top second P-type shielding region and a bottom second P-type shielding region, wherein the bottom second P-type shielding region is located below the top second P-type shielding region and has a lower doping concentration than the top second P-type shielding region; and At least one grounded P-type region, having the second conductivity type, surrounds a portion of the sidewall of the first type gate trench and connects the body region to the second P-type shielding region.

17. The integrated circuit of claim 15, further comprising a first source region having the first conductivity type, disposed on a top of the top epitaxial layer, and the first source region being connected to the gate trench and the source contact trench to reduce on-resistance, wherein the first source region is formed by a heavily doped nitride semiconductor layer having the first conductivity type or by silicon ions implanted in the top epitaxial layer.

18. The integrated circuit of claim 16, further comprising a buffer layer having the first conductivity type, disposed between the bottom epitaxial layer and the substrate, and having a resistance value Rb, wherein the bottom epitaxial layer has a resistance value R, and the resistance value R > the resistance value Rb; the substrate has a second conductivity type, or includes a plurality of highly doped regions having the first conductivity type and a plurality of highly doped regions having the second conductivity type, to form a plurality of alternating P+ regions and N+ regions on the substrate.

19. An integrated circuit, characterized in that, include: A gallium nitride gold oxide half-cell high electron mobility transistor and a gallium nitride super barrier rectifier are disposed in a gate trench of each cell; At least three epitaxial layers, including a top epitaxial layer, an intermediate epitaxial layer and a bottom epitaxial layer, each having a first conductivity type, and grown on a substrate; The bandgap of the top epitaxial layer is different from that of the intermediate epitaxial layer having the first conductivity type; At least one heterojunction surface is formed at a contact surface between the top epitaxial layer and the middle epitaxial layer, thereby forming a two-dimensional electron gas and allowing current to flow. A first body region of the gallium nitride gold oxide half-cell high electron mobility transistor has a second conductivity type and is formed on the top of the bottom epitaxial layer; A gate trench extends through the top epitaxial layer, the middle epitaxial layer, the first body region, and terminates at the bottom epitaxial layer; A source contact trench extends through the top epitaxial layer, the middle epitaxial layer, and multiple body contact regions, and terminates at the bottom epitaxial layer. A metal contact plug is filled in the source contact trench, and a source metal connects the heterojunction interface to the plurality of body contact areas, wherein the plurality of body contact areas have the second conductivity type. A second body region of the gallium nitride super barrier rectifier surrounds a second sidewall of the gate trench, and a portion of the bottom region of the gate trench is adjacent to the second sidewall, wherein the second sidewall is opposite to the first sidewall; A current spreading layer having the first conductivity type is formed on top of the bottom epitaxial layer and located below the first body region and the second body region, wherein the current spreading layer has a higher doping concentration than the bottom epitaxial layer; A first P-type shielding region, having the second conductivity type, surrounds the bottom of the source contact trench; A gate electrode is disposed at the top of the gate trench; A shielded gate electrode is disposed below the gate electrode and is isolated from the gate electrode by an intermediate polysilicon inter-oxide layer; The gate electrode architecture is a first gate electrode, which is laterally isolated from the epitaxial layer by a first gate oxide layer on a first sidewall of the gate trench in the gallium nitride gold oxide half-cell high electron mobility transistor. The shielded gate electrode architecture is a second gate electrode, which is vertically isolated from the epitaxial layer by a second gate oxide layer in the bottom region of the gate trench in the gallium nitride super barrier rectifier. The second gate oxide layer has a thickness thinner than the first gate oxide layer. The gallium nitride gold-oxide half-length high electron mobility transistor further includes: A first channel region of the gallium nitride gold oxide half-cell high electron mobility transistor is formed in the first body region and disposed along the first sidewall of the gate trench; This gallium nitride super barrier rectifier further includes: A first source region surrounds the second sidewall of the gate trench, and a portion of the bottom region of the gate trench is adjacent to the second sidewall, wherein the second sidewall is opposite to the first sidewall; A second channel region is formed in the second body region along the bottom region of the gate trench, wherein the second channel region has a shorter channel length than the first channel region; and The second gate electrode is short-circuited to the source metal through a shielded gate contact of the gallium nitride super barrier rectifier.

20. The integrated circuit of claim 19, further comprising a second source region having the first conductivity type, disposed on a top of the top epitaxial layer and connected to the first source region to reduce on-resistance, wherein the source region is formed by a heavily doped nitride semiconductor layer having the first conductivity type or by silicon ions implanted in the top epitaxial layer.

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