A P-type gallium nitride gate transistor based on self-stopping etching and its fabrication method

Abstract

This invention discloses a P-type gallium nitride gate transistor based on self-stopping etching and its fabrication method, belonging to the semiconductor field. It includes a silicon carbide substrate, an aluminum nitride buffer layer, a gallium nitride channel layer, an aluminum gallium nitride barrier layer, and an aluminum nitride stop layer, stacked sequentially. The upper part of the aluminum nitride stop layer contains a P-type gallium nitride, a passivation layer, a source, and a drain. The passivation layer surrounds the P-type gallium nitride, and the lower surfaces of both the P-type gallium nitride and the passivation layer are in contact with the upper surface of the aluminum nitride stop layer. A gate is located on the upper part of the P-type gallium nitride, with the lower surface of the gate in contact with the upper surface of the P-type gallium nitride. The gate penetrates the passivation layer. By introducing a thin aluminum nitride layer as a buffer layer on the silicon carbide insulating substrate and introducing an aluminum nitride stop layer between the aluminum gallium nitride barrier layer and the P-type gallium nitride to stop etching, characteristic degradation is suppressed, thereby improving the threshold voltage of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a P-type gallium nitride gate transistor based on self-stopping etching and its fabrication method. Background Technology

[0002] Gallium nitride (GaN) high electron mobility transistors (HEMs) have become key devices in high-frequency, high-power power electronics due to their superior characteristics such as high breakdown electric field, high electron mobility, low on-resistance, and fast switching speed. In enhancement-mode GaN HEMs, the P-type gate (e.g., P-type GaN) structure is the mainstream solution for achieving normally-off characteristics and has been successfully commercialized.

[0003] In traditional P-type gallium nitride gate transistors, such as Figure 1 As shown, the substrate is typically made of silicon or sapphire, on which gallium nitride (GaN), an aluminum gallium nitride (AlGaN) heterojunction, and a P-type GaN layer are sequentially heteroepitaxially formed. During fabrication, the P-type GaN layer is first selectively etched to form the gate structure. Then, a silicon dioxide layer approximately 50 nanometers thick is deposited as a passivation layer using plasma-enhanced chemical vapor deposition (PECVD). Finally, metal is deposited through openings in the passivation layer to fabricate the gate, source, and drain electrodes. This P-type GaN gate transistor structure has the following drawbacks: First, the inductively coupled plasma etching process has low selectivity for both P-type GaN and AlGaN. Etching the P-type GaN can damage the AlGaN barrier layer or cause over-etching, introducing interface states or reducing the two-dimensional electron gas concentration, thus affecting the device's output current. Second, the buffer layer, typically made of thick GaN to reduce lattice mismatch, leads to poor heat dissipation, increased thermal resistance, and current collapse, affecting device performance and potentially even causing device burnout. Finally, vertical leakage current will occur in the device when it is operating at high voltage, which will affect the static and dynamic characteristics of the device. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a P-type gallium nitride gate transistor based on self-stopping etching and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a P-type gallium nitride gate transistor based on self-stopping etching, comprising a silicon carbide substrate, an aluminum nitride buffer layer, a gallium nitride channel layer, an aluminum gallium nitride barrier layer, and an aluminum nitride stop layer stacked sequentially. The upper part of the aluminum nitride stop layer is provided with P-type gallium nitride, passivation layer, source and drain. The source and drain are located on both sides of the passivation layer and their lower surfaces are in contact with the upper surface of the aluminum nitride stop layer. The passivation layer surrounds the P-type gallium nitride, and the lower surfaces of the P-type gallium nitride and the passivation layer are in contact with the upper surface of the aluminum nitride stop layer. The upper part of the P-type gallium nitride has a gate, the lower surface of the gate is in contact with the upper surface of the P-type gallium nitride, and the gate is disposed through the passivation layer.

[0005] In one embodiment of the present invention, the aluminum nitride buffer layer is an aluminum nitride thin film grown by metal-organic chemical vapor deposition.

[0006] In one embodiment of the present invention, the thickness of the aluminum nitride buffer layer is 195nm~205nm.

[0007] In one embodiment of the present invention, the gallium nitride channel layer is in-situ undoped gallium nitride with a thickness of 195nm~205nm.

[0008] In one embodiment of the present invention, the thickness of the aluminum nitride stop layer is 1 nm to 5 nm.

[0009] In one embodiment of the present invention, the passivation layer is composed of one or more of air, silicon dioxide, aluminum oxide, and silicon nitride.

[0010] Secondly, the present invention provides a method for fabricating a P-type gallium nitride gate transistor based on self-stopping etching, comprising the P-type gallium nitride gate transistor based on self-stopping etching as described above, the method comprising: Step 1: Using metal-organic chemical vapor deposition, an aluminum nitride buffer layer, a gallium nitride channel layer, an aluminum gallium nitride barrier layer, an aluminum nitride stop layer, and a p-type gallium nitride are sequentially epitaxially grown on a silicon carbide substrate to obtain an epitaxial wafer. The epitaxial wafer is then placed in acetone, ethanol, and deionized water and sonicated for 5 minutes to remove surface impurities. Step 2: The pattern of the discrete device is determined by photolithography. The upper surface of the epitaxial wafer is etched using inductively coupled plasma etching process with chlorine and boron trichloride as etching gases. The etching stops at the aluminum nitride buffer layer. Step 3: The pattern of the P-type gallium nitride gate of the device is determined by photolithography. Using inductively coupled plasma etching process, chlorine and boron trichloride or sulfur hexafluoride and boron trichloride are used as etching gases to etch the upper surface of the epitaxial wafer. The etched part of the P-type gallium nitride is used as the gate, and the etching stops at the aluminum nitride stop layer. Step 4: Fabricate source and drain metal electrodes on the epitaxial wafer; Step 5: Fabricate the gate metal electrode on the epitaxial wafer; Step 6: Prepare a passivation layer on the upper surface of the epitaxial wafer; Step 7: Using metal interconnects, interconnect the source metal electrode, drain metal electrode, and gate metal with the outside to obtain a P-type gallium nitride gate transistor.

[0011] In one embodiment of the present invention, step four specifically includes: Photolithography is performed on the upper surface of the epitaxial wafer to obtain the source and drain forming regions. Using electron beam evaporation, source metal electrodes and drain metal electrodes are deposited in the forming regions of the source and drain, respectively. The metal types of the source metal electrodes and drain metal electrodes are stacks of titanium, aluminum, nickel and gold, with thicknesses of 20nm, 150nm, 50nm and 80nm, respectively. After deposition, the epitaxial wafer is immersed in acetone to remove excess metal, and then subjected to rapid thermal annealing at 810°C for 30 seconds to complete the preparation of the source and drain metal electrodes.

[0012] In one embodiment of the present invention, step five specifically includes: Photolithography is performed on the upper surface of the epitaxial wafer to obtain the gate forming region. The gate metal electrode is deposited in the gate forming region using an electron beam evaporation process. The gate metal electrode is a stack of nickel and gold, and the thickness of both nickel and gold is 20 nm. After deposition, the epitaxial wafer is immersed in acetone to remove excess metal, and then subjected to rapid thermal annealing at 550°C for 5 minutes to complete the fabrication of the gate metal electrode.

[0013] In one embodiment of the present invention, step six specifically includes: A passivation layer with a thickness of 50 nm was prepared on the upper surface of the epitaxial wafer using atomic layer deposition (ALD). The passivation layer on the source metal electrode, drain metal electrode and gate metal electrode is removed by reactive ion etching process.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: First, this application employs a novel epitaxial structure with a silicon carbide substrate and an aluminum nitride buffer layer, reducing the device's thermal resistance and improving its heat dissipation capabilities, thus minimizing the impact on device performance. Second, the use of aluminum nitride as a back barrier enhances the channel's confinement of the two-dimensional electron gas, strengthening the device's gate control capability. Furthermore, the smaller lattice fit between aluminum nitride and gallium nitride avoids lattice mismatch issues during epitaxy, reducing leakage current, improving voltage withstand capability, and expanding the device's high-voltage application range. Additionally, the passivation layer prepared by atomic layer deposition exhibits high quality and density, reducing leakage current caused by interface states on the device surface. Moreover, the introduction of an aluminum nitride etch stop layer between the P-type gate layer and the aluminum gallium nitride barrier layer serves multiple functions, including interface optimization, leakage current suppression, and process protection.

[0015] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a transistor in the prior art; Figure 2 This is a schematic diagram of a P-type gallium nitride gate transistor in an embodiment of the present invention; Figure 3 This is a flowchart illustrating the fabrication process of a P-type gallium nitride gate transistor in an embodiment of the present invention; Figure 4 This is a schematic diagram of the fabrication method of the P-type gallium nitride gate transistor in an embodiment of the present invention. Detailed Implementation

[0017] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0018] Example 1: Please see Figure 2 and Figure 3 This invention provides a P-type gallium nitride gate transistor based on self-stopping etching, comprising a silicon carbide substrate, an aluminum nitride buffer layer, a gallium nitride channel layer, an aluminum gallium nitride barrier layer, and an aluminum nitride stop layer stacked sequentially. The aluminum nitride stop layer has a P-type gallium nitride, a passivation layer, a source, and a drain on its upper part. The source and drain are located on opposite sides of the passivation layer, and their lower surfaces are in contact with the upper surface of the aluminum nitride stop layer. The passivation layer surrounds the P-type gallium nitride, and the lower surfaces of the P-type gallium nitride and the passivation layer are in contact with the upper surface of the aluminum nitride stop layer. A gate is located on the upper part of the P-type gallium nitride, and the lower surface of the gate is in contact with the upper surface of the P-type gallium nitride, and the gate penetrates the passivation layer.

[0019] In some embodiments of this application, a novel epitaxial structure based on a silicon carbide substrate and an aluminum nitride buffer layer is proposed.

[0020] In some embodiments of this application, the layer structure is grown by metal-organic chemical vapor deposition to obtain a good epitaxial structure.

[0021] In some embodiments of this application, an atomic layer deposition method is used to prepare a passivation layer on the surface.

[0022] In some embodiments of this application, aluminum nitride is introduced as an etch stop layer.

[0023] In the above-described scheme of this application, firstly, a novel epitaxial structure with a silicon carbide substrate and an aluminum nitride buffer layer is adopted to reduce the thermal resistance of the device, improve its heat dissipation capacity, and thus reduce the impact on device performance. Secondly, aluminum nitride is used as a back barrier, which can increase the confinement effect of the channel on the two-dimensional electron gas and enhance the gate control capability of the device. Furthermore, the lattice fit between aluminum nitride and gallium nitride is small, which can avoid lattice fit problems generated during epitaxy, reduce leakage current, improve the voltage withstand capability, and expand the high-voltage application range of the device. In addition, the passivation layer prepared by atomic layer deposition has good quality and high density, which can reduce leakage current caused by interface states on the device surface. Moreover, the introduction of an aluminum nitride etch stop layer between the P-type gate layer and the aluminum gallium nitride barrier layer plays multiple roles in interface optimization, leakage current suppression, and process protection.

[0024] In some embodiments of this application, the aluminum nitride buffer layer is an aluminum nitride thin film grown using a metal-organic chemical vapor deposition (MOCVD) process. In this structure, the aluminum nitride thin film grown by MOCVD serves as a buffer layer located between the silicon carbide substrate and the gallium nitride channel layer. The lattice constant of this aluminum nitride thin film is between that of silicon carbide and gallium nitride, which can alleviate the lattice mismatch between the two and reduce the dislocation density in the epitaxial layer. Simultaneously, the thermal conductivity of aluminum nitride is higher than that of gallium nitride, which helps to dissipate the heat generated in the channel region through the silicon carbide substrate and suppress the self-heating effect. Furthermore, this thin film serves as a back barrier layer, forming a heterojunction with the gallium nitride channel layer, enhancing the quantum confinement of the two-dimensional electron gas, reducing electron leakage to the buffer layer, and lowering the off-state leakage current of the device.

[0025] In some embodiments of this application, the thickness of the aluminum nitride buffer layer is 195 nm to 205 nm. Using this structure, controlling the thickness of the aluminum nitride buffer layer within the range of 195 nm to 205 nm allows for a lower dislocation density and a smoother surface morphology during metal-organic chemical vapor deposition. This thickness range ensures the buffer layer is sufficient to prevent impurities in the silicon carbide substrate from diffusing upwards into the gallium nitride channel layer, thus preventing a decrease in the mobility of the two-dimensional electron gas in the channel. Simultaneously, this thickness avoids increased thermal resistance caused by an excessively thick buffer layer, allowing heat generated in the channel to be more efficiently dissipated through the silicon carbide substrate. Furthermore, the heterojunction stress between the aluminum nitride buffer layer and the upper gallium nitride channel layer at this thickness is controlled, which helps maintain the crystal quality of subsequent epitaxial layers and reduces through dislocations caused by lattice mismatch.

[0026] In some embodiments of this application, the gallium nitride (GaN) channel layer is in-situ undoped GaN with a thickness of 195 nm to 205 nm. This structure, with the GaN channel layer being in-situ undoped and its thickness controlled within the range of 195 nm to 205 nm, avoids the introduction of additional impurities, reduces the background carrier concentration in the channel, and minimizes the degradation effect of ionized impurity scattering on electron mobility. This thickness range allows the channel layer to accommodate the two-dimensional electron gas induced by the aluminum gallium nitride (AlGaN) barrier layer, while avoiding an excessively thick channel layer that would increase the device's on-resistance. At this thickness, the heterojunction interface stress between the channel layer and the underlying aluminum nitride buffer layer and the upper AlGaN barrier layer is controlled, maintaining band continuity at the heterojunction and ensuring the areal density and mobility of the two-dimensional electron gas.

[0027] In some embodiments of this application, the thickness of the aluminum nitride stop layer is 1 nm to 5 nm. With this structure, the aluminum nitride stop layer thickness is 1 nm to 5 nm. Aluminum nitride films within this thickness range exhibit higher etching resistance than p-type gallium nitride in inductively coupled plasma etching (ICP-PE), allowing the etching process to spontaneously terminate at the surface of this layer during p-type gallium nitride etching, preventing over-etching into the underlying aluminum gallium nitride barrier layer. This thickness is sufficient to block the physical bombardment and chemical damage of the aluminum gallium nitride barrier layer by the etching plasma, reducing the generation of dangling bonds and interface states on the barrier layer surface. Simultaneously, this thickness does not substantially weaken the ability of the aluminum gallium nitride barrier layer to induce a two-dimensional electron gas into the gallium nitride channel layer, ensuring the electron gas surface density in the channel. Furthermore, the lattice mismatch between this ultrathin stop layer and the upper and lower layers is small, preventing the introduction of additional stress mismatch dislocations at the epitaxial interface.

[0028] In some embodiments of this application, the passivation layer is composed of one or more of air, silicon dioxide, aluminum oxide, and silicon nitride. Using this structure, the passivation layer is composed of one or more of air, silicon dioxide, aluminum oxide, and silicon nitride. When air is used as the passivation layer, its low dielectric constant reduces the parasitic capacitance between the gate and the source / drain. When silicon dioxide, aluminum oxide, or silicon nitride is used as the passivation layer, it can cover the upper surface of the device, isolating moisture and mobile ions from the external environment and reducing leakage paths caused by surface states. The combination of multiple materials can form a multilayer passivation structure, utilizing the interfaces between different dielectric layers to block vertical leakage current paths, while simultaneously utilizing the density differences within each dielectric layer to reduce pinhole density and improve the coverage integrity of the passivation layer. The differences in dielectric constant and bandgap arrangement of different dielectric materials can also adjust the surface electric field distribution of the device, suppressing current collapse effects.

[0029] Example 2: Please see Figure 3 and Figure 4This invention provides a method for fabricating a P-type gallium nitride gate transistor based on self-stopping etching, including the P-type gallium nitride gate transistor based on self-stopping etching as mentioned in Embodiment 1 above, the method comprising: Step 1: Using metal-organic chemical vapor deposition, an aluminum nitride buffer layer, a gallium nitride channel layer, an aluminum gallium nitride barrier layer, an aluminum nitride stop layer, and a p-type gallium nitride are sequentially epitaxially grown on a silicon carbide substrate to obtain an epitaxial wafer. The epitaxial wafer is then placed in acetone, ethanol, and deionized water and sonicated for 5 minutes to remove surface impurities. Step 2: The pattern of the discrete device is determined by photolithography. The upper surface of the epitaxial wafer is etched using inductively coupled plasma etching process with chlorine and boron trichloride as etching gases. The etching stops at the aluminum nitride buffer layer. Step 3: The pattern of the P-type gallium nitride gate of the device is determined by photolithography. Using inductively coupled plasma etching process, chlorine and boron trichloride or sulfur hexafluoride and boron trichloride are used as etching gases to etch the upper surface of the epitaxial wafer. The etched part of the P-type gallium nitride is used as the gate, and the etching stops at the aluminum nitride stop layer. Step 4: Fabricate source and drain metal electrodes on the epitaxial wafer; Step 5: Fabricate the gate metal electrode on the epitaxial wafer; Step 6: Prepare a passivation layer on the upper surface of the epitaxial wafer; Step 7: Connect the source metal electrode, drain metal electrode, and gate metal electrode using metal interconnects to obtain a P-type gallium nitride gate transistor.

[0030] The beneficial effects of Embodiment 2 and its various implementations of the present invention can be found in the analysis of the beneficial effects of Embodiment 1 and its various implementations, and will not be repeated here.

[0031] In some embodiments of this application, the device manufacturing process is as follows: (1) On a silicon carbide substrate, each layer structure is epitaxially grown sequentially using a metal-organic chemical vapor deposition process, and surface impurities are removed by organic cleaning.

[0032] (2) The desired pattern is formed by photolithography, and a P-type gallium nitride gate is obtained by etching; (3) The required source and drain patterns are formed by photolithography, and ohmic contacts are achieved by metal deposition and annealing; (4) The required gate metal pattern is formed by photolithography, and the metal is deposited and annealed to select Schottky contact or ohmic contact; (5) Passivation layers are deposited by atomic layer deposition or plasma-enhanced chemical vapor deposition, and contact holes for gate, source and drain are opened by reactive ion etching to realize the electrical interconnection of the device.

[0033] In some embodiments of this application, step four specifically includes: Photolithography is performed on the upper surface of the epitaxial wafer to obtain the source and drain forming regions. Using electron beam evaporation, source metal electrodes and drain metal electrodes are deposited in the forming regions of the source and drain, respectively. The metal types of the source metal electrodes and drain metal electrodes are stacks of titanium, aluminum, nickel and gold, with thicknesses of 20nm, 150nm, 50nm and 80nm, respectively. After deposition, the epitaxial wafer is immersed in acetone to remove excess metal, and then subjected to rapid thermal annealing at 810°C for 30 seconds to complete the fabrication of the source and drain metal electrodes. Using this structure, the source and drain metal electrodes in step four are composed of four metals: titanium, aluminum, nickel, and gold, with thicknesses of 20 nm, 150 nm, 50 nm, and 80 nm, respectively. The titanium layer, as the bottom metal, contacts the aluminum nitride stop layer or the underlying epitaxial layer. During annealing, titanium reacts with the nitride at the interface, reducing the barrier height of the ohmic contact. The aluminum layer, as the intermediate main conductive layer, reduces the series resistance between the source and drain due to its low resistivity. The nickel layer, as a diffusion barrier layer, inhibits the interdiffusion between aluminum and gold, preventing alloying between metal layers during annealing that could increase contact resistance. The gold layer, as the surface metal, has strong oxidation resistance, maintaining a low-resistivity state on the electrode surface during subsequent processes. The rapid thermal annealing process is carried out at a temperature of 810°C for 30 seconds. This thermal budget enables the titanium-nitride interface to form a low-resistance ohmic contact, while avoiding excessively high temperatures or excessively long times that could cause the metal electrode edges to climb or agglomerate and degrade.

[0034] In some embodiments of this application, step five specifically includes: Photolithography is performed on the upper surface of the epitaxial wafer to obtain the gate forming region. The gate metal electrode is deposited in the gate forming region using an electron beam evaporation process. The gate metal electrode is a stack of nickel and gold, and the thickness of both nickel and gold is 20 nm. After deposition, the epitaxial wafer is immersed in acetone to remove excess metal, and then subjected to rapid thermal annealing at 550°C for 5 minutes to complete the fabrication of the gate metal electrode. Using this structure, the gate metal electrode in step five is a stack of nickel and gold, each 20 nm thick. During Schottky junction formation, nickel contacts p-type gallium nitride, and the barrier height determines the gate's turn-on voltage and reverse leakage current. Gold's high conductivity reduces resistance along the gate path, while its chemical inertness protects the underlying nickel layer from oxidation in subsequent processes. The 20 nm thickness of both metals facilitates uniform film coverage in electron beam evaporation and is compatible with photoresist stripping, avoiding excessive metal thickness that could hinder stripping. The rapid thermal annealing process at 550°C for 5 minutes ensures a stable ohmic contact between the nickel and p-type gallium nitride interfaces, while preventing excessively high temperatures from lowering the barrier height or causing interdiffusion between the metal and semiconductor, thus maintaining the gate's rectification characteristics.

[0035] In some embodiments of this application, step six specifically includes: A passivation layer with a thickness of 50 nm was prepared on the upper surface of the epitaxial wafer using atomic layer deposition (ALD). Reactive ion etching (RIE) is used to remove the passivation layers on the source, drain, and gate metal electrodes. With this structure, in step six, atomic layer deposition (ALD) is used to prepare a 50 nm thick silicon dioxide layer as a passivation layer on the upper surface of the epitaxial wafer. ALD is based on self-limiting surface chemical reactions, growing only a single atomic layer per deposition cycle. The resulting silicon dioxide film has a higher density than films prepared by plasma-enhanced chemical vapor deposition (PECVD), with lower pinhole density and reduced penetration paths for water vapor and mobile ions. This 50 nm thick silicon dioxide layer is sufficient to cover the steps and edges of the epitaxial wafer surface without affecting the subsequent filling of metal interconnects. Reactive ion etching (RIE) is then used to remove the passivation layers on the source, drain, and gate metal electrodes. This process utilizes the synergistic effect of physical bombardment and chemical reaction to obtain anisotropic etching morphology in the vertical direction, with steep opening edges and clean opening bottoms. This avoids lateral drilling caused by wet etching, ensuring complete exposure of the metal electrode surfaces and providing a low-contact-resistance interface for subsequent metal interconnects.

[0036] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0037] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0038] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0039] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0040] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A P-type gallium nitride gate transistor based on self-stopping etching, characterized in that, It includes a silicon carbide substrate, an aluminum nitride buffer layer, a gallium nitride channel layer, an aluminum gallium nitride barrier layer, and an aluminum nitride stop layer, which are stacked sequentially. The upper part of the aluminum nitride stop layer is provided with a P-type gallium nitride, a passivation layer, a source, and a drain. The source and the drain are located on both sides of the passivation layer, and their lower surfaces are in contact with the upper surface of the aluminum nitride stop layer. The passivation layer surrounds the P-type gallium nitride, and the lower surfaces of the P-type gallium nitride and the passivation layer are in contact with the upper surface of the aluminum nitride stop layer. The upper part of the P-type gallium nitride has a gate, the lower surface of the gate is in contact with the upper surface of the P-type gallium nitride, and the gate is disposed through the passivation layer.

2. The P-type gallium nitride gate transistor based on self-stopping etching according to claim 1, characterized in that, The aluminum nitride buffer layer is an aluminum nitride thin film grown using a metal-organic chemical vapor deposition process.

3. The P-type gallium nitride gate transistor based on self-stopping etching according to claim 2, characterized in that, The thickness of the aluminum nitride buffer layer is 195nm~205nm.

4. The P-type gallium nitride gate transistor based on self-stopping etching according to claim 1, characterized in that, The gallium nitride channel layer is in-situ undoped gallium nitride with a thickness of 195nm~205nm.

5. The P-type gallium nitride gate transistor based on self-stopping etching according to claim 1, characterized in that, The thickness of the aluminum nitride stop layer is 1 nm to 5 nm.

6. The P-type gallium nitride gate transistor based on self-stopping etching according to claim 1, characterized in that, The passivation layer is composed of one or more of air, silicon dioxide, aluminum oxide, and silicon nitride.

7. A method for fabricating a P-type gallium nitride gate transistor based on self-stopping etching, characterized in that, The method, comprising a P-type gallium nitride gate transistor based on self-stopping etching as described in any one of claims 1 to 6, includes: Step 1: Using metal-organic chemical vapor deposition, an aluminum nitride buffer layer, a gallium nitride channel layer, an aluminum gallium nitride barrier layer, an aluminum nitride stop layer, and a p-type gallium nitride are sequentially epitaxially grown on a silicon carbide substrate to obtain an epitaxial wafer. The epitaxial wafer is then sequentially immersed in acetone, ethanol, and deionized water and sonicated for 5 minutes to remove surface impurities. Step 2: The pattern of the discrete device is determined by photolithography. The upper surface of the epitaxial wafer is etched using inductively coupled plasma etching process with chlorine and boron trichloride as etching gases. The etching stops at the aluminum nitride buffer layer. Step 3: The pattern of the P-type gallium nitride gate of the device is determined by photolithography. Using inductively coupled plasma etching process, chlorine and boron trichloride or sulfur hexafluoride and boron trichloride are used as etching gases to etch the upper surface of the epitaxial wafer. The etched part of the P-type gallium nitride is used as the gate, and the etching stops at the aluminum nitride stop layer. Step 4: Fabricate source metal electrodes and drain metal electrodes on the epitaxial wafer; Step 5: Fabricate a gate metal electrode on the epitaxial wafer; Step 6: Prepare a passivation layer on the upper surface of the epitaxial wafer; Step 7: Using metal interconnects, interconnect the source metal electrode, drain metal electrode, and gate metal with the outside to obtain a P-type gallium nitride gate transistor.

8. The method for fabricating a P-type gallium nitride gate transistor based on self-stopping etching according to claim 7, characterized in that, Step four specifically includes: The upper surface of the epitaxial wafer is photolithographically etched to obtain the source and drain forming regions. Source metal electrodes and drain metal electrodes are deposited in the source and drain forming regions using electron beam evaporation. The source metal electrodes and drain metal electrodes are made of a stack of titanium, aluminum, nickel and gold, with thicknesses of 20 nm, 150 nm, 50 nm and 80 nm, respectively. After deposition, the epitaxial wafer is immersed in acetone to remove excess metal, and then subjected to rapid thermal annealing at 810°C for 30 seconds to complete the preparation of the source and drain metal electrodes.

9. The method for fabricating a P-type gallium nitride gate transistor based on self-stopping etching according to claim 7, characterized in that, Step five specifically includes: Photolithography is performed on the upper surface of the epitaxial wafer to obtain the gate forming region. The gate metal electrode is deposited in the gate forming region using an electron beam evaporation process. The gate metal electrode is a nickel and gold stack, and the thickness of both nickel and gold is 20 nm. After deposition, the epitaxial wafer is immersed in acetone to remove excess metal, and then subjected to rapid thermal annealing at 550°C for 5 minutes to complete the fabrication of the gate metal electrode.

10. The method for fabricating a P-type gallium nitride gate transistor based on self-stopping etching according to claim 7, characterized in that, Step six specifically includes: A passivation layer is obtained by preparing a 50 nm thick silicon dioxide layer on the upper surface of the epitaxial wafer using atomic layer deposition. The passivation layer on the source metal electrode, drain metal electrode and gate metal electrode is removed by reactive ion etching.

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