A lateral insulated gate double heterojunction gallium nitride field-effect transistor and its fabrication method

Abstract

This invention relates to a lateral insulated-gate double heterojunction gallium nitride field-effect transistor and its fabrication method. The transistor includes: a substrate layer, a buffer layer, an intrinsic GaN layer, an AlGaN barrier layer, a p-GaN layer, and an insulating gate dielectric layer stacked sequentially, wherein a heterojunction barrier is formed between the p-GaN layer and the AlGaN barrier layer; a source and a drain located at both ends of the intrinsic GaN layer and in contact with the side of the insulating gate dielectric layer, the side of the p-GaN layer, the side of the AlGaN barrier layer, and a portion of the side of the intrinsic GaN layer; an AlGaN region located on the intrinsic GaN layer and in contact with the lower end of the drain, wherein the AlGaN region forms a heterojunction with the intrinsic GaN layer; and a gate located on the insulating gate dielectric layer. By incorporating the p-GaN layer and the AlGaN region, this invention improves the transistor's current stability, voltage withstand capability, and current density and power density under high frequency and high voltage conditions.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a lateral insulated gate double heterojunction gallium nitride field-effect transistor and its fabrication method. Background Technology

[0002] Compared to traditional Si and AsGa materials, GaN materials possess superior properties such as a wide bandgap, high electron drift velocity, high thermal conductivity, and high breakdown electric field, making them suitable for fabricating high-voltage, high-frequency, and high-power electronic devices. With the development of new energy vehicles, 5G communications, aerospace, and other fields, GaN-based power devices have been widely applied. However, current GaN power devices still suffer from issues related to current stability and voltage withstand capability. Traditional GaN-based power devices exhibit low current stability and are prone to current collapse. After experiencing high-voltage turn-off stress, the drain current drops significantly upon re-applying a conduction bias, while the dynamic on-resistance increases sharply, severely impacting device performance. The voltage withstand capability of mass-produced devices is mostly concentrated around 650V, but the experimental limit is approximately 2.4kV, far exceeding the theoretical limit of GaN-based devices. Vertical structures can overcome the voltage withstand capability limitations of lateral structures, but production yields are low, and the cost is 8-10 times that of Si-based devices, making mass production difficult in the short term.

[0003] To address the current collapse effect, existing technologies often employ LPCVD to deposit passivation layers to passivate interfacial dangling bonds, or dope the buffer layer with Fe or C to reduce the trap density. To address the low breakdown voltage of devices, existing technologies often use undoped GaN cap layers to improve gate breakdown voltage, or add field plate structures to uniformly distribute the electric field between the gate and drain. However, passivation layers and AlGaN have inherent defect states, making it impossible to completely eliminate traps; the uniformity of Fe doping is difficult to control, and Fe ions easily diffuse at high temperatures, affecting long-term reliability; C doping leads to self-compensation effects and may introduce new traps; undoped GaN cap layers easily form traps such as N vacancies, exacerbating the current collapse effect; while field plate structures can reduce electric field spikes at the gate-drain edges, they create new electric field concentration points at the field plate ends, and suffer from multi-dimensional uneven distribution and a voltage ceiling problem.

[0004] Therefore, the current stability and voltage withstand capability of existing GaN-based power devices are not high enough. They are prone to current collapse under high frequency and high voltage environments, and their power density is somewhat different from the theoretical limit of GaN-based power devices. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a lateral insulated-gate double heterojunction gallium nitride field-effect transistor and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a lateral insulated-gate double heterojunction gallium nitride field-effect transistor, comprising: A substrate layer, a buffer layer, an intrinsic GaN layer, an AlGaN barrier layer, a p-GaN layer, and an insulating gate dielectric layer are stacked sequentially, wherein a heterojunction barrier is formed between the p-GaN layer and the AlGaN barrier layer; The source and drain are located at both ends of the intrinsic GaN layer and are in contact with the side of the gate dielectric layer, the side of the p-GaN layer, the side of the AlGaN barrier layer, and part of the side of the intrinsic GaN layer. An AlGaN region that is in contact with the lower end of the drain and is located on the intrinsic GaN layer, wherein the AlGaN region and the intrinsic GaN layer form a heterojunction; The gate located on the insulating gate dielectric layer.

[0006] In one embodiment of the present invention, the substrate material comprises n-type (111)Si with a thickness of 500~725μm and a resistivity of 0.01~0.02Ω·cm.

[0007] In one embodiment of the present invention, the buffer layer is made of AlN and has a thickness of 160~220nm.

[0008] In one embodiment of the present invention, the thickness of the intrinsic GaN layer is 1~1.5 μm.

[0009] In one embodiment of the present invention, the thickness of the AlGaN barrier layer is 15~25nm, wherein the Al composition is 20~30%.

[0010] In one embodiment of the present invention, the thickness of the p-GaN layer is 50~80 nm, and the doping element includes Mg with a doping concentration of 1×10⁻⁶. 17 ~5×10 17 cm -3 .

[0011] In one embodiment of the present invention, the thickness of the AlGaN region is 50-100 nm, wherein the Al composition is 20-30%.

[0012] In one embodiment of the present invention, the material of the insulating gate dielectric layer includes Al2O3, and the thickness is 10~20nm.

[0013] In one embodiment of the present invention, the source and drain are made of a multilayer metal of Ti, Al, Ni, and Au. The gate material includes a Ni and Au stacked metal.

[0014] Another embodiment of the present invention provides a method for fabricating a lateral insulated-gate double heterojunction gallium nitride field-effect transistor, comprising the steps of: A buffer layer, an intrinsic GaN layer, and an AlGaN barrier layer are sequentially grown on the substrate. Photolithography is used to remove the AlGaN barrier layer and part of the intrinsic GaN layer in the source and drain regions, and the etching depth of the drain region is greater than that of the source region, forming source and drain grooves. AlGaN is deposited at the bottom of the drain region groove until the surface of AlGaN is on the same plane as the bottom of the source region groove, forming an AlGaN region; A p-GaN layer is grown on the AlGaN barrier layer, wherein a heterojunction barrier is formed between the p-GaN layer and the AlGaN barrier layer, and wherein the AlGaN region forms a heterojunction with the intrinsic GaN layer. An insulating gate dielectric layer is grown on the p-GaN layer; Source metal is grown in the source region groove, and drain metal is grown on the AlGaN region in the drain region groove. Rapid thermal annealing is then performed to form ohmic contacts between the source and drain regions, thus obtaining the source and drain. A gate metal is generated on the insulating gate dielectric layer and then annealed to form a Schottky contact in the gate region, thus obtaining the gate.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention employs a p-GaN layer, which can form a depletion region when the device is turned off, making the device an enhancement-mode normally-off device and improving the gate reliability. An AlGaN region is set in the region below the drain in the intrinsic GaN layer. On the one hand, this can reduce surface traps at the interface between the AlGaN barrier layer and the GaN UID layer, suppress current collapse effect, and improve the dynamic performance of the device. On the other hand, the vertical heterojunction formed by the AlGaN region and the intrinsic GaN can improve the electric field distribution of the device, reduce the peak electric field value under the drain, and improve the voltage withstand capability of the device. Through the synergistic effect of the p-GaN layer and the AlGaN region, this invention improves the current stability, voltage withstand capability, and current density and power density of the transistor under high frequency and high voltage. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of a gallium nitride field-effect transistor with a lateral insulated gate double heterojunction provided in an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the fabrication process of a gallium nitride field-effect transistor with a lateral insulated gate double heterojunction provided in an embodiment of the present invention. Detailed Implementation

[0017] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0018] Example 1 Please see Figure 1 , Figure 1 This is a schematic diagram of a lateral insulated-gate double heterojunction gallium nitride field-effect transistor provided in an embodiment of the present invention. The transistor includes a substrate layer, a buffer layer, an intrinsic GaN layer, an AlGaN barrier layer, a p-GaN layer, an insulating gate dielectric layer, a source, a drain, a gate, and an AlGaN region.

[0019] The substrate, buffer layer, intrinsic GaN layer, AlGaN barrier layer, p-GaN layer, and insulating gate dielectric layer are stacked sequentially from bottom to top. A heterojunction barrier is formed between the p-GaN layer and the AlGaN barrier layer. The source and drain are located at opposite ends of the intrinsic GaN layer and are in contact with the sides of the insulating gate dielectric layer, the p-GaN layer, the AlGaN barrier layer, and a portion of the intrinsic GaN layer. At the lower end of the drain, an AlGaN region is formed on the intrinsic GaN layer, which contacts the lower end of the drain and forms a heterojunction with the intrinsic GaN layer. The gate is located above the insulating gate dielectric layer.

[0020] In one specific embodiment, the thickness of the AlGaN region is 50~100nm, wherein the Al composition is 20~30%. The specific thickness of the AlGaN region can be matched according to the depth of the source region groove, so that the surface of the AlGaN region and the bottom of the source region groove are on the same plane.

[0021] In one specific embodiment, the substrate material comprises n-type (111)Si with a thickness of 500~725μm and a resistivity of 0.01~0.02Ω·cm. The buffer layer material comprises AlN with a thickness of 160~220nm. The intrinsic GaN layer, i.e., the GaN UID layer, has a thickness of 1~1.5μm. The AlGaN barrier layer has a thickness of 15~25nm, wherein the Al composition is 20~30%. The p-GaN layer has a thickness of 50~80nm, and the doping element includes Mg with a doping concentration of 1×10⁻⁶. 17 ~5×10 17 cm -3 The insulating gate dielectric layer is made of Al₂O₃ with a thickness of 10–20 nm. The source and drain electrodes are made of a multilayer metal of Ti, Al, Ni, and Au, with Ti having a thickness of 20 nm, Al 160 nm, Ni 50 nm, and Au 45 nm. The gate electrode is made of a multilayer metal of Ni and Au, with Ni having a thickness of 50 nm and Au 150 nm.

[0022] Compared to existing technologies, this invention has the following advantages: 1. Existing LPCVD passivation layer deposition methods physically cover and block surface traps from contacting charge carriers; however, traps may still be activated under high temperature and high pressure conditions. In contrast, this invention directly uses holes in the AlGaN region to compensate for electrons trapped by traps, passivating interface traps at their source. 2. Existing methods doping the buffer layer with Fe and C only suppress bulk traps and still require a passivation layer. The dominant factor in current collapse is the surface traps at the AlGaN-GaN layer interface. This invention directly neutralizes the negatively impacting surface traps through the AlGaN region, providing a more targeted solution. This invention solves the following problems: 3. Existing technologies use undoped GaN cap layers, whose spontaneous polarization superimposes with the spontaneous polarization of AlGaN, enhancing the local electric field in the source and gate regions. While this improves the local electric field distribution in the drain region, it indirectly reduces the overall breakdown voltage characteristics. In contrast, the AlGaN deposition region under the drain in this invention improves the electric field distribution at the drain edge without affecting other regions. 4. Existing technologies use field plate structures, whose edges experience electric field spike distortion due to abrupt geometric changes, becoming weak points for device breakdown. In contrast, the AlGaN region in this invention utilizes the vertical PN junction principle to improve the electric field distribution, preventing the emergence of new electric field peaks.

[0023] Therefore, by setting an AlGaN region below the drain using the above structure, on the one hand, the holes in the AlGaN region can compensate for the electrons trapped at the interface, reduce surface traps at the interface between the AlGaN barrier layer and the GaN UID layer, improve the dynamic performance of the device, and suppress the current collapse effect; on the other hand, the AlGaN region and the intrinsic GaN form a vertical heterojunction. When the device is turned off and a high voltage is applied to the drain, this PN junction is reverse biased, and the depletion region extends from the drain region toward the channel, thereby modulating the electric field, improving the electric field distribution of the device, significantly reducing the peak electric field intensity, and increasing the breakdown voltage of the device.

[0024] In addition, the transistor of the present invention can form a depletion region by utilizing the heterojunction barrier formed by the p-GaN layer and the AlGaN barrier layer when it is turned off, thereby achieving enhancement-mode normally-off characteristics and improving the gate reliability of the device.

[0025] Furthermore, this invention simultaneously incorporates a p-GaN layer and an AlGaN region. On one hand, in the off-state, the p-GaN layer depletes the two-dimensional electron gas below the gate, while the vertical PN junction formed by the AlGaN region and the intrinsic GaN layer generates a depletion layer under reverse drain bias. These two depletion regions extend from the gate and drain ends into the channel, respectively. Their combined effect makes the channel easier to pinch off, resulting in lower off-state leakage current and higher breakdown voltage. On the other hand, during dynamic switching, holes at the edge of the p-GaN layer can be laterally injected under the influence of an electric field or migrate to the vicinity of the AlGaN region with the assistance of a polarization field, replenishing the holes required for trap compensation in this region and further enhancing the suppression effect on current collapse. Meanwhile, the hole compensation provided by the AlGaN region can reduce the depletion degree of the p-GaN layer during high-voltage switching, preventing threshold voltage drift due to excessive depletion of the p-GaN layer and improving the long-term stability of the device threshold voltage. Furthermore, the heterojunction of the p-GaN layer and the AlGaN barrier layer introduces an additional electric field peak at the gate edge. This peak, combined with the reduced electric field peak of the AlGaN region at the drain edge, results in a more uniform overall electric field distribution between the gate and drain, avoiding the problem of new electric field spikes at the ends of traditional field plate structures. Therefore, this invention improves the current stability, voltage withstand capability, and current density and power density of the transistor under high frequency and high voltage conditions through the synergistic effect of the p-GaN layer and the AlGaN region.

[0026] This embodiment also provides a method for fabricating a lateral insulated-gate double heterojunction gallium nitride field-effect transistor. Please refer to [link to documentation]. Figure 2 , Figure 2 This is a schematic diagram illustrating the fabrication process of a lateral insulated-gate double heterojunction gallium nitride field-effect transistor provided in an embodiment of the present invention. The fabrication method includes the following steps: S1. A buffer layer, an intrinsic GaN layer, and an AlGaN barrier layer are sequentially grown on the substrate.

[0027] Specifically, firstly, an n-type (111) Si substrate with a thickness of 500~725μm and a resistivity of 0.01~0.02Ω·cm is selected; the RCA standard cleaning is adopted. First, the substrate is cleaned with SC1 (NH4OH:H2O2:H2O=1:20:50) in a water bath at 75~85℃ for 10~15min to remove organic impurities and particles. Then, it is cleaned with SC2 (HCl:H2O2:H2O=1:1:50) in a water bath at 75~85℃ for 10~15min to remove metal ions. Finally, it is rinsed with deionized water for 3~5min. After cleaning, it is dried with high-purity N2 to obtain a clean substrate surface.

[0028] Then, the cleaned Si substrate is sent to the MOCVD reaction chamber with a chamber pressure of 50~100 Torr and H2 is introduced as the carrier gas. The temperature is set to 1050~1100℃, the growth rate is 0.1~0.25nm / s, the V / III ratio of NH3 to TMAl is 1800, and the thickness is 160~220nm to grow an AlN buffer layer.

[0029] Next, the intrinsic GaN UID layer was grown at a temperature of 1030~1080℃, a V / III ratio of NH3 to TMGa of 2500, and a growth thickness of 1~1.5μm.

[0030] Finally, the temperature was set to 1000~1050℃, the growth thickness was 15~25nm, the V / III ratio of NH3 and TMAl / TMGa was 1500, and the Al component was 20~30%, to grow an AlGaN barrier layer, so that a two-dimensional electron gas (2DEG) was formed at the interface.

[0031] S2. The AlGaN barrier layer and part of the intrinsic GaN layer in the source and drain regions are removed by photolithography, and the etching depth of the drain region is greater than that of the source region, forming source and drain grooves.

[0032] Specifically, first, AZ5214 photoresist is coated on the surface of the barrier layer at the positions shown in the figure, with a thickness of 1.5~2μm; after pre-baking for 60~90s and 90~100℃, it is exposed using a source / drain mask and developed with developer (MF-319) for 30~60s; finally, it is rinsed with deionized water and dried with N2 to form the photoresist pattern of the source / drain region.

[0033] Then, ICP etching is used to remove the AlGaN barrier layer and part of the GaN UID layer that need to be removed in the source and drain regions. The etching rate is set to 50~100nm / min, the etching depth of the source region is 300~500nm, the etching depth of the drain region is increased by 50~100nm based on the source region, and the etching damage layer needs to be less than 5nm.

[0034] Finally, ultrasonically clean with acetone, rinse with isopropanol, and dry with N2 to remove the photoresist.

[0035] S3. Deposit AlGaN at the bottom of the drain region groove until the surface of AlGaN and the bottom of the source region groove are on the same plane, forming an AlGaN region.

[0036] Specifically, the cleaned wafer is placed in a PECVD reaction chamber with a chamber pressure of 60~110 Torr and H2 is introduced as the carrier gas. The temperature is set to 820~920℃, the growth rate is 0.05~0.12nm / s, the V / III ratio is 1500, and the Al component is 20~30%. The wafer is deposited to the same height as the bottom of the source region groove to form an AlGaN region.

[0037] S4. A p-GaN layer is grown on the AlGaN barrier layer, wherein a heterojunction barrier is formed between the p-GaN layer and the AlGaN barrier layer, and the AlGaN region forms a heterojunction with the intrinsic GaN layer.

[0038] Specifically, the temperature was set at 950~1000℃, the growth thickness was 50~80nm, the V / III ratio of NH3 and TMAl / TMMg was 1000, and a p-GaN layer was grown, in which the Mg doping concentration was 1×10⁻⁶. 17 ~5×10 17 cm -3 .

[0039] S5. An insulating gate dielectric layer is grown on the p-GaN layer.

[0040] Specifically, the wafer is placed in the ALD reaction chamber, the deposition temperature is set to 250~350℃, the deposition thickness is 10~20nm, the dielectric constant is 10, the uniformity error is less than ±5%, and an Al2O3 gate dielectric layer is deposited.

[0041] S6. Source metal is grown in the source region groove, and drain metal is grown on the AlGaN region in the drain region groove. Rapid thermal annealing is then performed to form ohmic contacts between the source and drain regions, thus obtaining the source and drain.

[0042] Specifically, Ti / Al / Ni / Au metal is deposited using magnetron sputtering technology, with Ti thickness of 20nm, Al thickness of 160nm, Ni thickness of 50nm, and Au thickness of 45nm; Rapid thermal annealing (RTA): In an N2 atmosphere, the temperature is set at 800~850℃, the heating rate is 50~100℃ / s, and the holding time is 30~60s to achieve rapid thermal annealing and form ohmic contacts in the source and drain regions.

[0043] S7. Generate gate metal on the insulating gate dielectric layer and perform annealing to form a Schottky contact in the gate region to obtain the gate.

[0044] Specifically, photoresist is coated, and exposure and development are performed using a gate mask to define the gate pattern window; ICP etching is used to remove the gate region dielectric, with an etching rate of 100~120nm / min, and the etch damage layer must be less than 5nm; Ni / Au metal is deposited by electron beam evaporation, with a Ni thickness of 50nm and an Au thickness of 150nm; ultrasonic cleaning with acetone, rinsing with isopropanol, drying with N2, and photoresist is stripped to form the gate electrode pattern; annealing treatment: in an N2 atmosphere, the temperature is set at 450~500℃ and held for 40~50min to form the Schottky contact of the gate region.

[0045] This invention relates to a lateral insulated gate double heterojunction transistor based on p-GaN / AlGaN / GaN double heterojunction design and its fabrication method. It can fabricate power devices with normally-off characteristics, high gate reliability, high breakdown voltage, and stable current density. It can significantly improve the stability and withstand voltage of GaN-based power devices, reduce switching losses, and maximize the advantages of GaN materials in the field of power devices, thereby promoting further improvement in the key indicators of power devices.

[0046] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A gallium nitride field-effect transistor with a lateral insulated gate double heterojunction, characterized in that, include: A substrate layer, a buffer layer, an intrinsic GaN layer, an AlGaN barrier layer, a p-GaN layer, and an insulating gate dielectric layer are stacked sequentially, wherein a heterojunction barrier is formed between the p-GaN layer and the AlGaN barrier layer; The source and drain are located at both ends of the intrinsic GaN layer and are in contact with the side of the gate dielectric layer, the side of the p-GaN layer, the side of the AlGaN barrier layer, and part of the side of the intrinsic GaN layer. An AlGaN region that is in contact with the lower end of the drain and is located on the intrinsic GaN layer, wherein the AlGaN region and the intrinsic GaN layer form a heterojunction; The gate located on the insulating gate dielectric layer.

2. The gallium nitride field-effect transistor with a lateral insulated gate double heterojunction according to claim 1, characterized in that, The substrate is made of n-type (111)Si with a thickness of 500~725μm and a resistivity of 0.01~0.02Ω·cm.

3. The gallium nitride field-effect transistor with a lateral insulated gate double heterojunction according to claim 1, characterized in that, The buffer layer is made of AlN and has a thickness of 160~220nm.

4. The gallium nitride field-effect transistor with a lateral insulated gate double heterojunction according to claim 1, characterized in that, The thickness of the intrinsic GaN layer is 1~1.5μm.

5. The gallium nitride field-effect transistor with a lateral insulated gate double heterojunction according to claim 1, characterized in that, The AlGaN barrier layer has a thickness of 15~25nm, and the Al composition is 20~30%.

6. The gallium nitride field-effect transistor with a lateral insulated gate double heterojunction according to claim 1, characterized in that, The p-GaN layer has a thickness of 50~80 nm and is doped with Mg at a concentration of 1×10⁻⁶. 17 ~5×10 17 cm -3 .

7. The gallium nitride field-effect transistor with a lateral insulated gate double heterojunction according to claim 1, characterized in that, The thickness of the AlGaN region is 50~100nm, and the Al composition is 20~30%.

8. The gallium nitride field-effect transistor with a lateral insulated gate double heterojunction according to claim 1, characterized in that, The insulating gate dielectric layer is made of Al2O3 and has a thickness of 10~20nm.

9. The gallium nitride field-effect transistor with a lateral insulated gate double heterojunction according to claim 1, characterized in that, The source and drain electrodes are made of a multilayer metal of Ti, Al, Ni, and Au. The gate material includes a Ni and Au stacked metal.

10. A method for fabricating a lateral insulated-gate double heterojunction gallium nitride field-effect transistor, characterized in that, Including the following steps: A buffer layer, an intrinsic GaN layer, and an AlGaN barrier layer are sequentially grown on the substrate. Photolithography is used to remove the AlGaN barrier layer and part of the intrinsic GaN layer in the source and drain regions, and the etching depth of the drain region is greater than that of the source region, forming source and drain grooves. AlGaN is deposited at the bottom of the drain region groove until the surface of AlGaN is on the same plane as the bottom of the source region groove, forming an AlGaN region; A p-GaN layer is grown on the AlGaN barrier layer, wherein a heterojunction barrier is formed between the p-GaN layer and the AlGaN barrier layer, and wherein the AlGaN region forms a heterojunction with the intrinsic GaN layer. An insulating gate dielectric layer is grown on the p-GaN layer; Source metal is grown in the source region groove, and drain metal is grown on the AlGaN region in the drain region groove. Rapid thermal annealing is then performed to form ohmic contacts between the source and drain regions, thus obtaining the source and drain. A gate metal is generated on the insulating gate dielectric layer and then annealed to form a Schottky contact in the gate region, thus obtaining the gate.

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