Two-dimensional material transistors based on metal oxygen abstraction mechanism and their fabrication method

Abstract

This invention discloses a two-dimensional material transistor based on a metal oxygen abstraction mechanism and its fabrication method. The transistor includes a substrate, a two-dimensional semiconductor material layer, an oxide structure layer disposed only in the source / drain contact region, and source / drain metal electrodes. The oxide structure layer includes a first metal oxide upper layer and a low-valence transition metal oxide lower layer formed by in-situ reduction of the surface oxide layer. During fabrication, the source / drain regions are selectively oxidized to form a surface oxide layer, followed by global deposition of oxygen-abstracting metal. The oxygen-abstracting metal abstracts oxygen atoms from the surface oxide layer, generating the first metal oxide and reducing it to a low-valence transition metal oxide. Unreacted oxygen-abstracting metal in the channel region is then removed, finally forming the source / drain metal electrodes. This invention constructs a low-contact-resistance interface in-situ using a metal oxygen abstraction method, avoiding damage to the two-dimensional material lattice, significantly reducing contact resistance, and offering controllable process capabilities. It is applicable to various two-dimensional materials and flexible substrates.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices and their manufacturing technology, and in particular to a two-dimensional material transistor with low contact resistance formed based on a metal oxygen abstraction mechanism and its fabrication method. Background Technology

[0002] As semiconductor technology continues to shrink feature sizes to the nanoscale, traditional silicon-based materials face severe challenges due to physical limitations such as the short-channel effect. Two-dimensional semiconductor materials, represented by transition metal chalcogenides (TMDCs, such as MoS2 and WS2), are considered core candidate materials for building next-generation ultra-large-scale integrated (ULSI) transistors, optoelectronic devices, and flexible electronic devices due to their atomic-level thickness, dangling bond-free surfaces, excellent carrier mobility, and tunable bandgap characteristics.

[0003] However, in the practical application of two-dimensional material transistors, the source / drain contact problem between the metal electrode and the two-dimensional semiconductor material has become one of the main technical bottlenecks. Specifically: First, when metal is directly deposited on the surface of a two-dimensional material, a strong Fermi level pinning effect and a high Schottky barrier are usually generated at the interface, resulting in low electron injection efficiency and excessively high contact resistance, severely restricting the on-state current and frequency characteristics of the device. Second, traditional metal deposition processes (such as electron beam evaporation and magnetron sputtering) are often accompanied by high-energy particle bombardment or high process temperatures, which can easily damage the atomically thin lattice of two-dimensional materials, introducing defect states and reducing the intrinsic mobility of the material, thus offsetting the structural advantages of two-dimensional materials.

[0004] To reduce contact resistance, various interface modification methods have been explored in existing technologies. For example, plasma treatment (such as oxygen plasma or argon plasma) is used to activate the surface or induce phase transformation in the contact region of two-dimensional materials, aiming to form an intermediate layer conducive to charge injection. However, these methods have significant drawbacks: on the one hand, the high-energy particles from plasma treatment can easily bombard and damage the lattice of two-dimensional materials, introducing uncontrollable defects and reducing device stability and uniformity; on the other hand, the conductive phases (such as metallic 1T phases) or oxides (such as MoO2) induced by plasma are often limited by processing conditions, making precise control of their formation depth, spatial distribution, and stoichiometry extremely difficult, resulting in poor repeatability of contact resistance improvement and low process yield. Another approach is to introduce two-dimensional buffer layers such as graphene or hexagonal boron nitride (h-BN) to modulate the interface, but their preparation and transfer processes are complex, have poor compatibility with existing semiconductor processes, and increase manufacturing costs and complexity.

[0005] Therefore, how to construct a stable, controllable metal-two-dimensional material interface with low contact resistance without damaging the intrinsic structure of two-dimensional materials is a key technical problem that urgently needs to be solved in this field. Summary of the Invention

[0006] The present invention aims to overcome the defects of existing two-dimensional material transistors, such as excessively high source / drain contact resistance, difficulty in precise control of interface state, and easy damage to the lattice structure of two-dimensional materials during the process. It provides a two-dimensional material transistor and its fabrication method that can achieve low contact resistance, high interface stability and compatibility with existing semiconductor processes.

[0007] To achieve the above objectives, this invention proposes an interface control method based on a metal oxygen abstraction mechanism. This invention utilizes oxygen-abstracting metals such as Ti, Zr, or Hf, which have a strong chemical affinity for oxygen atoms, to spontaneously abstract oxygen atoms from a pre-formed oxide layer on the surface of a two-dimensional semiconductor material. This simultaneously achieves: the oxygen-abstracting metal itself is oxidized into a stable first metal oxide, and the high-valence oxide on the surface of the original oxide layer is in situ reduced into a low-valence transition metal oxide with higher conductivity. This forms an oxide structure layer composed of a low-valence transition metal oxide and a first metal oxide, serving as a transition layer between the metal electrode and the two-dimensional semiconductor material, significantly reducing the contact barrier and improving carrier injection efficiency. The high-valence oxide can be MoO3 or WO3, and the low-valence transition metal oxide formed after oxygen abstraction is MoO2, WO2, or their non-stoichiometric oxides. Based on this, this invention provides the following technical solution.

[0008] On one hand, the present invention provides a two-dimensional material transistor based on a metal oxygen abstraction mechanism, comprising: Substrate; A two-dimensional semiconductor material layer is disposed on the substrate and has a channel region and source contact regions and drain contact regions located on both sides of the channel region; An oxide structure layer is disposed on the surface of the source contact region and the drain contact region, the oxide structure layer comprising: a first metal oxide upper layer and a low-valence transition metal oxide lower layer; The lower layer of the low-valence transition metal oxide is formed in situ by reducing the surface oxide layer of the source and drain contact regions of the two-dimensional semiconductor material layer through an oxygen abstraction reaction; the upper layer of the first metal oxide is formed by the oxygen abstraction metal originally deposited on the surface oxide layer abstracting oxygen atoms from the surface oxide layer; the surface oxide layer is formed by oxidation treatment of the two-dimensional semiconductor material of the source and drain contact regions; The source metal electrode and the drain metal electrode are respectively disposed on the oxide structure layer above the source contact region and the drain contact region.

[0009] Furthermore, the two-dimensional semiconductor material layer is a transition metal chalcogenide, selected from any one of MoS2, WS2, MoSe2, and WSe2.

[0010] Furthermore, the oxygen-extracting metal is any one of Ti, Zr, and Hf, and the first metal oxide corresponds to TiO. x ZrO x or HfO x When the two-dimensional semiconductor material layer is MoS2 or WS2, the corresponding low-valence transition metal oxide is MoO2, WO2, or an oxide of transition metal Mo or W in a non-stoichiometric form.

[0011] Furthermore, the total thickness of the oxide structure layer is 1 nm to 10 nm; the source metal electrode and the drain metal electrode are made of Au, Pd, Cu or their alloys; the substrate is SiO2 / Si, Al2O3, sapphire or a polymer flexible substrate.

[0012] On the other hand, the present invention also provides a method for fabricating a two-dimensional material transistor with low contact resistance based on a metal oxygen abstraction mechanism, comprising the following steps.

[0013] Step S1, two-dimensional material preparation step: a substrate is provided, and a two-dimensional semiconductor material layer is formed on the substrate.

[0014] Step S2, surface oxidation treatment step: The surfaces of the predetermined source and drain regions of the two-dimensional semiconductor material layer are oxidized to form a surface oxide layer.

[0015] Step S3, Metal Oxygen Absorption Processing Step: An oxygen-absorption metal layer is deposited on the surface oxide layer, and the oxygen-absorption metal layer and the surface oxide layer undergo an oxygen-absorption reaction under a controlled atmosphere and temperature. The oxygen-absorption metal in the oxygen-absorption metal layer abstracts oxygen atoms from the surface oxide layer, thereby transforming the oxygen-absorption metal layer into a first metal oxide layer. At the same time, the surface oxide layer is reduced to a low-valence transition metal oxide layer, thereby forming an oxide structure layer composed of the first metal oxide upper layer and the low-valence transition metal oxide lower layer.

[0016] Step S4, Electrode Formation Step: Form a source metal electrode and a drain metal electrode on the oxide structure layer.

[0017] Furthermore, the oxidation treatment is oxygen plasma treatment, thermal oxidation treatment, or chemical oxidation treatment; wherein the oxygen plasma treatment has a power of 20W to 80W, a treatment time of 10s to 220s, and a surface oxide layer thickness of 1nm to 5nm.

[0018] Furthermore, the metal oxygen abstraction treatment step is performed in any of the following ways: Method 1: Simultaneous oxygen-exclusion metal deposition and oxygen-exclusion reaction: During the deposition of the oxygen-exclusion metal layer, the substrate is heated to 200°C to 300°C, so that the oxygen-exclusion reaction and oxygen-exclusion metal deposition occur simultaneously.

[0019] Method 2, oxygen-absorping metal deposition and oxygen-absorping reaction are carried out sequentially: after depositing the oxygen-absorping metal layer at room temperature, annealing is performed at 200°C to 400°C. During the annealing process, the oxygen-absorping metal abstracts oxygen atoms from the surface oxide layer to carry out an oxygen-absorping reaction.

[0020] Method 3 involves forming multiple layers of oxygen-absorping metal and performing multiple oxygen-absorping reactions: At least two oxygen-absorping metal layers are deposited sequentially, and each layer is annealed at least once after deposition to perform multiple oxygen-absorping reactions, forming a dense first metal oxide layer. For example, in Example 3, a first oxygen-absorping metal layer is first deposited and annealed to perform an oxygen-absorping reaction, followed by a second oxygen-absorping metal layer and annealing to perform another oxygen-absorping reaction, thereby forming a dense upper layer of the first metal oxide layer and simultaneously improving the continuity of the lower layer of low-valence transition metal oxide.

[0021] Furthermore, the oxygen abstraction reaction or annealing treatment is carried out in an inert gas, reducing gas, or vacuum atmosphere, and the thickness of the oxygen abstraction metal layer is 3 nm to 20 nm.

[0022] Furthermore, after forming the source metal electrode and the drain metal electrode, the process further includes a secondary annealing process in an inert atmosphere or a reducing atmosphere, wherein the temperature of the secondary annealing process is 200°C to 400°C.

[0023] Furthermore, the material of the two-dimensional semiconductor material layer is any one of MoS2, WS2, MoSe2, and WSe2, and the oxygen-extracting metal is any one of Ti, Zr, and Hf.

[0024] Compared with the prior art, the two-dimensional material transistor and its fabrication method based on the metal oxygen abstraction mechanism provided by the present invention have the following beneficial effects.

[0025] (1) Significantly reduce contact resistance: The low-valence transition metal oxide lower layer (such as MoO2, WO2) formed in situ through oxygen abstraction reaction has metal-like conductivity or high carrier concentration, which can serve as an efficient electron injection buffer layer, effectively reducing the Schottky barrier between the metal electrode and the two-dimensional semiconductor material, reducing its source / drain contact resistance, and improving the on-state current of the device.

[0026] (2) Avoid damage to the lattice of two-dimensional materials: Unlike the existing technology that uses direct bombardment with high-energy plasma or high-temperature reduction process, the present invention utilizes the spontaneous chemical adsorption and redox reaction of oxygen-extracting metals to achieve in-situ reduction of the surface oxide layer under mild conditions (low temperature, no high-energy particles). This process does not destroy the atomic-level lattice structure of the two-dimensional material, thus preserving the excellent carrier transport characteristics of the two-dimensional material.

[0027] (3) High process integration and good controllability: This invention integrates the formation of the surface oxide layer, the oxygen abstraction reaction and the deposition of the electrode metal into a single design, which can be completed continuously in the same vacuum system, avoiding the pollution risks of multiple transfers or exposure to the atmosphere. By selecting different oxygen abstraction metals (Ti, Zr, Hf), and adjusting the oxide layer thickness, annealing temperature and reaction mode (simultaneous, subsequent or multi-layer), the chemical composition, thickness and interfacial band arrangement of the oxide structure layer can be precisely controlled, thereby achieving customized control of the contact resistance.

[0028] (4) Low process temperature and wide substrate compatibility: The highest temperature in the entire preparation process does not exceed 400°C, which is far lower than the annealing temperature of more than 600°C required to form ohmic contacts in traditional semiconductor processes. This makes the present invention particularly suitable for temperature-sensitive substrates, such as flexible polymer substrates such as polyimide and PET, providing a feasible path for the large-area, low-cost manufacturing of high-performance flexible two-dimensional material transistors.

[0029] (5) High versatility: This invention does not depend on specific types of two-dimensional materials and is applicable to a variety of transition metal chalcogenides. At the same time, the three implementation methods of simultaneous reaction, subsequent annealing and multilayer oxygen abstraction provide flexible process windows that can adapt to different production conditions and device performance requirements, and have high industrial application value. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the structure of the two-dimensional material transistor of the present invention.

[0031] Wherein, 1 is the substrate, 2 is the two-dimensional semiconductor material layer, 3 is the lower layer of low-valence transition metal oxide, 4 is the upper layer of first metal oxide, 5 is the source metal electrode, 6 is the drain metal electrode, 21 is the source contact region, 22 is the drain contact region, and 23 is the channel region. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The following embodiments are for illustrative purposes only and do not constitute a limitation on the scope of protection of this invention. Any equivalent substitutions or improvements made within the spirit and principles of this invention, based on the concept of this invention, should be included within the scope of protection of this invention.

[0033] Figure 1 This is a schematic diagram of the structure of the two-dimensional material transistor provided by the present invention. Figure 1 As shown, the two-dimensional material transistor includes: a substrate 1; a two-dimensional semiconductor material layer 2 disposed on the substrate 1, the two-dimensional semiconductor material layer 2 having a channel region 23 and a source contact region 21 and a drain contact region 22 located on both sides of the channel region 23; an oxide structure layer disposed on the surface of the source contact region 21 and the drain contact region 22, the oxide structure layer including a first metal oxide upper layer 4 and a low-valence transition metal oxide lower layer 3; and a source metal electrode 5 and a drain metal electrode 6 respectively disposed on the oxide structure layer above the source contact region 21 and the drain contact region 22.

[0034] The lower layer 3 of the low-valence transition metal oxide is a low-valence oxide with good conductivity, formed in situ by reducing a surface oxide layer (e.g., MoO3 or WO3) formed by surface oxidation of the two-dimensional semiconductor material layer 2 through an oxygen abstraction reaction. Examples include MoO2, WO2, or oxides of Mo or W in non-stoichiometric forms. The upper layer 4 of the first metal oxide is a stable metal oxide formed by the oxygen abstraction metal layer (e.g., Ti, Zr, Hf) deposited on the surface oxide layer, which abstracts oxygen atoms from the surface oxide layer. Examples include TiO2. X ZrO X HfO X The total thickness of the oxide structure layer is preferably 1 nm to 10 nm.

[0035] The preparation method of the present invention is described in detail below through specific embodiments, corresponding to three implementation methods: simultaneous oxygen abstraction, subsequent annealing oxygen abstraction, and multi-layer oxygen abstraction. Each embodiment uses... Figure 1 The structure shown is the target structure to be prepared. Example 1

[0036] In this embodiment, Ti metal is used as the oxygen-exclusion metal, and a simultaneous deposition of the oxygen-exclusion metal and oxygen-exclusion reaction are employed to form a MoS2 transistor with low contact resistance through the oxygen-exclusion reaction. The specific steps are as follows.

[0037] Step 1, Preparation of the two-dimensional semiconductor material layer: A monolayer MoS2 thin film was prepared on a SiO2 / Si substrate using chemical vapor deposition (CVD). Specifically, MoO3 was used as the molybdenum source, H2S as the sulfur source, and Ar as the carrier gas. The substrate was placed in a tube furnace, and the reaction temperature was controlled at 750~850℃. The deposition time was 15~30 min, resulting in a monolayer MoS2 thin film with a thickness of approximately 1~2 nm. The film has a well-aligned crystal lattice and serves as the two-dimensional semiconductor material layer 2.

[0038] Step 2, Selective Surface Oxidation: Selective oxygen plasma treatment is performed on the regions designated for forming the source contact region 21 and drain contact region 22 using a mask. The treatment conditions are: O2 plasma power 30-60 W, treatment time 20-60 s, and chamber pressure 20-100 mTorr. Under these conditions, the MoS2 on the surfaces of the source contact region 21 and drain contact region 22 is oxidized, forming a MoO3 surface oxide layer with a thickness of approximately 1-3 nm. The channel region 23, due to masking, does not form a significant oxide layer.

[0039] Step 3, Oxygen-Abstracting Metal Deposition and Simultaneous Oxygen Abstracting Reaction: The substrate is heated to 200-300°C, and a Ti metal layer with a thickness of 5-15 nm is deposited on the entire substrate surface using electron beam evaporation at this temperature, with a deposition rate of 0.1-1.0 Å / s. During the deposition process, the Ti metal layer located on the surface of the source contact region 21 and the drain contact region 22 undergoes an oxygen-abstracting reaction with the underlying MoO3 surface oxide layer: Ti abstracts oxygen atoms from MoO3 and is oxidized to TiO2. x This forms the first metal oxide upper layer 4, while the surface oxide layer of MoO3 is reduced in situ to MoO2 or MoO. 3-x A low-valence transition metal oxide lower layer 3 is formed. Since there is no oxide layer below the channel region 23, the deposited Ti metal layer basically remains metallic Ti, and the surface may be slightly oxidized, but the main body is still metallic.

[0040] Step 4, Photolithography and Etching to Remove the Ti Metal Layer in the Channel Region: A protective photoresist mask is formed above the source contact region 21 and the drain contact region 22 using standard photolithography. Then, RIE or wet etching, such as with diluted HF or TMAH solutions, is used to remove the Ti metal layer on the surface of the channel region 23, exposing the MoS2 surface of the channel region 23. The photoresist is then removed, leaving a complete oxide structure layer, i.e., TiO2, on the surfaces of the source contact region 21 and the drain contact region 22. x The upper layer and the lower layer of MoO2.

[0041] Step 5, Source / Drain Metal Electrode Deposition: Electrode patterns are again formed above the source contact region 21 and drain contact region 22 using photolithography. Au with a thickness of 50-100 nm is deposited by electron beam evaporation, followed by a lift-off process to form the source metal electrode 5 and drain metal electrode 6. The Au electrodes are then connected to the underlying TiO₂. x The layers form good electrical contacts.

[0042] Step 6, optional annealing optimization: Perform low-temperature annealing at 200~300℃ for 10~30min under vacuum or nitrogen atmosphere to further improve TiO₂. x Improve the stability of the / MoO2 interface and enhance carrier transport performance.

[0043] The MoS2 transistor prepared by the above steps has the following structure. Figure 1 As shown in the figure. Tests show that the source / drain contact resistance is reduced by about 40% compared to the comparison device with directly deposited Ti / Au electrodes, and the on-state current of the device is significantly improved. Example 2

[0044] In this embodiment, Zr is used as the oxygen-exclusion metal, and a low-contact-resistance WS2 transistor is formed through an oxygen-exclusion reaction during subsequent annealing. The specific steps are as follows.

[0045] Step 1, Fabrication of two-dimensional semiconductor material: A monolayer WS2 thin film is prepared on a sapphire substrate by CVD. A tungsten-containing precursor WO3 or WCl6, a mixed gas of H2S and Ar is used, the growth temperature is 600~800℃, and the deposition time is 10~20 min to obtain a monolayer WS2 with a thickness of about 1~2 nm, which serves as the second layer of the two-dimensional semiconductor material.

[0046] Step 2, Selective Surface Oxidation: Selective oxidation of the predetermined source contact region 21 and drain contact region 22 is performed using oxygen plasma at a power of 40-70W for a processing time of 30-90s, forming a WO3 surface oxide layer with a thickness of approximately 2-5nm. The channel region 23 is not oxidized.

[0047] Step 3, oxygen-exclusion metal deposition: A Zr metal layer with a thickness of 3~8 nm is deposited on the entire substrate surface using magnetron sputtering at room temperature.

[0048] Step 4, Subsequent Annealing Oxygen Absorption Reaction: The substrate is placed in a nitrogen, argon, or vacuum atmosphere and annealed at 250-350℃ for 10-30 min. During the annealing process, the Zr metal layer located on the surface of the source contact region 21 and the drain contact region 22 undergoes an oxygen absorption reaction with WO3: Zr abstracts oxygen atoms from WO3 to generate ZrO. x That is, the upper layer 4 of the first metal oxide, where WO3 is reduced to WO2 or WO. 3-xThat is, the lower layer 3 of the low-valence transition metal oxide. Since there is no oxide layer below, the Zr metal layer in the channel region 23 only undergoes slight oxidation on the surface, and the main body remains in the metallic state.

[0049] Step 5. Photolithography and etching to remove the Zr metal layer in the channel region: The Zr metal layer on the surface of the channel region 23, including its thin oxide layer, is removed by photolithography and etching to expose the WS2 channel. The ZrO2 layer in the source contact region 21 and drain contact region 22 is then removed. x The WO2 oxide structure layer was preserved.

[0050] Step 6, source and drain metal electrode deposition: Au or Pd metal electrodes are formed on the oxide structure layer above the source contact region 21 and the drain contact region 22 by photolithography, electron beam evaporation or magnetron sputtering deposition, and lift-off process, serving as source metal electrode 5 and drain metal electrode 6.

[0051] Step 7, optional secondary annealing: Perform a secondary low-temperature annealing at around 300℃ for 10-20 minutes to enhance the ZrO. x / WS2 interface stability and improved current transmission performance.

[0052] The resulting WS2 transistor also has Figure 1 The structure shown reduces contact resistance by approximately 30% to 50% compared to untreated devices. Example 3

[0053] In this embodiment, a low-contact-resistance MoS2 transistor is further optimized and formed on a flexible substrate through multilayer Ti oxygen abstraction and annealing oxygen abstraction reactions. The specific steps are as follows.

[0054] Step 1, Two-dimensional material preparation: A multilayer MoS2 thin film is formed on a flexible polyimide (PI) substrate. Specifically, a multilayer MoS2 (5-10 nm thick) can first be grown on a temporary rigid substrate (such as SiO2 / Si) by CVD. Then, the MoS2 is transferred to the PI substrate by polymethyl methacrylate (PMMA) assisted transfer method, and the PMMA is removed to obtain the MoS2 layer on the flexible substrate, which serves as the two-dimensional semiconductor material layer 2.

[0055] Step 2, Selective Oxidation Treatment: Selective oxidation treatment is performed on the predetermined source contact region 21 and drain contact region 22 using oxygen plasma at a power of 30-50W for a treatment time of 20-60 seconds, forming a MoO3 surface oxide layer with a thickness of approximately 2-4 nm. The channel region 23 is not oxidized. Because the PI substrate is not resistant to high temperatures, the process temperature must be controlled to not exceed 300℃ throughout the entire process.

[0056] Step 3, First layer oxygen-exclusion metal deposition and preliminary annealing: A first Ti thin layer with a thickness of 1-3 nm is deposited on the entire substrate surface. Then, it is annealed in a vacuum or nitrogen atmosphere at 200-300℃ for 5-20 min to allow the Ti and MoO3 to undergo a preliminary oxygen-exclusion reaction, forming a thin TiO2 layer. x And reduce some MoO3 to MoO2 or MoO 3-x .

[0057] Step 4, Second layer oxygen-exclusion metal deposition and further annealing: After the first layer oxygen-exclusion reaction is completed, a second Ti metal layer with a thickness of 3-10 nm is deposited. It is then annealed at 200-350℃ for 10-30 min to form a denser TiO₂ layer. x The first metal oxide upper layer 4 further enhances the continuity and conductivity of the lower low-valence transition metal oxide lower layer 3. This multilayer deposition strategy effectively avoids problems such as incomplete reaction or loose oxide layer caused by excessive thickness of a single Ti layer.

[0058] Those skilled in the art will understand that the above deposition-annealing steps can be repeated three or more times as needed to further optimize the density and uniformity of the oxide structure layer.

[0059] Step 5, Photolithography and Etching to Remove Ti Metal Layer in the Channel Region: The Ti / TiO layer on the surface of the channel region 23 is removed by photolithography and etching. x The layers, including the first and second layers of deposits in the channel region, expose the MoS2 surface of the channel region 23. The oxide structure layers of the source contact region 21 and drain contact region 22, namely dense TiO2... x +MoO2 / MoO 3-x It was completely preserved.

[0060] Step 6, Source / Drain Metal Electrode Deposition: Au or Cu metal electrodes are formed on the oxide structure layer above the source contact region 21 and the drain contact region 22 through photolithography, deposition, and lift-off processes, serving as the source metal electrode 5 and the drain metal electrode 6. The deposition is performed using electron beam evaporation, and the substrate temperature is controlled between room temperature and 150°C to avoid damaging the flexible substrate.

[0061] The flexible MoS2 transistor prepared by the above method still maintains good electrical performance under a bending radius of 5 mm. The contact resistance is reduced by about 35% compared with the flexible device without oxygen abstraction treatment, and the performance degradation is less than 10% after 1000 cycles of bending.

[0062] The three embodiments described above correspond to three oxygen-exclusion reaction implementation methods of the present invention, including simultaneous reaction, subsequent annealing, and multilayer deposition annealing. Those skilled in the art will understand that the specific parameters in the embodiments, such as temperature, time, thickness, and power, are exemplary descriptions and can be adjusted within a certain range according to actual material and equipment conditions. All two-dimensional material transistors constructed using the metal oxygen-exclusion mechanism described in this invention, regardless of the specific oxygen-exclusion metal, two-dimensional material, or combination of process parameters used, fall within the protection scope of this invention.

[0063] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art can make various improvements and modifications without departing from the spirit and principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A two-dimensional material transistor, characterized in that, include: Substrate; A two-dimensional semiconductor material layer is disposed on the substrate, the two-dimensional semiconductor material layer having a channel region and source contact regions and drain contact regions located on both sides of the channel region; An oxide structure layer is disposed only on the surfaces of the source contact region and the drain contact region, the oxide structure layer comprising: The upper layer of the first metal oxide, and The lower layer of low-valence transition metal oxides; Wherein, the lower layer of the low-valence transition metal oxide is formed in situ by reducing the surface oxide layer of the two-dimensional semiconductor material layer on the surface of the source contact region and the drain contact region through an oxygen abstraction reaction; the upper layer of the first metal oxide is formed by the oxygen abstraction metal in the oxygen abstraction metal layer deposited on the surface oxide layer abstracting oxygen atoms from the surface oxide layer; the surface oxide layer is formed by oxidation treatment of the two-dimensional semiconductor material of the source contact region and the drain contact region; The source metal electrode and the drain metal electrode are respectively disposed on the oxide structure layer above the source contact region and the drain contact region.

2. The two-dimensional material transistor according to claim 1, characterized in that, The two-dimensional semiconductor material layer is a transition metal chalcogenide, selected from either MoSe2 or WSe2.

3. The two-dimensional material transistor according to claim 1, characterized in that, The oxygen-extracting metal is any one of Ti, Zr, and Hf, and the first metal oxide is TiO. x ZrO x or HfO x When the two-dimensional semiconductor material layer is MoS2 or WS2, the low-valence transition metal oxides are respectively MoO2, WO2, or their non-stoichiometric forms.

4. The two-dimensional material transistor according to claim 1, characterized in that, The total thickness of the oxide structure layer is 1 nm to 10 nm; the source metal electrode and the drain metal electrode are made of Au, Pd, Cu or their alloys; the substrate is SiO2 / Si, Al2O3, sapphire or a polymer flexible substrate.

5. The method for fabricating a two-dimensional material transistor according to any one of claims 1-4, characterized in that, Includes the following steps: Step 1: Provide a substrate and form a two-dimensional semiconductor material layer on the substrate; Step 2: Selectively oxidize the regions on the two-dimensional semiconductor material layer that are intended to form source and drain contact regions, so as to form surface oxide layers on the surfaces of the source and drain contact regions. Step 3: Deposit an oxygen-exclusion metal layer on the entire surface of the two-dimensional semiconductor material layer; Step four involves causing the oxygen-abstracting metal layer to undergo an oxygen-abstracting reaction with the surface oxide layer on the surface of the source contact region and the drain contact region. This results in the oxygen-abstracting metal layer located in the source contact region and the drain contact region being transformed into a first metal oxide upper layer, and the surface oxide layer being reduced to a low-valence transition metal oxide lower layer. This forms an oxide structure layer on the source contact region and the drain contact region, consisting of the first metal oxide upper layer and the low-valence transition metal oxide lower layer. Step 5: Remove the oxygen-abstracting metal layer located on the surface of the channel region, while retaining the oxide structure layer located on the surface of the source contact region and the drain contact region; Step 6: Form source metal electrodes and drain metal electrodes on the oxide structure layer above the source contact region and the drain contact region, respectively.

6. The method for fabricating a two-dimensional material transistor according to claim 5, characterized in that, The selective oxidation treatment is oxygen plasma treatment, thermal oxidation treatment, or chemical oxidation treatment; wherein the oxygen plasma treatment has a power of 20W to 80W, a treatment time of 10s to 120s, and a surface oxide layer thickness of 1nm to 5nm.

7. The method for fabricating a two-dimensional material transistor according to claim 5, characterized in that, The oxygen abstraction reaction is carried out in any of the following ways: Method 1: When depositing the oxygen-exclusion metal layer in step 3, the substrate is heated to 200°C to 300°C so that the oxygen-exclusion reaction in step 4 occurs simultaneously with the deposition of the oxygen-exclusion metal layer in step 3. Method 2: After depositing the oxygen-abstracting metal layer at room temperature, annealing is performed at 200°C to 400°C, during which the oxygen-abstracting reaction occurs; Method 3: Sequentially deposit at least two oxygen-exclusion metal layers, and perform at least one annealing treatment after each layer deposition to carry out multiple oxygen-exclusion reactions, forming a dense first metal oxide upper layer.

8. The method for fabricating a two-dimensional material transistor according to claim 7, characterized in that, The oxygen abstraction reaction or annealing treatment is carried out in an inert gas, reducing gas, or vacuum atmosphere; the thickness of the oxygen abstraction metal layer is 3 nm to 20 nm.

9. The method for fabricating a two-dimensional material transistor according to claim 5, characterized in that, After forming the source metal electrode and the drain metal electrode, the process further includes a secondary annealing process in an inert atmosphere or a reducing atmosphere, wherein the temperature of the secondary annealing process is 200°C to 400°C.

10. A method for fabricating a two-dimensional material transistor according to any one of claims 5 to 9, characterized in that, The material of the two-dimensional semiconductor material layer is any one of MoS2, WS2, MoSe2, and WSe2, and the material of the oxygen-extracting metal layer is any one of Ti, Zr, and Hf.

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