Semiconductor devices

Abstract

A semiconductor device capable of suppressing cell pitch constraints is provided. The semiconductor device of the embodiment includes a semiconductor component, a source electrode located on one side of the semiconductor component in a first direction, a plurality of field plate electrodes extending along the first direction, a gate electrode, and a gate wiring electrically connected to the gate electrode. The plurality of field plate electrodes are electrically connected to the source electrode and are disposed separately from each other at multiple locations. The gate electrode has a plurality of first extensions extending in a second direction. The gate wiring has a plurality of second extensions extending in the second direction. Each second extension is connected to each first extension at a position that is inside the formation region where the plurality of field plate electrodes are formed when viewed along the first direction, and extends from the portion connected to the first extension to one side in the second direction to a position that is outside the formation region when viewed along the first direction. The source electrode and the plurality of second extensions are disposed at different positions in the first direction.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2025-020720 (filed on February 12, 2025). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device. Background Technology

[0004] Semiconductor devices are known to have multiple field plate electrodes electrically connected to a source electrode. These multiple field plate electrodes are sometimes separately arranged at multiple locations along two directions that intersect and cross each other along the thickness direction of the semiconductor device. In such a semiconductor device, when viewed along the thickness direction of the semiconductor device, if a gate electrode is arranged outside the region where the multiple field plate electrodes are formed, it is possible that a voltage from the drain electrode is applied to the insulating film covering the gate electrode, causing insulation breakdown in the insulating film.

[0005] To address the aforementioned problems, a structure is sometimes employed where, when viewed along the thickness direction of the semiconductor device, a gate electrode is positioned inside a formation region where multiple field plate electrodes are formed, and the gate electrode is electrically connected to contact wiring formed outside the formation region via gate wiring. In this case, the gate electrode, for example, has multiple first extensions extending in a direction intersecting the thickness direction of the semiconductor device. The multiple first extensions are arranged at intervals in a direction intersecting both the direction in which the multiple first extensions extend and the thickness direction of the semiconductor device. The gate wiring has multiple second extensions extending from the outside to the inside of the formation region. The multiple second extensions are electrically connected to the multiple first extensions respectively.

[0006] In the aforementioned gate wiring, multiple second extensions are disposed, for example, in multiple gaps formed on the source electrode. In this case, to ensure the insulation distance between the source electrode and the multiple second extensions, the multiple second extensions need to be disposed with some degree of separation from the edges of the multiple gaps formed on the source electrode. Therefore, the spacing between the second extensions needs to be increased to the amount of gap between the edge of the gap and the multiple second extensions, thus limiting the spacing between the multiple second extensions. As a result, the spacing between the multiple first extensions to which the multiple second extensions are connected also becomes limited. Therefore, the spacing between the first extensions in the direction in which the multiple first extensions in the gate electrode are arranged, i.e., the cell pitch of the semiconductor device, is also limited. Consequently, it becomes difficult to reduce the on-resistance of the semiconductor device. Summary of the Invention

[0007] The problem to be solved by the present invention is to provide a semiconductor device that can suppress the limitation of cell pitch.

[0008] A semiconductor device according to an embodiment includes: a semiconductor component having a drift layer having a first conductivity type impurity; a source electrode located on one side of the semiconductor component in a first direction; a drain electrode located on the other side of the semiconductor component in the first direction; a plurality of field plate electrodes extending in the first direction, at least a portion of which are located inside the drift layer; a gate electrode, at least a portion of which is located inside the semiconductor component; and a gate wiring electrically connected to the gate electrode. The plurality of field plate electrodes are electrically connected to the source electrode, insulated from the semiconductor component by a first insulating film, and are disposed separately from each other at multiple locations along a second direction intersecting the first direction and a third direction intersecting both the first and second directions. The semiconductor component includes: a substrate layer located on one side of the drift layer in the first direction, having a second conductivity type impurity; and a source layer located on one side of the substrate layer in the first direction, having the first conductivity type impurity. The gate electrode has a plurality of first extensions extending in the second direction and is insulated from the semiconductor component by a second insulating film. The plurality of first extensions are arranged at intervals in the third direction. At least a portion of the gate electrode is disposed adjacent to the source layer and the substrate layer, separated by the second insulating film. The source layer is electrically connected to the source electrode. The source electrode extends along a plane orthogonal to the first direction. The gate wiring has a plurality of second extensions extending in the second direction. The plurality of second extensions are arranged at intervals in the third direction. Each second extension is connected to each first extension at a position that forms the inner side of the formation region of the plurality of field plate electrodes when viewed along the first direction, and extends from the portion connected to each first extension to one side of the second direction to a position that forms the outer side of the formation region when viewed along the first direction. The source electrode and the plurality of second extensions are disposed at different positions in the first direction. Attached Figure Description

[0009] Figure 1 This is a top view showing a portion of the semiconductor device according to the first embodiment. Figure 2 Section II in the diagram.

[0010] Figure 2 yes Figure 1 Sectional view II-II in the middle.

[0011] Figure 3 yes Figure 1 Section III-III in the diagram.

[0012] Figure 4 This is a top view with an enlarged view of the ends of the source electrode and gate wiring in the first embodiment.

[0013] Figure 5 This is a top view showing an enlarged view of the ends of the source electrode and gate wiring in the second embodiment.

[0014] Figure 6 This is a top view showing an enlarged view of the ends of the source electrode and gate wiring in the third embodiment. Detailed Implementation

[0015] Hereinafter, the semiconductor device according to the embodiments will be described with reference to the accompanying drawings. In the following description, structures having the same or similar functions are sometimes labeled with the same reference numerals. Also, repeated descriptions of these structures are sometimes omitted.

[0016] (First Implementation)

[0017] The configuration of the semiconductor device 1 in the first embodiment will be described below. Figure 1 This is a top view showing a portion of semiconductor device 1. Figure 2 yes Figure 1 Sectional view II-II in the middle. Figure 3 yes Figure 1 Section III-III in the diagram.

[0018] In the following explanation, Figure 1 Let the vertical direction of the paper be the X direction, and then... Figure 1 The left-right direction of the paper in the image is set as the Y direction, and it is then compared with... Figure 1 The direction orthogonal to the paper and to both the X and Y directions is defined as the Z direction for explanation. The Z direction is the thickness direction of semiconductor device 1. The X, Y, and Z directions are mutually orthogonal. In the following explanation, the Z direction is equivalent to the "first direction". The side in which the arrow indicating the Z direction points (+Z side) is equivalent to "one side of the first direction", and the side opposite to the side in which the arrow indicating the Z direction points (-Z side) is equivalent to "the other side of the first direction".

[0019] Figure 1 Semiconductor device 1 is a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). For example... Figure 1 and Figure 2 As shown, the semiconductor device 1 includes a semiconductor component 1A, a drain electrode 36, a source electrode 15, multiple field plate electrodes 6, a gate electrode 10, and a gate wiring 33.

[0020] Semiconductor component 1A is formed by adding impurities to semiconductor materials such as silicon (Si). For example... Figure 2 As shown, semiconductor component 1A includes: a drift layer 39 having an n-type impurity as a first conductivity type impurity; a substrate layer 7 located on the +Z side of the drift layer 39 having a p-type impurity as a second conductivity type impurity; a source layer 8 located on the +Z side of the substrate layer 7 having an n-type impurity as the first conductivity type impurity; and a surface field reduction layer (RESURF layer) 31 having a p-type impurity as the second conductivity type impurity. Alternatively, the first conductivity type impurity can also be a p-type impurity, and the second conductivity type impurity can also be an n-type impurity.

[0021] Drift layer 39, for example, is composed of n - A layer formed of p-type semiconductor. Substrate layer 7 is located on the +Z side of drift layer 39. Substrate layer 7 is a layer formed of p-type semiconductor. Source layer 8 is located on the +Z side of substrate layer 7. Source layer 8 is formed of n-type semiconductor. + A layer formed from a type of semiconductor.

[0022] Furthermore, in this specification, the term "n" is used for semiconductors. + Type", n-type", n - The term "n-type" indicates the relative magnitudes of the n-type carrier concentrations in a semiconductor. + Compared to "n-type" semiconductors, "n-type" semiconductors have a higher carrier concentration. - Compared to "n-type" semiconductors, "n-type" semiconductors have a lower carrier concentration. "Carrier concentration" refers to the effective impurity concentration that contributes to the conductivity of a semiconductor material; in a region containing both donor and acceptor impurities, it is equivalent to a net impurity concentration after removing the offsetting factors. In the first embodiment, n-type semiconductors have a lower carrier concentration. + The source layer 8 formed by the type of semiconductor and the n - Compared to the drift layer 39 formed by the n-type semiconductor, the impurity concentration, i.e. the carrier concentration, is relatively high in the n-type.

[0023] Semiconductor component 1A has multiple field plate trenches (hereinafter referred to as FP trenches 4) and gate trenches 23. For example... Figure 1 As shown, the plurality of FP trenches 4 are arranged in a dotted pattern when viewed along the thickness direction (Z direction) of the semiconductor device 1. In the first embodiment, the plurality of FP trenches 4 are arranged in a matrix pattern, separated from each other along the X and Y directions, at multiple locations on the semiconductor component 1A when viewed along the Z direction. The shape of each FP trench 4 is not particularly limited when viewed along the Z direction. Figure 2 As shown, the FP trench 4 is formed by recessing from the +Z side of the semiconductor component 1A toward the -Z side. The ends of the FP trenches 4 on the -Z side are located closer to the -Z side than the source layer 8 and the substrate layer 7. The portions of the FP trenches 4 on the -Z side are formed in the drift layer 39.

[0024] like Figure 1 As shown, the FP trenches 4 located at both ends in the X direction and the FP trenches 4 located at both ends in the Y direction, which are arranged in a matrix, are referred to as first FP trenches 4A. The multiple first FP trenches 4A, viewed along the Z direction, are arranged to surround the multiple FP trenches 4 other than the first FP trenches 4A. The other multiple FP trenches 4 surrounded by the multiple first FP trenches 4A, viewed along the Z direction, are referred to as second FP trenches 4B.

[0025] like Figure 2 As shown, a field plate insulating film 5 and a field plate electrode 6 are formed inside each FP trench 4. The field plate electrode 6 extends in the Z direction. At least a portion of the field plate electrode 6 is located inside the drift layer 39. In the first embodiment, the portion of the field plate electrode 6 located on the -Z side relative to the substrate layer 7 is located inside the drift layer 39. The +Z side end of the field plate electrode 6 is connected to the plate contact 16 described later.

[0026] Multiple field plate electrodes 6 are electrically connected to source electrodes 15. In the first embodiment, the +Z side ends of the multiple field plate electrodes 6 are electrically connected to the source electrodes 15 via multiple plate contacts 16. The multiple plate contacts 16 are made of metal. The multiple plate contacts 16 are formed, for example, of a Ti / TiN / W laminate. The multiple plate contacts 16 may also be made of other metals. The plate contacts 16 penetrate the insulating film 42 (described later) in the Z direction, electrically connecting the source electrodes 15 and the field plate electrodes 6. The source electrodes 15 are electrically connected to the field plate electrodes 6 in the multiple FP trenches 4 via the multiple plate contacts 16.

[0027] A field plate insulating film 5 is disposed in the portion of each FP trench 4 other than the portion where the field plate electrode 6 is disposed. Each field plate insulating film 5 is disposed between the inner surface of each FP trench 4 and each field plate electrode 6. The field plate insulating film 5 is, for example, a silicon oxide film. Each field plate electrode 6 is embedded in the semiconductor component 1A in a state of insulation from the semiconductor component 1A through each field plate insulating film 5. In the first embodiment, the field plate insulating film 5 is equivalent to a "first insulating film".

[0028] In the first embodiment, the edges of the substrate layer 7 and the source layer 8 on the +X side are positioned in the same X direction as the center portion of the field electrode 6 in the field plate electrode 6 located in the second FP trench 4B closest to the +X side. The edges of the substrate layer 7 and the source layer 8 on the +Y side are positioned in the same Y direction as the center portion of the field electrode 6 in the field plate electrode 6 located in the field plate electrode 6 located in the field plate electrode 6 located in the field plate electrode 4B closest to the +Y side. Although not shown in the figure, the edges of the substrate layer 7 and the source layer 8 on the -X side are positioned in the same X direction as the center portion of the field plate electrode 6 in the field plate electrode 6 located in the field plate electrode 6 located in the field plate electrode 6 located in the field plate electrode 4B closest to the -X side. Although not shown in the figure, the edges of the substrate layer 7 and the source layer 8 on the -Y side are positioned in the same Y direction as the center portion of the field plate electrode 6 in the field plate electrode 6 located in the field plate electrode 6 located in the field plate electrode 4B closest to the -Y side.

[0029] The surface electric field reduction layer 31 has p-type impurities as the second conductivity type impurity. The surface electric field reduction layer 31 is composed of p-type impurities. - A layer formed from a type of semiconductor. For example... Figure 2 As shown, the surface electric field reduction layer 31 is stacked on the +Z side of the drift layer 39. When viewed along the Z direction, the surface electric field reduction layer 31 is located outside the substrate layer 7 and the source layer 8. When viewed along the Z direction, the surface electric field reduction layer 31 surrounds the substrate layer 7 and the source layer 8. When viewed from the Z direction, the outer edge of the surface electric field reduction layer 31 is located further outward than the formation region 2 described later, surrounding the formation region 2. The surface electric field reduction layer 31 is not a necessary structure and can be omitted, but when the surface electric field reduction layer 31 is provided, an increase in the breakdown voltage of the semiconductor device 1 can be expected, and therefore it is preferred.

[0030] Furthermore, in this specification, the term "p" is used for semiconductors. + "Type", "p type", "p" - The term "p-type" indicates the relative magnitudes of the p-type carrier concentrations in a semiconductor. + Compared to p-type semiconductors, p-type semiconductors have a higher carrier concentration. - Compared to p-type semiconductors, p-type semiconductors have a lower carrier concentration. - Compared to the substrate layer 7 formed by a p-type semiconductor, the p-type impurity concentration, i.e., carrier concentration, is relatively low in the p-type semiconductor-formed surface electric field-reducing layer 31.

[0031] like Figure 1 As shown, when viewed along the Z-direction, source contacts 14 are formed around the field plate electrodes 6. The source contacts 14 are made of metal. For example, the source contacts 14 are formed of a Ti / TiN / W laminated film. The source contacts 14 can also be made of other metals. Each source contact 14 surrounds the upper end of each field plate insulating film 5. Figure 2As shown, each source contact 14 extends from the source electrode 15 toward the -Z side. Each source contact 14 penetrates the insulating film 42 (described later) in the Z direction. Each source contact 14 surrounds the +Z side end of the field plate electrode 6 and the plate contact 16. The -Z side end of the source contact 14 disposed relative to the field plate electrode 6 in the second FP trench 4B penetrates the source layer 8 and is electrically connected to the +Z side surface of the substrate layer 7. The portion of the source contact 14 disposed relative to the field plate electrode 6 in the second FP trench 4B that penetrates the source layer 8 is electrically connected to the source layer 8. Thus, the substrate layer 7 and the source layer 8 are electrically connected to the source electrode 15 via the source contact 14. The -Z side end of the source contact 14 disposed relative to the field plate electrode 6 in the first FP trench 4A is connected to the surface field reduction layer 31.

[0032] like Figure 1 As shown, a formation region 2 is provided in the semiconductor device 1, which forms multiple field plate electrodes 6 when viewed along the Z direction. Figure 1 In the diagram, the formed region 2 is indicated by a double-dotted line. In the first embodiment, the formed region 2 is a region in which a plurality of field plate electrodes 6 and portions thereof are arranged in a matrix when viewed along the Z direction. In the first embodiment, each portion of the plurality of field plate electrodes 6 includes a field plate insulating film 5 and a source contact 14. In the first embodiment, the outer edge of the formed region 2 is defined by the outer edge of the source contact 14 disposed for the field plate electrodes 6 within the plurality of first FP trenches 4A when viewed along the Z direction. When viewed along the Z direction, the edge of the formed region 2 on the +X side extends in the Y direction through the edge of the source contact 14 disposed at the end on the +X side. When viewed along the Z direction, the edge of the formed region 2 on the +Y side extends in the X direction through the edge of the source contact 14 disposed at the end on the +Y side.

[0033] like Figure 2 As shown, the drain electrode 36 is located on the -Z side of the semiconductor component 1A. More specifically, the drain electrode 36 is located on the -Z side of the drift layer 39 in the semiconductor component 1A. The drain electrode 36 is made of metal. For example, the drain electrode 36 is formed of aluminum. The drain electrode 36 may also be made of a metal other than aluminum, such as copper. For example, the drain electrode 36 may also be formed of a Cu / Al / Ni laminated film. In addition, a metal film formed of Ti / TiN laminated film or the like may be provided as a barrier metal between the drain electrode 36 and the surface on the -Z side of the semiconductor component 1A.

[0034] A protective film 32 and an insulating film 42 are formed on the +Z side of the semiconductor device 1A. The protective film 32 is formed entirely on the +Z side of the semiconductor device 1A in the formation region 2, except for the portion where the gate trench 23 is formed. The protective film 32 is formed on the +Z side surface of the surface reducing layer 31 and the source layer 8 in the formation region 2. The protective film 32 is formed on the third insulating film 38 (described later) outside the formation region 2. The thickness of the portion 32b of the protective film 32 formed on the third insulating film 38 is thinner than the thickness of the portion 32a of the protective film 32 formed on the +Z side surface of the surface reducing layer 31 and the source layer 8. The protective film 32 is formed, for example, of silicon nitride (SiN). By configuring the protective film 32, ions and the like that that affect reliability can be blocked, thus improving the reliability of the semiconductor device 1. Alternatively, the protective film 32 may not have portion 32a.

[0035] The insulating film 42 is, for example, a film formed of a silicon compound. The insulating film 42 is, for example, a TEOS film formed using tetraethoxysilane (TEOS) as a raw material. The insulating film 42 is formed, for example, using plasma CVD (Chemical Vapor Deposition). The insulating film 42 is located on the +Z side of the protective film 32. The insulating film 42 is stacked on the +Z side of the protective film 32. The thickness of the insulating film 42 in the Z direction is greater than the thickness of the protective film 32 in the Z direction. An active electrode 15 is formed on the +Z side surface of the insulating film 42.

[0036] The source electrode 15 is located on the +Z side of the semiconductor component 1A. The source electrode 15 extends along a surface orthogonal to the Z direction. Figure 1 As shown, the source electrode 15 is positioned to contact the field plate electrodes 6 within the plurality of first FP trenches 4A. The source electrode 15 is made of metal. For example, the source electrode 15 is formed of a Ti / TiN / W laminated film. The source electrode 15 can also be made of other metals such as aluminum or copper. For example, the source electrode 15 can also be formed of a Cu / Al / Ni laminated film. Furthermore, a metal film formed of a Ti / TiN laminated film or the like can be provided as a barrier metal between the source electrode 15 and the +Z side surface of the semiconductor component 1A. Figure 2 As shown, a contact wiring 35S is formed on the +Z side surface of the source electrode 15. The contact wiring 35S is made of metal. For example, the contact wiring 35S is formed of aluminum. The contact wiring 35S may also be made of a metal other than aluminum, such as copper. The contact wiring 35S is electrically connected to the source electrode 15. The contact wiring 35S is exposed on the surface of the semiconductor device 1. Figure 1 In the diagram, the source electrode 15 and the contact wiring 35S are represented by a double-dotted line.

[0037] like Figure 1As shown, when viewed along the Z direction, a plurality of gap portions 15a extending toward the -X side are formed on the edge of the source electrode 15 on the +X side. The plurality of gap portions 15a are arranged at intervals in the Y direction. The ends of the plurality of gap portions 15a on the -X side overlap with the forming region 2 when viewed along the Z direction. The ends of the plurality of gap portions 15a on the -X side are located closer to the +X side than the field plate electrodes 6 within the plurality of second FP trenches 4B. When viewed from the Z direction, the plurality of gap portions 15a are respectively disposed between the field plate electrodes 6 in adjacent first FP trenches 4A in the Y direction. When viewed from the Z direction, the portion of the edge of the source electrode 15 on the +X side other than the portion where the gap portions 15a are formed is located closer to the +X side than the forming region 2.

[0038] Viewed from the Z direction, a plurality of gaps 15b extending toward the -Y side are formed on the edge of the source electrode 15 on the +Y side. The plurality of gaps 15b are arranged at intervals in the X direction. The ends of the plurality of gaps 15b on the -Y side overlap with the forming region 2 when viewed along the Z direction. The ends of the plurality of gaps 15b on the -Y side are located closer to the +Y side than the field plate electrodes 6 within the plurality of second FP trenches 4B. Viewed from the Z direction, the plurality of gaps 15b are respectively disposed between the field plate electrodes 6 in adjacent first FP trenches 4A in the X direction. Viewed from the Z direction, the portion of the edge of the source electrode 15 on the +Y side, excluding the portion where the gaps 15b are formed, is located closer to the +Y side than the forming region 2. A portion of a nitride film 40 is formed inside each gap 15a, 15b.

[0039] like Figure 2 As shown, a nitride film 40 is formed on the surface of the insulating film 42 on the +Z side, excluding the portion where the active electrode 15 is formed. The nitride film 40 is formed, for example, from silicon nitride. The nitride film 40 is formed, for example, using plasma CVD. Contact wiring 35GX is formed on the surface of the nitride film 40 on the +Z side. Contact wiring 35GX is made of metal. Contact wiring 35GX is formed, for example, from aluminum. Contact wiring 35GX can also be made of a metal other than aluminum, such as copper. Contact wiring 35GX is exposed on the surface of the semiconductor device 1. In addition, although not shown in the figure, contact wiring 35GY is formed on the surface of the nitride film 40 on the +Z side. The material forming contact wiring 35GY is the same as the material forming contact wiring 35GY. Contact wiring 35GY is exposed on the surface of the semiconductor device 1. Furthermore, in Figure 1 In the diagram, contact wiring 35GX and contact wiring 35GY are represented by double-dotted lines.

[0040] Gate trench 23 is formed by recessing from the +Z side of semiconductor component 1A toward the -Z side. For example... Figure 1As shown, in the first embodiment, the gate trench 23 is configured as a lattice structure in which a plurality of first trench portions 23a, extending in the X direction and spaced apart in the Y direction when viewed along the Z direction, intersect with a plurality of second trench portions 23b, extending in the Y direction and spaced apart in the X direction. The entire gate trench 23 overlaps with the forming region 2 when viewed along the Z direction. The +X side ends of the plurality of first trench portions 23a are located on the +X side compared to the field plate electrodes 6 located in the plurality of second FP trenches 4B closest to the +X side. The +Y side ends of the plurality of second trench portions 23b are located on the +Y side compared to the field plate electrodes 6 located in the plurality of second FP trenches 4B closest to the +Y side.

[0041] like Figure 3 As shown, the gate electrode 10 and the gate insulating film 9 are located inside the gate trench 23. At least a portion of the gate electrode 10 is located inside the semiconductor device 1A. The gate electrode 10 is formed, for example, from polysilicon. Alternatively, the gate electrode 10 may also be formed from a metal such as tungsten. When the gate electrode 10 is formed from a metal such as tungsten, the high-temperature heat treatment performed during the manufacture of the semiconductor device 1 is performed before the gate electrode 10 is formed. The high-temperature heat treatment is, for example, a heat treatment at a temperature higher than 100°C. Figure 1 As shown, the gate electrode 10 has a plurality of first extensions 10a and a plurality of first extensions 10b. The plurality of first extensions 10a extend in the X direction and are arranged at intervals in the Y direction. The plurality of first extensions 10b extend in the Y direction and are arranged at intervals in the X direction. The gate electrode 10 is configured in a lattice shape where the plurality of first extensions 10a extending in the X direction and arranged at intervals in the Y direction intersect with the plurality of first extensions 10b extending in the Y direction and arranged at intervals in the X direction when viewed along the Z direction. The plurality of first extensions 10a are located inside the plurality of first trench portions 23a. The plurality of first extensions 10b are located inside the plurality of second trench portions 23b. When viewed along the Z direction, the entire gate electrode 10 overlaps with the forming region 2. The +X side ends of the plurality of first extensions 10a are located on the +X side compared to the field plate electrodes 6 located in the plurality of second FP trenches 4B closest to the +X side. The +Y side ends of the plurality of first extensions 10b are located on the +Y side compared to the field plate electrodes 6 located within the plurality of second FP trenches 4B closest to the +Y side. For example... Figure 2 As shown, an insulating film 42 is formed on the +Z side of the gate electrode 10.

[0042] The gate insulating film 9 is, for example, a silicon oxide film. The gate insulating film 9 is, for example, a film formed from a silicon compound. The gate insulating film 9 is, for example, a TEOS film formed from tetraethoxysilane. The gate insulating film 9 is, for example, formed using plasma CVD. The gate insulating film 9 is formed on the entire inner surface of the gate trench 23. The gate insulating film 9 is connected to the insulating film 42. The gate electrode 10 is buried in the semiconductor device 1A in a state of insulation from the semiconductor device 1A through the gate insulating film 9. In the first embodiment, the gate insulating film 9 is equivalent to a "second insulating film". At least a portion of the gate electrode 10 is disposed adjacent to the source layer 8 and the substrate layer 7 through the gate insulating film 9. In the first embodiment, the central portion of each first extension 10a in the Z direction is disposed adjacent to the source layer 8 and the substrate layer 7 in the Y direction through the gate insulating film 9. The central portion of each first extension 10b in the Z direction is disposed adjacent to the source layer 8 and the substrate layer 7 in the X direction through the gate insulating film 9. In the first embodiment, the gate electrode 10, which is formed in a lattice shape, disconnects the source layer 8 and the base layer 7.

[0043] Semiconductor device 1 includes a gate wiring 33 electrically connected to a gate electrode 10. The gate wiring 33 is formed, for example, of polysilicon. Alternatively, the gate wiring 33 may also be made of a metal, for example, of tungsten. The gate wiring 33 may also be made of a metal other than tungsten. In the case where the gate wiring 33 is formed of a metal such as tungsten, the high-temperature heat treatment performed during the manufacture of semiconductor device 1 is performed before the formation of the gate wiring 33. Figure 1 As shown, in the first embodiment, a plurality of gate wirings 33 are provided. The plurality of gate wirings 33 include gate wirings 33X connected to a plurality of first extensions 10a and gate wirings 33Y connected to a plurality of first extensions 10b. Gate wiring 33Y is identical to gate wiring 33X except that its orientation relative to gate wiring 33X when viewed along the Z direction is rotated 90° about an axis extending along the Z direction and that it is connected to the plurality of first extensions 10b. Therefore, in the following description, gate wiring 33X will be described using gate wirings 33X and 33Y as examples, and the description of gate wiring 33Y will sometimes be omitted. Furthermore, in Figure 1 In the diagram, double-dotted lines are used to represent gate wirings 33X and 33Y.

[0044] The gate wiring 33X has a base 33a and a plurality of second extensions 33b. The base 33a of the gate wiring 33X extends along the Y direction. When viewed along the Z direction, the base 33a is located outside the forming region 2. The plurality of second extensions 33b extend along the X direction. The plurality of second extensions 33b extend from the base 33a toward the -X side. The plurality of second extensions 33b are arranged at intervals in the Y direction. When viewed along the Z direction, the field plate electrodes 6 in adjacent first FP trenches 4A in the Y direction extend toward each other in the X direction. The -X side portion of each second extension 33b overlaps with the forming region 2 when viewed along the Z direction. The -X side end of each second extension 33b is located further toward the -X side than the field plate electrodes 6 in the plurality of first FP trenches 4A disposed on the +X side. At least a portion of each second extension 33b overlaps with each gap portion 15a when viewed along the Z direction. Therefore, the amount by which the second extension 33b overlaps with the gap 15a when viewed along the Z direction can be reduced. This reduces the parasitic capacitance between the source electrode 15 and the gate wiring 33X. In the first embodiment, a portion of the -X side of each second extension 33b overlaps with each gap 15a formed on the source electrode 15 when viewed along the Z direction.

[0045] like Figure 3 As shown, each second extension 33b is located on the +Z side relative to the gate electrode 10. Each second extension 33b is positioned differently from the source electrode 15 in the Z direction. In the first embodiment, each second extension 33b is located on the -Z side relative to the source electrode 15. Each second extension 33b is electrically connected to the gate electrode 10 via a contact 41. The contact 41 is formed, for example, of polysilicon. Alternatively, the contact 41 may also be made of a metal such as tungsten. When the contact 41 is formed of a metal such as tungsten, the high-temperature heat treatment performed during the manufacture of the semiconductor device 1 is performed before the contact 41 is formed. In the first embodiment, the +X side end of each first extension 10a is electrically connected to the -X side end of each second extension 33b via the contact 41. The +X side end of the first extension 10a is located inside the formation region 2 when viewed along the Z direction. That is, each second extension 33b, when viewed along the Z direction, is located inside the formation region 2 where multiple field plate electrodes 6 are formed, and is connected to each first extension 10a of the gate electrode 10. Each second extension 33b extends from the portion of the gate electrode 10 connected to each first extension 10a toward the +X side to a position outside the formation region 2 when viewed along the Z direction.

[0046] The base 33a is positioned in the Z direction at the same location as the second extension 33b. Alternatively, the base 33a may be positioned differently in the Z direction from the second extension 33b. The base 33a is electrically connected to the contact wiring 35GX via a contact 34X. The contact 34X is made of, for example, metal. The contact 34X is formed, for example, of a Ti / TiN / W laminate. The contact 34X may also be made of other metals. The gate wiring 33X, positioned outside the forming region 2 when viewed along the Z direction, is connected to the contact wiring 35GX via the contact 34X. The contact 34X is electrically connected to the contact wiring 35GX by penetrating the nitride film 40 in the Z direction. The gate wiring 33X is connected to the contact wiring 35GX via the contact 34X. Thus, the contact wiring 35GX is electrically connected to the gate electrode 10 via the contact 34X, the gate wiring 33X, and the contact 41.

[0047] like Figure 1 As shown, the gate wiring 33Y has a base 33c and a plurality of second extensions 33d. Although not shown, each second extension 33d is electrically connected to the gate electrode 10 via a contact, just like each second extension 33b. The plurality of second extensions 33d are connected to the plurality of first extensions 10b respectively. The base 33c of the gate wiring 33Y and the base 33a of the gate wiring 33X are electrically connected to the contact wiring 35GY via a contact 34Y. The material forming the contact 34Y is, for example, the same as the material forming the contact 34X. The position where the gate wiring 33Y is located outside the formation region 2 when viewed along the Z direction is connected to the contact wiring 35GY via the contact 34Y. Although not shown, the contact 34Y is electrically connected to the contact wiring 35GY through the nitride film 40 in the Z direction. The gate wiring 33Y is connected to the contact wiring 35GY via the contact 34Y. Thus, the contact wiring 35GY is electrically connected to the gate electrode 10 via the contact 34Y, the gate wiring 33Y, and a contact not shown.

[0048] Furthermore, in gate wiring 33X, the X direction corresponds to the "second direction" intersecting the first direction, and the Y direction corresponds to the "third direction" intersecting both the first and second directions. In gate wiring 33X, the side towards which the arrow representing the X direction points (+X side) corresponds to "one side of the second direction," and the side opposite to the side towards which the arrow representing the X direction points (-X side) corresponds to "the other side of the second direction." On the other hand, in gate wiring 33Y, the Y direction corresponds to the "second direction" intersecting the first direction, and the X direction corresponds to the "third direction" intersecting both the first and second directions. In gate wiring 33Y, the side towards which the arrow representing the Y direction points (+Y side) corresponds to "one side of the second direction," and the side opposite to the side towards which the arrow representing the Y direction points (-Y side) corresponds to "the other side of the second direction."

[0049] For example, consider the case where each second extension 33b of the gate wiring 33X is connected to each first extension 10a of the gate electrode 10 at a position that is inside the formation region 2 when viewed along the Z direction, and the Z-direction positions of the source electrode 15 and the second extension 33b are the same. In this case, for example, consider forming each second extension 33b in each gap 15a formed on the source electrode 15 to avoid short circuits between the source electrode 15 and the second extension 33b, and connecting the second extension 33b to the gate electrode 10 at a position that is inside the formation region 2 when viewed along the Z direction. However, in this case, to avoid short circuits, the edges of the gaps 15a of the source electrode 15 in the Y direction and the edges of the second extensions 33b in the Y direction need to be sufficiently separated. Therefore, the Y-direction spacing between the edges of the gaps 15a of the source electrode 15 and the edges of the second extensions 33b in the Y direction needs to be set to a certain degree of largeness. Therefore, without changing the width of the second extension 33b in the Y direction, it is necessary to increase the Y-direction spacing between the edges of each gap 15a and the edges of the second extension 33b in the Y direction, and correspondingly, it is necessary to increase the Y-direction spacing between the second extensions 33b. As a result, it becomes difficult to reduce the Y-direction spacing between the second extensions 33b. Consequently, it is difficult to reduce the Y-direction spacing between the plurality of first extensions 10a of the gate electrode 10, and difficult to reduce the cell spacing in the semiconductor device 1.

[0050] In contrast, in the first embodiment, the source electrode 15 and the plurality of second extensions 33b are arranged at different positions in the Z direction. That is, the source electrode 15 and the plurality of second extensions 33b are arranged at different layer levels. Therefore, the source electrode 15 and the plurality of second extensions 33b can be arranged without considering short circuits. As a result, the edges of the plurality of second extensions 33b in the Y direction can be freely arranged relative to the edge of the gap 15a in the Y direction, and the Y-direction spacing between the plurality of second extensions 33b can be reduced. Therefore, without changing the width of the plurality of second extensions 33b in the Y direction, the Y-direction spacing of the plurality of second extensions 33b can be reduced, and the constraint on the Y-direction spacing of the plurality of second extensions 33b can be suppressed. Therefore, the Y-direction spacing between the plurality of first extensions 10a that respectively connect the plurality of second extensions 33b can be reduced, and the cell spacing in the semiconductor device 1 can be reduced. Thus, according to the first embodiment, the constraint on the cell spacing in the semiconductor device 1 can be suppressed.

[0051] Figure 4 This is a top view showing an enlarged view of the end of the source electrode 15 and the gate wiring 33X. In the first embodiment, as... Figure 4As shown, at least a portion of each second extension 33b overlaps with the source electrode 15 when viewed along the Z direction. Therefore, compared to the case where the entire configuration of each second extension 33b does not overlap with the source electrode 15 when viewed along the Z direction, it is possible to suppress constraints on the shape and width of each second extension 33b. Consequently, it is easier to increase the width of each second extension 33b and reduce the wiring resistance of the gate wiring 33X. In the first embodiment, the two edges in the Y direction of the portion of each second extension 33b disposed at the same position as the gap 15a in the X direction overlap with the source electrode 15 when viewed along the Z direction. Therefore, compared to the case where the entire second extension 33b does not overlap with the source electrode 15 when viewed along the Z direction, without changing the width of the second extension 33b in the Y direction, it is possible to further reduce the spacing in the Y direction of the plurality of second extensions 33b, and further suppress constraints on the cell spacing in the semiconductor device 1. Furthermore, compared to the case where the second extension 33b does not overlap with the source electrode 15 when viewed entirely along the Z direction, the width of the second extension 33b in the Y direction can be increased without changing the spacing of the second extension 33b. This reduces the resistance of the gate wiring 33X. Additionally, since a portion of the second extension 33b overlaps with the gap 15a when viewed along the Z direction, the increase in parasitic capacitance between the source electrode 15 and the gate wiring 33X can be suppressed compared to the case where the gap 15a is not formed.

[0052] In addition, Figure 4 In the source electrode 15 and the second extension 33b of the gate wiring 33X shown, parasitic capacitance is generated in the overlapping portions when viewed along the Z direction. However, if the effect of this parasitic capacitance in the semiconductor device 1 is so slight as to not affect the required operation of the semiconductor device 1, then it is possible to employ... Figure 4 The source electrode 15 and the second extension 33b of the gate wiring 33X are arranged as shown.

[0053] Here, for example, when the gate electrode 10 is connected to the gate wiring 33X outside the formation region 2 when viewed along the Z direction, the potential of the drain electrode 36 is applied to the gate electrode 10 via the drift layer 39, which is not depleted by the multiple field plate electrodes 6, and the gate insulating film 9. The gate insulating film 9 is often thinner than other insulating films, and if the potential of the drain electrode 36 is applied without depletion of the drift layer 39, insulation breakdown may occur. In contrast, by connecting the gate electrode 10 to the gate wiring 33X at a position inside the formation region 2 when viewed along the Z direction, the portion of the drift layer 39 positioned relative to the gate electrode 10 and sandwiching the gate insulating film 9 can be depleted using the multiple field plate electrodes 6. Therefore, the potential of the drain electrode 36 is not directly applied to the gate insulating film 9, and insulation breakdown of the gate insulating film 9 can be suppressed. When viewed along the Z-direction, there are no constraints such as the need to thin the insulating film to a certain extent, like the gate insulating film 9, at a position further out than where the gate electrode 10 is located. Therefore, an insulating film thicker than the gate insulating film 9 can be provided. Thus, a relatively thick insulating film can be provided between the portion of the gate wiring 33X located outside the formation region 2 and the drift layer 39 when viewed along the Z-direction. Therefore, even if the second extension 33b is located closer to the drift layer 39 in the Z-direction than the source electrode 15, the insulating film provided between the second extension 33b and the drift layer 39 can be thickened to the point that insulation breakdown does not occur.

[0054] like Figure 3 As shown, the semiconductor device 1 includes a third insulating film 38, at least a portion of which is located outside the formation region 2 when viewed along the Z direction. In the first embodiment, the third insulating film 38 is substantially entirely located outside the formation region 2 when viewed along the Z direction. The third insulating film 38 is located between the semiconductor component 1A and the plurality of second extensions 33b of the gate wiring 33X in the Z direction. In the first embodiment, the third insulating film 38 is located between the protective film 32 and the drift layer 39 in the Z direction. The thickness of the third insulating film 38 is thicker than the thickness of the gate insulating film 9. By distributing the third insulating film 38, which is thicker than the gate insulating film 9, between the semiconductor component 1A and the plurality of second extensions 33b in the Z direction, it is easier to ensure the insulation between the drift layer 39 and the gate wiring 33X. Therefore, it is possible to further suppress insulation breakdown between the gate wiring 33X and the drift layer 39.

[0055] The material of the third insulating film 38 is not particularly limited as long as it has insulating properties. For example, the third insulating film 38 can be made of the same material as the field plate insulating film 5. As an example, the field plate insulating film 5 is integrally formed as a silicon oxide film on the +Z side surface of the semiconductor component 1A where multiple FP trenches 4 are formed by thermal oxidation or CVD. Then, among the silicon oxide films provided in the FP trenches 4 other than the silicon oxide film, the silicon oxide film located on the outer side of the formation region 2 when viewed in the Z direction is retained, and the other silicon oxide films are removed by etching or the like. Thus, the third insulating film 38 can be easily configured without performing a separate film formation process.

[0056] Furthermore, if the plurality of second extensions 33b of the gate wiring 33X are configured at positions different from the source electrode 15 in the Z direction, the positional relationship between the portion of the gate wiring 33X other than the plurality of second extensions 33b and the source electrode 15 in the Z direction is not particularly limited. Each second extension 33b is connected to each first extension 10a of the gate electrode 10, and can be any structure as long as it extends from the inner side to the outer side of the forming region 2. For example, other portions connecting the plurality of second extensions 33b to the base 33a may also be formed in the gate wiring 33X, and these other portions and the base 33a may be configured at positions different from the plurality of second extensions 33b in the Z direction.

[0057] (Second Implementation)

[0058] The configuration of the semiconductor device 201 in the second embodiment will be described below. Figure 5 This is a top view showing an enlarged view of the source electrode 15 and the end of the gate wiring 233X in the second embodiment. In this figure, the... Figures 1 to 4 Elements that are identical to those in the semiconductor device 1 of the first embodiment are labeled with the same symbols, and their descriptions are omitted. The second embodiment differs from the first embodiment in the structure of the source electrode 15 and the gate wiring 233X.

[0059] like Figure 5As shown, in the gate wiring 233X, the portion of the second extension 233b disposed at the same position as the gap 15a in the X direction overlaps with the gap 15a when viewed in the Z direction. In the second embodiment, the entire second extension 233b does not overlap with the source electrode 15 when viewed in the Z direction. The width of the second extension 233b in the Y direction is smaller than the width of the gap 15a in the Y direction. Therefore, when viewed in the Z direction, the source electrode 15 and the second extension 233b are disposed at a distance. Similar to the second extension 33b in the first embodiment, the second extension 233b is disposed at a different position from the source electrode 15 in the Z direction, so insulation between the second extension 233b and the source electrode 15 does not need to be considered. Therefore, compared to the case where the second extension 233b and the source electrode 15 are disposed at the same position in the Z direction, the distance between the source electrode 15 and the second extension 233b when viewed in the Z direction can be reduced. Other structures are the same as those in the semiconductor device 1 of the first embodiment described above.

[0060] According to the second embodiment, the portion of the second extension 233b disposed at the same position as the gap 15a in the X direction (second direction) overlaps with the gap 15a when viewed in the Z direction. Therefore, parasitic capacitance between the source electrode 15 and the gate wiring 233X can be suppressed. Furthermore, according to the second embodiment, the second extension 233b does not overlap with the source electrode 15 when viewed in the Z direction. Therefore, parasitic capacitance between the source electrode 15 and the gate wiring 233X can be further suppressed.

[0061] (Third Implementation)

[0062] The configuration of the semiconductor device 301 in the third embodiment will be described below. Figure 6 This is a top view showing an enlarged view of the source electrode 15 and the end of the gate wiring 333X in the third embodiment. In this figure, the... Figures 1 to 4 The semiconductor device 1 of the first embodiment shown herein uses the same reference numerals for its constituent elements, and its description is omitted. The third embodiment differs from the first embodiment described above in the structure of the source electrode 15 and the gate wiring 333X.

[0063] like Figure 6As shown, in the gate wiring 333X, the width of the second extension 333b in the Y direction varies in the X direction. Each second extension 333b has a first portion 333e and a second portion 333f. The first portion 333e and the second portion 333f extend in the X direction. The first portion 333e is the -X side portion of the second extension 333b. The first portion 333e has a portion connected to the gate electrode 10. The +X side end of the first portion 333e is located on the +X side of the source electrode 15. The first portion 333e has a portion disposed in the X direction at the same position as the gap portion 15a. The width of the first portion 333e in the Y direction is less than or equal to the width of the gap portion 15a in the Y direction. In the third embodiment, the width of the first portion 333e in the Y direction is smaller than the width of the gap portion 15a in the Y direction. The entire portion of the first portion 333e disposed in the X direction at the same position as the gap portion 15a overlaps with the gap portion 15a when viewed along the Z direction. In other words, the first portion 333e does not overlap with the source electrode 15 when viewed along the Z direction. The second portion 333f is the +X side portion of the second extension 333b. The second portion 333f is connected to the end of the first portion 333e on the +X side. The second portion 333f is located closer to the +X side than the source electrode 15. The width of the second portion 333f in the Y direction is larger than the width of the first portion 333e in the Y direction. The width of the second portion 333f in the Y direction is larger than the width of the gap 15a in the Y direction. Other structures are the same as those in the semiconductor device 1 of the first embodiment described above.

[0064] According to the third embodiment, the portion of the first portion 333e that is positioned at the same location as the gap portion 15a in the X direction (second direction) overlaps with the gap portion 15a when viewed along the Z direction. The width of the second portion 333f in the Y direction (third direction) is greater than the width of the first portion 333e in the Y direction, and also greater than the width of the gap portion 15a in the Y direction. Therefore, parasitic capacitance between the source electrode 15 and the first portion 333e can be suppressed, and the wiring resistance in the gate wiring 333X can be reduced by increasing the second portion 333f in the Y direction.

[0065] According to at least one embodiment described above, a semiconductor device includes: a semiconductor component having a drift layer having a first conductivity type impurity; a source electrode located on one side of a first direction of the semiconductor component; a drain electrode located on the other side of the first direction of the semiconductor component; a plurality of field plate electrodes extending in the first direction, at least a portion of which is located inside the drift layer; a gate electrode located at least a portion of which is located inside the semiconductor component; and a gate wiring electrically connected to the gate electrode. The plurality of field plate electrodes are electrically connected to the source electrode, insulated from the semiconductor component by a first insulating film, and are disposed separately from each other at multiple locations along a second direction intersecting the first direction and a third direction intersecting both the first and second directions. The semiconductor component includes: a substrate layer located on one side of the drift layer in the first direction, having a second conductivity type impurity; and a source layer located on one side of the substrate layer in the first direction, having a first conductivity type impurity. The gate electrode has a plurality of first extensions extending in the second direction and is insulated from the semiconductor component by a second insulating film. The plurality of first extensions are arranged at intervals in a third direction. At least a portion of the gate electrode is disposed adjacent to the source layer and the substrate layer, separated by a second insulating film. The source layer is electrically connected to the source electrode. The source electrode extends along a plane orthogonal to a first direction. The gate wiring has a plurality of second extensions extending in a second direction. The plurality of second extensions are arranged at intervals in a third direction. Each second extension is connected to the first extension at a position that is inside the formation region where the plurality of field plate electrodes are formed when viewed along the first direction, and extends from the portion connected to each first extension to one side in the second direction to a position that is outside the formation region when viewed along the first direction. The source electrode and the plurality of second extensions are disposed at different positions in the first direction. Thus, short circuits between the source electrode and the plurality of second extensions of the gate wiring are not considered, and therefore, as described above, the constraint of cell spacing in the semiconductor device can be suppressed.

[0066] Furthermore, if at least a portion of the plurality of second extensions overlaps with the source electrode when viewed along the first direction, it is sufficient that at least a portion of one or more of the plurality of second extensions overlaps with the source electrode when viewed along the first direction. The portion of the second extension that overlaps with the source electrode when viewed along the first direction can be any part of the second extension. For example, the end of the second extension in the second direction may also overlap with the source electrode when viewed along the first direction.

[0067] The semiconductor device of this embodiment includes the following appendix.

[0068] (Postscript 1)

[0069] A semiconductor device comprising:

[0070] A semiconductor component having a drift layer having a first conductivity type impurity;

[0071] The source electrode is located on one side of the semiconductor component in a first direction;

[0072] The drain electrode is located on the other side of the first direction of the semiconductor component;

[0073] Multiple field plate electrodes extend in the first direction, with at least a portion located inside the drift layer;

[0074] The gate electrode, at least a portion of which is located inside the semiconductor component; and

[0075] The gate wiring is electrically connected to the gate electrode.

[0076] The plurality of field plate electrodes are electrically connected to the source electrode, insulated from the semiconductor component by a first insulating film, and are separately configured at multiple locations along a second direction intersecting the first direction and a third direction intersecting both the first and second directions.

[0077] The semiconductor component has:

[0078] A substrate layer, located on one side of the drift layer in the first direction, has a second type of conductivity impurity; and

[0079] The source layer, located on one side of the substrate layer in the first direction, has the first conductivity type impurity.

[0080] The gate electrode has a plurality of first extensions extending in the second direction, and is insulated from the semiconductor component by a second insulating film.

[0081] The plurality of first extensions are arranged at intervals on the third side.

[0082] At least a portion of the gate electrode is disposed adjacent to the source layer and the substrate layer, separated by the second insulating film.

[0083] The source layer is electrically connected to the source electrode.

[0084] The source electrode extends along a plane orthogonal to the first direction.

[0085] The gate wiring has a plurality of second extensions extending in the second direction.

[0086] The plurality of second extensions are arranged at intervals on the third side.

[0087] Each of the second extensions, when viewed along the first direction, is located inside the formation region where the plurality of field plate electrodes are formed, and is connected to each of the first extensions respectively. Furthermore, each extension extends from the portion connected to the first extension towards one side of the second direction to a position outside the formation region when viewed along the first direction.

[0088] The source electrode and the plurality of second extensions are configured at different positions in the first direction.

[0089] (Postscript 2)

[0090] According to the semiconductor device described in Appendix 1, wherein,

[0091] A plurality of gaps extending toward the other side of the second direction are formed on one side of the source electrode.

[0092] The plurality of gaps are arranged at intervals on the third side upwards.

[0093] At least a portion of each of the second extensions overlaps with each of the gap portions when viewed along the first direction.

[0094] (Note 3)

[0095] According to the semiconductor device described in Appendix 2, wherein,

[0096] When viewed along the first direction, the two edges of the third direction of each of the second extensions, which are arranged in the second direction at the same position as each of the gaps, overlap with the source electrode.

[0097] (Postscript 4)

[0098] According to the semiconductor device described in Appendix 2, wherein,

[0099] When viewed along the first direction, the portion of each of the second extensions that is positioned at the same location as each of the gap portions in the second direction overlaps with each of the gap portions.

[0100] (Note 5)

[0101] According to the semiconductor device described in Appendix 2, wherein,

[0102] Each of the second extension portions has:

[0103] The first portion has a portion connected to the first extension and extends in the second direction; and

[0104] The second part is connected to the end of the first part on one side in the second direction and extends in the second direction.

[0105] The second portion is located on the side further in the second direction than the source electrode.

[0106] The portion of the first part that is positioned in the second direction at the same location as the gap overlaps with the gap when viewed along the first direction.

[0107] The width of the third direction of the second part is larger than the width of the third direction of the first part, and also larger than the width of the third direction of the gap.

[0108] (Note 6)

[0109] According to the semiconductor device described in Appendix 1, wherein,

[0110] At least a portion of the plurality of second extensions overlaps with the source electrode when viewed along the first direction.

[0111] (Note 7)

[0112] The semiconductor device according to any one of Appendices 1, 4 and 5, wherein,

[0113] Each of the second extensions does not overlap with the source electrode when viewed along the first direction.

[0114] (Postscript 8)

[0115] The semiconductor device according to any one of Appendices 1 to 7, wherein,

[0116] The semiconductor device includes a third insulating film, at least a portion of which is located outside the formation region when viewed along the first direction.

[0117] The third insulating film is located between the semiconductor component and the plurality of second extensions in the first direction.

[0118] The thickness of the third insulating film is greater than the thickness of the second insulating film.

[0119] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are also included within the scope of the invention as described in the claims and their equivalents.

[0120] Explanation of reference numerals in the attached figures

[0121] 1, 201, 301… Semiconductor device, 1A… Semiconductor component, 2… Forming region, 5… Field plate insulating film (first insulating film), 6… Field plate electrode, 7… Substrate layer, 8… Source layer, 9… Gate insulating film (second insulating film), 10… Gate electrode, 10a, 10b… First extension, 15… Source electrode, 15a, 15b… Gap, 33, 33X, 33Y, 233X, 333X… Gate wiring, 33b, 33d, 233b, 333b… Second extension, 36… Drain electrode, 38… Third insulating film, 39… Drift layer, 42… Insulating film, 333e… First portion, 333f… Second portion.

Claims

1. A semiconductor device comprising: A semiconductor component having a drift layer having a first conductivity type impurity; The source electrode is located on one side of the semiconductor component in a first direction; The drain electrode is located on the other side of the first direction of the semiconductor component; Multiple field plate electrodes extend in the first direction, with at least a portion located inside the drift layer; The gate electrode, at least a portion of which is located inside the semiconductor component; as well as The gate wiring is electrically connected to the gate electrode. The plurality of field plate electrodes are electrically connected to the source electrode, insulated from the semiconductor component by a first insulating film, and are separately configured at multiple locations along a second direction intersecting the first direction and a third direction intersecting both the first and second directions. The semiconductor component has: The base layer, located on one side of the drift layer in the first direction, has a second type of conductivity impurity; as well as The source layer, located on one side of the substrate layer in the first direction, has the first conductivity type impurity. The gate electrode has a plurality of first extensions extending in the second direction, and is insulated from the semiconductor component by a second insulating film. The plurality of first extensions are arranged at intervals on the third side. At least a portion of the gate electrode is disposed adjacent to the source layer and the substrate layer, separated by the second insulating film. The source layer is electrically connected to the source electrode. The source electrode extends along a plane orthogonal to the first direction. The gate wiring has a plurality of second extensions extending in the second direction. The plurality of second extensions are arranged at intervals on the third side. Each of the second extensions, when viewed along the first direction, is located inside the formation region where the plurality of field plate electrodes are formed, and is connected to each of the first extensions respectively. Furthermore, each extension extends from the portion connected to the first extension towards one side of the second direction to a position outside the formation region when viewed along the first direction. The source electrode and the plurality of second extensions are configured at different positions in the first direction.

2. The semiconductor device according to claim 1, wherein, A plurality of gaps extending toward the other side of the second direction are formed on one side of the source electrode. The plurality of gaps are arranged at intervals on the third side upwards. At least a portion of each of the second extensions overlaps with each of the gap portions when viewed along the first direction.

3. The semiconductor device according to claim 2, wherein, When viewed along the first direction, the two edges of the third direction of each of the second extensions, which are arranged in the second direction at the same position as each of the gaps, overlap with the source electrode.

4. The semiconductor device according to claim 2, wherein, When viewed along the first direction, the portion of each of the second extensions that is positioned at the same location as each of the gap portions in the second direction overlaps with each of the gap portions.

5. The semiconductor device according to claim 2, wherein, Each of the second extension portions has: The first part has a portion connected to the first extension and extends in the second direction; as well as The second part is connected to the end of the first part on one side in the second direction and extends in the second direction. The second portion is located on the side further in the second direction than the source electrode. The portion of the first part that is positioned in the second direction at the same location as the gap overlaps with the gap when viewed along the first direction. The width of the third direction of the second part is larger than the width of the third direction of the first part, and also larger than the width of the third direction of the gap.

6. The semiconductor device according to claim 1, wherein, At least a portion of the plurality of second extensions overlaps with the source electrode when viewed along the first direction.

7. The semiconductor device according to claim 1, wherein, Each of the second extensions does not overlap with the source electrode when viewed along the first direction.

8. The semiconductor device according to any one of claims 1 to 7, wherein, The semiconductor device includes a third insulating film, at least a portion of which is located outside the formation region when viewed along the first direction. The third insulating film is located between the semiconductor component and the plurality of second extensions in the first direction. The thickness of the third insulating film is greater than the thickness of the second insulating film.

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