A power device
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-13
- Publication Date
- 2026-08-14
AI Technical Summary
而器件的反向恢复过程中，除有源区中存在大量电荷外，终端区同样会存在数量较大的载流子，而由于终端区的导通区域占比通常小于有源区，因此若未对终端区进行优化设计，器件在反向恢复过程中极易出现烧毁
[0022]本发明的技术效果是毋庸置疑的，本发明可在器件反向恢复阶段，增大流经CDS的位移电流比例，减小流经CDG和体区PN结的位移电流比例，进而减小栅极振荡和反向恢复烧毁的可能性，增强器件的反向恢复可靠性能力。
Smart Images
Figure CN122579655A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power semiconductor device technology, specifically a power device. Background Technology
[0002] Power semiconductor devices, as core components in power electronic systems, are used in a wide range of fields, including power grid systems, new energy vehicles, power management systems, and consumer electronics. Metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used in various power systems due to their advantages such as fast switching speed, low power consumption, easy gate drive, low drive power, high input impedance, and fast frequency response.
[0003] In practical power devices, because the periodic arrangement of edge cells is disrupted, the device is divided into an active region and a termination region. The termination region surrounds the active region and extends the electric field laterally to ensure the device's withstand voltage. During the reverse recovery process, in addition to the large amount of charge in the active region, the termination region also contains a large number of charge carriers. Since the conducting area of the termination region is usually smaller than that of the active region, if the termination region is not optimized, the device is very prone to burnout during the reverse recovery process. Summary of the Invention
[0004] The purpose of this invention is to provide a power device, including a source structure, an insulating dielectric layer structure, a gate structure, a drift region structure, and a drain structure;
[0005] The source structure includes a top metal layer, a first conductivity type ohmic contact region, a second conductivity type source region, a first conductivity type body region, and a source polycrystalline structure.
[0006] The second conductivity type source region and the first conductivity type ohmic contact region are arranged on top of the first conductivity type body region, and the second conductivity type source region is located on the side close to the gate structure.
[0007] The insulating dielectric layer structure isolates the gate polycrystalline structure and the source polycrystalline structure from the source region of the second conductivity type and the body region of the first conductivity type.
[0008] The drift region structure is located below the first conductivity type body region.
[0009] The drain structure includes a second conductivity type drain region and a drain metal layer.
[0010] The second conductivity type drain region is located below the drift region structure.
[0011] The lower surface of the drain region is in contact with the drain metal layer.
[0012] Furthermore, the gate structure includes a gate polycrystalline structure.
[0013] Furthermore, the insulating dielectric layer structure includes an insulating dielectric layer.
[0014] Furthermore, the drift region structure includes a second conductivity type drift region.
[0015] Furthermore, the source polycrystalline structure is connected to the source metal S in the top metal layer through contact holes.
[0016] Furthermore, the gate structure is isolated from the source metal S in the top metal layer through an insulating dielectric layer structure.
[0017] Furthermore, the source polycrystalline structure 702 is located on the side of the terminal area close to the active area, forming a displacement current control region.
[0018] Furthermore, the number of source pole polycrystalline structures is ≥1.
[0019] Furthermore, the first type of conductivity semiconductor in the source structure is doped with a P-type semiconductor, and the second type of conductivity semiconductor is an N-type semiconductor.
[0020] Alternatively, the first type of conductivity semiconductor may be doped with an N-type semiconductor, and the second type of conductivity semiconductor may be doped with a P-type semiconductor.
[0021] Furthermore, the substrate and epitaxial layer materials of the device are selected from any one or more combinations of silicon, silicon carbide, gallium nitride, gallium arsenide, indium phosphide, gallium oxide, or germanium silicon.
[0022] The technical effects of this invention are undeniable. This invention can increase the current flowing through C during the reverse recovery stage of the device. DS The proportion of displacement current, reducing the current flowing through C DG The ratio of displacement current in the PN junction of the body region is increased, thereby reducing the possibility of gate oscillation and reverse recovery burnout, and enhancing the reverse recovery reliability of the device. Attached Figure Description
[0023] Figure 1 This is a schematic diagram of a conventional MOSFET device structure in the background art of this invention.
[0024] Figure 2 The diagram shows the SGT structure and reverse recovery current distribution as referenced in this invention.
[0025] Figure 3 This is a schematic diagram of a MOSFET device structure according to Embodiment 1 of the present invention.
[0026] Figure 4 This is a schematic diagram of a MOSFET device structure according to Embodiment 2 of the present invention.
[0027] Figure 5 This is a schematic diagram of a MOSFET device structure according to Embodiment 3 of the present invention.
[0028] The markings in the figure are: 1-drain metal layer, 2-drain region of the second conductivity type, 3-epitaxy layer of the second conductivity type, 4-body region of the first conductivity type, 5-ohmic contact region of the first conductivity type, 6-source region of the second conductivity type, 701-gate polycrystalline structure, 702-source polycrystalline structure, 8-insulating dielectric layer, 9-top metal layer. Detailed Implementation
[0029] The present invention will be further described below with reference to embodiments, but it should not be construed that the scope of the present invention is limited to the following embodiments. Various substitutions and modifications made based on ordinary technical knowledge and common practices in the art without departing from the above-described technical concept of the present invention should be included within the scope of protection of the present invention.
[0030] Example 1:
[0031] A power device includes a source structure, an insulating dielectric layer structure, a gate structure, a drift region structure, and a drain structure;
[0032] The source structure includes a top metal layer 9, a first conductivity type ohmic contact region 5, a second conductivity type source region 6, a first conductivity type body region 4, and a source polycrystalline structure 702.
[0033] The second conductivity type source region 6 and the first conductivity type ohmic contact region 5 are arranged on top of the first conductivity type body region 4, and the second conductivity type source region 6 is located on the side close to the gate structure.
[0034] The insulating dielectric layer structure isolates the gate polycrystalline structure 701 and the source polycrystalline structure 702 from the second conductivity type source region 6 and the first conductivity type body region 4.
[0035] The drift region structure is located below the first conductivity type body region 4.
[0036] The drain structure includes a second conductivity type drain region 2 and a drain metal layer 1.
[0037] The second conductivity type drain region 2 is located below the drift region structure.
[0038] The lower surface of the drain region 2 is in contact with the drain metal layer 1.
[0039] Example 2:
[0040] A power device, with the same technical content as in Embodiment 1, further wherein the gate structure includes a gate polycrystalline structure 701.
[0041] Example 3:
[0042] A power device, with the same technical content as any one of Embodiments 1-2, further wherein the insulating dielectric layer structure includes an insulating dielectric layer 8.
[0043] Example 4:
[0044] A power device, with the same technical content as any one of embodiments 1-3, further wherein the drift region structure includes a second conductivity type drift region 3.
[0045] Example 5:
[0046] A power device, with the same technical content as any one of embodiments 1-4, further wherein the source polycrystalline structure 702 is connected to the source metal S in the top metal layer 9 through a contact hole.
[0047] Example 6:
[0048] A power device, with the same technical content as any one of embodiments 1-5, further wherein the gate structure is isolated from the source metal S in the top metal layer 9 through an insulating dielectric layer structure.
[0049] Example 7:
[0050] A power device, with the same technical content as any one of embodiments 1-6, further wherein the source polycrystalline structure 702 is located on the side of the terminal area close to the active area, forming a displacement current control region.
[0051] The number of source polycrystalline structures 702 is ≥1.
[0052] Example 8:
[0053] A power device, with the same technical content as any one of embodiments 1-7, further wherein the first type of conductivity semiconductor in the source structure is doped with a P-type semiconductor and the second type of conductivity semiconductor is an N-type semiconductor.
[0054] Alternatively, the first type of conductivity semiconductor may be doped with an N-type semiconductor, and the second type of conductivity semiconductor may be doped with a P-type semiconductor.
[0055] Example 9:
[0056] A power device, with the same technical content as any one of Embodiments 1-8, further wherein the substrate layer and epitaxial layer material of the device are selected from any one or more combinations of silicon, silicon carbide, gallium nitride, gallium arsenide, indium phosphide, gallium oxide, or germanium silicon.
[0057] Example 10:
[0058] Taking a MOSFET device as an example, a power device includes a source structure, an insulating dielectric layer structure, a gate structure, a drift region structure, and a drain structure.
[0059] The source structure includes a top metal layer 9, a first conductivity type ohmic contact region 5, a second conductivity type source region 6, a first conductivity type body region 4, and a source polycrystalline structure 702; wherein the source region 6 and the ohmic contact region 5 are arranged on top of the body region 4, and the source region 6 is located on the side close to the gate structure.
[0060] The gate structure includes a gate polycrystalline structure 701;
[0061] The insulating dielectric layer structure includes an insulating dielectric layer 8, through which the gate polycrystalline structure 701 and the source polycrystalline structure 702 are isolated from the body region 4 and the source region 6;
[0062] The drift region structure includes a second conductivity type drift region 3, which is located below the body region 4;
[0063] The drain structure includes a second conductivity type drain region 2 and a bottom drain metal layer 1; the drain region 2 is located below the drift region 3, and the lower surface of the drain region 2 is in direct contact with the drain metal layer 1.
[0064] Example 11:
[0065] A power device, with the same technical content as Embodiment 10, further wherein the source polycrystalline structure 702 is connected to the source metal S in the top metal layer 9 through a contact hole, and the gate polycrystalline structure 701 is isolated from the source metal S in the top metal layer 9 through an insulating dielectric layer 8.
[0066] Example 12:
[0067] A power device, with the same technical content as any one of embodiments 10-11, further wherein the source polycrystalline structure 702 is located at the transition position of the terminal area near the active area, wherein the number of polycrystalline structures 702 can be freely selected according to the layout design, and the number is ≥1;
[0068] Example 13:
[0069] A power device, with the same technical content as any one of embodiments 10-12, further wherein the first type of conductivity semiconductor in the source structure is doped with a P-type semiconductor and the second type of conductivity semiconductor is an N-type semiconductor; or the first type of conductivity semiconductor is doped with an N-type semiconductor and the second type of conductivity semiconductor is a P-type semiconductor.
[0070] Example 14:
[0071] A power device, with the same technical content as any one of embodiments 10-13, further, the power device is not limited to MOSFET devices, the structure proposed herein is also applicable to power devices such as IGBT, Diode, and MCT.
[0072] Example 15:
[0073] A power device, with the same technical content as any one of embodiments 10-14, further wherein the material of the device may be selected from silicon, silicon carbide, gallium nitride, gallium arsenide, indium phosphide, gallium oxide, or germanium silicon.
[0074] Example 16:
[0075] A power device, with the same technical content as any one of embodiments 1-14, wherein... Figure 2 Taking the SGT structure shown as an example, the optimization principle of this invention is as follows:
[0076] During the reverse recovery process of the device, since the source polysilicon is directly opposite the drift region and the drain, it can deplete the drift region. During the reverse recovery process, the gate and source are connected to a low potential, and the drain is connected to a high potential. At this time, the reverse recovery current can flow out through the body region PN junction and the CDS and CDG paths. By increasing the proportion of CDS, the proportion of CDS displacement current in the total reverse recovery current can be increased, and the proportion of displacement current flowing through CDG and body region PN junction can be reduced, thereby reducing the possibility of gate oscillation and reverse recovery burnout.
[0077] This embodiment allows for free adjustment of the number of polysilicon sources connected to the displacement current control region on the device layout, thereby controlling and optimizing the reverse recovery current path and enhancing the reverse recovery reliability of the device.
[0078] Compared with conventional MOSFET devices (such as Figure 1 Compared to the previous version, the present invention removes the source region 6 near the source polycrystalline structure 702, thereby eliminating the parasitic transistor structure in the displacement current regulation region during the reverse recovery process, and further reducing the possibility of the device burning out during the reverse recovery process.
[0079] Compared with conventional MOSFET devices (such as Figure 1 Compared to (as shown), the displacement current regulation structure proposed in this invention can also be used in superjunction devices. Furthermore, it can also be used in device structures such as SGT, Diode, IGBT, and MCT.
Claims
1. A power device, characterized in that: This includes source structure, insulating dielectric layer structure, gate structure, drift region structure, and drain structure; The source structure includes a top metal layer (9), a first conductivity type ohmic contact region (5), a second conductivity type source region (6), a first conductivity type body region (4), and a source polycrystalline structure (702). The second conductivity type source region (6) and the first conductivity type ohmic contact region (5) are arranged on top of the first conductivity type body region (4), and the second conductivity type source region (6) is located on the side close to the gate structure; The insulating dielectric layer structure isolates the gate polycrystalline structure (701), the source polycrystalline structure (702) from the second conductivity type source region (6) and the first conductivity type body region (4); The drift region structure is located below the first conductivity type body region (4); The drain structure includes a second conductivity type drain region (2) and a drain metal layer (1). The second conductivity type drain region (2) is located below the drift region structure; The lower surface of the drain region (2) is in contact with the drain metal layer (1).
2. The power device according to claim 1, characterized in that: The gate structure includes a gate polycrystalline structure (701).
3. A power device according to claim 1, characterized in that: The insulating dielectric layer structure includes an insulating dielectric layer (8).
4. A power device according to claim 1, characterized in that: The drift region structure includes a second conductivity type drift region (3).
5. A power device according to claim 1, characterized in that: The source polycrystalline structure (702) is connected to the source metal S in the top metal layer (9) through a contact hole.
6. A power device according to claim 1, characterized in that: The gate structure is isolated from the source metal S in the top metal layer (9) by an insulating dielectric layer structure.
7. A power device according to claim 1, characterized in that: The source polycrystalline structure (702) is located on the side of the terminal region close to the active region, forming a displacement current control region.
8. A power device according to claim 1, characterized in that: The number of source polycrystalline structures (702) is ≥1.
9. A power device according to claim 1, characterized in that: The first type of semiconductor in the source structure is doped with a P-type semiconductor, and the second type of semiconductor is doped with an N-type semiconductor. Alternatively, the first type of conductivity semiconductor may be doped with an N-type semiconductor, and the second type of conductivity semiconductor may be doped with a P-type semiconductor.
10. A power device according to claim 1, characterized in that: The substrate and epitaxial layer materials of the device are selected from any one or more combinations of silicon, silicon carbide, gallium nitride, gallium arsenide, indium phosphide, gallium oxide, or germanium silicon.