A transverse MOSFET device structure with a RESURF layer and its manufacturing method

Abstract

A lateral MOSFET device structure with a RESURF layer and its manufacturing method are disclosed, belonging to the field of semiconductor technology. The device structure includes: a bottom RESURF layer having a second conductivity type; a drift layer disposed on the bottom RESURF layer having a first conductivity type; a top RESURF layer disposed within or on the drift layer having a second conductivity type; a body region located on one side of the drift layer having a second conductivity type; a first connection region having a second conductivity type, connecting the drift layer and the body region to form a first transmission path; and a second connection region having a second conductivity type, connecting the top RESURF layer and the body region to form a second transmission path. This application, by introducing the first and second connection regions, eliminates the current path narrowing effect caused by the charge recovery hysteresis of the RESURF layer, thereby significantly suppressing the on-resistance degradation of the device structure during dynamic switching.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device structure technology, and particularly relates to a lateral MOSFET device structure with a RESURF layer and its manufacturing method. Background Technology

[0002] With the widespread application of silicon carbide (SiC) materials in high-voltage and high-frequency fields, SiC MOSFET device structures have gradually become key components in high-power electronic devices. Lateral SiC MOSFET device structures, as a typical power switching device structure, possess advantages such as high breakdown voltage, high on-current, and high-temperature stability, and are widely used in power electronics, automotive electric drives, power management, and other fields.

[0003] To improve the breakdown voltage and stability of SiC MOSFET device structures, RESURF (Reduced Surface Field) technology is widely used. RESURF technology optimizes the surface electric field of the lateral device structure by introducing one or more shallow doped layers with the opposite doping type to the drift layer, thereby improving the breakdown voltage of the device structure. This technology can effectively control the surface electric field of the MOSFET device structure, avoiding excessive concentration of the electric field in the surface region, thus significantly improving the breakdown voltage of the device structure.

[0004] However, in practical applications, when a SiC MOSFET device is subjected to a forward high voltage and re-turned on, the depletion layer formed by the RESURF layer lacks an effective hole path. This prevents timely hole injection or discharge during dynamic switching, hindering the device's ability to restore its original charge balance. Consequently, the accumulated charge fails to release effectively, narrowing the current path and causing dynamic resistance degradation. This degradation leads to increased on-resistance, affecting switching efficiency and long-term stability.

[0005] Therefore, it is urgent to develop a lateral MOSFET device structure with a RESURF layer and its manufacturing method to solve the problems in the existing technology. Summary of the Invention

[0006] The present invention aims to provide a structure of a lateral MOSFET device with a RESURF layer and a method for manufacturing the same. By introducing a first connection region and a second connection region, the dynamic on-resistance degradation problem of existing lateral MOSFET devices with a RESURF layer mentioned in the background art is solved.

[0007] To solve the above-mentioned technical problems, the specific technical solution of the present invention is as follows:

[0008] A lateral MOSFET device structure with a RESURF layer, comprising:

[0009] The bottom RESURF layer has a second conductivity type;

[0010] A drift layer, disposed on the bottom RESURF layer, has a first conductivity type;

[0011] A top RESURF layer, disposed on or on top of the drift layer, has a second conductivity type;

[0012] The body region, located on one side of the drift layer, has a second conductivity type;

[0013] The first connection region has a second conductivity type and connects the drift layer and the bulk region to form a first transmission path;

[0014] The second connection region, having a second conductivity type, connects the top RESURF layer and the body region to form a second transmission path.

[0015] Furthermore, the drift current within the drift layer flows from either side or below the second connection region.

[0016] Furthermore, in a cross-section perpendicular to the channel current direction, the width of the second connection region is smaller than the width of the drift layer.

[0017] Furthermore, the structural relationship between the first connection region and the second connection region includes the following:

[0018] The first connection area and the second connection area are spatially separated; or

[0019] The first connection area and the second connection area overlap in space; or

[0020] The first connection region and the second connection region are composed of the same continuous doped region, which simultaneously connects the top RESURF layer and the bottom RESURF layer;

[0021] The structural relationship between the first connection region and the body region includes the following:

[0022] The first connection region contacts or overlaps with the body region;

[0023] The structural relationship between the first connection region and the bottom RESURF layer is as follows:

[0024] The first connection area contacts or overlaps with the bottom RESURF layer.

[0025] Furthermore, both the first connection region and the second connection region are ion implantation regions; wherein, the first connection region and the body region are co-doped regions formed by the same ion implantation process, and the first connection region is configured as a longitudinal extension or deep implantation portion of the body region toward the substrate, and the doping concentration of the first connection region is greater than the doping concentration of the bottom RESURF layer.

[0026] Furthermore, a source region of a second conductivity type is provided in the body region. The source region of the second conductivity type and the second connection region are prepared by the same ion implantation process and have substantially the same doping concentration distribution and junction depth.

[0027] Furthermore, the body region is also provided with a source region of a first conductivity type, and the source region of the second conductivity type is in contact with the source region of the first conductivity type.

[0028] Furthermore, it also includes:

[0029] The substrate has a first type of conductivity;

[0030] A buffer layer, disposed on the substrate, has a second conductivity type; the bottom RESURF layer is disposed on the buffer layer;

[0031] The drain region, located on the other side of the drift layer, has a first conductivity type;

[0032] The source metal electrode is connected to the source region.

[0033] Drain metal electrode, connected to the drain region;

[0034] A gate structure is located between a drift layer and a source metal electrode. The gate structure includes a polysilicon gate and a gate oxide. The gate oxide is located between the polysilicon gate and the source metal electrode, the body region, the source region, the drain region, and the second connection region.

[0035] The first conductivity type is N-type, the second conductivity type is P-type, and the first and second transmission paths are hole transmission paths.

[0036] A method for manufacturing a lateral MOSFET device structure containing a RESURF layer includes the following steps:

[0037] A buffer layer of the first conductivity type, a bottom RESURF layer of the second conductivity type, and a drift layer of the first conductivity type are constructed on a substrate of the first conductivity type.

[0038] Construct a top RESURF layer of the second conductivity type on or on top of the drift layer;

[0039] By ion implantation, a bulk region of a second conductivity type and a first connection region of a second conductivity type are constructed in the drift layer; wherein, the first connection region connects the drift layer and the bulk region;

[0040] A source region is constructed in the body region, and a second connection region of a second conductivity type is constructed between the top RESURF layer and the body region; wherein, the second connection region connects the top RESURF layer and the body region;

[0041] Construct a drain region in the drift layer;

[0042] A gate structure and metal electrodes are constructed on the drift layer.

[0043] Furthermore, the body region and the first connection region are formed through the same ion implantation process, and the doping concentration of the first connection region is greater than the doping concentration of the bottom RESURF layer;

[0044] The source region includes a source region of a first conductivity type and a source region of a second conductivity type. The source region of the second conductivity type and the second connection region are prepared by the same ion implantation process.

[0045] The present invention has the following advantages:

[0046] (1) This application constructs a bidirectional hole transport path for the top and bottom RESURF layers by introducing a first connection region and a second connection region. When the device structure is in a high-voltage blocking state, the holes in the RESURF layer can be rapidly discharged through this path, assisting in the establishment of the depletion layer. When the device structure switches from the blocking state to the conducting state, the holes at the source can be rapidly injected through this path and backfilled into the RESURF layer, allowing it to quickly return to electrical neutrality. This mechanism eliminates the current path narrowing effect caused by the lag in charge recovery of the RESURF layer, thereby significantly suppressing the degradation of the on-resistance of the device structure during dynamic switching.

[0047] (2) At the same time, while significantly improving the dynamic characteristics, this application avoids excessive electric field concentration caused by potential clamping by optimizing the geometry of the second connection area and the top RESURF layer, so that the device structure does not have a significant negative impact on maintaining high breakdown voltage (BV) performance.

[0048] (3) In addition, the first connection area and the second connection area of ​​this application can respectively utilize the existing P-type body area and P-type body contact area / P + The ion implantation process of the source region is carried out simultaneously without the need for additional process steps or photomasks. Under the premise of being fully compatible with standard manufacturing processes and without increasing manufacturing costs, the dynamic stability and reliability of the device structure are greatly improved.

[0049] Other features and advantages of the present invention will be disclosed in detail in the following detailed description and accompanying drawings. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of the overall structure of this application;

[0051] Figure 2 This is a cross-sectional view of the structure of this application on a section perpendicular to the channel current direction;

[0052] Figure 3 A comparison of the output characteristics of a silicon carbide lateral MOSFET device with a RESURF layer that does not employ a charge release structure before and after applying a forward drain-source high voltage.

[0053] Figure 4 A comparison of the output characteristic curves of the silicon carbide lateral MOSFET device with a RESURF layer for suppressing dynamic resistance degradation in this application before and after applying a forward drain-source high voltage;

[0054] Figure 5 This is a comparison of the blocking characteristic curves of a silicon carbide lateral MOSFET device with a RESURF layer that does not employ a charge release structure and the silicon carbide lateral MOSFET device with a RESURF layer of this application.

[0055] Explanation of markings in the figure: 1. Substrate; 2. Buffer layer; 3. Bottom RESURF layer; 4. Drift layer; 5. Bulk region; 6. First connection region; 7. N + Source region; 8, P + 9. Source region; 10. Drain region; 11. Top RESURF layer; 12. Second connection region; 13. Source metal electrode; 14. Drain metal electrode; 15. Polysilicon gate; 16. Gate oxide. Detailed Implementation

[0056] To better understand the purpose, structure, and function of this invention, the invention will be described in further detail below with reference to the accompanying drawings.

[0057] A lateral MOSFET device structure with a RESURF layer, such as Figure 1 As shown, it includes:

[0058] Substrate 1 has a first conductivity type;

[0059] Buffer layer 2, disposed on substrate 1, has a second conductivity type;

[0060] The bottom RESURF layer 3, disposed on the buffer layer 2, has a second conductivity type;

[0061] Drift layer 4, disposed on the bottom RESURF layer 3, has a first conductivity type;

[0062] A top RESURF layer 10, disposed on or on top of the drift layer 4, has a second conductivity type;

[0063] Body region 5, located on one side of the drift layer 4, has a second conductivity type;

[0064] The first connection region 6 has a second conductivity type and connects the drift layer 4 and the body region 5 to form a first transmission path;

[0065] The second connection region 11 has a second conductivity type and connects the top RESURF layer 10 and the body region 5 to form a second transmission path.

[0066] In this embodiment, the first conductivity type is N-type, the second conductivity type is P-type, and the first and second transmission paths are hole transmission paths. Optionally, the first conductivity type can also be P-type, and the second conductivity type can be N-type.

[0067] In this embodiment, the device structure further includes:

[0068] N + Source region 7 is located within body region 5;

[0069] P + Source region 8 is located within body region 5;

[0070] N + Type-apart area 9 is located on the other side of drift layer 4;

[0071] Source metal electrode 12, with N + Type source region 7 and P + Source area 8 connections;

[0072] Drain metal electrode 13, with N + Type 9 leak area connection;

[0073] A gate structure is located between the drift layer 4 and the source metal electrode 12. The gate structure includes a polysilicon gate 14 and a gate oxide 15. The gate oxide 15 is located between the polysilicon gate 14 and the source metal electrode 12, the body region 5, the source region, the drain region 9, and the second connection region 11.

[0074] Optionally, the drift current within the drift layer 4 flows from either side or below the second connection region 11. Preferably, as... Figure 2 As shown, in a cross-section perpendicular to the channel current direction, the width of the second connection region 11 is smaller than the width of the drift layer 4, so that the drift current flows through the sides or below the second connection region 11. Figure 2 The cross-sectional position perpendicular to the channel current direction corresponds to Figure 1 The position of the dotted line in the text.

[0075] Preferably, in this embodiment, the first connection region 6 and the second connection region 11 are ion implantation regions; wherein, the first connection region 6 and the body region 5 are co-doped regions formed in the same ion implantation process, and the first connection region 6 is configured as a longitudinal extension or deep implantation portion of the body region 5 towards the substrate 1, and its doping concentration is greater than that of the bottom RESURF layer 3. The second connection region 11 and the P + The source region 8 is prepared through the same ion implantation process and has substantially the same doping concentration distribution and junction depth.

[0076] With the above settings, on the one hand, the first connection area 6 and the second connection area 11 respectively reuse the existing P-type body area 5 and P-type body area 6. + The ion implantation process in source region 8 eliminates the need for any additional photomasks or separate implantation steps beyond the standard SiC MOSFET fabrication process, significantly reducing manufacturing costs and ensuring excellent process compatibility. Furthermore, by ensuring that the doping concentration of the connection region is significantly higher than that of the connected RESURF layer, an extremely low-impedance bidirectional hole transport path is successfully constructed within the device structure, ensuring hole discharge and backfilling during high-speed switching. In summary, this structure effectively improves the conductivity of the device structure and maintains low dynamic resistance under high-voltage conditions.

[0077] The structural relationship between the first connection region 6 and the second connection region 11 is as follows:

[0078] The first connection area 6 and the second connection area 11 are spatially separated; or

[0079] The first connection area 6 and the second connection area 11 have an overlapping area in space; or

[0080] The first connection region 6 and the second connection region 11 are composed of the same continuous doped region, which simultaneously connects the top RESURF layer 10 and the bottom RESURF layer 3.

[0081] The structural relationship between the first connection region 6 and the body region 5 is as follows:

[0082] The first connection region 6 contacts or overlaps with the body region 5.

[0083] Optionally, the first connection area 6 includes a longitudinal extension extending downward from the body area 5, or an independent deep injection area located directly below the body area 5.

[0084] The structural relationship between the first connection region 6 and the bottom RESURF layer 3 is as follows:

[0085] The first connection area 6 contacts or overlaps with the bottom RESURF layer 3.

[0086] A method for manufacturing a lateral MOSFET device structure containing a RESURF layer includes the following steps:

[0087] A buffer layer 2 of the first conductivity type, a bottom RESURF layer 3 of the second conductivity type, and a drift layer 4 of the first conductivity type are constructed on a substrate 1 of the first conductivity type.

[0088] A second conductivity type top RESURF layer 10 is constructed on or on top of drift layer 4;

[0089] By ion implantation, a body region 5 of a second conductivity type and a first connection region 6 of a second conductivity type are constructed in the drift layer 4; wherein, the first connection region 6 connects the drift layer 4 and the body region 5;

[0090] A source region is constructed in the body region 5, and a second connection region 11 of the second conductivity type is constructed between the top RESURF layer 10 and the body region 5; wherein, the second connection region 11 connects the top RESURF layer 10 and the body region 5;

[0091] Construct a leak region 9 in drift layer 4;

[0092] A gate structure and a metal electrode are constructed on the drift layer 4.

[0093] The construction methods of the buffer layer 2, the bottom RESURF layer 3, the drift layer 4 of the first conductivity type, the body region 5, the first connection region 6 and the second connection region 11 are existing technologies and will not be described in detail in this application.

[0094] Preferably, the body region 5 and the first connection region 6 are formed by the same ion implantation process, and the doping concentration of the first connection region 6 is greater than the doping concentration of the bottom RESURF layer 3; the source region includes a source region of a first conductivity type and a source region of a second conductivity type, and the source region of the second conductivity type and the second connection region 11 are prepared by the same ion implantation process.

[0095] On the one hand, the first connection region 6 and the second connection region 11 respectively reuse the existing P-type body region 5 and P + The ion implantation process in source region 8 does not require any additional photomask or independent implantation step outside the standard SiC MOSFET process, which greatly reduces manufacturing costs and ensures excellent process compatibility. On the other hand, by ensuring that the doping concentration of the connection region is significantly higher than that of the RESURF layer it is connected to, a bidirectional hole transport path with extremely low impedance is successfully constructed inside the device structure, ensuring that holes can be discharged and backfilled when the device structure is switched at high speed.

[0096] With a blocking voltage of 650V and a specific on-resistance of 10mΩ·cm 2 Taking a silicon carbide lateral metal-oxide-semiconductor field-effect transistor (MOSFET) device as an example, the optimal parameter configurations for the first connection region 6 and the second connection region 11 are as follows:

[0097] The first junction region 6 is P-type doped, and its longitudinal extension structure is formed by adjusting the ion implantation energy and dose of the P-type body region 5 (P-Well). The longitudinal junction depth of the P-type body region 5 is 0.8 μm, and the thickness of the N-type drift layer 4 is 1.2 μm. For the increased depth implantation step, the recommended dose range is 4 × 10⁻⁶. 13 Up to 8×10 13 The recommended implantation energy range is 900 keV to 1050 keV, thereby forming the first connection region 6, which is located below the P-type body region 5, with an effective length exceeding 0.4 μm, thus enabling an overall implantation depth exceeding 1.2 μm to connect to the bottom RESURF layer 3; its doping concentration is preferably consistent with that of the P-type body region 5, approximately 2 × 10⁻⁶. 18 cm -3 This concentration is significantly higher than that of the P-type bottom RESURF layer (34 × 10⁻⁶). 15 cm -3 The concentration of P-type doping is such that a low-impedance discharge path is formed; the second connection region 11 has a high concentration of P-type doping, which interacts with P... + Source region 8 is prepared through the same ion implantation process, and its doping concentration is preferably 1×10⁻⁶. 19 cm -3 Its longitudinal knot depth is 0.5 μm and its width is 0.2 μm.

[0098] A comparative simulation experiment was designed in TCAD to compare this application with a comparative example. This application is a SiC lateral MOSFET device with a RESURF layer that introduces a first connection region 6 and a second connection region 11 to form a charge release structure. The comparative example is a SiC lateral MOSFET device with a RESURF layer that does not adopt the charge release structure of this application. The only difference between this application and the comparative example is the presence or absence of the first connection region 6 and the second connection region 11.

[0099] Table 1:

[0100] Cell thickness (µm) 7.7 Cell length (um) 18 Cell width (um) 1 N-type substrate thickness (µm) 0.5 <![CDATA[N-type substrate concentration (cm -3 ).]]> 1e19 P-type bottom RESURF layer thickness (µm) 5.0 <![CDATA[P-type bottom RESURF layer concentration (cm -3 ).]]> 4e15 N-type drift layer thickness (µm) 1.2 <![CDATA[N-type drift layer concentration (cm -3 ).]]> 5e16 P-type body region thickness (µm) 0.8 P-type body region length (µm) 3.0 <![CDATA[P-type body region concentration (cm -3 ).]]> 2e18 N-type source region thickness (µm) 0.3 N-type source region length (µm) 2.0 <![CDATA[N-type source region concentration (cm -3 ).]]> 1e19 P-type source region thickness (µm) 0.6 P-type source region length (µm) 0.5 <![CDATA[P-type source region concentration (cm -3 ).]]> 1e19 N-type leak thickness (µm) 0.2 N-type leak length (µm) 2.0 <![CDATA[N-type drain region concentration (cm -3 ).]]> 1e19 Thickness of the first connection region (µm) 0.4 First connection region length (µm) 3.0 <![CDATA[First connection area concentration (cm -3 ).]]> 2e18 Second connection region thickness (µm) 0.5 Second connection region length (µm) 2.0 Second connection area width (µm) 0.2 <![CDATA[Second connection area concentration (cm -3 ).]]> 1e19 P-type top RESURF layer thickness (µm) 0.3 Length of the top RESURF layer of the P-type (um) 9.0 <![CDATA[P-type top RESURF layer concentration (cm -3 ).]]> 1.5e17 Gate coverage N-type source region length (µm) 0.3 Gate length (µm) 3.2 Gate oxide thickness (µm) 0.05

[0101] Table 1 shows the main parameters of the LDMOSFET in the simulation experiment of the embodiments of this application.

[0102] The specific steps of the control experiment are as follows:

[0103] The output characteristic curves of the two devices were measured with a gate voltage of 18V.

[0104] Adjust the gate voltage to 0V, keep the MOSFET in the off state, and apply a positive drain-source voltage of 400V;

[0105] Adjust the drain-source voltage to 0V, and then measure the output characteristic curves of the two devices with a gate voltage of 18V.

[0106] Measure the blocking characteristic curves of the two devices.

[0107] like Figure 3 The figure shows a comparison of the output characteristic curves of a lateral MOSFET device before and after applying a positive drain-source high voltage. It can be seen that for the device without a charge release structure, after experiencing high voltage blocking, the slope of its output characteristic curve decreases significantly, and the drain-source current at the same voltage decreases drastically, exhibiting a severe dynamic on-resistance degradation phenomenon. This is attributed to the floating body effect of the RESURF layer, which prevents holes from being filled in time, and the residual negative charge has a parasitic depletion effect on the drift layer 4.

[0108] like Figure 4 The figure shows a comparison of the output characteristic curves of the silicon carbide lateral MOSFET device with a RESURF layer that suppresses dynamic resistance degradation before and after applying a forward drain-source high voltage, as proposed in this application. It can be seen that the improved device, employing the first connection region 6 and the second connection region 11 structure proposed in this application, shows that the two output characteristic curves before and after applying high voltage stress almost completely overlap, with no observed decrease in current or increase in resistance. This proves that the present invention successfully clamps the top and bottom RESURF layers 3 to the source potential by constructing a low-impedance bidirectional hole transport path, enabling the device to quickly complete hole backfilling and eliminate charge imbalance at the moment of conduction. This effectively suppresses or even eliminates dynamic resistance degradation while maintaining high withstand voltage.

[0109] like Figure 5 As shown in the figure, a comparison of the blocking characteristic curves of a lateral MOSFET device and the lateral MOSFET device of this application is presented. It can be seen that the breakdown voltage of the device of this invention only shows a slight shift compared to the conventional device. This fully demonstrates that the connection region structure introduced in this invention to construct the hole discharge path does not substantially disrupt the charge balance mechanism of the original RESURF layer.

[0110] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

[0111] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A lateral MOSFET device structure containing a RESURF layer, characterized in that, include: The bottom RESURF layer has a second conductivity type; A drift layer, disposed on the bottom RESURF layer, has a first conductivity type; A top RESURF layer, disposed on or on top of the drift layer, has a second conductivity type; The body region, located on one side of the drift layer, has a second conductivity type; The first connection region has a second conductivity type and connects the drift layer and the bulk region to form a first transmission path; The second connection region, having a second conductivity type, connects the top RESURF layer and the body region to form a second transmission path.

2. The lateral MOSFET device structure with a RESURF layer according to claim 1, characterized in that, The drift current in the drift layer flows from the sides or below the second connection region.

3. The lateral MOSFET device structure with a RESURF layer according to claim 2, characterized in that, On a cross section perpendicular to the channel current direction, the width of the second connection region is smaller than the width of the drift layer.

4. The lateral MOSFET device structure with a RESURF layer according to claim 2, characterized in that, The structural relationship between the first connection region and the second connection region is as follows: The first connection area and the second connection area are spatially separated; or The first connection area and the second connection area overlap in space; or The first connection region and the second connection region are composed of the same continuous doped region, which simultaneously connects the top RESURF layer and the bottom RESURF layer; The structural relationship between the first connection region and the body region includes the following: The first connection region contacts or overlaps with the body region; The structural relationship between the first connection region and the bottom RESURF layer is as follows: The first connection area contacts or overlaps with the bottom RESURF layer.

5. The lateral MOSFET device structure with a RESURF layer according to any one of claims 1-4, characterized in that, Both the first connection region and the second connection region are ion implantation regions; wherein, the first connection region and the body region are co-doped regions formed by the same ion implantation process, and the first connection region is configured as a longitudinal extension or deep implantation portion of the body region toward the substrate, and the doping concentration of the first connection region is greater than the doping concentration of the bottom RESURF layer.

6. The lateral MOSFET device structure with a RESURF layer according to claim 5, characterized in that, The body region is provided with a source region of a second conductivity type. The source region of the second conductivity type and the second connection region are prepared by the same ion implantation process and have substantially the same doping concentration distribution and junction depth.

7. The lateral MOSFET device structure with a RESURF layer according to claim 6, characterized in that, The body region is further provided with a source region of a first conductivity type, and the source region of the second conductivity type is in contact with the source region of the first conductivity type.

8. The lateral MOSFET device structure with a RESURF layer according to claim 7, characterized in that, Also includes: The substrate has a first type of conductivity; A buffer layer, disposed on the substrate, has a second conductivity type; the bottom RESURF layer is disposed on the buffer layer; The drain region, located on the other side of the drift layer, has a first conductivity type; The source metal electrode is connected to the source region. Drain metal electrode, connected to the drain region; A gate structure is located between a drift layer and a source metal electrode. The gate structure includes a polysilicon gate and a gate oxide. The gate oxide is located between the polysilicon gate and the source metal electrode, the body region, the source region, the drain region, and the second connection region. The first conductivity type is N-type, the second conductivity type is P-type, and the first and second transmission paths are hole transmission paths.

9. A method for manufacturing a lateral MOSFET device structure containing a RESURF layer, characterized in that, Includes the following steps: A buffer layer of the first conductivity type, a bottom RESURF layer of the second conductivity type, and a drift layer of the first conductivity type are constructed on a substrate of the first conductivity type. Construct a top RESURF layer of the second conductivity type on or on top of the drift layer; A second conductivity type bulk region and a second conductivity type first connection region are constructed in the drift layer by ion implantation; wherein the first connection region connects the drift layer and the bulk region; A source region is constructed in the body region, and a second connection region of a second conductivity type is constructed between the top RESURF layer and the body region; wherein, the second connection region connects the top RESURF layer and the body region; Construct a drain region in the drift layer; A gate structure and metal electrodes are constructed on the drift layer.

10. The method for manufacturing a lateral MOSFET device structure containing a RESURF layer according to claim 9, characterized in that, The body region and the first connection region are formed through the same ion implantation process, and the doping concentration of the first connection region is greater than the doping concentration of the bottom RESURF layer. The source region includes a source region of a first conductivity type and a source region of a second conductivity type. The source region of the second conductivity type and the second connection region are prepared by the same ion implantation process.

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