A semiconductor MOSFET device and its fabrication method

Abstract

This invention discloses a semiconductor MOSFET device and its fabrication method, relating to the technical field of semiconductor devices. The device includes a silicon carbide substrate, a silicon carbide epitaxial layer, a well region, a source region, a gate structure, an interlayer dielectric layer, a source electrode, and a drain electrode; the semiconductor bodies between adjacent well regions constitute a JFET region. The core of this invention lies in the presence of an insulating dielectric layer directly above the JFET region, which divides the gate oxide layer into left and right parts. The gate electrode can be a single unit spanning across the insulating dielectric layer; or it can employ a split structure, extending downwards from the source electrode to cover the insulating dielectric layer. This invention effectively reduces the gate-drain overlap capacitance through the above structure, thereby reducing the device's Miller capacitance and improving the switching speed. Furthermore, by embedding a current spreading layer directly below the insulating dielectric layer within the JFET region, the increase in on-resistance is precisely compensated, achieving optimization of the device's overall performance.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor devices, and more specifically, to a semiconductor MOSFET device and its fabrication method. Background Technology

[0002] Silicon carbide (SiC) planar gate MOSFETs have wide applications in power electronics. However, in practical applications, the impact of their Miller capacitance (a parasitic capacitance mainly existing between the drain and gate) is particularly prominent. During switching, Miller capacitance introduces additional charge, causing a delay in gate voltage change, thereby reducing the device's switching speed and increasing switching losses.

[0003] Currently, in order to reduce Miller capacitance, some designs attempt to optimize the geometry of the device to reduce the capacitance area. However, this often weakens the gate's control over the JFET region, leading to increased on-resistance and making it difficult to achieve comprehensive performance optimization. On the other hand, external circuit compensation increases the complexity and cost of the circuit, and cannot fundamentally solve the problem at the device physical level. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its fabrication method, which aims to reduce the Miller capacitance of the device by changing the gate structure above the JFET region or introducing an insulating dielectric layer, and on this basis, to solve the technical contradiction of increased on-resistance by using a current spreading layer.

[0005] The technical solution of the present invention is: to provide a semiconductor MOSFET device, which has a planar gate structure, and the device includes:

[0006] The semiconductor body has a first surface and a second surface that are relatively planar, and the semiconductor body includes a silicon carbide substrate and a silicon carbide epitaxial layer in sequence from the second surface to the first surface.

[0007] Multiple well regions are spaced apart within a silicon carbide epitaxial layer near the first surface, and the semiconductor body between two adjacent well regions constitutes a JFET region.

[0008] The source region is located within the trap region near the first surface and is surrounded by the trap region below;

[0009] An insulating dielectric layer is disposed on the first surface and is located directly above the JFET region;

[0010] A gate oxide layer is laid on the first surface. The gate oxide layer is separated by an intermediate insulating dielectric layer, thus dividing it into two parts located on the left and right sides of the insulating dielectric layer.

[0011] The gate is positioned above the gate oxide layer;

[0012] Interlayer dielectric layer, which wraps around the outside of the gate, is used to electrically isolate the gate from the surrounding structure;

[0013] The source electrode is disposed above the first surface, covering the interlayer dielectric layer, and extends downward through the interlayer dielectric layer to be electrically connected to the source region and the well region.

[0014] The drain electrode is located on one side of the second surface.

[0015] In any of the above technical solutions, the gate is a complete integral structure that spans and completely covers the top and left and right sidewalls of the insulating dielectric layer, and the gate covers the gate oxide layers on both sides.

[0016] In any of the above technical solutions, the gate is further divided into a split structure that is broken in the middle, consisting of two parts, left and right, which respectively cover the gate oxide layer on both sides; the gate does not cover the insulating dielectric layer.

[0017] In any of the above technical solutions, a current spreading layer is further provided inside the JFET region and immediately adjacent to the first surface; the current spreading layer is located directly below the insulating dielectric layer, and the projections of the two in the vertical direction at least partially overlap.

[0018] In any of the above technical solutions, the doping polarity of the silicon carbide substrate, silicon carbide epitaxial layer, JFET region, source region and current extension layer is the first doping polarity; the doping polarity of the well region is the second doping polarity, and the first doping polarity and the second doping polarity are opposite.

[0019] A method for fabricating the semiconductor MOSFET device according to any of the above technical solutions is also provided, the method comprising:

[0020] A silicon carbide substrate is provided, and a silicon carbide epitaxial layer is epitaxially grown on the silicon carbide substrate to form a semiconductor body having opposing first and second surfaces;

[0021] Multiple spaced well regions are formed in the silicon carbide epitaxial layer near the first surface, and the semiconductor body between two adjacent well regions constitutes a JFET region.

[0022] A source region is formed within the well region near the first surface;

[0023] An insulating dielectric layer is formed on the first surface at a location corresponding to the JFET region;

[0024] A gate oxide layer and a gate electrode are formed on one side of the first surface;

[0025] A source electrode is formed on one side of the first surface, and the source electrode is electrically connected to the source region and the well region.

[0026] A drain electrode is formed on one side of the second surface.

[0027] In any of the above technical solutions, the steps of forming the well region and the source region further include:

[0028] A hard mask is formed and patterned on the first surface to form the first mask plate;

[0029] Using the first mask as a barrier layer, a trap region is formed using ion implantation.

[0030] An injection barrier layer is formed and patterned on the first surface to form a sidewall located on the sidewall of the first mask and a source region barrier layer on the periphery;

[0031] The source region is formed at the opening between the sidewall and the source region barrier layer using ion implantation technology;

[0032] Remove the first mask, sidewalls, and source region blocking layer.

[0033] In any of the above technical solutions, further comprising, before forming the insulating dielectric layer, the following:

[0034] A hard mask is formed and patterned on the first surface to form a second mask, the second mask having an opening above the JFET region;

[0035] A current extension layer is formed in the JFET region below the opening using an ion implantation process;

[0036] The implanted doped regions are activated by a high-temperature annealing process;

[0037] The insulating dielectric layer remains directly above the current spreading layer.

[0038] In any of the above technical solutions, the steps of forming the insulating dielectric layer, the gate oxide layer, and the gate further include:

[0039] An insulating dielectric material is deposited and patterned on the first surface, leaving only the insulating dielectric layer directly above the JFET region.

[0040] A gate oxide layer is formed on the area of ​​the first surface not covered by the insulating dielectric layer by an oxidation process.

[0041] A polysilicon layer is formed and patterned above the first surface to form the gate.

[0042] In any of the above technical solutions, the step of forming the source electrode further includes:

[0043] An interlayer dielectric layer is formed on one side of the first surface, and the interlayer dielectric layer covers the gate.

[0044] The interlayer dielectric layer and gate oxide layer are etched to expose the source contact region on the first surface;

[0045] The source electrode is formed above the first surface by metal sputtering, and the source electrode fills the source electrode contact area and covers the interlayer dielectric layer.

[0046] The beneficial effects of this invention are:

[0047] This invention increases the equivalent dielectric thickness between the gate and drain by introducing an additional insulating dielectric layer directly above the JFET region; or by employing a split gate structure and extending the source downwards to form an electric field shield, it reduces the gate-drain overlap area. Both structures can directly reduce the gate-drain overlap capacitance at the physical level, thereby reducing the overall Miller capacitance of the device, improving switching speed, and reducing switching losses.

[0048] To address the issue that introducing an insulating dielectric layer leads to a decrease in surface charge density and an increase in on-resistance in the JFET region, this invention employs a synergistic design by embedding a current spreading layer within the JFET region. The current spreading layer provides a current path with lower resistivity, precisely compensating for the loss in on-resistance and achieving a balance between low Miller capacitance and low on-resistance.

[0049] The preparation method of this invention is highly compatible with the existing standard manufacturing process of silicon carbide planar gate MOSFETs, and does not require the introduction of complex special processing equipment, thus possessing good industrialization feasibility. Attached Figure Description

[0050] The advantages of the above and additional aspects of the present invention will become apparent and readily understood in the description of the embodiments in conjunction with the following drawings, wherein:

[0051] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor MOSFET device according to Embodiment 4 of the present invention;

[0052] Figure 2 This is a schematic cross-sectional view of a planar gate MOSFET in the prior art, according to an embodiment of the present invention.

[0053] Figure 3 This is a schematic cross-sectional view of a semiconductor MOSFET device according to Embodiment 1 of the present invention;

[0054] Figure 4 This is a cross-sectional schematic diagram of a semiconductor MOSFET device according to Embodiment 2 of the present invention;

[0055] Figure 5 This is a schematic cross-sectional view of a semiconductor MOSFET device according to Embodiment 3 of the present invention;

[0056] Figure 6This is a schematic cross-sectional view of a semiconductor MOSFET device according to Embodiment 4 of the present invention;

[0057] Figure 7 This is a schematic diagram of the structure of the well region formed in step S1 of the method for fabricating a semiconductor MOSFET device according to an embodiment of the present invention;

[0058] Figure 8 This is a schematic diagram of the structure of the source region formed in step S1 of the method for fabricating a semiconductor MOSFET device according to an embodiment of the present invention;

[0059] Figure 9 This is a schematic diagram of the structure of the current spreading layer formed in step S1 of the method for fabricating a semiconductor MOSFET device according to an embodiment of the present invention;

[0060] Figure 10 This is a schematic diagram of the structure formed in step S2 of a method for fabricating a semiconductor MOSFET device according to an embodiment of the present invention;

[0061] Figure 11 This is a schematic diagram of the structure formed by step S2 of a method for fabricating a semiconductor MOSFET device according to an embodiment of the present invention;

[0062] Figure 12 This is a schematic diagram of the structure formed by step S2 of a method for fabricating a semiconductor MOSFET device according to an embodiment of the present invention.

[0063] Figure 13 This is a schematic diagram of the structure formed by step S2 of a method for fabricating a semiconductor MOSFET device according to an embodiment of the present invention;

[0064] Figure 14 This is a schematic diagram of the structure of step S3, forming the source contact region, in a method for fabricating a semiconductor MOSFET device according to an embodiment of the present invention.

[0065] Figure 15 This is a schematic diagram of the source electrode formation step S3 in the fabrication method of a semiconductor MOSFET device according to an embodiment of the present invention.

[0066] Among them, 1-semiconductor body, 2-gate structure, 3-source, 4-drain, 11-silicon carbide substrate, 12-silicon carbide epitaxial layer, 13-well region, 14-source region, 15-first mask, 16-sidewall, 17-source barrier layer, 18-second mask, 21-gate oxide layer, 22-insulating dielectric layer, 23-gate, 24-interlayer dielectric layer, 101-first surface, 102-second surface, 121-JFET region, 122-current spreading layer. Detailed Implementation

[0067] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments of the present invention and the features thereof can be combined with each other.

[0068] In the following description, many specific details are set forth in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0069] like Figure 2 The diagram shown is a cross-sectional view of a prior art planar gate MOSFET. The Miller capacitance is the parasitic capacitance between the MOSFET gate and drain, consisting of two capacitors connected in series: the overlapping oxide capacitance between the gate and drain regions and the depletion layer capacitance of the drain PN junction. The formula for calculating the Miller capacitance is: C gd =C1·C2 / (C1+C2). Where the drain PN junction capacitance C2 varies with the drain-source voltage; while the gate-drain overlap capacitance C1 is a fixed value, which can be calculated using a parallel-plate capacitor model, specifically: C1=ε r ·ε0·S / d. In this formula, ε r ε represents the relative permittivity of gate oxide layer 21, ε0 represents the vacuum permittivity, S represents the area of ​​gate oxide layer 21, and d represents the thickness of gate oxide layer 21.

[0070] As can be seen from the above formula, reducing at least one of C1 and C2 will reduce the Miller capacitance C. gd Based on this, various embodiments of the present invention reduce the gate-drain overlap area or increase the equivalent dielectric thickness by changing the gate structure directly above the JFET region or introducing an additional dielectric layer, thereby reducing the overlap oxide capacitance C1 and ultimately achieving the goal of reducing the device's Miller capacitance.

[0071] Various embodiments of the present invention provide a semiconductor MOSFET device, the basic structure of which includes a semiconductor body 1, the semiconductor body 1 having a first surface 101 and a second surface 102 opposite to each other.

[0072] The semiconductor body 1 includes a silicon carbide substrate 11 and a silicon carbide epitaxial layer 12 sequentially from the second surface 102 toward the first surface 101. Multiple well regions 13 are spaced apart within the silicon carbide epitaxial layer 12 near the first surface 101; the semiconductor body between two adjacent well regions 13 constitutes a JFET region 121. A source region 14 is provided within the well region 13 near the first surface 101.

[0073] In addition, the device includes a gate structure 2 and a source 3 located on one side of the first surface 101, and a drain 4 located on one side of the second surface 102. An insulating dielectric layer 22 is disposed on the first surface 101 and is located directly above the JFET region 121; a gate oxide layer 21 is disposed on the first surface 101 and is separated by the intermediate insulating dielectric layer 22, thus being divided into two parts located on the left and right sides of the insulating dielectric layer 22; a gate 23 is disposed above the gate oxide layer 21; an interlayer dielectric layer 24 covers the outside of the gate 23 and is used to electrically isolate the gate 23 from the peripheral structure; the source 3 is disposed above the first surface 101, covers the interlayer dielectric layer 24, and passes downward through the interlayer dielectric layer 24 to be electrically connected to the source region 14 and the well region 13; and the drain 4 is disposed on one side of the second surface 102.

[0074] In this embodiment of the invention, the silicon carbide substrate 11, the silicon carbide epitaxial layer 12, the JFET region 121, and the source region 14 have the same doping polarity, collectively referred to as the first doping polarity; the well region 13 has the second doping polarity, and the first doping polarity is the opposite of the second doping polarity. For example, when the device is an N-channel MOSFET, the first doping polarity is N-type and the second doping polarity is P-type; when the device is a P-channel MOSFET, the first doping polarity is P-type and the second doping polarity is N-type.

[0075] like Figure 3 As shown, Embodiment 1 of the present invention provides a planar gate MOSFET structure. An additional insulating dielectric layer 22 is provided directly above the JFET region 121, i.e., on one side of the first surface 101. In this embodiment, the gate 23 is a single structure that spans and completely covers the top and sidewalls of the insulating dielectric layer 22, and both sides of the gate 23 extend above the gate oxide layer 21. This structure, by adding an insulating dielectric layer 22 above the JFET region 121, locally increases the total thickness of the dielectric layer between the gate 23 and the JFET region 121, thereby reducing the gate-drain overlap capacitance C1, and consequently reducing the device's Miller capacitance C. gd .

[0076] like Figure 4As shown, Embodiment 2 of the present invention provides a planar gate MOSFET structure. Unlike Embodiment 1, this embodiment employs a split gate 23 structure. Specifically, an insulating dielectric layer 22 is implanted directly above the JFET region 121 near the first surface 101. The gate 23 is divided into left and right parts, located on opposite sides of the insulating dielectric layer 22. The vertical projections of the gate 23 and the insulating dielectric layer 22 do not overlap. The source 3 extends towards the JFET region 121 and covers the insulating dielectric layer 22. The insulating dielectric layer 22 isolates the electrical connection between the drain 4 and the gate 23 or the source 3. Simultaneously, the split gate 23 removes most of the gate conductive material directly above the JFET region 121, reducing the gate-drain overlap area and thus lowering the gate-drain overlap capacitance C1.

[0077] like Figure 5 As shown, Embodiment 3 of the present invention provides a planar gate MOSFET structure. The difference from Embodiment 2 is that this embodiment does not include an insulating dielectric layer 22. The gate 23 also adopts a split structure, with the source 3 extending downwards from the JFET region 121 to the split gate 23. An interlayer dielectric layer 24 is used for electrical isolation between the source 3 and the gate 23, and a gate oxide layer 21 is retained between the source 3 and the JFET region 121 for electrical isolation. This embodiment utilizes the downward extension of the source 3 to the split gate 23 to form a grounded electric field shielding structure. This source metal blocks the electric field coupling between the gate 23 and the JFET region 121, transforming the original gate-drain capacitance into gate-source capacitance and drain-source capacitance, thereby weakening the influence of the Miller capacitance.

[0078] It should be further explained that in the structure of this embodiment three, since the downwardly extending source 3 is isolated from the JFET region 121 only by a relatively thin gate oxide layer 21, this limits the maximum drain-source breakdown voltage capability of the device to some extent. However, it is precisely thanks to this extreme source electric field shielding structure that the Miller capacitance of the device is reduced to an extremely low level, thereby achieving extremely excellent ultra-high frequency switching characteristics. Therefore, the device structure provided in this embodiment three has specific industrial application value, and it is particularly suitable for low-voltage ultra-high frequency application scenarios where the operating voltage requirements are not high, but the switching speed and high-frequency parasitic capacitance are extremely sensitive, such as: RF power amplifiers, ultra-narrow pulse drive circuits for lidar, and low-voltage logic control switches in extreme high-temperature environments such as aerospace. In these specific scenarios, the operating voltage of the device is within the safe tolerance range of the gate oxide layer 21, and this embodiment three can maximize its technical advantages of extremely low switching losses and extremely fast switching speed.

[0079] like Figure 6As shown, Embodiment 4 of the present invention is a further optimization based on Embodiment 1. In Embodiment 1, the introduction of the insulating dielectric layer 22 reduces the control capability of the gate 23 over the JFET region 121 when the device is turned on, resulting in a decrease in the charge density of the surface layer of the JFET region 121, thereby increasing the on-resistance of the JFET region 121. To address this, in this embodiment, a current spreading layer 122 is implanted in the JFET region 121 near the first surface 101. The doping polarity of the current spreading layer 122 is the same as that of the silicon carbide epitaxial layer 12, and the projections of the current spreading layer 122 and the insulating dielectric layer 22 in the vertical direction at least partially overlap. The current spreading layer 122 can compensate for the increased on-resistance of the JFET region 121 caused by the introduction of the insulating dielectric layer 22, thereby reducing the device's Miller capacitance while avoiding deterioration of the on-resistance.

[0080] like Figure 1 As shown, this embodiment of the invention also provides a method for fabricating the above-mentioned semiconductor MOSFET device. Taking the structure of Embodiment 4 as an example, the specific steps of other embodiments are part of Embodiment 4, and their fabrication methods mainly include the following steps:

[0081] S1. Provide a semiconductor body and form a doped region within the semiconductor body.

[0082] Specifically, a silicon carbide epitaxial layer 12 is formed on a silicon carbide substrate 11 using an epitaxial process. The silicon carbide substrate 11 and the silicon carbide epitaxial layer 12 together constitute the semiconductor body. The first surface 101 of the semiconductor body is patterned at zero layer, and then alignment marks are formed by a wet etching process or a dry etching process.

[0083] like Figure 7 As shown, a hard mask is formed on the first surface 101 by chemical vapor deposition, and the first surface 101 is patterned to form a first mask 15; a trap region 13 is formed on the first surface 101 by ion implantation.

[0084] like Figure 8 As shown, an injection barrier layer is formed on the first surface 101 by chemical vapor deposition, and the first surface 101 is patterned. A sidewall 16 located on the sidewall of the first mask 15 and a source barrier layer 17 on the periphery are formed by wet etching or dry etching. A source region 14 is formed at the opening between the sidewall 16 and the source barrier layer 17 by ion implantation. Subsequently, the first mask 15, the sidewall 16 and the source barrier layer 17 are removed by wet etching or dry etching.

[0085] like Figure 9As shown, a hard mask is formed again on the first surface 101 by chemical vapor deposition, and the first surface 101 is patterned to form a second mask 18; a current extension layer 122 is formed in the JFET region 121 between adjacent well regions 13 by ion implantation; finally, the implanted doped region is activated by high-temperature annealing.

[0086] S2, A gate structure is formed on one side of the first surface.

[0087] Specifically, a field oxide layer is formed on the first surface 101 by chemical vapor deposition, and an active region is formed on one side of the first surface 101 by patterning, wet etching or dry etching.

[0088] like Figure 10 As shown, an insulating dielectric layer 22 is formed on the active region by chemical vapor deposition or oxidation process. Other parts of the insulating dielectric layer are removed by patterning, wet etching or dry etching process, leaving only the insulating dielectric layer 22 above the current spreading layer 122. The material of the insulating dielectric layer 22 can be SiO2, HfO2, etc.

[0089] like Figure 11 As shown, a gate oxide layer 21 is formed on one side of the first surface 101 by an oxidation process.

[0090] like Figure 12 As shown, a polysilicon layer is formed on one side of the first surface 101 by chemical vapor deposition, and the gate 23 is formed by patterning, wet etching or dry etching.

[0091] like Figure 13 As shown, an interlayer dielectric layer 24 is formed on the side away from the first surface 101 by chemical vapor deposition, wherein the interlayer dielectric layer 24 covers the gate 23.

[0092] S3, a source electrode is formed on one side of the first surface.

[0093] like Figure 14 As shown, the interlayer dielectric layer 24 and gate oxide layer 21 located on one side of the first surface 101 are etched by patterning and dry etching processes, and the source contact area is exposed on the first surface 101.

[0094] like Figure 15 As shown, the source electrode 3 is formed on one side of the first surface 101 and on the side of the gate structure 2 away from the first surface 101 by a metal sputtering process.

[0095] S4. A drain electrode is formed on one side of the second surface.

[0096] like Figure 6 As shown, the drain electrode 4 is formed on one side of the second surface 102 by metal sputtering process.

[0097] In summary, this invention proposes a semiconductor MOSFET device, comprising:

[0098] The semiconductor body 1 has a first surface 101 and a second surface 102 opposite to each other. The semiconductor body 1 includes a silicon carbide substrate 11 and a silicon carbide epitaxial layer 12 in sequence from the second surface 102 toward the first surface 101.

[0099] Multiple well regions 13 are spaced apart within the silicon carbide epitaxial layer 12 near the first surface 101, and the semiconductor body 1 between two adjacent well regions 13 constitutes a JFET region 121.

[0100] The source region 14 is located within the trap region 13 near the first surface 101 and is surrounded below by the trap region 13.

[0101] An insulating dielectric layer 22 is disposed on the first surface 101 and is located directly above the JFET region 121.

[0102] The gate oxide layer 21 is laid on the first surface 101. The gate oxide layer 21 is separated by the middle insulating dielectric layer 22, thus dividing it into two parts located on the left and right sides of the insulating dielectric layer 22.

[0103] Gate 23 is disposed above gate oxide layer 21.

[0104] Interlayer dielectric layer 24, which wraps around the outside of gate 23, is used to electrically isolate gate 23 from the surrounding structure.

[0105] The source electrode 3 is disposed above the first surface 101, covering the interlayer dielectric layer 24, and extending downward through the interlayer dielectric layer 24 to be electrically connected to the source region 14 and the well region 13.

[0106] Drain 4 is disposed on one side of the second surface 102.

[0107] A method for fabricating the above-mentioned semiconductor MOSFET device is also provided, the method comprising:

[0108] A silicon carbide substrate 11 is provided, and a silicon carbide epitaxial layer 12 is epitaxially grown on the silicon carbide substrate 11 to form a semiconductor body 1 having opposing first surfaces 101 and second surfaces 102.

[0109] Multiple spaced well regions 13 are formed in the silicon carbide epitaxial layer 12 near the first surface 101, and the semiconductor body 1 between two adjacent well regions 13 constitutes a JFET region 121.

[0110] A source region 14 is formed within the well region 13 near the first surface 101.

[0111] An insulating dielectric layer 22 is formed on the first surface 101 at a position corresponding to the JFET region 121.

[0112] A gate oxide layer 21 and a gate electrode 23 are formed on one side of the first surface 101.

[0113] A source electrode 3 is formed on one side of the first surface 101, and the source electrode 3 is electrically connected to the source region 14 and the well region 13.

[0114] A drain electrode 4 is formed on one side of the second surface 102.

[0115] The steps in this invention can be adjusted, combined, or deleted according to actual needs.

[0116] The units in the device of the present invention can be merged, divided, or reduced according to actual needs.

[0117] In this invention, the terms "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; "linking" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of these terms in this invention according to the specific circumstances.

[0118] The shapes of the components in the accompanying drawings are schematic and may differ from their actual shapes. The drawings are only used to illustrate the principles of the present invention and are not intended to limit the present invention.

[0119] Although the invention has been disclosed in detail with reference to the accompanying drawings, it should be understood that these descriptions are merely exemplary and not intended to limit the application of the invention. The scope of protection of the invention is defined by the appended claims and may include various modifications, alterations, and equivalents made to the invention without departing from the scope and spirit of the invention.

Claims

1. A semiconductor MOSFET device, characterized in that, The device has a planar gate structure, and the device includes: The semiconductor body (1) has a first surface (101) and a second surface (102) that are relatively planar. The semiconductor body (1) includes a silicon carbide substrate (11) and a silicon carbide epitaxial layer (12) in sequence from the second surface (102) toward the first surface (101). Multiple well regions (13) are spaced apart in the silicon carbide epitaxial layer (12) near the first surface (101), and the semiconductor body (1) between two adjacent well regions (13) constitutes a JFET region (121). The source region (14) is located in the trap region (13) near the first surface (101) and is surrounded by the trap region (13) below; An insulating dielectric layer (22) is disposed on the first surface (101) and is located directly above the JFET region (121); A gate oxide layer (21) is laid on the first surface (101). The gate oxide layer (21) is separated by an insulating dielectric layer (22) in the middle, thus dividing it into two parts located on the left and right sides of the insulating dielectric layer (22). The gate (23) is disposed above the gate oxide layer (21); An interlayer dielectric layer (24) is wrapped around the outside of the gate (23) to electrically isolate the gate (23) from the surrounding structure; The source electrode (3) is disposed above the first surface (101), covering the interlayer dielectric layer (24), and passing down through the interlayer dielectric layer (24) to be electrically connected to the source region (14) and the well region (13); The drain electrode (4) is disposed on one side of the second surface (102).

2. The semiconductor MOSFET device as described in claim 1, characterized in that, The gate (23) is a complete integral structure that spans and completely covers the top and left and right sidewalls of the insulating dielectric layer (22), and the gate (23) covers the gate oxide layer (21) on both sides.

3. The semiconductor MOSFET device as described in claim 1, characterized in that, The gate (23) is a split structure that is broken in the middle and divided into two parts, left and right. The two parts of the gate (23) cover the gate oxide layer (21) on both sides respectively; the gate (23) does not cover the insulating dielectric layer (22).

4. The semiconductor MOSFET device as described in claim 2, characterized in that, Inside the JFET region (121) and immediately adjacent to the first surface (101), there is a current spreading layer (122); the current spreading layer (122) is located directly below the insulating dielectric layer (22), and the projections of the two in the vertical direction at least partially overlap.

5. The semiconductor MOSFET device as described in claim 4, characterized in that, The doping polarity of the silicon carbide substrate (11), silicon carbide epitaxial layer (12), JFET region (121), source region (14) and current extension layer (122) is the first doping polarity; the doping polarity of the well region (13) is the second doping polarity, and the first doping polarity is opposite to the second doping polarity.

6. A method for fabricating a semiconductor MOSFET device as described in any one of claims 1 to 5, characterized in that, The preparation method includes: A silicon carbide substrate (11) is provided, and a silicon carbide epitaxial layer (12) is epitaxially grown on the silicon carbide substrate (11) to form a semiconductor body (1) having opposing first surfaces (101) and second surfaces (102). Multiple spaced well regions (13) are formed in the silicon carbide epitaxial layer (12) near the first surface (101), and the semiconductor body (1) between two adjacent well regions (13) constitutes a JFET region (121). A source region (14) is formed in the well region (13) near the first surface (101); An insulating dielectric layer (22) is formed on the first surface (101) at a position corresponding to the JFET region (121). A gate oxide layer (21) and a gate (23) are formed on one side of the first surface (101). A source electrode (3) is formed on one side of the first surface (101), and the source electrode (3) is electrically connected to the source region (14) and the well region (13); A drain electrode (4) is formed on one side of the second surface (102).

7. The preparation method according to claim 6, characterized in that, The steps for forming the well region (13) and the source region (14) include: A hard mask is formed and patterned on the first surface (101) to form a first mask plate (15). Using the first mask (15) as a barrier layer, a trap region (13) is formed by ion implantation. An injection barrier layer is formed and patterned on the first surface (101) to form a sidewall (16) located on the sidewall of the first mask (15) and a source region barrier layer (17) on the periphery. Using ion implantation, a source region (14) is formed at the opening between the sidewall (16) and the source region barrier layer (17). Remove the first mask (15), sidewalls (16) and source region blocking layer (17).

8. The preparation method according to claim 6, characterized in that, Before forming the insulating dielectric layer (22), the following are also included: A hard mask is formed and patterned on the first surface (101) to form a second mask (18), the second mask (18) having an opening above the JFET region (121); Using an ion implantation process, a current extension layer (122) is formed in the JFET region (121) below the opening. The implanted doped regions are activated by a high-temperature annealing process; The insulating dielectric layer (22) is positioned directly above the current spreading layer (122).

9. The preparation method according to claim 6, characterized in that, The steps for forming the insulating dielectric layer (22), the gate oxide layer (21), and the gate (23) include: An insulating dielectric material is deposited and patterned on the first surface (101), leaving only the insulating dielectric layer (22) directly above the JFET region (121). A gate oxide layer (21) is formed in the area of ​​the first surface (101) not covered by the insulating dielectric layer (22) by an oxidation process. A polysilicon layer is formed and patterned over the first surface (101) to form a gate (23).

10. The preparation method according to claim 6, characterized in that, The steps for forming the source (3) include: An interlayer dielectric layer (24) is formed on one side of the first surface (101), and the interlayer dielectric layer (24) covers the gate (23). The interlayer dielectric layer (24) and the gate oxide layer (21) are etched to expose the source contact region on the first surface (101); The source electrode (3) is formed above the first surface (101) by metal sputtering process. The source electrode (3) fills the source electrode contact area and covers the interlayer dielectric layer (24).

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