Shielded gate trench MOSFET device and its fabrication method

Abstract

This invention provides a shielded gate trench MOSFET device and its fabrication method. The device includes a semiconductor substrate, an epitaxial layer, a source trench, a gate trench, a high-k dielectric layer, a Schottky metal layer, and a front metal layer. Two gate trenches are arranged side-by-side and spaced apart between two source trenches. A high-k dielectric layer is disposed within the first trench. The Schottky metal layer is formed between the two gate trenches and forms a Schottky contact with the epitaxial layer, and is electrically connected to the source polysilicon through the front metal layer. This invention integrates a Schottky junction between the two gate trenches, utilizing the fast recovery property of the Schottky junction to optimize reverse recovery performance. Simultaneously, the high-k dielectric layer modulates the electric field distribution, reducing leakage current and breakdown risk, thus improving the device's reliability.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a shielded gate trench MOSFET device and its fabrication method. Background Technology

[0002] In the field of low- and medium-voltage power devices, trench power MOSFETs are widely used in motor drives, power management, synchronous rectification, and energy storage control due to their advantages such as low on-resistance, fast switching speed, and high cell density. However, breakdown voltage is positively correlated with on-resistance, and reducing on-resistance usually leads to breakdown voltage degradation, making it difficult to significantly reduce on-resistance.

[0003] Traditional shielded gate trench MOSFETs (SGT MOSFETs) utilize polysilicon connected to the source within a trench. This polysilicon, through its internal field-plate effect, assists in the depletion of the epitaxial drift region, modulating the triangular electric field distribution into an approximately rectangular distribution. This improves the breakdown voltage while simultaneously reducing on-resistance by increasing the doping concentration of the epitaxial layer. Furthermore, the grounded source polysilicon shields the electric field coupling between the gate and drain, effectively reducing switching losses.

[0004] In existing shielded gate trench MOS devices, when operating in reverse conduction (i.e., when the gate-source voltage Vgs is less than the threshold voltage Vth and the drain-source voltage Vds is less than 0), the reverse current flows from the source through the body diode to the drain. At this time, the body diode current exhibits minority carrier injection. These minority carriers undergo reverse recovery when the body diode is reverse biased again, resulting in a large reverse recovery current and a long reverse recovery time.

[0005] Therefore, optimizing the reverse recovery characteristics of traditional shielded gate trench MOS devices to reduce their reverse recovery losses has become an urgent technical problem to be solved.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a shielded gate trench MOSFET device and its fabrication method, which optimizes the reverse recovery characteristics of traditional shielded gate trench MOSFET devices and thereby reduces the reverse recovery loss of shielded gate trench MOSFET devices.

[0008] To achieve the above and other related objectives, the present invention provides a shielded gate trench MOSFET device, comprising:

[0009] Semiconductor substrate;

[0010] An epitaxial layer is formed on the surface of the semiconductor substrate;

[0011] Multiple source trenches extend downward from the surface of the epitaxial layer;

[0012] Sidewall oxide layer, the sidewall oxide layer being located on the sidewall and bottom of the source trench;

[0013] Source polycrystalline silicon is filled in the source trench and is in contact with the sidewall oxide layer;

[0014] Multiple gate trenches are arranged in pairs between two adjacent source trenches. The source trenches extend downward from the surface of the epitaxial layer and are arranged side by side and spaced apart. The mesa region of the epitaxial layer between the adjacent sidewall surfaces of two gate trenches is the first mesa region.

[0015] The gate oxide layer is located on the inner wall of the gate trench;

[0016] A gate polysilicon is filled in the gate trench and is in contact with the gate oxide layer;

[0017] The first trench is located in the sidewalls of the gate trench near both sides of the first mesa region, and a high-k dielectric layer is provided in the first trench.

[0018] A Schottky metal layer is formed in the first mesa region and forms a Schottky contact with the epitaxial layer;

[0019] The front metal layer includes a source metal region and a gate metal region that are isolated from each other; the source metal region covers the source polysilicon and the Schottky metal layer and is electrically connected to them, and the gate metal region is electrically connected to the gate polysilicon.

[0020] Optionally, it also includes:

[0021] The body region 250 is located within the epitaxial layer and between the gate trench and the source trench. The body region 250 extends downward from the surface of the epitaxial layer 200 to a first depth and is adjacent to the gate trench and the source trench.

[0022] The source region is located on the upper surface of the body region, extends downward from the surface of the epitaxial layer 200 to a second depth, the second depth being less than the first depth; and is adjacent to the gate trench and the source trench, and the source region is electrically connected to the source polysilicon;

[0023] An interlayer dielectric layer covers the upper surfaces of the epitaxial layer and the Schottky metal layer, and the interlayer dielectric layer has contact holes that expose the body region, the source polysilicon, the gate polysilicon and the Schottky metal layer;

[0024] The front metal layer is also located on the interlayer dielectric layer. Through the contact hole, the source metal region is electrically connected to the body region, the source region, the source polysilicon, and the Schottky metal layer, and the gate metal region is electrically connected to the gate polysilicon.

[0025] Optionally, the epitaxial layer is N-type doped, the body region is P-type doped, and the source region is N-type doped to form an N-type MOSFET; or the epitaxial layer is P-type doped, the body region is N-type doped, and the source region is P-type doped to form a P-type MOSFET.

[0026] Optionally, the depth of the first trench is less than or equal to the depth of the gate trench.

[0027] Optionally, the ratio of the depth of the first trench to the depth of the gate trench is in the range of 1 / 10 to 4 / 5.

[0028] Optionally, the distance between adjacent sidewall surfaces of the gate trench ranges from 0.5 μm to 10 μm.

[0029] Optionally, the high-k dielectric layer includes at least one of HfO2, Al2O3, ZrO2, Ta2O5, TiO2, and Si3N4, or a stacked structure of the above materials.

[0030] Optionally, the Schottky metal layer includes at least one of titanium, nickel, platinum, molybdenum, chromium, and tungsten, or a stacked structure of the above metals, or a stacked structure of the above metal nitrides, or a stacked structure of the above metals and the above metal nitrides, or a stacked structure of the above metal nitrides and the above metal nitrides.

[0031] This application also provides a method for fabricating a shielded gate trench MOSFET device, the method comprising the following steps:

[0032] A semiconductor substrate is provided, and an epitaxial layer is grown on the semiconductor substrate;

[0033] Multiple source trenches are formed extending downwards from the surface of the epitaxial layer;

[0034] A sidewall oxide layer is formed on the sidewall and bottom of the source trench;

[0035] The source trench is filled with source polycrystalline silicon;

[0036] Between each pair of adjacent source trenches, two parallel and spaced gate trenches are formed extending downward from the surface of the epitaxial layer; the epitaxial layer mesa region between the adjacent sidewall surfaces of the two gate trenches constitutes a first mesa region.

[0037] A gate oxide layer is formed, the gate oxide layer covering the inner wall of the gate trench;

[0038] The gate trench is filled with gate polysilicon;

[0039] A portion of the gate oxide layer near both sides of the first mesa region within the gate trench is removed to form a first trench; and simultaneously, the gate oxide layer located in the first mesa region is removed.

[0040] A high-k dielectric layer is filled into the first trench, and the high-k dielectric layer is located on both sides of the first mesa area;

[0041] A Schottky metal layer is formed on the first mesa region, and the Schottky metal layer forms a Schottky contact with the epitaxial layer;

[0042] A front metal layer is formed, the front metal layer including a source metal region and a gate metal region that are isolated from each other; the source metal region covers and electrically connects the source polysilicon and the Schottky metal layer, and the gate metal region is electrically connected to the gate polysilicon.

[0043] Optionally, it also includes:

[0044] After forming the high-k dielectric layer, a body region and a source region are formed in the mesa region between the gate trench and the source trench;

[0045] After the Schottky metal layer is formed, an interlayer dielectric layer is formed to cover the epitaxial layer, the gate trench, the source trench, and the upper surface of the Schottky metal layer.

[0046] Etching forms contact holes that expose at least the body region, the source region, the source polysilicon, the gate polysilicon, and the Schottky metal layer.

[0047] After the front metal layer is formed, the front metal layer is patterned to form a gate metal region and a source metal region; the source metal region is electrically connected to the body region, the source region, the source polysilicon and the Schottky metal layer through the contact hole; the gate metal region is electrically connected to the gate polysilicon through the contact hole.

[0048] The substrate is thinned on the back side to form a drain.

[0049] As described above, this invention discloses a shielded gate trench MOSFET device and its fabrication method, belonging to the field of power semiconductor technology. The device includes: a semiconductor substrate and an epitaxial layer; multiple source trenches filled with source polysilicon; multiple gate trenches arranged side-by-side and spaced apart between two source trenches, each gate trench filled with gate polysilicon; a first trench formed within the gate trench on one side near the region between two gate trenches, the first trench containing a high-k dielectric layer; a Schottky metal layer formed between two gate trenches and forming a Schottky contact with the epitaxial layer; and a front metal layer electrically connected to the source polysilicon through the front metal layer. This invention integrates a Schottky junction between two gate trenches, utilizing the fast recovery property of the Schottky junction to effectively optimize the reverse recovery performance of the device and reduce reverse recovery losses. Simultaneously, the high-k dielectric layers on both sides of the Schottky junction modulate the electric field, optimizing the electric field distribution at the Schottky junction and reducing the risk of device leakage and premature breakdown. Attached Figure Description

[0050] Figure 1 The diagram shows a schematic of the shielded gate trench MOSFET device of the present invention.

[0051] Figure 2 The diagram shows a flow chart of the fabrication method of the shielded gate trench MOSFET device in this invention.

[0052] Figure 3 The diagram shows the structure of the semiconductor substrate after the epitaxial layer has been grown in this invention.

[0053] Figure 4 The diagram shows the structure after the first hard mask layer is formed on the epitaxial layer in this invention.

[0054] Figure 5 The diagram shown is a schematic of the structure after the source trench is formed in this invention.

[0055] Figure 6 The diagram shown is a schematic representation of the structure after the sidewall oxide layer is formed in this invention.

[0056] Figure 7 The diagram shows the structure of the present invention after filling the source polysilicon and removing the first hard mask layer.

[0057] Figure 8 The diagram shows the structure after the gate trench is formed in this invention.

[0058] Figure 9 The diagram shows the structure after the gate oxide layer is formed and the gate polysilicon is filled in the present invention.

[0059] Figure 10The diagram shows the structure after the first trench is formed in this invention.

[0060] Figure 11 The diagram shown is a schematic representation of the structure after filling with a high-k dielectric layer in this invention.

[0061] Figure 12 The diagram shows the structure after the source region and body region are formed in this invention.

[0062] Figure 13 The diagram shown is a schematic representation of the structure after the formation of the Schottky metal layer in this invention.

[0063] Figure 14 The diagram shows the structure after the front metal layer is formed in this invention.

[0064] Explanation of reference numerals in the attached figures

[0065] 100 Semiconductor substrate; 200 Epitaxial layer; 210 Source trench; 211 Sidewall oxide layer; 212 Source polysilicon; 220 Gate trench; 221 Gate oxide layer; 222 Gate polysilicon; 230 First trench; 231 High-k dielectric layer; 240 Schottky metal layer; 250 Body region; 251 Heavily doped body region; 260 Source region; 270 Interlayer dielectric layer; 271 Contact hole; 280 Front metal layer; 310 First hard mask layer; 320 Second hard mask layer; 400 Drain. Detailed Implementation

[0066] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0067] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0068] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0069] Please see Figures 1-14 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0070] Example 1

[0071] This embodiment provides a shielded gate trench MOSFET device. Please refer to [link / reference]. Figure 1 The diagram shows a schematic of a shielded gate trench MOSFET device, including:

[0072] Semiconductor substrate 100; specifically, the semiconductor substrate 100 serves as a support structure for the device. The semiconductor substrate 100 may be a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, or other suitable semiconductor material substrate. In this embodiment, the semiconductor substrate 100 is preferably a single-crystal silicon substrate.

[0073] As an example, depending on the conductivity type of the device, the semiconductor substrate 100 can be of N-type or P-type conductivity. When the semiconductor substrate 100 is of N-type conductivity, the device forms an N-type MOSFET; when the semiconductor substrate 100 is of P-type conductivity, the device forms a P-type MOSFET. This embodiment uses an N-type MOSFET as an example, that is, the semiconductor substrate 100 is a heavily doped N-type silicon substrate with low resistivity, used to reduce the on-resistance of the device.

[0074] The thickness of the semiconductor substrate 100 can be selected according to the voltage withstand requirements of the device and the fabrication process. In subsequent processes, the back side of the semiconductor substrate 100 will be thinned to form a metal layer corresponding to the drain electrode.

[0075] An epitaxial layer 200 is formed on the surface of the semiconductor substrate 100.

[0076] As an example, the epitaxial layer 200 is formed on the upper surface of the semiconductor substrate 100 by an epitaxial growth process. The epitaxial layer 200 has the same conductivity type as the semiconductor substrate 100, but its doping concentration is lower than that of the semiconductor substrate 100. Specifically, when the semiconductor substrate 100 is N-type, the epitaxial layer 200 is a lightly doped N-type epitaxial layer, serving as a drift region of the device to withstand reverse voltage.

[0077] The doping concentration and thickness of the epitaxial layer 200 are determined according to the voltage rating of the device. The higher the voltage rating, the lower the doping concentration and the greater the thickness of the epitaxial layer 200; the lower the voltage rating, the higher the doping concentration and the smaller the thickness of the epitaxial layer 200.

[0078] The upper surface of the epitaxial layer 200 is the active surface of the device, and subsequent trench structures, injection regions, etc., are formed on this surface. The epitaxial layer 200 provides space for the formation of trench structures, and at the same time serves as a drift region to provide a current path when the device is turned on, and is depleted to withstand reverse voltage when the device is turned off.

[0079] Multiple source trenches 210 extend downward from the surface of the epitaxial layer 200.

[0080] Specifically, two or more source trenches 210 are provided, extending vertically downward from the upper surface of the epitaxial layer 200 to a predetermined depth inside the epitaxial layer 200. The depth of the source trenches 210 is greater than the depth of the subsequent gate trenches 220, allowing the subsequent source polysilicon 212 to penetrate deeper into the epitaxial layer 200, thereby better utilizing the field plate effect and assisting in the depletion of the epitaxial drift region. The width and depth of the source trenches 210 can be selected according to the voltage rating and process capability of the device, and are not limited here. For the sake of simplicity, only a portion of the source trench structure is shown in the accompanying drawings of this embodiment.

[0081] As an example, the cross-sectional shape of the source trench 210 can be rectangular, trapezoidal, or U-shaped. This embodiment uses a rectangular shape as an example, but the invention is not limited thereto. The number of source trenches 210 can be set according to the cell size and current capacity requirements of the device, with at least two trenches provided to ensure symmetry. Multiple source trenches 210 are arranged in parallel, forming a mesa region between adjacent source trenches 210 for setting the subsequent gate trench 220, body region 250, and source region 260.

[0082] Sidewall oxide layer 211, the sidewall oxide layer 211 is located on the sidewall and bottom of the source trench 210.

[0083] Specifically, the sidewall oxide layer 211 serves as an insulating layer to electrically isolate the subsequent source polysilicon 212 from the epitaxial layer 200. The material of the sidewall oxide layer 211 is silicon dioxide (SiO2) or silicon nitride (Si3N4), preferably silicon dioxide. The thickness of the sidewall oxide layer 211 is determined according to the voltage withstand requirements of the device and is not limited here. A thicker sidewall oxide layer 211 can withstand higher voltages and prevent breakdown between the subsequent source polysilicon 212 and the epitaxial layer 200.

[0084] The sidewall oxide layer 211 can be formed by thermal oxidation or chemical vapor deposition. When thermal oxidation is used, the sidewall oxide layer 211 forms a high-quality silicon-silicon dioxide interface with the silicon material of the epitaxial layer 200, resulting in a low interface state density, which is beneficial to improving device reliability. The sidewall oxide layer 211 covers the entire inner wall of the source trench 210, including the sidewalls and bottom, ensuring complete isolation between the subsequent source polysilicon 212 and the epitaxial layer 200. In the bottom corner region of the source trench 210, the thickness of the sidewall oxide layer 211 can be appropriately increased to alleviate the electric field concentration effect and improve the breakdown voltage of the device.

[0085] The source polycrystalline silicon 212 is filled in the source trench 210 and is in contact with the sidewall oxide layer 211.

[0086] As an example, the source polysilicon 212 is doped polysilicon with high conductivity, and its doping type is the same as that of the semiconductor substrate 100.

[0087] Specifically, the source polysilicon 212 is electrically connected to the source potential, and in this embodiment, it is electrically connected to the source metal region through a subsequently formed front metal layer 280. During operation, the source polysilicon 212 is grounded, acting as a body field plate. Specifically, when the device is turned off, a potential difference is formed between the source polysilicon 212 and the epitaxial layer 200, which helps to deplete the epitaxial layer 200 and introduces a new electric field peak at the bottom of the source trench 210, modulating the traditional triangular electric field distribution into an approximately rectangular electric field distribution. This allows the device to withstand a higher reverse voltage with the same thickness of the epitaxial layer 200, or to allow the use of an epitaxial layer 200 with a higher doping concentration under the same withstand voltage requirements, thereby reducing the on-resistance of the device. In addition, the source polysilicon 212 also reduces the electric field coupling between the gate and drain through electric field shielding, converting the gate-drain capacitance that affects the switching speed into gate-source capacitance and drain-source capacitance, effectively reducing switching losses.

[0088] The upper surface of the source polysilicon 212 can be flush with the upper surface of the epitaxial layer 200 or slightly recessed. In this embodiment, the upper surface of the source polysilicon 212 is flush with the upper surface of the epitaxial layer 200 to facilitate the planarization deposition of the interlayer dielectric layer 270. The filling of the source polysilicon 212 can be performed using a low-pressure chemical vapor deposition process, and planarization can be achieved by etching back or chemical mechanical polishing.

[0089] Multiple gate trenches 220 are arranged in pairs between two adjacent source trenches 210. The gate trenches 220 extend downward from the surface of the epitaxial layer 200 and are arranged side by side and spaced apart. The mesa region of the epitaxial layer 200 between the adjacent sidewall surfaces of two gate trenches 220 is the first mesa region (not labeled).

[0090] As an example, the first mesa region is used for the subsequent formation of the Schottky metal layer 240. Additionally, the mesa region of the epitaxial layer 200 between the gate trench 220 and the adjacent source trenches 210 on both sides constitutes the second mesa region.

[0091] As an example, each of the gate trenches 220 and the structures on both sides form different functional regions. The side of the gate trench 220 facing the first mesa region is subsequently used to form the first trench 230 and the high-k dielectric layer 231. The side of the gate trench 220 facing the second mesa region is subsequently used to form the body region 250 and the source region 260, and serves as the channel region.

[0092] The depth of the gate trench 220 can be designed according to the voltage withstand requirements and channel length of the device. In this embodiment, the depth of the gate trench 220 is less than the depth of the source trench 210, so that the source polysilicon 212 can extend below the gate trench 220, thus better utilizing the field plate effect.

[0093] As an example, the distance between adjacent sidewall surfaces of the gate trench 220 ranges from 0.5 μm to 10 μm.

[0094] Specifically, the spacing between the two gate trenches 220 can be set according to the size requirements and electric field distribution requirements of the Schottky junction, preferably in the range of 0.5μm to 10μm, such as any value within this range, including 0.5μm, 1μm, 3μm, 5μm, 7μm, and 10μm. Of course, the distance between the gate trenches 220 is not limited to this.

[0095] Furthermore, the cross-sectional shape of the gate trench 220 can be rectangular, trapezoidal, or U-shaped; this embodiment uses a rectangular shape as an example. The inner wall of the gate trench 220 will subsequently form a gate oxide layer 221 and be filled with gate polysilicon 222 for controlling the opening and closing of the channel.

[0096] Gate oxide layer 221 is located on the inner wall of the gate trench 220.

[0097] Specifically, the gate oxide layer 221 covers the sidewalls and bottom of the gate trench 220. The gate oxide layer 221 serves as an insulating layer between the subsequent gate polysilicon 222 and the epitaxial layer 200, and its quality directly affects the device's threshold voltage, channel mobility, gate-drain capacitance, and reliability.

[0098] As an example, the gate oxide layer 221 is preferably made of silicon dioxide (SiO2), which can be formed by a thermal oxidation process. The thermal oxidation process can form a high-quality silicon-silicon dioxide interface on the sidewalls and bottom of the gate trench 220, with a low interface state density, which is beneficial for improving the channel carrier mobility and the long-term reliability of the device. The thickness of the gate oxide layer 221 is determined according to the threshold voltage requirements and gate drive voltage of the device, and those skilled in the art can select it according to actual needs.

[0099] It should be noted that in subsequent processes, the gate oxide layer 221 on the side of the gate trench 220 closest to the region between the two gate trenches 220 will be removed to form the subsequent first trench 230 for filling the high-k dielectric layer 231. The gate oxide layer 221 in other regions of the gate trench 220 (such as the sidewalls and bottom of the trench facing the source trench 210) is retained to ensure insulation between the subsequent gate polysilicon 222 and the epitaxial layer 200.

[0100] The gate polysilicon 222 is filled in the gate trench 220 and is in contact with the gate oxide layer 221.

[0101] Specifically, the gate polysilicon 222 is doped polysilicon with high conductivity. For N-type MOSFETs, the gate polysilicon 222 is preferably N-type doped; for P-type MOSFETs, the gate polysilicon 222 is preferably P-type doped. Those skilled in the art can select the appropriate doping type based on process compatibility and threshold voltage requirements.

[0102] The gate polysilicon 222 is electrically connected to the gate potential, and in this embodiment, it is electrically connected to the gate metal region through a subsequently formed front metal layer 280. During operation, when a forward voltage (for an N-type MOSFET) is applied to the gate and exceeds the threshold voltage, an inversion layer channel is formed on the side of the body region 250 near the gate oxide layer 221. Electrons from the source region 260 flow into the epitaxial layer 200 through the channel, and the device is turned on. When the gate voltage is lower than the threshold voltage, the channel disappears, and the device is turned off.

[0103] As an example, the upper surface of the gate polysilicon 222 can be flush with the upper surface of the epitaxial layer 200 or slightly recessed. In this embodiment, the upper surface of the gate polysilicon 222 is flush with the upper surface of the epitaxial layer 200 to facilitate the planarization deposition of the interlayer dielectric layer 270. The gate polysilicon 222 can be filled using a low-pressure chemical vapor deposition process and planarized by etch-back or chemical mechanical polishing.

[0104] The first trench 230 is located within the sidewalls of the gate trench 220 near the first mesa region. A high-k dielectric layer 231 is provided within the first trench 230. Specifically, after forming the gate oxide layer 221 and filling the gate polysilicon 222, the gate oxide layer 221 facing the first mesa region of the gate trench 220 is removed by an etching process, and a predetermined depth is etched downwards from the surface of the epitaxial layer 200 from this sidewall position to form the first trench 230. The first trench 230 is located on the sidewall of the gate trench 220, with its opening facing upwards and flush with the upper surface of the epitaxial layer 200. The subsequently filled high-k dielectric layer 231 contacts the gate polysilicon 222.

[0105] As an example, the depth of the first trench 230 is less than or equal to the depth of the gate trench 220.

[0106] Specifically, the depth of the first trench 230 can be designed according to the electric field modulation requirements. In this embodiment, the depth of the first trench 230 is less than or equal to the depth of the gate trench 220, so as to fully utilize the modulation effect of the high-k dielectric layer 231 on the electric field at the Schottky junction.

[0107] In a preferred embodiment, the ratio of the depth of the first trench 230 to the depth of the gate trench 220 is in the range of 1 / 10 to 4 / 5, such as any value within this range, including 1 / 10, 1 / 8, 1 / 6, 1 / 4, 2 / 5, 4 / 5, etc. Within this range, a good balance between electric field modulation effect and process feasibility can be achieved.

[0108] Specifically, when the depth ratio of the first trench 230 is in the range of 1 / 10 to 4 / 5, the high-k dielectric layer 231 can effectively couple the electric field of the Schottky junction region. If the ratio is too low (less than 1 / 10), the depth of the high-k dielectric layer 231 is insufficient to fully cover the depletion region of the Schottky junction, resulting in limited electric field modulation. Local electric field concentration may still occur at the edge of the Schottky junction, leading to increased reverse leakage current and even premature breakdown. If the ratio is in the range of 1 / 10 to 4 / 5, the depth of the high-k dielectric layer 231 is sufficient to cover the main depletion region of the Schottky junction. Through the capacitive coupling effect of the high-k dielectric, the electric field originally concentrated at the edge of the Schottky junction is dispersed to a wider vertical region, making the electric field distribution more uniform and effectively suppressing local electric field spikes, thereby reducing reverse leakage current and improving breakdown voltage. If the ratio is too high (greater than 4 / 5), the high-k dielectric layer 231 extends excessively, which may adversely affect the electric field distribution at the bottom of the gate trench 220. At the same time, it increases the process difficulty, reduces the uniformity of the high-k dielectric filling in the deep trench, and the resulting improvement in electric field modulation effect is limited, reducing cost-effectiveness.

[0109] Furthermore, within this ratio range, the high-k dielectric layer 231 forms an effective capacitive coupling with the source polysilicon 212. When the device is turned off, the source polysilicon 212 acts as a field plate to assist in the depletion of the epitaxial layer 200. The high-k dielectric layer 231 further enhances this depletion effect, allowing the use of the epitaxial layer 200 with a higher doping concentration under the same breakdown voltage requirements, thereby reducing the on-resistance of the device. Simultaneously, the ratio range of 1 / 10 to 4 / 5 balances process feasibility, with the lower limit ensuring a sufficient process window and the upper limit avoiding excessively high aspect ratios. This allows the high-k dielectric layer 231 to achieve good step coverage and filling uniformity, ensuring device yield and reliability. Therefore, by limiting the ratio of the depth of the first trench 230 to the depth of the gate trench 220 to the range of 1 / 10 to 4 / 5, this invention achieves precise modulation of the electric field at the Schottky junction, optimizing the reverse...

[0110] While restoring performance, it reduced reverse leakage current, improved breakdown voltage, and took into account on-resistance and process feasibility, achieving comprehensive technical results.

[0111] As an example, the high-k dielectric layer 231 includes at least one of HfO2, Al2O3, ZrO2, Ta2O5, TiO2, Si3N4, or a stacked structure of the above materials.

[0112] Specifically, the high-k dielectric layer 231 is filled in the first trench 230, and its dielectric constant is higher than that of silicon dioxide (SiO2, k≈3.9), which can provide higher capacitance density without increasing the thickness of the dielectric layer.

[0113] Furthermore, the material of the high-k dielectric layer 231 includes, but is not limited to, at least one of HfO2 (hafnium oxide), Al2O3 (aluminum oxide), ZrO2 (zirconia), Ta2O5 (tantalum oxide), TiO2 (titanium oxide), and Si3N4 (silicon nitride). In this embodiment, the high-k dielectric layer 231 is preferably HfO2, which has a high dielectric constant and good thermal stability, and good compatibility with existing semiconductor processes.

[0114] As an example, the high-k dielectric layer 231 is a multilayer stacked structure, such as consisting of a first high-k sublayer and a second high-k sublayer. The first high-k sublayer (e.g., hafnium oxide) has a high dielectric constant, while the second high-k sublayer (e.g., aluminum oxide) has a high breakdown field strength and a low leakage current. This multilayer structure combines the advantages of different materials, ensuring capacitive coupling while reducing leakage current through the high-k dielectric layer, thus improving device reliability.

[0115] The high-k dielectric layer 231 can be formed using processes such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). AALD, in particular, allows for precise control of atomic-level thickness and provides excellent step coverage in high aspect ratio trenches, making it suitable for filling the first trench 230. After deposition, excess high-k dielectric material outside the first trench 230 can be removed by etchback or chemical mechanical polishing.

[0116] The high-k dielectric layer 231 of the present invention uses the polarization effect of high dielectric constant material to physically smooth the electric field distribution. Its process is highly compatible with existing CMOS processes and can be completed by deposition and etch-back only. It does not involve high-temperature impurity activation and does not consume additional thermal budget in the MOSFET channel region.

[0117] The high-k dielectric layer 231 and the Schottky metal layer 240 work together to optimize the electric field distribution of the device. Specifically, when the device is in reverse blocking mode, the high-k dielectric layer 231 can modulate the electric field distribution at the Schottky junction, making the electric field more uniform and avoiding local electric field concentration at the edge of the Schottky junction, thereby reducing reverse leakage current and preventing premature device breakdown. Simultaneously, the high-k dielectric layer 231 and the source polysilicon 212 work together to further optimize the depletion effect of the epitaxial drift region, improving the device's withstand voltage capability. The process is simple and low-cost. As an example, before filling the high-k dielectric layer 231, an interface buffer layer can be formed on the inner wall of the first trench 230. The interface buffer layer is located on the sidewalls and bottom of the first trench 230, sandwiched between the semiconductor material of the epitaxial layer 200 and the high-k dielectric layer 231. The interface buffer layer can be a silicon oxide layer, formed by thermal oxidation or atomic layer deposition. By setting the interface buffer layer, without affecting the electric field modulation function of the high-k dielectric layer, the potential lattice mismatch or interface states between the high-k dielectric material and the silicon semiconductor material (when the epitaxial layer material is silicon) can be improved, reducing the possibility of leakage current. Furthermore, by preventing impurities or defects in the high-k dielectric layer 231 from diffusing to the semiconductor surface, the long-term reliability of the device is improved.

[0118] A Schottky metal layer 240 is formed in the first mesa region and forms a Schottky contact with the epitaxial layer 200.

[0119] Specifically, the Schottky metal layer 240 and the semiconductor material of the epitaxial layer 200 form a metal-semiconductor contact. Due to the difference between the work function of the metal and the electron affinity of the semiconductor, a Schottky barrier is formed at the contact interface, thereby constituting a Schottky diode.

[0120] The Schottky metal layer 240 is formed between the two gate trenches 220, specifically in the first mesa region between the two gate trenches 220, and covers the upper surface of the epitaxial layer 200. The Schottky metal layer 240 is in direct contact with the epitaxial layer 200, forming a Schottky junction at the contact interface. As an example, the width of the Schottky metal layer 240 is less than or equal to the width of the first mesa region, eliminating electric field concentration and leakage paths at the edges of the Schottky metal layer 240.

[0121] The Schottky metal layer 240 is electrically connected to the source polysilicon 212, specifically through a subsequently formed front metal layer 280. During operation, the Schottky junction is integrated in parallel with the MOSFET structure. When the device is reverse-biased, the reverse current preferentially flows through the Schottky junction. Since the Schottky junction is a majority carrier device, there is no minority carrier injection phenomenon, thus eliminating the minority carrier storage effect. The reverse recovery time is extremely short, and the reverse recovery loss is extremely low, effectively optimizing the reverse recovery performance of the device. Simultaneously, the high-k dielectric layers 231 on both sides of the Schottky junction modulate the electric field, preventing electric field concentration at the edge of the Schottky junction, reducing reverse leakage current, preventing premature device breakdown, and further improving the reliability and stability of the device.

[0122] This application achieves cell-level integration of the Schottky junction and MOSFET structure by directly integrating the Schottky junction into the first mesa region inside the MOSFET cell. This saves chip area and increases current density. At the same time, it shortens the current path between the Schottky junction and the channel region, reducing parasitic inductance. Furthermore, it enables the high-k dielectric layer 231 to simultaneously modulate the Schottky junction electric field and the auxiliary shielding gate depletion.

[0123] As an example, for an N-type MOSFET, the epitaxial layer 200 is of N-type conductivity, and the Schottky metal layer 240 forms a Schottky contact with the N-type epitaxial layer; for a P-type MOSFET, the epitaxial layer 200 is of P-type conductivity, and the Schottky metal layer 240 forms a Schottky contact with the P-type epitaxial layer. In a preferred embodiment, the Schottky metal layer 240 is a titanium / titanium nitride (Ti / TiN) stacked structure, and the epitaxial layer 200 is a silicon epitaxial layer, wherein the titanium layer forms a low-barrier Schottky contact with the silicon epitaxial layer, reducing the forward conduction voltage. The titanium nitride layer acts as a barrier layer and adhesion layer, preventing oxidation of the titanium layer and enhancing the adhesion to the subsequent interlayer dielectric layer 270, thereby improving the reliability and process stability of the device.

[0124] As an example, the Schottky metal layer 240 includes at least one of titanium, nickel, platinum, molybdenum, chromium, and tungsten, or a stacked structure of the above metals, or a stacked structure of the above metal nitrides, or a stacked structure of the above metals and the above metal nitrides, or a stacked structure of the above metal nitrides and the above metal nitrides.

[0125] Specifically, the choice of material for the Schottky metal layer 240 determines the height of the Schottky barrier, which in turn affects the forward voltage drop and reverse leakage current of the Schottky diode. As an example, the material of the Schottky metal layer 240 includes, but is not limited to, at least one of titanium (Ti), nickel (Ni), platinum (Pt), molybdenum (Mo), chromium (Cr), and tungsten (W), or a stacked structure of the above metals (such as Ti / Ni, Ti / Pt, Ni / Pt, etc.), or nitrides of the above metals (such as TiN, NiN, PtN, etc.), and composite structures formed by the above metals and their nitrides (such as Ti / TiN, Ni / TiN, Pt / TiN, etc.).

[0126] As an example, the Schottky metal layer 240 can be formed using physical or chemical deposition processes such as sputtering, electron beam evaporation, or chemical vapor deposition. Before forming the Schottky metal layer 240, the surface of the epitaxial layer 200 can be cleaned and pretreated to remove the native oxide layer, ensuring the formation of high-quality Schottky contacts. After deposition, the unwanted areas of the Schottky metal layer 240 can be removed using photolithography and etching processes, retaining only the first mesa region between the two gate trenches 220. Of course, the formation method of the Schottky metal layer 240 is not limited to this.

[0127] Those skilled in the art will understand that the above examples of materials and processes are only used to illustrate possible implementations of the present invention, and are not intended to limit the present invention.

[0128] As an example, the width of the Schottky metal layer 240 is smaller than the width of the first mesa region, such that a gap is formed between the edge of the Schottky metal layer 240 and the sidewall of the high-k dielectric layer 231; preferably, the distance of the gap is in the range of 0.05~0.3μm.

[0129] Specifically, the purpose of this gap is to prevent the edge of the Schottky metal layer 240 from directly covering or adhering to the sidewall of the high-k dielectric layer 231, thereby further mitigating the electric field concentration effect at the metal edge. When the gap is within the aforementioned range, it can effectively reduce the electric field spike at the edge of the Schottky junction without sacrificing the effective Schottky contact area due to an excessively large gap, thus achieving a better balance between reverse leakage current and forward conduction voltage drop.

[0130] As an example, the shielded gate trench MOSFET device further includes a body region 250, a source region 260, and an interlayer dielectric layer 270.

[0131] As an example, the epitaxial layer 200 is N-type doped, the body region 250 is P-type doped, and the source region 260 is N-type doped to form an N-type MOSFET; or the epitaxial layer 200 is P-type doped, the body region 250 is N-type doped, and the source region 260 is P-type doped to form a P-type MOSFET. This embodiment uses an N-type MOSFET as an example for illustration. When the device is a P-type MOSFET, only the conductivity type of each region needs to be interchanged accordingly, and those skilled in the art can implement it based on the description of this embodiment.

[0132] The body region 250 is located within the epitaxial layer 200 and between the gate trench 220 and the source trench 210. The body region 250 extends downward from the surface of the epitaxial layer 200 to a first depth and is adjacent to the gate trench 220 and the source trench 210.

[0133] Specifically, the lower surface of the body region is higher than the lower surface of the source trench; the body region is adjacent to the sidewalls of the gate trench 220 and the source trench 210. The conductivity type of the body region 250 is opposite to that of the epitaxial layer 200, being P-type doped for N-type MOSFETs and N-type doped for P-type MOSFETs.

[0134] As an example, the body region 250 can be formed by photolithographic ion implantation followed by high-temperature annealing. After forming the source trench 210 and the gate trench 220, the implantation region is defined by a photoresist mask, ion implantation is performed, and then high-temperature annealing is carried out to form the body region 250 with a suitable doping concentration and junction depth.

[0135] The body region 250 is adjacent to the sidewall of the gate trench 220. When a voltage is applied to the gate, an inversion layer channel is formed in the region of the body region 250 near the sidewall of the gate trench 220, enabling the device to conduct. The body region 250 is electrically connected to the subsequent source metal region through the contact hole 271, fixed at the source potential, and is potential-connected to the Schottky metal layer 240 through the source metal region, allowing the Schottky junction to operate in parallel with the MOSFET and optimizing reverse recovery performance. Simultaneously, the high-k dielectric layer 231 on both sides of the Schottky junction modulates the electric field, improving the breakdown voltage and reliability of the device. Preferably, a heavily doped body region 251 is also provided within the body region 250 to reduce contact resistance and suppress parasitic effects.

[0136] The source region 260 is located on the upper surface of the body region 250; it extends downward from the surface of the epitaxial layer 200 to a second depth, the second depth being less than the first depth; and it is adjacent to the gate trench 220 and the source trench 210, and the source region 260 is electrically connected to the source polysilicon 212 through the subsequent formation of a front metal layer 280.

[0137] The source region 260 is located on the upper surface of the body region 250, extending downward from the surface of the epitaxial layer 200, and its depth is less than the depth of the body region 250. The source region 260 is adjacent to the sidewalls of the gate trench 220 and the source trench 210, and is electrically connected to the source polysilicon 212. The conductivity type of the source region 260 is opposite to that of the body region 250; it is N-type doped for N-type MOSFETs and P-type doped for P-type MOSFETs.

[0138] The source region 260 is formed by photolithographic ion implantation followed by high-temperature annealing. When a voltage is applied to the gate, the source region 260 is connected to the epitaxial layer 200 through a channel formed by the body region 250 near the sidewall of the gate trench 220. The source region 260 is electrically connected to the source metal region through a contact hole 271, thereby achieving source lead-out.

[0139] The interlayer dielectric layer 270 covers the upper surfaces of the epitaxial layer 200 and the Schottky metal layer 240, and the interlayer dielectric layer 270 has contact holes 271 that expose the body region 250, the source polysilicon 212, the gate polysilicon 222 and the Schottky metal layer 240.

[0140] The interlayer dielectric layer 270 has contact holes 271, which expose the Schottky metal layer 240. The contact holes 271 are formed above the Schottky metal layer 240 and are used to realize the potential connection between the Schottky junction and the source.

[0141] The front metal layer 280 includes a source metal region and a gate metal region that are isolated from each other; the source metal region covers and is electrically connected to the source polysilicon 212 and the Schottky metal layer 240, and the gate metal region is electrically connected to the gate polysilicon 222.

[0142] Specifically, the front metal layer 280 is formed on the front side of the device to realize the electrical lead-out and interconnection of each electrode. The front metal layer 280 is electrically connected to the Schottky metal layer 240 and simultaneously electrically connected to the source polysilicon 212, so that the Schottky metal layer 240 and the source polysilicon 212 are potential-connected through the front metal layer 280, that is, the anode of the Schottky junction and the source of the MOSFET are connected at the same potential. This potential connection structure allows the Schottky junction and the MOSFET structure to operate in parallel: when the device is forward-biased, the MOSFET channel is turned on, and the current mainly flows through the channel; when the device is reverse-biased, the reverse current preferentially flows through the Schottky junction. Since the Schottky junction is a majority carrier device, there is no minority carrier injection phenomenon, and the reverse recovery time is extremely short, thereby effectively reducing the reverse recovery loss.

[0143] In a preferred embodiment, the front metal layer 280 is also located on the interlayer dielectric layer 270. Through the contact hole 271, the source metal region is electrically connected to the body region 250, the source region 260, the source polysilicon 212, and the Schottky metal layer 240, and the gate metal region is electrically connected to the gate polysilicon 222, for applying a gate control voltage to independently control the turning on and off of the MOSFET. Through this patterned design, the source and gate are brought out separately, avoiding signal interference and ensuring the stability of device operation.

[0144] As an example, the material of the front metal layer 280 is preferably a high-conductivity metal or alloy, including but not limited to aluminum (Al), copper (Cu), aluminum-silicon alloy (Al-Si), aluminum-copper alloy (Al-Cu), etc., to reduce metal interconnect resistance and decrease signal transmission delay and power loss. The front metal layer 280 can be formed using processes such as sputtering, evaporation, or electroplating to meet the requirements of current carrying capacity and reliability. Of course, the material of the front metal layer 280 is not limited to these.

[0145] Example 2

[0146] The shielded gate trench MOSFET device described in Embodiment 1 above can be fabricated using various methods. The following describes the process in conjunction with the appendix... Figures 1 to 14 This specification provides a detailed description of an exemplary fabrication method for this device. This method is not the only approach, and those skilled in the art can employ other reasonable modifications based on the description herein.

[0147] First, refer to Figure 2 and Figure 3 Step S1 is executed, a semiconductor substrate 100 is provided, and an epitaxial layer 200 is grown on the semiconductor substrate 100.

[0148] Specifically, the conductivity type, doping concentration, and other parameters of the semiconductor substrate 100 and the epitaxial layer 200 are as described in Example 1, and will not be repeated here.

[0149] Next, refer to Figure 2 and Figures 4-5 In step S2, a plurality of source trenches 210 are formed extending downward from the surface of the epitaxial layer 200.

[0150] Specifically, in one embodiment, a first hard mask layer 310 with the source trench 210 pattern is formed on the surface of the epitaxial layer 200 using a photolithography process. Then, an anisotropic dry etching process (such as reactive ion etching) is used to etch vertically downwards from the surface of the epitaxial layer 200 to form the source trench 210 with a predetermined depth and width. In one embodiment, the first hard mask layer 310 may be temporarily retained and can serve as a protective layer for the epitaxial layer 200 and as a stop layer for subsequent CMP processes. The source trench 210 is then cleaned to remove etching residues and contaminants, preparing for the formation of the subsequent sidewall oxide layer 211. Of course, in other embodiments, the first hard mask layer 310 may also be removed in this step.

[0151] The structural features of the source trench 210 (such as cross-sectional shape, arrangement, depth design principles, etc.) are as described in Embodiment 1, and will not be repeated here.

[0152] As an example, the first hard mask layer 310 includes at least one of silicon nitride and silicon oxide, or a stacked structure of both. Preferably, in this embodiment, the first hard mask layer 310 adopts a structure composed of an oxide layer, a silicon nitride layer, and an oxide layer stacked together. This is to protect the non-etched areas during dry etching and improve the topography control and dimensional accuracy of the trenches.

[0153] Next, refer to Figure 2 and Figure 6 Step S3 is executed to form a sidewall oxide layer 211 on the sidewall and bottom of the source trench 210.

[0154] Specifically, after the source trench 210 is formed, the inner wall of the source trench 210 is cleaned and pretreated to remove etching residues and natural oxide layer. Then, a uniform sidewall oxide layer 211 is formed on the sidewall and bottom of the source trench 210 by thermal oxidation process or chemical vapor deposition process.

[0155] In one embodiment, when using a thermal oxidation process, the semiconductor structure is placed in a high-temperature oxidation furnace and thermally oxidized in an oxygen or water vapor atmosphere, causing the exposed silicon surface of the source trench 210 to react with oxygen to form a silicon dioxide (SiO2) layer. The thermal oxidation process can form a high-quality silicon-silicon dioxide interface with a low interface state density, which is beneficial for improving the reliability and stability of the device. In another embodiment, when using a chemical vapor deposition process, a silicon oxide layer can be deposited on the inner wall of the source trench 210 through low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition. This process has good step coverage and is suitable for filling trenches with high aspect ratios. Of course, the formation process of the sidewall oxide layer 211 is not limited to these methods.

[0156] As an example, after the sidewall oxide layer 211 is formed, the sidewall oxide layer 211 at the bottom of the source trench 210 can be selectively thickened to alleviate the electric field concentration effect in the corner region at the bottom of the trench and further improve the breakdown voltage of the device.

[0157] The structural features of the sidewall oxide layer 211 (such as material, thickness design principles, function, etc.) are as described in Example 1, and will not be repeated here.

[0158] Next, refer to Figure 2 and Figure 7 Step S4 is executed to form source polysilicon 212 within the source trench 210.

[0159] Specifically, the source polysilicon 212 is deposited using a chemical vapor deposition process to completely fill the source trench 210. In-situ doping is performed during the deposition process, or doping is performed after deposition via ion implantation, to give the source polysilicon 212 high conductivity.

[0160] As an example, after polysilicon deposition, excess polysilicon on the surface of the epitaxial layer 200 is removed by an etch-back process or a chemical mechanical polishing process, leaving only the source polysilicon 212 within the source trench 210, and making the upper surface of the source polysilicon 212 flush with the upper surface of the epitaxial layer 200. In a preferred embodiment, the aforementioned first hard mask layer 310 adopts a stacked structure of silicon oxide, silicon nitride, and silicon oxide. If the sidewall oxide layer 211 is formed by a thermal oxidation process in step S3, there is no new oxide on the surface of the first hard mask layer 310, and the silicon nitride layer can be directly used as the CMP stop layer. If a CVD deposition process is used in step S3, the surface of the first hard mask layer 310 is covered with CVD oxide. In this case, the CVD oxide must be removed by an etch-back process before silicon nitride can be used as the CMP stop layer to protect the epitaxial layer 200. Then, residual polysilicon is further removed using a back-etching process until the upper surface of the source polysilicon 212 is flush with the upper surface of the epitaxial layer 200; then, the residual first hard mask layer 310 is removed. A planarized surface facilitates the coating of photoresist and control of etching precision in subsequent processes. Of course, in another embodiment, the upper surface of the source polysilicon 212 may be slightly lower than the upper surface of the epitaxial layer 200. In other embodiments, the first hard mask layer 310 may not serve as a CMP stop layer; after polysilicon deposition in this step, the source polysilicon 212 can be directly obtained using CMP or etching processes. The deposition and processing technology of the source polysilicon 212 is not limited here.

[0161] The structural features and working principle of the source polycrystalline silicon 212 are as described in Example 1, and will not be repeated here.

[0162] Next, refer to Figure 2 and Figure 8 In step S5, two parallel and spaced gate trenches 220 are formed between each two adjacent source trenches 210, extending downward from the surface of the epitaxial layer 200; the mesa region of the epitaxial layer 200 between the adjacent sidewall surfaces of the two gate trenches 220 constitutes the first mesa region.

[0163] Specifically, a second hard mask layer 320 with the gate trench 220 pattern is formed on the surface of the epitaxial layer 200 using photolithography. An anisotropic dry etching process is then used to etch vertically downwards from the surface of the epitaxial layer 200 to form two parallel and spaced-apart gate trenches 220. A first mesa region is formed between the two gate trenches 220 for subsequent formation of the Schottky metal layer 240; a second mesa region is formed between the gate trench 220 and the source trench 210 for subsequent formation of the body region 250 and the source region 260.

[0164] The depth of the gate trench 220 is less than the depth of the source trench 210, allowing the source polysilicon 212 to extend below the gate trench 220, thus better utilizing the field plate effect. After etching, the mask layer is removed, and the gate trench 220 is cleaned to remove etching residues and contaminants, preparing for the subsequent formation of the gate oxide layer 221.

[0165] The structural features of the gate trench 220 (such as cross-sectional shape, arrangement, and spacing range) are as described in Embodiment 1, and will not be repeated here.

[0166] Next, refer to Figure 2 and Figure 9 Step S6 is executed to form the gate oxide layer 221, which covers the inner wall of the gate trench 220.

[0167] Specifically, after the gate trench 220 is formed, the inner wall of the gate trench 220 and the surface of the epitaxial layer 200 are cleaned and pretreated to remove etching residues and native oxide layers, and then the gate oxide layer 221 is formed by thermal oxidation or chemical vapor deposition.

[0168] As an example, in the thermal oxidation process, the semiconductor structure is placed in a high-temperature oxidation furnace and thermally oxidized in an oxygen or water vapor atmosphere, causing the exposed silicon surface to react with oxygen to form a silicon dioxide (SiO2) layer. The thermal oxidation process can form a high-quality silicon-silicon dioxide interface with a low interface state density, which is beneficial for improving the channel carrier mobility and the long-term reliability of the device. In another embodiment, a chemical vapor deposition process is used, where a silicon oxide layer can be deposited on the inner wall of the gate trench 220 and the surface of the epitaxial layer 200 through low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition.

[0169] The thickness of the gate oxide layer 221 is determined according to the threshold voltage requirement and gate drive voltage of the device, and those skilled in the art can select it according to actual needs. The gate oxide layer 221 serves as an insulating layer between the gate polysilicon 222 and the epitaxial layer 200, and its quality directly affects the threshold voltage, channel mobility, gate-drain capacitance, and reliability of the device.

[0170] It should be noted that in subsequent processes, the gate oxide layer 221 on the side of the gate trench 220 near the region between the two gate trenches 220 will be removed to form the first trench 230 for filling the high-k dielectric layer 231. The gate oxide layer 221 in other regions of the gate trench 220 (such as the sidewalls and bottom of the trench facing the source trench 210) is retained to ensure insulation between the gate polysilicon 222 and the epitaxial layer 200.

[0171] Next, refer to Figure 2 and Figure 9 Step S7 is executed, in which the gate polysilicon 222 is filled into the gate trench 220.

[0172] Specifically, after forming the gate oxide layer 221, a layer of polysilicon is deposited in the gate trench 220 and on the surface of the epitaxial layer 200 using a low-pressure chemical vapor deposition process, so that the polysilicon completely fills the gate trench 220. In-situ doping is performed during the deposition process, or doping is performed by ion implantation after deposition, so that the gate polysilicon 222 has high conductivity, thereby reducing the gate resistance and improving the switching speed of the device.

[0173] In one embodiment, after polysilicon deposition, a chemical mechanical polishing (CMP) process is first used to globally planarize the polysilicon. Then, a back-etching process is used to further remove residual polysilicon until the upper surface of the gate polysilicon 222 is flush with or slightly lower than the upper surface of the epitaxial layer 200. This two-step removal process can precisely control the height of the gate polysilicon 222, avoiding over-etching or residue. At the same time, the planarized surface is beneficial for the coating of photoresist and the control of etching accuracy in subsequent processes.

[0174] In another embodiment, an etch-back process can be used to remove excess polysilicon, making the upper surface of the gate polysilicon 222 flush with the upper surface of the epitaxial layer 200.

[0175] The structural features of the gate polysilicon 222 (such as doping type, electrical connection relationship, working principle, etc.) are as described in Example 1, and will not be repeated here.

[0176] Next, refer to Figure 2 and Figure 10 Step S8 is executed to remove a portion of the gate oxide layer 221 near both sides of the first mesa region within the gate trench 220 to form a first trench 230; and at the same time, the gate oxide layer 221 located in the first mesa region is removed.

[0177] Specifically, after forming the gate polysilicon 222, a third hard mask layer (unmarked) is formed on the surface of the epitaxial layer 200 using a photolithography process, exposing only one side of the gate trench 220 near the first mesa region and the surface of the epitaxial layer 200 between the two gate trenches 220. Then, a wet etching or dry etching process is used to selectively remove the gate oxide layer 221 in the exposed areas.

[0178] Because the gate oxide layer 221 has a good etching selectivity with the gate polysilicon 222 and the epitaxial layer 200, the etching process can be precisely stopped on the surfaces of the gate polysilicon 222 and the epitaxial layer 200. Within the gate trench 220, the first trench 230 is formed at the location where the gate oxide layer 221 has been removed. The first trench 230 is located on the sidewall of the gate trench 220 and is used for subsequent filling with a high-k dielectric layer 231. Simultaneously, the gate oxide layer 221 on the surface of the epitaxial layer 200 between the two gate trenches 220 is completely removed, exposing the surface of the epitaxial layer 200 for subsequent formation of the Schottky metal layer 240.

[0179] The structural features of the first trench 230 (such as depth, width, and depth ratio to the gate trench 220) are as described in Embodiment 1, and will not be repeated here.

[0180] Next, refer to Figure 2 and Figure 11 Step S9 is executed, in which a high-k dielectric layer 231 is filled into the first trench 230, and the high-k dielectric layer 231 is located on both sides of the first platform area.

[0181] Specifically, after the first trench 230 is formed, a high-k dielectric material is deposited in the first trench 230 and on the surface of the epitaxial layer 200 using processes such as atomic layer deposition, chemical vapor deposition, or physical vapor deposition, so that the high-k dielectric material completely fills the first trench 230. Among them, the atomic layer deposition process can achieve precise control of atomic-level thickness and has good step coverage in high aspect ratio trenches, making it particularly suitable for filling the first trench 230.

[0182] Furthermore, after deposition, excess high-k dielectric material on the surface of the epitaxial layer 200 is removed by an etch-back process or a chemical mechanical polishing process, leaving only the high-k dielectric layer 231 within the first trench 230, and ensuring that the upper surface of the high-k dielectric layer 231 is flush with the upper surface of the epitaxial layer 200. It is understood that in actual processes, the upper surface of the high-k dielectric layer 231 can also be slightly lower or slightly higher than the upper surface of the epitaxial layer 200, both achieving the technical effects of this invention.

[0183] The material and structural characteristics of the high-k dielectric layer 231 are as described in Example 1, and will not be repeated here.

[0184] As an example, see Figure 12 After forming the high-k dielectric layer 231, the system also includes a mesa region forming body region 250 and a source region 260 formed between the gate trench 220 and the source trench 210.

[0185] Specifically, the implantation region of the body region 250 is defined by photolithography, forming a photoresist mask layer that covers the first mesa region between the two gate trenches 220 (i.e., the region where the Schottky metal layer 240 will subsequently be formed), exposing the second mesa region between the gate trench 220 and the source trench 210. Ion implantation is performed, with the implanted ion type opposite to that of the epitaxial layer 200, forming the body region 250 in the second mesa region. Afterward, the photoresist mask layer is removed.

[0186] Next, the implantation region of source region 260 is defined using photolithography. A photoresist mask layer is formed, covering the first mesa region and exposing the upper surface region of body region 250. High-concentration ion implantation is then performed, with the implanted ion type opposite to that of body region 250, forming source region 260. After implantation, high-temperature annealing is performed to activate impurities and repair lattice damage. After annealing, body region 250 extends downward from the surface of epitaxial layer 200 to a first depth, and source region 260 is located on the upper surface of body region 250, with a depth less than that of body region 250.

[0187] It should be noted that the first mesa region is always covered by photoresist throughout the implantation process, and no ion implantation is performed on the body region 250 and the source region 260, in order to maintain the intrinsic or lightly doped characteristics of the epitaxial layer 200 in this region and ensure that the Schottky junction formed subsequently has good rectification characteristics.

[0188] The structural features of the body region 250 and the source region 260 are as described in Embodiment 1, and will not be repeated here.

[0189] Next, refer to Figure 2 and Figure 13 In step S10, a Schottky metal layer 240 is formed on the first mesa region, and the Schottky metal layer 240 forms a Schottky contact with the epitaxial layer 200.

[0190] Specifically, Schottky metal material is deposited on the surface of the epitaxial layer 200 using sputtering or electron beam evaporation processes. Before deposition, the surface of the epitaxial layer 200 is cleaned and pretreated to remove the native oxide layer and contaminants, ensuring the formation of high-quality Schottky contacts. After deposition, the unwanted areas of the Schottky metal layer 240 are removed using photolithography and etching processes, retaining only the first mesa region between the two gate trenches 220.

[0191] In another embodiment, a stripping process can also be used, in which a photoresist mask is first formed by photolithography to expose the first mesa region, then a Schottky metal layer 240 is deposited, and finally the photoresist and excess metal on it are removed by a stripping process.

[0192] During operation, the Schottky junction is integrated in parallel with the MOSFET structure. When the device is reverse-biased, the reverse current preferentially flows through the Schottky junction. Since the Schottky junction is a majority carrier device, there is no minority carrier injection phenomenon, resulting in an extremely short reverse recovery time and effectively reducing reverse recovery losses. Simultaneously, the high-k dielectric layers 231 on both sides of the Schottky junction modulate the electric field, preventing electric field concentration at the junction edge, reducing reverse leakage current, and preventing premature device breakdown.

[0193] The material and structural characteristics of the Schottky metal layer 240 are as described in Example 1, and will not be repeated here.

[0194] As an example, see Figure 14 After forming the Schottky metal layer 240, an interlayer dielectric layer 270 is deposited using a chemical vapor deposition process, covering the epitaxial layer 200, the gate trench 220, the source trench 210, and the upper surface of the Schottky metal layer 240. Then, contact holes 271 are etched to form, exposing at least the body region 250, the source region 260, the source polysilicon 212, the gate polysilicon 222, and the Schottky metal layer 240.

[0195] The structural features of the interlayer dielectric layer 270 and the contact hole 271 are as described in Embodiment 1, and will not be repeated here.

[0196] Next, refer to Figure 2 and Figure 14 Step S11 is executed to form a front metal layer 280, which includes a source metal region and a gate metal region that are isolated from each other; the source metal region covers and electrically connects the source polysilicon 212 and the Schottky metal layer 240, and the gate metal region is electrically connected to the gate polysilicon 222.

[0197] Specifically, in one embodiment, after forming the contact hole 271, a front metal layer 280 is deposited on the surface of the interlayer dielectric layer 270 using processes such as sputtering, evaporation, or chemical vapor deposition. The front metal layer 280 fills the contact hole 271 and achieves electrical connection with the body region 250, the source region 260, the source polysilicon 212, the gate polysilicon 222, and the Schottky metal layer 240.

[0198] As an example, after forming the front metal layer 280, the front metal layer 280 is patterned to form a gate metal region and a source metal region; the source metal region is electrically connected to the body region 250, the source region 260, the source polysilicon 212 and the Schottky metal layer 240 through the contact hole 271, so that the Schottky junction is connected to the source potential; the gate metal region is electrically connected to the gate polysilicon 222 through the contact hole 271 for leading out the gate.

[0199] The structural features and material selection of the front metal layer 280 are as described in Embodiment 1, and will not be repeated here.

[0200] As an example, see Figure 14 After the front metal layer 280 is patterned, the semiconductor substrate 100 is thinned on the back side to form the drain 400.

[0201] Specifically, the back side of the semiconductor substrate 100 is thinned to a target thickness using mechanical grinding or chemical mechanical polishing processes to reduce the on-resistance and thermal resistance of the device. After thinning, the back side is cleaned and pretreated to remove damaged layers and contaminants.

[0202] Then, a drain 400 is deposited on the back side of the thinned semiconductor substrate 100 using a sputtering or evaporation process. The drain 400 is preferably made of a titanium / nickel / silver (Ti / Ni / Ag) stacked structure, a titanium / nickel / gold (Ti / Ni / Au) stacked structure, or other suitable metal systems for soldering to ensure good ohmic contact and solderability. After deposition, alloying annealing is performed to form good ohmic contact.

[0203] This completes the entire fabrication process of the shielded gate trench MOSFET device. The drain 400 is electrically connected to the semiconductor substrate 100, serving as the drain lead-out terminal of the device.

[0204] In summary, this invention discloses a shielded gate trench MOSFET device and its fabrication method, belonging to the field of power semiconductor technology. The device includes: a semiconductor substrate and an epitaxial layer; multiple source trenches filled with source polysilicon; two gate trenches arranged side-by-side and spaced apart between the two source trenches, each filled with gate polysilicon; a first trench formed within the gate trench on one side near the region between the two gate trenches, containing a high-k dielectric layer; a Schottky metal layer formed between the two gate trenches and forming a Schottky contact with the epitaxial layer; and a front metal layer electrically connected to the source polysilicon through the front metal layer. This invention integrates a Schottky junction between the two gate trenches, utilizing the fast recovery property of the Schottky junction to effectively optimize the reverse recovery performance of the device and reduce reverse recovery losses. Simultaneously, the high-k dielectric layers on both sides of the Schottky junction modulate the electric field, optimizing the electric field distribution at the Schottky junction and reducing the risk of device leakage and premature breakdown. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0205] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A shielded gate trench MOSFET device, characterized in that, include: Semiconductor substrate; An epitaxial layer is formed on the surface of the semiconductor substrate; Multiple source trenches extend downward from the surface of the epitaxial layer; Sidewall oxide layer, the sidewall oxide layer being located on the sidewall and bottom of the source trench; Source polycrystalline silicon is filled in the source trench and is in contact with the sidewall oxide layer; Multiple gate trenches are arranged in pairs between two adjacent source trenches, and the source trenches extend downward from the surface of the epitaxial layer, arranged side by side and spaced apart; The mesa region of the epitaxial layer between the adjacent sidewall surfaces of the two gate trenches is the first mesa region; The gate oxide layer is located on the inner wall of the gate trench; A gate polysilicon is filled in the gate trench and is in contact with the gate oxide layer; The first trench is located in the sidewalls of the gate trench near both sides of the first mesa region, and a high-k dielectric layer is provided in the first trench. A Schottky metal layer is formed in the first mesa region and forms a Schottky contact with the epitaxial layer; The front metal layer includes a source metal region and a gate metal region that are isolated from each other; the source metal region covers the source polysilicon and the Schottky metal layer and is electrically connected to them, and the gate metal region is electrically connected to the gate polysilicon.

2. The shielded gate trench MOSFET device according to claim 1, characterized in that, Also includes: The body region 250 is located within the epitaxial layer and between the gate trench and the source trench. The body region 250 extends downward from the surface of the epitaxial layer 200 to a first depth and is adjacent to the gate trench and the source trench. The source region is located on the upper surface of the body region, extends downward from the surface of the epitaxial layer 200 to a second depth, the second depth being less than the first depth; and is adjacent to the gate trench and the source trench, and the source region is electrically connected to the source polysilicon; An interlayer dielectric layer covers the upper surfaces of the epitaxial layer and the Schottky metal layer, and the interlayer dielectric layer has contact holes that expose the body region, the source polysilicon, the gate polysilicon and the Schottky metal layer; The front metal layer is also located on the interlayer dielectric layer. Through the contact hole, the source metal region is electrically connected to the body region, the source region, the source polysilicon, and the Schottky metal layer, and the gate metal region is electrically connected to the gate polysilicon.

3. The shielded gate trench MOSFET device according to claim 2, characterized in that: The epitaxial layer is N-type doped, the body region is P-type doped, and the source region is N-type doped, forming an N-type MOSFET; Alternatively, the epitaxial layer may be P-type doped, the body region may be N-type doped, and the source region may be P-type doped to form a P-type MOSFET.

4. The shielded gate trench MOSFET device according to claim 1, characterized in that: The depth of the first trench is less than or equal to the depth of the gate trench.

5. The shielded gate trench MOSFET device according to claim 4, characterized in that: The ratio of the depth of the first trench to the depth of the gate trench is in the range of 1 / 10 to 4 / 5.

6. The shielded gate trench MOSFET device according to claim 1, characterized in that: The distance between adjacent sidewall surfaces of the gate trench ranges from 0.5 μm to 10 μm.

7. The shielded gate trench MOSFET device according to claim 1, characterized in that: The high-k dielectric layer includes at least one of HfO2, Al2O3, ZrO2, Ta2O5, TiO2, and Si3N4, or a stacked structure of the above materials.

8. The shielded gate trench MOSFET device according to claim 1, characterized in that: The Schottky metal layer includes at least one of titanium, nickel, platinum, molybdenum, chromium, and tungsten, or a stacked structure of the above metals, or a stacked structure of the above metal nitrides, or a stacked structure of the above metals and the above metal nitrides, or a stacked structure of the above metal nitrides and the above metal nitrides.

9. A method for fabricating a shielded gate trench MOSFET device, characterized in that, The preparation method includes the following steps: A semiconductor substrate is provided, and an epitaxial layer is grown on the semiconductor substrate; Multiple source trenches are formed extending downwards from the surface of the epitaxial layer; A sidewall oxide layer is formed on the sidewall and bottom of the source trench; The source trench is filled with source polycrystalline silicon; Between each pair of adjacent source trenches, two parallel and spaced gate trenches are formed extending downward from the surface of the epitaxial layer; the epitaxial layer mesa region between the adjacent sidewall surfaces of the two gate trenches constitutes a first mesa region. A gate oxide layer is formed, the gate oxide layer covering the inner wall of the gate trench; The gate trench is filled with gate polysilicon; A portion of the gate oxide layer near both sides of the first mesa region within the gate trench is removed to form a first trench; and simultaneously, the gate oxide layer located in the first mesa region is removed. A high-k dielectric layer is filled into the first trench, and the high-k dielectric layer is located on both sides of the first mesa area; A Schottky metal layer is formed on the first mesa region, and the Schottky metal layer forms a Schottky contact with the epitaxial layer; A front metal layer is formed, the front metal layer including a source metal region and a gate metal region that are isolated from each other; the source metal region covers and electrically connects the source polysilicon and the Schottky metal layer, and the gate metal region is electrically connected to the gate polysilicon.

10. The method for fabricating a shielded gate trench MOSFET device according to claim 9, characterized in that, Also includes: After forming the high-k dielectric layer, a body region and a source region are formed in the mesa region between the gate trench and the source trench; After the Schottky metal layer is formed, an interlayer dielectric layer is formed to cover the epitaxial layer, the gate trench, the source trench, and the upper surface of the Schottky metal layer. Etching forms contact holes that expose at least the body region, the source region, the source polysilicon, the gate polysilicon, and the Schottky metal layer. After the front metal layer is formed, the front metal layer is patterned to form a gate metal region and a source metal region; the source metal region is electrically connected to the body region, the source region, the source polysilicon and the Schottky metal layer through the contact hole; the gate metal region is electrically connected to the gate polysilicon through the contact hole. The substrate is thinned on the back side to form a drain.

Images