Vertical channel transistors and DRAM structure

Abstract

This invention provides a vertical channel transistor and a DRAM structure. The vertical channel transistor includes at least an oxide semiconductor pillar, a first electrode, a second electrode, a gate layer, and a gate oxide layer. The oxide semiconductor pillar has a first end and a second end. The first electrode is connected to the first end of the oxide semiconductor pillar, and the second electrode is connected to the second end of the oxide semiconductor pillar. The gate layer surrounds the middle portion of the oxide semiconductor pillar, wherein the gate layer is made of a metal-containing barrier material that is difficult to react with oxygen. The gate oxide layer is located between the oxide semiconductor pillar and the gate layer.

Description

Technical Field

[0001] This invention relates to a memory device, and more particularly to a vertical channel transistor and dynamic random access memory (DRAM) structure. Background Technology

[0002] To continue the development path of DRAM below 10 nm, a 4F architecture using vertical channel / pillar transistors (VCT / VPT) is proposed. 2 Unit cell structure replacing 6F 2 Unit cell structure to meet the requirements of high density and low cost.

[0003] To achieve 4F 2 Vertical channel / pillar transistors (VCT / VPT) in DRAM use oxide semiconductor transistors as the channel material because they have extremely low leakage current, large bandgap and high electron mobility.

[0004] However, there are some problems that affect the performance of oxide semiconductor transistors, such as the side effects caused by Vth instability (Vth negative shift), namely, deterioration of gate controllability, poor high turn-off current and low drive current. Summary of the Invention

[0005] This invention relates to a vertical channel transistor and DRAM structure that can avoid Vth instability and obtain high drive current.

[0006] According to an embodiment of the present invention, a vertical channel transistor includes at least an oxide semiconductor pillar having a first end and a second end, a first electrode connected to the first end of the oxide semiconductor pillar, a second electrode connected to the second end of the oxide semiconductor pillar, a gate layer, and a gate oxide layer. The gate layer surrounds the middle portion of the oxide semiconductor pillar, wherein the gate layer is made of a metal-containing barrier material that is difficult to react with oxygen. The gate oxide layer is located between the oxide semiconductor pillar and the gate layer.

[0007] In the vertical channel transistor according to an embodiment of the present invention, the aforementioned oxide semiconductor pillars are vertically disposed above the substrate.

[0008] In a vertical channel transistor according to an embodiment of the present invention, the distance between the first electrode and the gate layer is equal to or different from the distance between the second electrode and the gate layer.

[0009] In the vertical channel transistor according to an embodiment of the present invention, the aforementioned metal barrier material includes titanium nitride or tantalum nitride.

[0010] In the vertical channel transistor according to an embodiment of the present invention, the gate layer has a thickness of less than 20 nm.

[0011] In the vertical channel transistor according to an embodiment of the present invention, the gate layer is a single-layer structure.

[0012] In a vertical channel transistor according to an embodiment of the present invention, the vertical channel transistor further includes an insulating structure, and the oxide semiconductor pillar, the gate oxide layer and the gate layer are located within the insulating structure.

[0013] In the vertical channel transistor according to an embodiment of the present invention, the aforementioned gate oxide layer may also be disposed between the oxide semiconductor pillar and the insulating structure.

[0014] In the vertical channel transistor according to an embodiment of the present invention, the oxygen vacancy concentration in the middle portion of the oxide semiconductor pillar is less than the oxygen vacancy concentration in the remaining portion of the oxide semiconductor pillar.

[0015] According to another embodiment of the present invention, a DRAM structure includes at least the aforementioned vertical channel transistor and a memory device coupled to the vertical channel transistor.

[0016] In a DRAM structure according to another embodiment of the present invention, the above-described storage device includes a capacitor.

[0017] Based on the above, the vertical channel transistor of the present invention, by employing a barrier material as the gate layer, can prevent oxygen from diffusing out from the middle part of the oxide semiconductor, thereby improving the stability of the threshold voltage (Vth). Furthermore, oxygen vacancies exist at both the upper and lower ends of the oxide semiconductor, thus reducing the resistivity of the interface between the oxide semiconductor and the two electrodes. Attached Figure Description

[0018] Figure 1 A plan view of a vertical channel transistor according to some embodiments of the present invention is shown;

[0019] Figure 2 show Figure 1 A cross-sectional view of the vertical channel transistor;

[0020] Figure 3 show Figure 2 A cross-sectional view of the vertical channel transistor after high-temperature (HT) processing;

[0021] Figure 4 A cross-sectional view of a DRAM structure according to some embodiments of the present invention is shown. Detailed Implementation

[0022] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. However, the invention can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, for clarity and explicitness, the dimensions of layers and regions and their relative dimensions may not be shown to exact scale.

[0023] Figure 1 This diagram shows a plan view of a plurality of vertical channel transistors according to some embodiments of the present disclosure. Figure 2 show Figure 1 A cross-sectional view of the vertical channel transistor. For clarity, Figure 1 Some components are not shown, such as Figure 2 The insulating structure 112 and the second electrode 104 are included.

[0024] Please refer to Figure 1 and Figure 2 Each vertical channel transistor 100 includes at least an oxide semiconductor pillar OS having a first terminal e1 and a second terminal e2, a first electrode 102 connected to the first terminal e1 of the oxide semiconductor pillar OS, a second electrode 104 connected to the second terminal e2 of the oxide semiconductor pillar OS, a gate layer 106, and a gate oxide layer 108. In some embodiments, the oxide semiconductor pillar OS is vertically disposed above the substrate 110. In some embodiments, the material of the oxide semiconductor pillar OS can be at least one of indium gallium zinc oxide (IGZO), manganese oxide (MnO2), zinc oxide (ZnO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), etc., and the present invention does not impose any limitations thereon.

[0025] A gate layer 106 surrounds the central portion MP of the oxide semiconductor pillar OS, wherein the central portion MP may be a central part occupying one-third of the height of the oxide semiconductor pillar OS. In some embodiments, the height of the gate layer 106 is less than the height of the central portion MP, but is not limited thereto. The gate layer 106 is made of a metal barrier material that is not easily reactive with oxygen. For example, the aforementioned metal barrier material may include titanium nitride or tantalum nitride. Figure 1The gate layer 106 shown can also serve as a word line of the vertical channel transistor 100. A gate oxide layer 108 is located between the oxide semiconductor pillar OS and the gate layer 106. In some embodiments, the vertical channel transistor 100 also includes an insulating structure 112. The oxide semiconductor pillar OS, gate oxide layer 108, and gate layer 106 described above can be disposed within the insulating structure 112. In some embodiments, the gate oxide layer 108 is also disposed between the oxide semiconductor pillar OS and the insulating structure 112. In some embodiments, the gate layer 106 has a thickness t1 of less than 20 nm; for example, 15 nm or less. "Thickness t1" in this document represents the dimension of the gate layer 106 perpendicular to the extension direction of the oxide semiconductor pillar OS. Studies have shown that when the thickness t1 of titanium nitride is less than a certain value, its conductivity will be the same as, or even higher than, that of a metal of comparable thickness (e.g., tungsten). Therefore, a metal barrier material can indeed serve as the gate of the vertical channel transistor 100. In some embodiments, the gate layer 106 is a single-layer structure, that is, the gate layer 106 does not contain other layers, but only contains one layer of metal barrier material.

[0026] In some embodiments, the distance d2 between the first electrode 102 and the gate layer 106 is different from the distance d1 between the second electrode 104 and the gate layer 106. For example, distance d1 is shorter than distance d2, or distance d1 is greater than distance d2. In some embodiments, the distance d2 between the first electrode 102 and the gate layer 106 is equal to the distance d1 between the second electrode 104 and the gate layer 106.

[0027] In some embodiments, the insulating structure 112 includes a lower insulating layer 112L, an intermediate insulating layer 112M, and an upper insulating layer 112U stacked in sequence. The gate layer 106 may be located in the intermediate insulating layer 112M, which may be made of an oxide or other suitable insulating material.

[0028] In some embodiments, the oxygen vacancy concentration in the middle portion MP of the oxide semiconductor pillar OS is lower than the oxygen vacancy concentration in the remaining portion of the oxide semiconductor pillar OS, such as... Figure 3 As shown. In Figure 3In this process, the vertical channel transistor 100 undergoes a high-temperature (HT) process, such as a hydrogen / chlorine / fluorine-related process, to reduce the resistance at the top of the oxide semiconductor pillar OS, and oxygen out-diffusion occurs at both ends of the oxide semiconductor pillar OS, generating oxygen vacancies OV. Since oxygen vacancies help create space in the lattice, allowing elements to move when an electric field is applied, they help reduce the channel resistance, thus potentially generating a larger drive current. On the other hand, since the gate layer 106 is made of a metal barrier material, oxygen does not diffuse out of the oxide semiconductor pillar OS or diffuses very little from it; therefore, the middle portion MP has no oxygen vacancies or has fewer oxygen vacancies. Therefore, when the gate layer 106 has a shielding function to prevent oxygen vacancies, Vth (threshold voltage) can become stable.

[0029] Figure 4 This shows a cross-sectional view of a DRAM structure according to some embodiments of this disclosure.

[0030] Please see Figure 4 The DRAM structure includes the vertical channel transistor 100 described in the above embodiments and a memory device 200 coupled to the vertical channel transistor 100. In some embodiments, the second electrode 104 of the vertical channel transistor 100 is connected to the memory device 200, and the first electrode 102 of the vertical channel transistor 100 can be connected to a bit line (not shown) or the memory device 200 via an interconnect (not shown). In some embodiments, the memory device 200 includes a capacitor. For example, the DRAM structure employs a 1T1C memory cell, where 1T represents the vertical channel transistor 100 and 1C represents the capacitor (memory device 200). In some embodiments, the capacitor may include two conductive layers (not shown) and a capacitive medium layer located between the two conductive layers, and the capacitive medium layer (not shown) and the two conductive layers may form a cylindrical structure. However, the content disclosed herein is not limited thereto.

[0031] In summary, the gate layer acts as a barrier, preventing oxygen outdiffusion around the gate. Therefore, no oxygen vacancies are generated, and Vth remains stable (without negative shift). On the other hand, oxygen outdiffusion occurs in other areas (such as the top and bottom of the channel), creating oxygen vacancies. This helps reduce channel resistance and is expected to enable a larger drive current.

[0032] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A vertical channel transistor, characterized in that, include: An oxide semiconductor pillar having a first end and a second end; The first electrode is connected to the first end of the oxide semiconductor pillar; The second electrode is connected to the second end of the oxide semiconductor pillar; A gate layer surrounding the middle portion of the oxide semiconductor pillar, wherein the gate layer is made of a metal-containing barrier material that is difficult to react with oxygen; and A gate oxide layer is located between the oxide semiconductor pillar and the gate layer.

2. The vertical channel transistor according to claim 1, characterized in that, The oxide semiconductor pillars are vertically disposed above the substrate.

3. The vertical channel transistor according to claim 1, characterized in that, The distance between the first electrode and the gate layer is equal to the distance between the second electrode and the gate layer.

4. The vertical channel transistor according to claim 1, characterized in that, The distance between the first electrode and the gate layer is different from the distance between the second electrode and the gate layer.

5. The vertical channel transistor according to claim 1, characterized in that, The metal-containing barrier material includes titanium nitride or tantalum nitride.

6. The vertical channel transistor according to claim 1, characterized in that, The gate layer has a thickness of less than 20 nm.

7. The vertical channel transistor according to claim 1, characterized in that, It also includes an insulating structure, and the oxide semiconductor pillar, the gate oxide layer and the gate layer are disposed in the insulating structure.

8. The vertical channel transistor according to claim 7, characterized in that, The gate oxide layer is further disposed between the oxide semiconductor pillar and the insulating structure.

9. The vertical channel transistor according to claim 1, characterized in that, The oxygen vacancy concentration in the middle portion of the oxide semiconductor pillar is less than the oxygen vacancy concentration in the remaining portion of the oxide semiconductor pillar.

10. The vertical channel transistor according to claim 1, characterized in that, The gate layer has a single-layer structure.

11. A DRAM structure, characterized in that, include: The vertical channel transistor according to claim 1; as well as A storage device coupled to the vertical channel transistor.

12. The DRAM structure according to claim 11, characterized in that, The storage device includes a capacitor.

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