Semiconductor devices with field release layers and their integrated manufacturing methods

Abstract

This disclosure describes a semiconductor device having a field release layer and a method for integrating it. For example, a method of manufacturing a semiconductor device (100) includes forming a first field release layer (122) on a first surface (107) of a semiconductor layer (108), wherein the first field release layer (122) is a stepped oxide field release layer formed from a first oxide layer (218), and the first oxide layer (218) is formed via a local oxidation of silicon (LOCOS) process. The method further includes forming a first drain region (144), a first source region (142), and a first gate stack (133, 134), wherein the first drain region (144) is located near a first end of the first field release layer (122), the first source region (142) is located near a second end of the first field release layer (122), and the first gate stack (133, 134) is located between the first drain region (144) and the first source region (142) and partially above the first field release layer (122).

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor devices, and more specifically, but not exclusively, to laterally diffused metal-oxide-semiconductor (LDMOS) transistors. Background Technology

[0002] LDMOS devices are field-effect transistors (FETs) used in high-power applications. In LDMOS devices, compared to MOS devices used in other applications, there is a relatively large gap between the drain and source, and lateral diffusion is used to create a well-controlled channel region below the gate. The operating performance of LDMOS devices is typically affected by parameters including, for example, specific on-resistance (Rsp) and breakdown voltage (BV). One desirable approach for LDMOS devices is to reduce Rsp and increase BV, or at least improve one parameter without significantly adversely affecting the other. Summary of the Invention

[0003] This disclosure describes a semiconductor device having a field-release layer and a method for integrating it. This summary is not an exhaustive overview of the invention. Rather, the purpose of this summary is to present some examples of the invention in a simplified form as a prelude to the more detailed description that follows.

[0004] In one example, a method of manufacturing a semiconductor device includes forming a first field-release layer on a first surface of a semiconductor layer, wherein the first field-release layer is a stepped oxide field-release layer formed from a first oxide layer, and the first oxide layer is formed via a local oxidation of silicon (LOCOS) process. The method further includes forming a first drain region, a first source region, and a first gate stack, wherein the first drain region is adjacent to a first end of the first field-release layer, the first source region is adjacent to a second end of the first field-release layer, and the first gate stack is located between the first drain region and the first source region and partially above the first field-release layer.

[0005] In another example, a method of manufacturing a semiconductor device includes forming a first transistor. The first transistor is formed to include: (i) a first field-release layer on a first surface of a semiconductor layer, wherein the first field-release layer is a stepped oxide field-release layer formed of a first localized silicon oxide (LOCOS) layer; (ii) a first drain region; (iii) a first source region; and (iv) a first gate stack, wherein the first drain region is adjacent to a first end of the first field-release layer, the first source region is adjacent to a second end of the first field-release layer, and the first gate stack is located between the first drain region and the first source region and partially above the first field-release layer. The method further includes forming a second transistor. The second transistor is formed to include: (i) a second field release layer on a second surface of a semiconductor layer, wherein the second field release layer is a second LOCOS field release layer formed via the same LOCOS process as the first LOCOS layer, (ii) a second drain region, (iii) a second source region, and (iv) a second gate stack, wherein the second drain region is adjacent to a first end of the second field release layer, the second source region is adjacent to a second end of the second field release layer, and the second gate stack is located between the second drain region and the second source region and is partially located above the second field release layer.

[0006] In an additional example, the semiconductor device includes a semiconductor layer, a first transistor, and a second transistor. The first transistor is disposed in a first region of the semiconductor layer and includes: a first field-release layer; a first drain region disposed near a first end of the first field-release layer; a first source region disposed near a second end of the first field-release layer; and a first gate stack including a first gate electrode and a first gate dielectric layer. The first gate stack is disposed between the first drain region and the first source region, and is partially disposed above the first field-release layer. The second transistor is disposed in a second region of the semiconductor layer, different from the first region, and the second transistor includes a second gate dielectric layer, wherein the first gate dielectric layer is recessed relative to the second gate dielectric layer. Attached Figure Description

[0007] Figure 1 This is a cross-sectional view of a semiconductor device having a field-release layer according to an example of the present disclosure;

[0008] Figure 2A-2J It is used to form a basis Figure 1 A cross-sectional view of the process flow of a semiconductor device with a field-release layer;

[0009] Figure 3 This is a cross-sectional view of a semiconductor device having a field-release layer according to another embodiment of the present disclosure; and

[0010] Figure 4A-4J It is used to form a basis Figure 3A cross-sectional view of the process flow of a semiconductor device with an asymmetric field release layer, as exemplified by the example. Detailed Implementation

[0011] This disclosure is described with reference to the accompanying drawings. The components in the drawings are not drawn to scale. The focus is on clearly illustrating the general features and principles of this disclosure. Numerous specific details and relationships are illustrated with reference to the examples in the drawings to provide an understanding of this disclosure. The drawings and examples are not intended to limit the scope of this disclosure to such examples, and other examples are possible by interchange or modification of at least some of the described or illustrated elements. Furthermore, where elements of this disclosure are implemented partially or entirely using known components, certain portions of such components that facilitate an understanding of this disclosure are described, and detailed descriptions of other portions of such components are omitted to avoid obscuring this disclosure.

[0012] As used herein, terms such as “first” and “second” are used to arbitrarily distinguish elements described by such terms. Therefore, these terms in the embodiments and claims are not intended to indicate a temporal or other priority order of such elements. Furthermore, considering the orientations shown in the figures, terms such as “front,” “back,” “top,” “bottom,” “above,” “below,” “vertical,” “horizontal,” “lateral,” “downward,” “upward,” “upper,” and “lower” are used to indicate the relative orientation or position of features in the device. For example, “upper” or “topmost” may refer to a feature positioned closer to the top of the page than other features. The terms thus used are interchangeable where appropriate, allowing examples and illustrations of the techniques described herein to operate, for example, in orientations other than those described or otherwise. In the following discussion and claims, the terms “including,” “includes,” “having,” “has,” “with,” or variations thereof are intended to be inclusive in a manner similar to the term “comprising,” and should therefore be interpreted as meaning, for example, “including but not limited to.” Additionally, in some instances, the terms "approximately" or "roughly" preceding a value mean + / - 10-20% of that value. The terms "substantially" or "substantially equal to" mean a value within ±2.5% of that value. Furthermore, unless otherwise stated, the order of steps in the specification and claims is not intended to limit the order in which steps are performed, and alternative orderings of steps may be appropriately considered.

[0013] The various structures disclosed herein can be formed using semiconductor process technologies. Layers comprising various materials can be formed over a substrate (e.g., a semiconductor wafer) using deposition techniques (e.g., chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, plating), thermal processing techniques (e.g., oxidation, nitriding, epitaxy), and / or other suitable techniques. Similarly, portions of the layers can be selectively removed, for example, using etching techniques (e.g., plasma (or dry) etching, wet etching), chemical mechanical planarization, and / or other suitable techniques, some of which can be used in conjunction with photolithography steps. The conductivity (or resistivity) of the substrate (or regions of the substrate) can be controlled by doping techniques using various chemical substances (which may also be referred to as dopants, dopant atoms, etc.), including but not limited to boron, gallium, indium, arsenic, phosphorus, or antimony. Doping can be performed during the initial formation or growth of the substrate (or epitaxial layer grown on the substrate) by ion implantation or other suitable doping techniques.

[0014] As mentioned, the operating performance of LDMOS devices is typically subject to a trade-off between the specific on-resistance (Rsp) and breakdown voltage (BV) parameters. For example, seeking to achieve the advantage of a higher BV by increasing the device volume inevitably leads to the disadvantage of a higher Rsp. Similarly, seeking to reduce Rsp usually comes at the cost of a reduced BV rating. Therefore, the desired method for effectively managing this trade-off in LDMOS devices offers a technological advantage.

[0015] LDMOS devices and other power devices can utilize field release regions to tune Rsp and BV parameters. These field release regions, typically comprising (at least partially) one or more dielectric materials disposed beneath the gate stack, can take various forms. Examples of field release regions include: (i) shallow trench isolation (STI) layers, which are field release regions formed in trenches beneath the surface of the semiconductor layer of the LDMOS device; (ii) stepped gate (e.g., stepped dielectric, stepped oxide) layers, which are field release regions formed above the surface of the semiconductor layer; and (iii) localized silicon oxide (LOCOS) layers, which are field release regions formed at least partially within the semiconductor layer (e.g., partially above and partially below the surface of the semiconductor layer).

[0016] While each form of field release region offers technical advantages over the absence of one in the device, each form of field release provides relatively different improvements to the device's Rsp and BV parameters compared to the others. For example, while a LOCOS layer improves one or more device parameters by avoiding the relatively abrupt dielectric sidewall transitions inherent in an STI layer, a stepped gate layer's improvement over a LOCOS layer lies in the absence of transitions in the semiconductor layer; for example, the channel formed between the source and drain is a direct path.

[0017] However, while using one form of field release may be technically advantageous for some components on a die, using a different form of field release may be more technically advantageous for others. However, utilizing different forms of field release on the same die can introduce a significant number of additional (often repetitive) process steps, thus increasing workload. For example, using a typical process flow, transistors with different forms of field release regions may require separate mask setups, followed by separate patterning and etching steps—this increases cost and the likelihood of device defects.

[0018] To address the aforementioned and other technical challenges in LDMOS and other power devices, examples of this disclosure describe semiconductor devices with field-release layers and methods for their integrated fabrication. While examples of this disclosure may provide improvements such as those described herein, no particular result is claimed unless expressly stated in the specific claims.

[0019] In one example, a method of manufacturing a semiconductor device includes forming a first field-release layer on a first surface of a semiconductor layer. The first field-release layer is a stepped oxide field-release layer formed from a first oxide layer, and the first oxide layer is formed via a local oxidation of silicon (LOCOS) process. The method further includes forming a first drain region, a first source region, and a first gate stack. The first drain region is located near a first end of the first field-release layer, and the first source region is located near a second end of the first field-release layer. The first gate stack is formed between the first drain region and the first source region and is partially formed above the first field-release layer.

[0020] In some instances, the method includes forming a second field-release layer on a second surface of the semiconductor layer, wherein the second field-release layer is formed simultaneously with the first oxide layer via a LOCOS process. The method further includes forming a second drain region, a second source region, and a second gate stack, the second drain region being adjacent to a first end of the second field-release layer, the second source region being adjacent to a second end of the second field-release layer, and the second gate stack being located between the second drain region and the second source region and partially above the second field-release layer.

[0021] In other examples, due to the LOCOS process, the first surface of the semiconductor layer is recessed relative to the second surface of the semiconductor layer. In yet another example, a first source region, a first drain region, a first gate stack, and a first field release layer are formed in the recessed region, and a second source region, a second drain region, a second gate stack, and a second field release layer are formed outside the recessed region.

[0022] In some instances, for example, as will be discussed in this article Figure 1 and 2A As described in the context of 2J, forming the first field-release layer involves forming a thin oxide layer on the second surface of the semiconductor layer, with a thickness relative to the first oxide layer, the thin oxide layer being situated between a pair of isolation regions. Then, a first portion and a second portion of a nitride layer are formed, the first portion of the nitride layer being formed over the first isolation region in the pair of isolation regions and the first portion of the thin oxide layer, and the second portion of the nitride layer being formed over the second isolation region in the pair of isolation regions and the second portion of the thin oxide layer. An opening is formed between the first portion and the second portion of the nitride layer. The method further includes thermally growing a first oxide layer in the opening, the first oxide layer extending to the first surface of the semiconductor layer, wherein, due to a LOCOS process, the first surface of the semiconductor layer is recessed relative to the second surface of the semiconductor layer.

[0023] In an additional example, forming the first field-release layer further includes etching the first oxide layer substantially to a first surface of the semiconductor layer using a first mask to form a middle portion of the first oxide layer and two end portions of the first oxide layer separated from the middle portion and located on opposite sides of the middle portion, the middle portion being the first field-release layer. The two end portions of the first oxide layer have corresponding beak profiles separated from corresponding isolation regions of the pair of isolation regions.

[0024] In other instances, for example, as will be discussed in this article Figure 3 and 4A As described in the context of 4J, forming the first field-release layer further comprises forming a thin oxide layer on the second surface of the semiconductor layer with a thickness relative to the first oxide layer, the thin oxide layer being located between a pair of isolation regions. Then, a first portion and a second portion of a nitride layer are formed, the first portion of the nitride layer being partially formed over the first isolation region of the pair of isolation regions, and the second portion of the nitride layer being partially formed over the second isolation region of the pair of isolation regions. An opening is formed between the first portion and the second portion of the nitride layer. The method further comprises thermally growing a first oxide layer in the opening, the first oxide layer extending to the first surface of the semiconductor layer, wherein, due to the LOCOS process, the first surface of the semiconductor layer is recessed relative to the second surface of the semiconductor layer.

[0025] In an additional example, forming the first field-release layer further includes etching the first oxide layer substantially to a first surface of the semiconductor layer using a first mask to form a middle portion of the first oxide layer and two end portions of the first oxide layer separated from the middle portion and located on opposite sides of the middle portion, the middle portion being the first field-release layer. Each of the two end portions of the first oxide layer is adjacent to a corresponding isolation region in the pair of isolation regions.

[0026] In another example, a method of manufacturing a semiconductor device includes forming a first transistor, the first transistor comprising: (i) a first field release layer on a first surface of a semiconductor layer, the first field release layer being a stepped oxide field release layer formed of a first localized silicon oxide (LOCOS) layer; (ii) a first drain region; (iii) a first source region; and (iv) a first gate stack, the first drain region being adjacent to a first end of the first field release layer, the first source region being adjacent to a second end of the first field release layer, and the first gate stack being located between the first drain region and the first source region and partially above the first field release layer. The method further includes forming a second transistor comprising: (i) a second field release layer on a second surface of a semiconductor layer, the second field release layer being a second LOCOS field release layer formed via the same LOCOS process as the first LOCOS layer; (ii) a second drain region; (iii) a second source region; and (iv) a second gate stack, the second drain region being adjacent to a first end of the second field release layer, the second source region being adjacent to a second end of the second field release layer, and the second gate stack being located between the second drain region and the second source region and partially above the second field release layer.

[0027] In another example, the semiconductor device includes a semiconductor layer, a first transistor, and a second transistor. The first transistor is disposed in a first region of the semiconductor layer. The first transistor includes a first field-release layer, a first drain region disposed near a first end of the first field-release layer, a first source region disposed near a second end of the first field-release layer, and a first gate stack including a first gate electrode and a first gate dielectric layer, the first gate stack being disposed between the first drain region and the first source region and partially above the first field-release layer. The second transistor is disposed in a second region of the semiconductor layer, different from the first region, and the second transistor includes a second gate dielectric layer, with the first gate dielectric layer recessed relative to the second gate dielectric layer.

[0028] In another example, the second transistor includes: a second field release layer having a first portion partially disposed in a semiconductor layer and a second portion partially disposed above the semiconductor layer; a second drain region disposed near a first end of the second field release layer; a second source region disposed near a second end of the second field release layer; and a second gate stack including a second gate electrode and a second gate dielectric layer, the second gate stack being disposed between the second drain region and the second source region and partially disposed above the second field release layer.

[0029] In other instances, the semiconductor device further includes a pair of isolation regions, the pair of isolation regions including a first isolation region disposed at a first end of a first region and a second isolation region disposed at a second end of the first region.

[0030] In other instances, the first transistor includes a first oxide region separated from the first isolation region and the first end of the first field release layer, and a second oxide region separated from the second isolation region and the second end of the first field release layer.

[0031] In other instances, the first transistor includes a first oxide region adjacent to the first isolation region and separated from the first end of the first field release layer, and a second oxide region adjacent to the second isolation region and separated from the second end of the first field release layer.

[0032] In some instances, the first release layer comprises one or more substantially straight sidewalls, and the second release layer comprises opposing ends with a beak-like profile.

[0033] In some instances, the first field release layer and the second field release layer are formed at least partially simultaneously. In other instances, the first field release layer has a width defined along the direction between the first source region and the first drain region, said width being smaller than the width of the first region. Still in some instances, the first field release layer is a stepped oxide field release layer.

[0034] Now for reference Figure 1 The image illustrates a semiconductor device 100. The semiconductor device 100 is illustrated in an example three-dimensional space having a first direction X, a perpendicular (or orthogonal) second direction Y, and a third direction Z perpendicular (or orthogonal) to both the first direction X and the second direction Y. Structures or features along any two of these directions are orthogonal to each other.

[0035] Although semiconductor device 100 is shown as comprising two LDMOS transistors, such as LDMOS transistor 101 and LDMOS transistor 103, in various other instances, additional transistors (e.g., LDMOS and / or other transistor types) and / or other components, not explicitly shown, may be integrated as part of semiconductor device 100. Furthermore, although Figure 1The LDMOS transistors described herein are described as n-channel LDMOS transistors, but in one or more alternative instances, one or more p-channel LDMOS transistors may be formed when the n-type region is replaced by a p-type region and vice versa. As used herein, regions, layers, structures, etc., considered to belong to the "first conductivity type" may be either p-type or n-type, while regions, layers, structures, etc., considered to belong to the "opposite second conductivity type" may be either p-type or n-type.

[0036] As shown in the figure, the semiconductor device 100 includes a semiconductor substrate 102, a first buried layer 104 disposed on the semiconductor substrate 102, a second buried layer 106 disposed on the first buried layer 104, and a semiconductor layer 108 disposed on the second buried layer 106. In some embodiments, the semiconductor layer 108 can be formed by an epitaxial process and therefore can be referred to as an epitaxial or "epi" layer 108. Figure 1 In one example, semiconductor substrate 102 is a p-type substrate, second buried layer 106 is a p-type buried layer (PBL 106), and semiconductor layer 108 is a p-type semiconductor layer, while first buried layer 104 is an n-type buried layer (NBL 104). In some examples, PBL 106 has a higher dopant concentration than semiconductor layer 108 and can be used to implement the principle of reducing surface electric field (RESURF) to improve the safe operating area (SOA) in semiconductor device 100. Although in Figure 1 The example shows two buried layers, such as NBL 104 and PBL 106, but other instances may contain one of the two buried layers or no buried layer at all.

[0037] Multiple isolation zones 112 are disposed in the semiconductor layer 108. Figure 1 This is a cross-sectional view illustrating that LDMOS transistors 101 and 103 are each disposed between a pair of isolation regions 112, wherein LDMOS transistors 101 and 103 are separated by a shared isolation region 112. In a top view (e.g., a layout view), the isolation region 112 may laterally surround each of LDMOS transistors 101 and 103. In some instances, the isolation region 112 is an STI region, while in other instances, the isolation region 112 is a deep trench (DT) region, both an STI region and a DT region, or some combination thereof. In other instances, various other forms of component (e.g., transistor) isolation may be implemented additionally or alternatively.

[0038] The following text will be Figure 2A-2JAs further described in the context, the corresponding elements (e.g., source region, drain region, gate stack, field release layer, etc.) of LDMOS transistors 101 and 103 are formed in an integrated (e.g., modular) manner. In this context, for example, integration means that the corresponding elements in LDMOS transistors 101 and 103 are formed simultaneously (or substantially simultaneously) using the same process steps. For example, the source regions in LDMOS transistor 101 and LDMOS transistor 103 are formed simultaneously (or substantially simultaneously) using the same mask and implantation steps, the drain regions in LDMOS transistor 101 and LDMOS transistor 103 are formed simultaneously (or substantially simultaneously) using the same mask and implantation steps, and so on. Again, although Figure 1 Only LDMOS transistors 101 and 103 are depicted, but semiconductor device 100 may include one or more additional transistors and / or other components, wherein one or more corresponding elements of one or more transistors and / or other components may be similarly formed together with LDMOS transistors 101 and 103 in an integrated or modular manner.

[0039] As further shown in the figure, the LDMOS transistor 101 includes a first field-release layer 116. The first field-release layer 116 is formed via a localized oxidation of silicon (LOCOS) process, and is therefore also referred to herein as the LOCOS layer 116. This will be explained below. Figure 2A-2J As described in the context of the second field release layer 122 (which takes the form of a stepped dielectric (stepped gate) layer and is also referred to herein as a stepped oxide layer 122) as part of the LDMOS transistor 103 is formed in an integrated manner at least initially via the same LOCOS process used to form the first field release layer 116 (e.g., LOCOS layer 116).

[0040] The LDMOS transistor 101 further includes an n-type drain drift region 128, an n-type source region 138, and an n-type drain region 140 disposed in the drain drift region 128, all disposed in the semiconductor layer 108. A first field release layer 116 is disposed between the source region 138 and the drain region 140, partially disposed above the first surface of the semiconductor layer 108 indicated by the dashed line 105 (also referred to as the first surface 105), and partially disposed below the first surface 105 and in the drain drift region 128.

[0041] In some instances, although Figure 1Not explicitly shown, but the LDMOS transistor 101 may also include a p-type body contact region adjacent to the source region 138, both disposed in a deep p-type well (DPWELL). The DPWELL may be disposed in the semiconductor layer 108. A shallow p-type well (SPWELL) (not explicitly shown) may also be disposed within the DPWELL. In such examples, the DPWELL may partially extend into the PBL 106. In some examples, the SPWELL has a higher dopant density than the semiconductor layer 108. When implementing the SPWELL, the base region doping level of the semiconductor layer 108 is increased to suppress parasitic lateral NPN bipolar transistors formed by the n-type source / p-type body region / n-type drain, which may limit the high-current operation of the LDMOS transistor 101, thereby constraining its SOA.

[0042] The LDMOS transistor 101 further includes a gate stack. The gate stack includes a gate dielectric layer 131 disposed on a portion of a first surface 105 of the semiconductor layer 108. The gate stack further includes a gate electrode 132 disposed over the gate dielectric layer 131 and at least a portion of the first field-release layer 116. Figure 1 As shown, the gate electrode 132 extends along the gate dielectric layer 131 and slopes upward in the Z direction along a first beak portion near the source region 138 of the first field release layer 116, then terminates along the top non-sloping surface of the first field release layer 116 before an edge (e.g., before reaching a second beak portion near the drain region 140 of the first field release layer 116). In some embodiments, the edge of the gate electrode 132 above the top non-sloping surface of the first field release layer 116 may be... Figure 1 The termination position shown is closer to the source region 138 or closer to the drain region 140.

[0043] In some instances, gate electrode 132 comprises polysilicon. In other instances, gate electrode 132 comprises metal or other suitable material. The channel region can be considered as a portion extending beneath gate electrode 132 between source region 138 and drain region 140 across semiconductor layer 108.

[0044] like Figure 1 As further shown, the LDMOS transistor 101 includes a sidewall spacer structure 136 along the lateral side of the gate electrode 132. In one example, the sidewall spacer structure 136 includes an oxide layer and a nitride layer (not explicitly shown). In another example, a sidewall spacer structure containing only nitride (or only oxide) may be implemented.

[0045] The LDMOS transistor 101 also includes metal silicide layers 146 extending over the source region 138, drain region 140, and gate electrode 132, respectively. Additionally, in some embodiments, the LDMOS transistor 101 includes a nitride etch stop layer (not explicitly shown) extending over the metal silicide layer 146 and portions of the sidewall spacer structure 136. The LDMOS transistor 101 may include a single-level or multi-level metallization structure (e.g., shared with the LDMOS transistor 103) having a metal front dielectric (PMD) layer 150 and conductive metal (e.g., tungsten) contacts 152, terminating on the respective metal silicide layers 146 for the source region 138, drain region 140, and gate electrode 132. In some embodiments, the metal silicide layer 146 may be made of cobalt silicide (CoSi). x Material formation.

[0046] Now, referring to LDMOS transistor 103, such as Figure 1 As shown, a second field release layer 122 (e.g., also referred to as a stepped dielectric layer 122, a stepped gate layer 122, or a stepped oxide layer 122) is disposed on the second surface (also referred to as second surface 107) of the semiconductor layer 108, indicated by the dashed line 107. The second surface 107 of the semiconductor layer 108 is recessed relative to the first surface 105 of the semiconductor layer 108 to a depth D1 (in the Z direction). In some instances, the depth D1 is in the range of approximately 20-100 nanometers (nm), for example, approximately 50 nm.

[0047] As described above, and as will be discussed below Figure 2A-2J As further described in the context, the second field release layer 122 is formed at least initially via the same LOCOS process used to form the first field release layer 116 (e.g., LOCOS layer 116)—for example, in an integrated manner. More specifically, as will be described below... Figure 2D and 2E As described, the second field release layer 122, together with the first oxide layer 124 and the second oxide layer 124, which are separated from and located on the opposite side of the second field release layer 122 (and separated from the adjacent isolation region 112), are initially formed as part of a continuous LOCOS layer (before further processing) formed simultaneously with the LOCOS layer of the first field release layer 116. Advantageously, in this way, two different forms of field release regions—e.g., a LOCOS layer (e.g., the first field release layer 116) and a stepped gate layer (e.g., the second field release layer 122)—are formed in different LDMOS transistors in the same semiconductor layer 108 via one or more integration process steps.

[0048] like Figure 1As further shown, the LDMOS transistor 103 also includes an n-type drain drift region 130, an n-type source region 142, and an n-type drain region 144 disposed in the drain drift region 130 in the semiconductor layer 108. The second field release layer 122 is disposed between the source region 142 and the drain region 144, above the second surface 107 of the semiconductor layer 108.

[0049] In some instances, although Figure 1 Not explicitly shown, but the LDMOS transistor 103 may also include a p-type body contact region adjacent to the source region 142, both disposed in a deep p-type well (DPWELL). The DPWELL may be disposed in the semiconductor layer 108. A shallow p-type well (SPWELL) (not explicitly shown) may also be disposed within the DPWELL. In such examples, the DPWELL may partially extend into the PBL 106. In some examples, the SPWELL has a higher dopant density than the semiconductor layer 108. When implementing the SPWELL, the same or similar benefits as described above for the SPWELL in the LDMOS transistor 101 are provided.

[0050] The LDMOS transistor 103 further includes a gate stack. The gate stack includes a gate dielectric layer 133 disposed on a portion of the second surface 107 of the semiconductor layer 108. The gate stack further includes a gate electrode 134 disposed over the gate dielectric layer 133 and at least a portion of the second field release layer 122. Figure 1 As shown, the gate electrode 134 extends along the gate dielectric layer 133 and slopes upward in the Z direction along the first tapered (or otherwise substantially straight) sidewall of the second field release layer 122 near the source region 142, before terminating along the top non-sloping surface of the second field release layer 122 before an edge (e.g., before reaching the second tapered (or otherwise substantially straight) sidewall of the second field release layer 122 near the drain region 144). In some embodiments, the edge of the gate electrode 134 above the top non-sloping surface of the second field release layer 122 may be aligned with... Figure 1 The termination position shown is closer to the source region 142 or closer to the drain region 144.

[0051] In some instances, the gate electrode 134 comprises polysilicon. In other instances, the gate electrode 134 comprises metal or other suitable material. The channel region can be considered as a portion extending beneath the gate electrode 134 between the source region 142 and the drain region 144, across the semiconductor layer 108.

[0052] like Figure 1As further shown, the LDMOS transistor 103 includes a sidewall spacer structure 136 along the lateral side of the gate electrode 134. In one example, the sidewall spacer structure 136 includes an oxide layer and a nitride layer (not explicitly shown). In another example, a sidewall spacer structure containing only nitride (or only oxide) may be implemented.

[0053] The LDMOS transistor 103 also includes metal silicide layers 146 extending over the source region 142, drain region 144, and gate electrode 134, respectively. Additionally, in some embodiments, the LDMOS transistor 103 includes a nitride etch stop layer (not explicitly shown) extending over the metal silicide layer 146 and portions of the sidewall spacer structure 136. The LDMOS transistor 103 may include a single-level or multi-level metallization structure (e.g., shared with the LDMOS transistor 101) having a metal front dielectric (PMD) layer 150 and conductive metal (e.g., tungsten) contacts 152, terminating on the respective metal silicide layers 146 for the source region 142, drain region 144, and gate electrode 134. In some embodiments, the metal silicide layer 146 may be made of cobalt silicide (CoSi). x Material formation.

[0054] Now for reference Figure 2A-2J The diagram shows a cross-sectional view of an integrated process flow for forming a semiconductor device 200 according to an example of the present disclosure, the semiconductor device comprising at least two LDMOS transistors, namely LDMOS transistor 201 and LDMOS transistor 203, each having a field-release layer of different forms. More specifically, for the semiconductor device 200... Figure 2A-2J The process flow can be represented Figure 1 An example of the formation of a semiconductor device 100. Therefore, unless otherwise stated, Figure 2A-2J The reference numerals in the accompanying drawings, numbered starting from 200, correspond to... Figure 1 The reference numerals in the accompanying drawings, numbered starting from 100, refer to the same layers and structures (e.g., Figure 2A-2J The semiconductor substrate 202 in the middle corresponds to Figure 1 In the semiconductor substrate 102, NBL 204 corresponds to NBL 104, etc.

[0055] Figure 2AThe intermediate stages of the formation of semiconductor device 200 are depicted. As shown, semiconductor device 200 includes a p-type semiconductor substrate 202, which can be implemented as a silicon wafer, a silicon-on-sapphire wafer, a silicon carbide wafer, etc. In some examples, a p-type semiconductor layer 208 is epitaxially grown on semiconductor substrate 202. Then, an n-type dopant or impurity (e.g., phosphorus) is implanted into semiconductor layer 208 to form an n-type buried layer (NBL) 204. In other examples, an n-type dopant or impurity (e.g., phosphorus) is introduced into p-type semiconductor substrate 202, and then p-type semiconductor layer 208 is epitaxially grown on semiconductor substrate 202. In other examples, NBL 204 may be omitted.

[0056] Figure 2A The initial portion of the LOCOS process for forming the field release layers, which are part of LDMOS transistors 201 and 203, is further described. For example, as shown, a pad oxide layer 210 (e.g., silicon dioxide) is formed on semiconductor layer 208 using a thermal oxidation process or a deposition process such as chemical vapor deposition (CVD). In some instances, the thickness of the pad oxide layer 210 in the Z direction can be approximately 20 nanometers (nm), and it is referred to as a thin oxide layer.

[0057] like Figure 2A As further shown in the example, a plurality of isolation regions 212 are also formed in the semiconductor layer 208 for electrical isolation between the LDMOS transistor 201 and the LDMOS transistor 203 (and between any other adjacent components not explicitly shown). Although shown as a cross-sectional view Figure 2A Multiple isolation regions 212 are illustrated, but in a top view (e.g., a layout view), the isolation regions 212 may laterally surround each of the LDMOS transistors 201 and 203. As defined by the spacing of the isolation regions 212, the width of the region (in the X direction) in which the LDMOS transistor 201 will be formed may be relatively smaller than the width (in the X direction) of the region (in the X direction) in which the LDMOS transistor 203 will be formed.

[0058] Next, Figure 2BThe result of the next intermediate formation stage is depicted, in which a silicon nitride layer 214 is first deposited across the pad oxide layer 210. The deposited silicon nitride layer 214 may have a thickness of approximately 90 nm in the Z direction. The silicon nitride layer 214 is then etched (e.g., dry etching) using a mask layer (not explicitly shown) to form a field release opening 215 for the LDMOS transistor 201 and a field release opening 217 for the LDMOS transistor 203. For each of the field release openings 215 and 217, a portion of the silicon nitride layer 214 resides on each side of the respective opening and extends over the top surface of the adjacent isolation region 212 and the adjacent portion of the corresponding pad oxide layer 210. The pad oxide layer 210 in the field release openings 215 and 217 may be removed during nitride etching, thereby exposing a portion of the silicon of the semiconductor layer 208 beneath the pad oxide layer 210. In some instances, at least a portion of the pad oxide layer 210 may be retained in the field release openings 215 and 217 to protect the silicon surface during subsequent process steps. Although depending on the transistor type of the LDMOS transistors 201 and 203, in some instances, the field release opening 215 may have a width of approximately 100-300 nm (e.g., approximately 200 nm) in the X direction, and the field release opening 217 may have a width of approximately 500-2000 nm (e.g., approximately 1000 nm) in the X direction.

[0059] like Figure 2C As shown, a thermal oxidation process (e.g., a LOCOS process) is applied in the next intermediate stage of the formation of the semiconductor device 200. The thermal oxidation process is furnace oxidation at a relatively high temperature (e.g., approximately 700 to approximately 1200 degrees Celsius), causing oxidation of the silicon regions of the semiconductor layer 208 not covered by the silicon nitride layer 214 in the field release openings 215 and 217, and forming relatively thick silicon dioxide layers, such as LOCOS layer 216 and LOCOS layer 218, respectively, in the field release openings 215 and 217. As shown, each LOCOS layer is partially formed on the first surface 205 of the semiconductor layer 208 (e.g., Figure 1 The semiconductor layer 108 is formed above and partially below the first surface 105. As an example, the LOCOS thickness (in the Z direction) can be approximately 100 nm, although this thickness may depend on the widths of the field release openings 215 and 217 and the furnace oxidation operating parameters. In some instances, the LOCOS layer 218 can be thicker than the LOCOS layer 216. As is typical of LOCOS processes, portions of the silicon nitride layer 214 on each side of the field release openings 215 and 217 cause each end of the corresponding LOCOS layers 216 and 218 to exhibit a bird's beak profile.

[0060] In some alternative instances, such as Figure 2C As depicted, one or more patterned layers (e.g., patterned photoresist layers) can be used to etch the top portions of one or more of the LOCOS layers 216 and 218 to define new top surfaces, thereby achieving a target thickness (in the Z direction) for the corresponding LOCOS layer. For example only, dashed line 219 represents the etched top surface of LOCOS layer 218, which is formed to achieve a target thickness for LOCOS layer 218 (e.g., assuming an original thickness of approximately 100 nm and a target thickness of approximately 90 nm) – for example, in this case, LOCOS layer 216 is covered by a patterned photoresist layer. LOCOS layer 216 can be etched in a similar manner – for example, in this case, LOCOS layer 218 is covered by a patterned photoresist layer.

[0061] Next, as Figure 2D As shown, a mask layer 220 is deposited on the semiconductor device 200 and then patterned to form openings 221 and 223 above the LOCOS layer 218 of the LDMOS transistor 203. Then, as... Figure 2E As shown, the LOCOS layer 218 is etched using a mask layer 220 (e.g., via a dry etching process, a wet etching process, or some combination thereof) to form openings 225 (corresponding to opening 221 in the mask layer 220) and 227 (corresponding to opening 223 in the mask layer 220). Openings 225 and 227 extend downwards to the second surface 207 of the semiconductor layer 208 (corresponding to...). Figure 1 The second surface 107 of the semiconductor layer 108 is then removed. The mask layer 220 is then removed. Thus, the continuous LOCOS layer 218 is divided into an intermediate oxide portion 222 and two terminal oxide portions 224. The intermediate oxide portion 222 includes generally straight or tapered sidewalls 229 as shown, and represents a stepped dielectric (e.g., stepped gate, stepped oxide) layer—for example, corresponding to… Figure 1 The second release layer 122 is the second release layer 222. In some instances, the intermediate oxide portion 222 includes concave sidewalls—for example, in this case, an isotropic wet etching process is used to separate the continuous LOCOS layer 218. As shown, the two end oxide portions 224 (containing the beak outline of the original LOCOS layer) are also separated from the adjacent isolation region 212.

[0062] exist Figure 2FIn the process of removing a portion of the silicon nitride layer 214, a thin oxide layer 226 (e.g., approximately 5-10 nm) is formed on the second surface 207 of the semiconductor layer 208 in each of the openings 225 and 227 between the intermediate oxide portion 222 and the terminal oxide portion 224 of the original LOCOS layer 218. The thin oxide layer 226 protects the underlying silicon of the semiconductor layer 208 during nitride stripping (removal of a portion of the silicon nitride layer 214).

[0063] In the next intermediate stage, such as Figure 2G As shown, an n-type drain drift region 228 is formed in semiconductor layer 208 below the first field release layer 216, and an n-type drain drift region 230 is formed in semiconductor layer 208 below the second field release layer 222. In some instances, drain drift regions 228 and 230 can be formed simultaneously (or at least simultaneously or partially simultaneously) (e.g., in an integrated manner) by implanting phosphorus or other n-type dopants or impurities. In one instance, the implantation process may include four implantations: a shallow implantation of phosphorus dopant at a low-energy implantation energy of approximately 30 to 70 keV, a shallow implantation of arsenic at the same low-energy implantation energy, followed by a medium-energy implantation of phosphorus or arsenic at approximately 100 to 200 keV, and a high-energy implantation of phosphorus or arsenic at approximately 300 to 500 keV, wherein the implantation dose and energy may vary depending on the desired voltage rating of the particular device.

[0064] Advantageously, in this example, the formation of the drain drift region 230 occurs after the formation of the second field release layer 222. Otherwise, when the second field release layer 222 is formed, an additional (drain drift) mask layer may be required to prevent adverse effects on the doping concentration of the drain drift region 230. Alternatively, the formation of the second field release layer 222 after the drain drift region 230 may have an adverse effect on the BV rating of the LDMOS transistor 203.

[0065] Figure 2G The formation of the p-type buried layer (PBL) 206 is also described. For example, the PBL 206 can be formed by implanting boron or other p-type dopants into the p-type semiconductor layer 208 above the NBL 204. In one example, the implantation process is carried out at an energy of approximately 400 keV to 3 MeV at a rate of approximately 1 × 10⁻⁶. 12 cm -2 Up to 1×10 13 cm -2The dosage of boron implantation is used. In another example, the implantation process can implant indium or other p-type dopants. In some embodiments for low-voltage transistors, the implantation process is blanket implantation without using an implantation mask. In another embodiment for high-voltage transistors, an implantation mask can be used for selective implantation of PBL 206. In one example, the implantation process can be followed by one or more thermal processes to allow the implanted p-type dopant to extend or diffuse below the drain drift regions 228 and 230 and to activate the implanted p-type dopant. In other examples, the formation of PBL 206 can be omitted.

[0066] In the next intermediate stage, such as Figure 2H As shown, the respective gate stacks of LDMOS transistors 201 and 203 are formed in an integrated manner. First, gate dielectric layers 231 and 233 are formed in the respective regions where the gate electrodes 232 and 234 of LDMOS transistors 201 and 203 will be formed. In some instances, where pad oxide (e.g., pad oxide layer 210) or other thin oxide (e.g., thin oxide layer 226) is disposed in the target gate dielectric formation region, this oxide material can be removed before gate dielectric formation, while in other instances, this oxide material can be retained.

[0067] Therefore, in Figure 2H In some examples, a gate dielectric formation process is performed to form a gate dielectric layer 231 on a first surface 205 of semiconductor layer 208 and a gate dielectric layer 233 on a second surface 207 of semiconductor layer 208 in the respective regions where the gate electrodes 232 and 234 of LDMOS transistors 201 and 203 will be formed. In some examples, gate dielectric formation may include thermal oxidation or other suitable processes, such as high-temperature furnace operation or rapid thermal processing (RTP). In one example, for silicon dioxide, the gate dielectric layers 231 and 233 have a thickness of approximately 3-15 nm in the Z direction. Alternatively, a silicon oxynitride gate dielectric layer, thicker than silicon dioxide but with a higher dielectric constant, may be formed. In some examples, gate dielectric layers 231 and 233 may have different thicknesses in the Z direction. In some other examples, chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes may be used to deposit the gate dielectric layers 231 and 233.

[0068] Figure 2HThe formation of gate electrodes 232 and 234 is also described. In some instances, gate electrode formation may involve depositing a polycrystalline silicon (e.g., polysilicon) layer using one or more silane precursors, followed by a plasma etching process to define the shape of gate electrodes 232 and 234, and a wet or dry cleaning process to clean the exposed surfaces. In other instances, metal gate processes or CMOS-based displacement gate processes may also be used to form gate electrodes 232 and 234.

[0069] Next, Figure 2I The diagram illustrates the formation of a sidewall spacer structure 236 along the lateral sides of gate electrodes 232 and 234. In some instances, the sidewall spacer structure 236 may comprise an oxide layer and a nitride layer. In one instance, an oxide layer and a nitride layer (not explicitly shown) are deposited over the entire wafer surface, followed by a blanket-type anisotropic plasma etching process that removes portions of the oxide layer and the nitride layer to form the sidewall spacer structure 236. In another instance, a nitride-only (or oxide-only) sidewall spacer structure may be implemented.

[0070] Figure 2I Further illustration shows the formation of source regions 238 and 242 and drain regions 240 and 244 (for LDMOS transistors 201 and 203, respectively) in a semiconductor layer 208 having n-type dopant. More specifically, in some instances, an integrated implantation process is performed using relatively shallow source / drain implants that do not penetrate the gate stack and / or field release layer. Furthermore, in one instance, the average dopant density contained in each drain region is at least 100 times the average dopant density implanted into each drain drift region. In some instances, due to the use of angled implantation and / or additional implantation prior to the formation of the sidewall spacer structure 236, or otherwise due to diffusion, each source region may extend from beneath the gate stack (not explicitly shown). Additionally, in some instances, each drain region may extend from beneath the field release layer.

[0071] Next, Figure 2JThe formation of metal silicide layers 246 extending over source regions 238 and 242, drain regions 240 and 244, and gate electrodes 232 and 234 is described. In some instances, the metal silicide process includes, for example, using a blanket deposition process to deposit a metal layer (e.g., cobalt, not explicitly shown). In some instances, a silicide barrier layer may be formed prior to depositing the metal layer to define the area exposed to the blanket deposition process. The semiconductor device 200 is then heated to form the metal silicide layer 246 (e.g., a cobalt silicide layer) over the desired area, and unreacted metal is subsequently removed in a wet lift-off process.

[0072] Figure 2J The formation of a metal front dielectric (PMD) layer 250 and a conductive metal (e.g., tungsten) contact 252 for source regions 238 and 242, drain regions 240 and 244, and gate electrodes 232 and 234 is also shown.

[0073] exist Figure 2A-2J After the process flow, the finished wafer can then be separated (e.g., die separation) to separate individual semiconductor dies from the starting wafer, and the dies can then be packaged to form integrated circuits or other packaged semiconductor devices.

[0074] Now for reference Figure 3 The image illustrates a semiconductor device 300. The semiconductor device 300 is illustrated in an example three-dimensional space having a first direction X, a perpendicular (or orthogonal) second direction Y, and a third direction Z perpendicular (or orthogonal) to both the first direction X and the second direction Y. Structures or features along any two of these directions are orthogonal to each other.

[0075] Although semiconductor device 300 is shown as comprising two LDMOS transistors, such as LDMOS transistor 301 and LDMOS transistor 303, in various other instances, additional transistors (e.g., LDMOS and / or other transistor types) and / or other components, not explicitly shown, may be integrated as part of semiconductor device 300. Furthermore, although Figure 3 The LDMOS transistors described herein are described as n-channel LDMOS transistors, but in one or more alternative instances, one or more p-channel LDMOS transistors may be formed when the n-type region is replaced by a p-type region and vice versa. As used herein, regions, layers, structures, etc., considered to belong to the "first conductivity type" may be either p-type or n-type, while regions, layers, structures, etc., considered to belong to the "opposite second conductivity type" may be either p-type or n-type.

[0076] As shown in the figure, the semiconductor device 300 includes a semiconductor substrate 302, a first buried layer 304 disposed on the semiconductor substrate 302, a second buried layer 306 disposed on the first buried layer 304, and a semiconductor layer 308 disposed on the second buried layer 306. In some embodiments, the semiconductor layer 308 can be formed by an epitaxial process and therefore can be referred to as an epitaxial or "epi" layer 308. Figure 3 In one example, semiconductor substrate 302 is a p-type substrate, second buried layer 306 is a p-type buried layer (PBL 306), and semiconductor layer 308 is a p-type semiconductor layer, while first buried layer 304 is an n-type buried layer (NBL 304). In some examples, PBL 306 has a higher dopant concentration than semiconductor layer 308 and can be used to implement the principle of reducing surface electric field (RESURF) to improve the safe operating area (SOA) in semiconductor device 300. Although in Figure 3 The example shows two buried layers, such as NBL 304 and PBL 306, but other instances may contain one of the two buried layers or no buried layer at all.

[0077] Multiple isolation zones 312 are disposed in the semiconductor layer 308. Figure 3 This is a cross-sectional view illustrating that LDMOS transistors 301 and 303 are each disposed between a pair of isolation regions 312, wherein LDMOS transistors 301 and 303 are separated by a shared isolation region 312. In a top view (e.g., a layout view), the isolation region 312 may laterally surround each of LDMOS transistors 301 and 303. In some instances, the isolation region 312 is an STI region, while in other instances, the isolation region 312 is a deep trench (DT) region, both an STI region and a DT region, or some combination thereof. In other instances, various other forms of component (e.g., transistor) isolation may be implemented additionally or alternatively.

[0078] The following text will be Figure 4A-4J As further described in the context, the corresponding elements (e.g., source region, drain region, gate stack, field release layer, etc.) of LDMOS transistors 301 and 303 are formed in an integrated (e.g., modular) manner. In this context, for example, integration means that the corresponding elements in LDMOS transistors 301 and 303 are formed simultaneously (or substantially simultaneously) using the same process steps. For example, the source regions in LDMOS transistor 301 and LDMOS transistor 303 are formed simultaneously (or substantially simultaneously) using the same mask and implantation steps, the drain regions in LDMOS transistor 301 and LDMOS transistor 303 are formed simultaneously (or substantially simultaneously) using the same mask and implantation steps, and so on. Again, although Figure 3Only LDMOS transistors 301 and 303 are depicted, but semiconductor device 300 may include one or more additional transistors and / or other components, wherein one or more corresponding elements of one or more transistors and / or other components may be similarly formed together with LDMOS transistors 301 and 303 in an integrated or modular manner.

[0079] As further shown in the figure, the LDMOS transistor 301 includes a first field-release layer 316. The first field-release layer 316 is formed via a localized oxidation of silicon (LOCOS) process, and is therefore also referred to herein as the LOCOS layer 316. This will be discussed below. Figure 4A-4J As described in the context of the second field release layer 322 (which takes the form of a stepped dielectric (stepped gate) layer and is also referred to herein as a stepped oxide layer 322) as part of the LDMOS transistor 303 is formed in an integrated manner at least initially via the same LOCOS process used to form the first field release layer 316 (e.g., LOCOS layer 316).

[0080] The LDMOS transistor 301 further includes an n-type drain drift region 328, an n-type source region 338, and an n-type drain region 340 disposed in the drain drift region 328, all disposed in the semiconductor layer 308. A first field release layer 316 is disposed between the source region 338 and the drain region 340, partially disposed above the first surface of the semiconductor layer 308 indicated by the dashed line 305 (also referred to as the first surface 305), and partially disposed below the first surface 305 and in the drain drift region 328.

[0081] In some instances, although Figure 3 Not explicitly shown, but the LDMOS transistor 301 may also include a p-type body contact region adjacent to the source region 338, both disposed within a deep p-type well (DPWELL). The DPWELL may be disposed within the semiconductor layer 308. A shallow p-type well (SPWELL) (not explicitly shown) may also be disposed within the DPWELL. In such examples, the DPWELL may partially extend into the PBL 306. In some examples, the SPWELL has a higher dopant density than the semiconductor layer 308. When implementing the SPWELL, the base doping level of the semiconductor layer 308 is increased to suppress parasitic lateral NPN bipolar transistors formed by the n-type source / p-type body region / n-type drain, which may limit the high-current operation of the LDMOS transistor 301, thus constraining its SOA.

[0082] The LDMOS transistor 301 further includes a gate stack. The gate stack includes a gate dielectric layer 331 disposed on a portion of a first surface 305 of the semiconductor layer 308. The gate stack further includes a gate electrode 332 disposed over the gate dielectric layer 331 and at least a portion of the first field release layer 316. Figure 3 As shown, the gate electrode 332 extends along the gate dielectric layer 331 and slopes upward in the Z direction along a first beak portion near the source region 338 of the first field release layer 316, then terminates along the top non-sloping surface of the first field release layer 316 before an edge (e.g., before reaching a second beak portion near the drain region 340 of the first field release layer 316). In some embodiments, the edge of the gate electrode 332 above the top non-sloping surface of the first field release layer 316 may be... Figure 3 The termination position shown is closer to the source region 338 or closer to the drain region 340.

[0083] In some instances, the gate electrode 332 comprises polysilicon. In other instances, the gate electrode 332 comprises metal or other suitable material. The channel region can be considered as a portion extending across the semiconductor layer 308 beneath the gate electrode 332 between the source region 338 and the drain region 340.

[0084] like Figure 3 As further shown, the LDMOS transistor 301 includes a sidewall spacer structure 336 along the lateral side of the gate electrode 332. In one example, the sidewall spacer structure 336 includes an oxide layer and a nitride layer (not explicitly shown). In another example, a sidewall spacer structure containing only nitride (or only oxide) may be implemented.

[0085] The LDMOS transistor 301 also includes metal silicide layers 346 extending over the source region 338, drain region 340, and gate electrode 332, respectively. Additionally, in some embodiments, the LDMOS transistor 301 includes a nitride etch stop layer (not explicitly shown) extending over the metal silicide layer 346 and portions of the sidewall spacer structure 336. The LDMOS transistor 301 may include a single-level or multi-level metallization structure (e.g., shared with the LDMOS transistor 303) having a metal front dielectric (PMD) layer 350 and conductive metal (e.g., tungsten) contacts 352, terminating on the respective metal silicide layers 346 for the source region 338, drain region 340, and gate electrode 332. In some embodiments, the metal silicide layer 346 may be made of cobalt silicide (CoSi). x Material formation.

[0086] Now, referring to the LDMOS transistor 303, such as Figure 3As shown, a second field release layer 322 (e.g., also referred to as a stepped dielectric layer 322, a stepped gate layer 322, or a stepped oxide layer 322) is disposed on the second surface (also referred to as second surface 307) of the semiconductor layer 308, indicated by the dashed line 307. The second surface 307 of the semiconductor layer 308 is recessed relative to the first surface 305 of the semiconductor layer 308 to a depth D2 (in the Z direction). In some instances, the depth D2 is in the range of approximately 20-100 nanometers (nm), for example, approximately 50 nm.

[0087] As described above, and as will be discussed below Figure 4A-4J As further described in the context, the second field release layer 322 is formed at least initially via the same LOCOS process used to form the first field release layer 316 (e.g., LOCOS layer 316)—for example, in an integrated manner. More specifically, as will be described below... Figure 4D and 4E As described, the second field release layer 322, together with the first oxide layer 324 and the second oxide layer 324, which are separated from and located on the opposite side of the second field release layer 322 (and adjacent to the adjacent isolation region 312), are initially formed as part of a continuous LOCOS layer (before further processing) formed simultaneously with the LOCOS layer of the first field release layer 316. Advantageously, in this way, two different forms of field release regions—e.g., a LOCOS layer (e.g., the first field release layer 316) and a stepped gate layer (e.g., the second field release layer 322)—are formed in different LDMOS transistors in the same semiconductor layer 308 via one or more integration process steps.

[0088] like Figure 3 As further shown, the LDMOS transistor 303 also includes an n-type drain drift region 330, an n-type source region 342, and an n-type drain region 344 disposed in the semiconductor layer 308. A second field release layer 322 is disposed between the source region 342 and the drain region 344, above the second surface 307 of the semiconductor layer 308.

[0089] In some instances, although Figure 3Not explicitly shown, but the LDMOS transistor 303 may also include a p-type body contact region adjacent to the source region 342, both disposed in a deep p-type well (DPWELL). The DPWELL may be disposed in the semiconductor layer 308. A shallow p-type well (SPWELL) (not explicitly shown) may also be disposed within the DPWELL. In such examples, the DPWELL may partially extend into the PBL 306. In some examples, the SPWELL has a higher dopant density than the semiconductor layer 308. When implementing the SPWELL, the same or similar benefits as described above for the SPWELL in the LDMOS transistor 301 are provided.

[0090] The LDMOS transistor 303 further includes a gate stack. The gate stack includes a gate dielectric layer 333 disposed on a portion of the second surface 307 of the semiconductor layer 308. The gate stack further includes a gate electrode 334 disposed over the gate dielectric layer 333 and at least a portion of the second field release layer 322. Figure 3 As shown, the gate electrode 334 extends along the gate dielectric layer 333 and slopes upward in the Z direction along the first tapered (or otherwise substantially straight) sidewall of the second field release layer 322 near the source region 342, before terminating along the top non-tapered surface of the second field release layer 322 before an edge (e.g., before reaching the second tapered (or otherwise substantially straight) sidewall of the second field release layer 322 near the drain region 344). In some embodiments, the edge of the gate electrode 334 above the top non-tapered surface of the second field release layer 322 may be aligned with... Figure 3 The termination position shown is closer to the source region 342 or closer to the drain region 344.

[0091] In some instances, the gate electrode 334 comprises polysilicon. In other instances, the gate electrode 334 comprises metal or other suitable material. The channel region can be considered as a portion extending across the semiconductor layer 308 beneath the gate electrode 334 between the source region 342 and the drain region 344.

[0092] like Figure 3 As further shown, the LDMOS transistor 303 includes a sidewall spacer structure 336 along the lateral side of the gate electrode 334. In one example, the sidewall spacer structure 336 includes an oxide layer and a nitride layer (not explicitly shown). In another example, a sidewall spacer structure containing only nitride (or only oxide) may be implemented.

[0093] The LDMOS transistor 303 also includes metal silicide layers 346 extending over the source region 342, drain region 344, and gate electrode 334, respectively. Additionally, in some embodiments, the LDMOS transistor 303 includes a nitride etch stop layer (not explicitly shown) extending over portions of the metal silicide layer 346 and the sidewall spacer structure 336. The LDMOS transistor 303 may include a single-level or multi-level metallization structure (e.g., shared with the LDMOS transistor 301) having a metal front dielectric (PMD) layer 350 and conductive metal (e.g., tungsten) contacts 352, terminating on the respective metal silicide layers 346 for the source region 342, drain region 344, and gate electrode 334. In some embodiments, the metal silicide layer 346 may be made of cobalt silicide (CoSi). x Material formation.

[0094] Now for reference Figure 4A-4J The diagram shows a cross-sectional view of an integrated process flow for forming a semiconductor device 400 according to an example of the present disclosure, the semiconductor device comprising at least two LDMOS transistors, namely LDMOS transistor 401 and LDMOS transistor 403, each having a field-release layer of different forms. More specifically, for the semiconductor device 400... Figure 4A-4J The process flow can be represented Figure 3 An example of the formation of a semiconductor device 300. Therefore, unless otherwise stated, Figure 4A-4J The reference numerals in the accompanying drawings, numbered starting from 400, correspond to... Figure 3 The reference numerals in the accompanying drawings, numbered starting from 300, refer to the same layers and structures (e.g., Figure 4A-4J The semiconductor substrate 402 in the middle corresponds to Figure 3 In the semiconductor substrate 302, NBL 404 corresponds to NBL 304, etc.

[0095] Figure 4A The intermediate stages of the formation of the semiconductor device 400 are depicted. As shown, the semiconductor device 400 includes a p-type semiconductor substrate 402, which can be implemented as a silicon wafer, a silicon-on-sapphire wafer, a silicon carbide wafer, etc. In some examples, a p-type semiconductor layer 408 is epitaxially grown on the semiconductor substrate 402. Then, an n-type dopant or impurity (e.g., phosphorus) is implanted into the semiconductor layer 408 to form an n-type buried layer (NBL) 404. In other examples, an n-type dopant or impurity (e.g., phosphorus) is introduced into the p-type semiconductor substrate 402, and then the p-type semiconductor layer 408 is epitaxially grown on the semiconductor substrate 402. In other examples, the NBL 404 may be omitted.

[0096] Figure 4AThe initial portion of the LOCOS process for forming the field release layers, which are part of LDMOS transistors 401 and 403, is further described. For example, as shown, a pad oxide layer 410 (e.g., silicon dioxide) is formed on semiconductor layer 408 using a thermal oxidation process or a deposition process such as chemical vapor deposition (CVD). In some instances, the thickness of the pad oxide layer 410 in the Z direction can be approximately 20 nanometers (nm), and it is referred to as a thin oxide layer.

[0097] like Figure 4A As further shown in the example, a plurality of isolation regions 412 are also formed in the semiconductor layer 408 for electrical isolation between LDMOS transistors 401 and 403 (and between any other adjacent components not explicitly shown). Although shown as a cross-sectional view Figure 4A Multiple isolation regions 412 are illustrated, but in a top view (e.g., a layout view), the isolation regions 412 may laterally surround each of the LDMOS transistors 401 and 403. As defined by the spacing of the isolation regions 412, the width of the region (in the X direction) in which the LDMOS transistor 401 will be formed may be relatively smaller than the width (in the X direction) of the region (in the X direction) in which the LDMOS transistor 403 will be formed.

[0098] Next, Figure 4B The result of the next intermediate formation stage is depicted, in which a silicon nitride layer 414 is first deposited across the pad oxide layer 410. The deposited silicon nitride layer 411 may have a thickness of approximately 90 nm in the Z direction. The silicon nitride layer 414 is then etched (e.g., dry etching) using a mask layer (not explicitly shown) to form a field release opening 415 for the LDMOS transistor 401 and a field release opening 417 for the LDMOS transistor 403. For each of the field release openings 415 and 417, a portion of the silicon nitride layer 414 resides on each side of the respective opening, as shown. With respect to the field release opening 417, the corresponding portion of the silicon nitride layer 414 extends partially above the top surface of the adjacent isolation region 412, as shown. This corresponds to... Figure 2BThe portion of the silicon nitride layer 214 in the field release opening 217 for semiconductor device 200 differs—resulting in two different profiles for the two end oxide portions 424 described below (compared to the two end oxide portions 224 in FIG. 2). The pad oxide layer 410 in field release openings 415 and 417 can be removed during nitride etching, thereby exposing a portion of the silicon of the semiconductor layer 408 beneath the pad oxide layer 410. In some instances, at least a portion of the pad oxide layer 410 may remain in field release openings 415 and 417 to protect the silicon surface during subsequent process steps. While depending on the transistor type of LDMOS transistors 401 and 403, in some instances, field release opening 415 may have a width of approximately 100-300 nm (e.g., approximately 200 nm) in the X direction, and field release opening 417 may have a width of approximately 500-2000 nm (e.g., approximately 1000 nm) in the X direction.

[0099] like Figure 4C As shown, a thermal oxidation process (e.g., a LOCOS process) is applied in the next intermediate stage of the formation of the semiconductor device 400. The thermal oxidation process is furnace oxidation at a relatively high temperature (e.g., approximately 700 to approximately 1200 degrees Celsius), causing oxidation of the silicon regions of the semiconductor layer 408 not covered by the silicon nitride layer 414 in the field release openings 415 and 417, and forming relatively thick silicon dioxide layers, such as LOCOS layers 416 and 418, respectively, in the field release openings 415 and 417. As shown, each LOCOS layer is partially formed on the first surface 405 of the semiconductor layer 408 (e.g., Figure 3 The LOCOS layer 418 is formed above and partially below the first surface 305 of the semiconductor layer 308. As an example, the LOCOS thickness (in the Z direction) can be approximately 100 nm, although this thickness may depend on the widths of the field release openings 415 and 417 and the furnace oxidation operating parameters. In some instances, the LOCOS layer 418 can be thicker than the LOCOS layer 416. A portion of the silicon nitride layer 414 on each side of the field release opening 415 causes each end of the LOCOS layer 416 to exhibit a bird's beak profile. However, since a portion of the silicon nitride layer 414 is formed on each side of the field release opening 417 (e.g., the portion is only partially formed above the top surface of the adjacent isolation region 412, but does not extend above the pad oxide layer 410), no bird's beak profile is formed at the end of the LOCOS layer 418. Instead, the end profile of the LOCOS layer 418 is substantially straight in the Z direction and adjoins the adjacent isolation region 412, as shown.

[0100] In some alternative instances, such as Figure 4CAs depicted, one or more patterned layers (e.g., patterned photoresist layers) can be used to etch the top portions of one or more of the LOCOS layers 416 and 418 to define new top surfaces, thereby achieving a target thickness (in the Z direction) for the corresponding LOCOS layer. For example only, dashed line 419 represents the etched top surface of LOCOS layer 418, which is formed to achieve a target thickness for LOCOS layer 418 (e.g., assuming an original thickness of approximately 100 nm and a target thickness of approximately 90 nm) – for example, in this case, LOCOS layer 416 is covered by a patterned photoresist layer. LOCOS layer 416 can be etched in a similar manner – for example, in this case, LOCOS layer 418 is covered by a patterned photoresist layer.

[0101] Next, as Figure 4D As shown, a mask layer 420 is deposited on the semiconductor device 400 and then patterned to form openings 421 and 423 above the LOCOS layer 418 of the LDMOS transistor 403. Then, as... Figure 4E As shown, the LOCOS layer 418 is etched using a mask layer 420 (e.g., via a dry etching process, a wet etching process, or some combination thereof) to form openings 425 (corresponding to opening 421 in the mask layer 420) and 427 (corresponding to opening 423 in the mask layer 420). Openings 425 and 427 extend downwards to the second surface 407 of the semiconductor layer 408 (corresponding to...). Figure 3 The second surface 307 of the semiconductor layer 308 is then removed. The mask layer 420 is then removed. Thus, the continuous LOCOS layer 418 is divided into an intermediate oxide portion 422 and two terminal oxide portions 424. The intermediate oxide portion 422 includes generally straight or tapered sidewalls 429 as shown, and represents a stepped dielectric (e.g., stepped gate, stepped oxide) layer—for example, corresponding to… Figure 3 The second release layer 322 is a second release layer 422. In some instances, the intermediate oxide portion 422 includes concave sidewalls—for example, in this case, an isotropic wet etching process is used to segment the continuous LOCOS layer 418. Two end oxide portions 424 are adjacent to adjacent isolation regions 412, as shown. One advantage of the position of the two end oxide portions 422 relative to the adjacent isolation regions 412 is to avoid etching the adjacent isolation regions 412 during the wet etching used to form the opening 427.

[0102] exist Figure 4FIn the process of removing a portion of the silicon nitride layer 414, a thin oxide layer 426 (e.g., approximately 5-10 nm) is formed on the surface of the semiconductor layer 408 in each of the openings 425 and 427 between the intermediate oxide portion 422 and the terminal oxide portion 424 of the original LOCOS layer 418. The thin oxide layer 426 protects the underlying silicon of the semiconductor layer 408 during nitride stripping (removal of a portion of the silicon nitride layer 414).

[0103] In the next intermediate stage, such as Figure 4G As shown, an n-type drain drift region 428 is formed in semiconductor layer 408 below a first field release layer 416, and an n-type drain drift region 430 is formed in semiconductor layer 408 below a second field release layer 422. In some instances, drain drift regions 428 and 430 can be formed simultaneously (or at least simultaneously or partially simultaneously) (e.g., in an integrated manner) by implanting phosphorus or other n-type dopants or impurities. In one instance, the implantation process may include four implantations: a shallow implantation of phosphorus dopant at a low-energy implantation energy of approximately 30 to 70 keV, a shallow implantation of arsenic at the same low-energy implantation energy, followed by a medium-energy implantation of phosphorus or arsenic at approximately 100 to 200 keV, and a high-energy implantation of phosphorus or arsenic at approximately 300 to 500 keV, wherein the implantation dose and energy may vary depending on the desired voltage rating of the particular device.

[0104] Advantageously, in this example, the formation of the drain drift region 430 occurs after the formation of the second field release layer 422. Otherwise, when the second field release layer 422 is formed, an additional (drain drift) mask layer may be required to prevent adverse effects on the doping concentration of the drain drift region 430. Alternatively, the formation of the second field release layer 422 after the drain drift region 430 may have an adverse effect on the BV rating of the LDMOS transistor 403.

[0105] Figure 4G The formation of the p-type buried layer (PBL) 406 is also described. For example, the PBL 406 can be formed by implanting boron or other p-type dopants into the p-type semiconductor layer 408 above the NBL 404. In one example, the implantation process is carried out at an energy of approximately 400 keV to 3 MeV at a rate of approximately 1 × 10⁻⁶. 12 cm -2 Up to 1×10 13 cm -2The dosage of boron implantation is used. In another example, the implantation process can implant indium or other p-type dopants. In some embodiments for low-voltage transistors, the implantation process is blanket implantation without using an implantation mask. In another embodiment for high-voltage transistors, an implantation mask can be used for selective implantation of PBL 406. In one example, the implantation process can be followed by one or more thermal processes to allow the implanted p-type dopant to extend or diffuse below the drain drift regions 428 and 430 and to activate the implanted p-type dopant. In other examples, the formation of PBL 406 can be omitted.

[0106] In the next intermediate stage, such as Figure 4H As shown, the respective gate stacks of LDMOS transistors 401 and 403 are formed in an integrated manner. First, gate dielectric layers 431 and 433 are formed in the respective regions where the gate electrodes 432 and 434 of LDMOS transistors 401 and 403 will be formed. In some instances, pad oxide (e.g., pad oxide layer 410) or other thin oxide (e.g., thin oxide layer 426) is disposed in the target gate dielectric formation region, and this oxide material can be removed before the gate dielectric is formed, while in other instances, this oxide material can be retained.

[0107] Therefore, in Figure 4H In some examples, a gate dielectric formation process is performed to form a gate dielectric layer 431 on a first surface 405 of semiconductor layer 408 and a gate dielectric layer 433 on a second surface 407 of semiconductor layer 408 in the respective regions where the gate electrodes 432 and 434 of LDMOS transistors 401 and 403 will be formed. In some examples, gate dielectric formation may include thermal oxidation or other suitable processes, such as high-temperature furnace operation or rapid thermal processing (RTP). In one example, for silicon dioxide, the gate dielectric layers 431 and 433 have a thickness of approximately 3-15 nm in the Z direction. Alternatively, a silicon oxynitride gate dielectric layer, which is thicker than silicon dioxide but has a higher dielectric constant, can be formed. In some examples, gate dielectric layers 431 and 433 may have different thicknesses in the Z direction. In some other examples, chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes can be used to deposit the gate dielectric layers 431 and 433.

[0108] Figure 4HThe formation of gate electrodes 432 and 434 is also described. In some instances, gate electrode formation may involve depositing a polycrystalline silicon (e.g., polysilicon) layer using one or more silane precursors, followed by a plasma etching process to define the shape of gate electrodes 432 and 434, and a wet or dry cleaning process to clean the exposed surfaces. In other instances, metal gate processes or CMOS-based displacement gate processes may also be used to form gate electrodes 432 and 434.

[0109] Next, Figure 4I The diagram illustrates the formation of a sidewall spacer structure 436 along the lateral sides of gate electrodes 432 and 434. In some embodiments, the sidewall spacer structure 436 may comprise an oxide layer and a nitride layer. In one embodiment, an oxide layer and a nitride layer (not explicitly shown) are deposited over the entire wafer surface, followed by a blanket-type anisotropic plasma etching process that removes portions of the oxide layer and the nitride layer to form the sidewall spacer structure 436. In another embodiment, a nitride-only (or oxide-only) sidewall spacer structure may be implemented.

[0110] Figure 4I Further illustration shows the formation of source regions 438 and 442 and drain regions 440 and 444 (for LDMOS transistors 401 and 403, respectively) in a semiconductor layer 408 with n-type dopant. More specifically, in some instances, an integrated implantation process is performed using relatively shallow source / drain implants that do not penetrate the gate stack and / or field release layer. Furthermore, in one instance, the average dopant density contained in each drain region is at least 100 times the average dopant density of each drain drift region to which the drain region is implanted. In some instances, due to the use of angled implantation and / or additional implantation prior to the formation of the sidewall spacer structure 436, or otherwise due to diffusion, each source region may extend from beneath the gate stack (not explicitly shown). Furthermore, in some instances, each drain region may extend from beneath the field release layer.

[0111] Next, Figure 4JThe formation of metal silicide layers 446 extending over source regions 438 and 442, drain regions 440 and 444, and gate electrodes 432 and 434 is described. In some instances, the metal silicide process includes, for example, using a blanket deposition process to deposit a metal layer (e.g., cobalt, not explicitly shown). In some instances, a silicide barrier layer may be formed prior to depositing the metal layer to define the area exposed to the blanket deposition process. The semiconductor device 400 is then heated to form the metal silicide layer 446 (e.g., a cobalt silicide layer) over the desired area, and unreacted metal is subsequently removed in a wet stripping process.

[0112] Figure 4J The formation of a metal front dielectric (PMD) layer 450 and a conductive metal (e.g., tungsten) contact 452 for source regions 438 and 442, drain regions 440 and 444, and gate electrodes 432 and 434 is also shown.

[0113] exist Figure 4A-4J After the process flow, the finished wafer can then be separated (e.g., die separation) to separate individual semiconductor dies from the starting wafer, and the dies can then be packaged to form integrated circuits or other packaged semiconductor devices.

[0114] Furthermore, while various features or components have been shown to have a specific arrangement or configuration according to the illustrated embodiments, other arrangements and configurations are also possible. Moreover, aspects of the inventive technology described in the context of the exemplary embodiments may be combined or eliminated in other embodiments. Therefore, the breadth and scope of the description are not limited to any of the above embodiments.

Claims

1. A method for manufacturing a semiconductor device, comprising: A first field release layer is formed on the first surface of the semiconductor layer. The first field release layer is a stepped oxide field release layer formed by a first oxide layer. The first oxide layer is formed by a local silicon oxidation (LOCOS) process. as well as A first drain region, a first source region, and a first gate stack are formed. The first drain region is close to a first end of the first field-release layer, the first source region is close to a second end of the first field-release layer, and the first gate stack is located between the first drain region and the first source region and is partially located above the first field-release layer.

2. The method according to claim 1, further comprising: A second field release layer is formed on the second surface of the semiconductor layer, and the second field release layer is formed simultaneously with the first oxide layer via the LOCOS process; as well as A second drain region, a second source region, and a second gate stack are formed. The second drain region is close to the first end of the second field release layer, the second source region is close to the second end of the second field release layer, and the second gate stack is located between the second drain region and the second source region and is partially located above the second field release layer.

3. The method of claim 2, wherein, due to the LOCOS process, the first surface of the semiconductor layer is recessed relative to the second surface of the semiconductor layer.

4. The method of claim 2, wherein the first source region, the first drain region, the first gate stack and the first field release layer are formed in the recessed region, and the second source region, the second drain region, the second gate stack and the second field release layer are formed outside the recessed region.

5. The method of claim 1, wherein forming the first field release layer further comprises: A thin oxide layer with a thickness relative to the first oxide layer is formed on the second surface of the semiconductor layer, the thin oxide layer being located between a pair of isolation regions; A first portion and a second portion of a nitride layer are formed, wherein the first portion of the nitride layer is formed over a first isolation region in a pair of isolation regions and a first portion of the thin oxide layer, and the second portion of the nitride layer is formed over a second isolation region in a pair of isolation regions and a second portion of the thin oxide layer, wherein an opening is formed between the first portion of the nitride layer and the second portion of the nitride layer; as well as The first oxide layer is thermally grown in the opening, the first oxide layer extending to the first surface of the semiconductor layer, wherein the first surface of the semiconductor layer is recessed relative to the second surface of the semiconductor layer due to the LOCOS process.

6. The method of claim 5, wherein forming the first field release layer further comprises: The first oxide layer is etched using a first mask to substantially reach the first surface of the semiconductor layer to form a middle portion of the first oxide layer and two end portions of the first oxide layer separated from the middle portion and located on opposite sides of the middle portion, the middle portion being the first field release layer.

7. The method of claim 6, wherein the two end portions of the first oxide layer have corresponding beak profiles separated from the corresponding isolation regions of the pair of isolation regions.

8. The method of claim 1, wherein forming the first field release layer further comprises: A thin oxide layer with a thickness relative to the first oxide layer is formed on the second surface of the semiconductor layer, the thin oxide layer being located between a pair of isolation regions; A first portion and a second portion of a nitride layer are formed, the first portion of the nitride layer being partially formed above a first isolation region in a pair of isolation regions, and the second portion of the nitride layer being partially formed above a second isolation region in a pair of isolation regions, wherein an opening is formed between the first portion of the nitride layer and the second portion of the nitride layer; as well as The first oxide layer is thermally grown in the opening, the first oxide layer extending to the first surface of the semiconductor layer, wherein the first surface of the semiconductor layer is recessed relative to the second surface of the semiconductor layer due to the LOCOS process.

9. The method of claim 8, wherein forming the first field release layer further comprises: The first oxide layer is etched using a first mask to substantially reach the first surface of the semiconductor layer to form a middle portion of the first oxide layer and two end portions of the first oxide layer separated from the middle portion and located on opposite sides of the middle portion, the middle portion being the first field release layer.

10. The method of claim 9, wherein the two end portions of the first oxide layer are adjacent to a corresponding isolation region in the pair of isolation regions.

11. A method for manufacturing a semiconductor device, comprising: A first transistor is formed, the first transistor comprising: (i) a first field release layer on a first surface of a semiconductor layer, the first field release layer being a stepped oxide field release layer formed by a first silicon local oxidation LOCOS layer; (ii) a first drain region; (iii) a first source region; and (iv) a first gate stack, the first drain region being adjacent to a first end of the first field release layer, the first source region being adjacent to a second end of the first field release layer, and the first gate stack being located between the first drain region and the first source region and partially above the first field release layer; as well as A second transistor is formed, the second transistor comprising: (i) a second field release layer on a second surface of the semiconductor layer, the second field release layer being a second LOCOS field release layer formed via the same LOCOS process as the first LOCOS layer; (ii) a second drain region; (iii) a second source region; and (iv) a second gate stack, the second drain region being adjacent to a first end of the second field release layer; the second source region being adjacent to a second end of the second field release layer; and the second gate stack being located between the second drain region and the second source region and partially above the second field release layer.

12. The method of claim 11, wherein the first surface of the semiconductor layer is recessed relative to the second surface of the semiconductor layer.

13. The method of claim 11, wherein the first source region, the first drain region, the first gate stack and the first field release layer are formed in the recessed region, and the second source region, the second drain region, the second gate stack and the second field release layer are formed outside the recessed region.

14. A semiconductor device comprising: Semiconductor layer; A first transistor, disposed in a first region of the semiconductor layer, the first transistor comprising: First release layer; A first drain region is located near the first end of the first field release layer; A first source region is located near the second end of the first field release layer; as well as A first gate stack comprising a first gate electrode and a first gate dielectric layer, the first gate stack being disposed between the first drain region and the first source region and partially disposed above the first field release layer; as well as A second transistor is disposed in a second region of the semiconductor layer that is different from the first region. The second transistor includes a second gate dielectric layer, and the first gate dielectric layer is recessed relative to the second gate dielectric layer.

15. The semiconductor device of claim 14, wherein the second transistor comprises: The second field release layer has a first portion partially disposed in the semiconductor layer and a second portion partially disposed above the semiconductor layer; A second drain region is located near the first end of the second field release layer; A second source region is located near the second end of the second field release layer; as well as A second gate stack comprising a second gate electrode and a second gate dielectric layer, the second gate stack being disposed between the second drain region and the second source region and partially disposed above the second field release layer.

16. The semiconductor device of claim 14, further comprising: A pair of isolation zones, comprising a first isolation zone disposed at a first end of the first zone and a second isolation zone disposed at a second end of the first zone.

17. The semiconductor device of claim 16, wherein the first transistor comprises: A first oxide region, which is separated from the first isolation region and the first end of the first field release layer; and The second oxide region is separated from the second isolation region and the second end of the first field release layer.

18. The semiconductor device of claim 16, wherein the first transistor comprises: A first oxide region, adjacent to the first isolation region and separated from the first end of the first field release layer; and The second oxide region is adjacent to the second isolation region and is separated from the second end of the first field release layer.

19. The semiconductor device of claim 15, wherein the first field release layer includes one or more substantially straight sidewalls, and the second field release layer includes opposing ends having a beak-like profile.

20. The semiconductor device of claim 15, wherein the first field release layer and the second field release layer are formed at least partially simultaneously.

21. The semiconductor device of claim 14, wherein the first field release layer has a width defined along a direction between the first source region and the first drain region, the width being smaller than the width of the first region.

22. The semiconductor device of claim 14, wherein the first field release layer is a stepped oxide field release layer.

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