SiC LDMOS devices based on PNPN quadruple RESURF structure

Abstract

This invention relates to a SiC LDMOS device based on a P-N-P-N quadruple RESURF structure, belonging to the field of semiconductor device technology. It includes a P+ substrate region, a P- epitaxial layer on the upper surface of the P+ substrate region, and a P-base region, an N-drift region, and an L-type drift region extension layer on the upper surface of the P-epitaxy layer. The P-base region contains a source P+ region and a source P+ region. A source metal is disposed on the upper surface of the source P+ region and the source P+ region. A heavily doped N+ drain is disposed within the L-type drift region extension layer. A drain metal field plate is disposed on the upper surface of the heavily doped N+ drain. A gate oxide and field oxide layer are disposed on the upper surface of the N-drift region. A gate polysilicon ramp field plate is disposed within the gate oxide and field oxide layer. A P-N-P-N quadruple RESURF structure is disposed within the N-drift region.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology and relates to a SiCLDMOS device based on a PNPN quadruple RESURF structure. Background Technology

[0002] Third-generation semiconductor materials, represented by silicon carbide (SiC), have gradually replaced traditional silicon-based materials in recent years due to their outstanding advantages such as wide bandgap, high critical breakdown electric field, high thermal conductivity, and excellent chemical stability. They have become the core choice for high-voltage, high-frequency, high-temperature, and high-power-density power electronic equipment, and have been rapidly promoted and applied in fields such as new energy vehicle electronic control, photovoltaic inverters, industrial power supplies, and aerospace power systems. Laterally diffused metal-oxide-semiconductor transistors (SiC LDMOS) combine good layout integration capabilities, compatibility with planar processes, and excellent switching characteristics, and have been developed into key switching devices in high-voltage power integrated circuits and smart power modules, making them a key research direction in the current field of SiC power devices.

[0003] Traditional SiC LDMOS devices generally suffer from uneven lateral electric field distribution and significant electric field concentration at the gate edge, field plate edge, and drift region surface under reverse bias. This limits their breakdown voltage and makes it difficult to overcome the trade-off between on-resistance and breakdown voltage. Conventional single-RESURF and dual-RESURF technologies achieve depletion control only through simple charge compensation, resulting in low charge balance freedom and limited electric field modulation capabilities. They cannot achieve global smooth optimization of the lateral electric field in the drift region, which easily leads to reliability problems such as excessively high local electric field peaks, premature breakdown, and accelerated hot carrier degradation. These issues make it difficult to meet the urgent need for precise lateral electric field control in next-generation high-voltage, high-reliability, and low-loss SiC power integrated devices. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a SiC LDMOS device based on a PNPN quadruple RESURF structure. This device employs a PNPN four-layer alternating doped structure, achieving precise charge balance and complete depletion of the drift region through multi-layer space charge compensation. This effectively smooths the overall electric field distribution and eliminates local electric field peaks, improving the device's breakdown voltage. Simultaneously, the quadruple RESURF mechanism enhances the freedom of electric field control, reduces the interface electric field strength, and improves the device's breakdown voltage characteristics while optimizing the on-resistance. This comprehensively solves the shortcomings of insufficient electric field control and poor reliability in traditional L-type drift region SiC LDMOS devices.

[0005] To achieve the above objectives, the present invention provides the following technical solution: A SiC LDMOS device based on a PNPN quadruple RESURF structure includes a P+ substrate region, a P- epitaxial layer on the upper surface of the P+ substrate region, a P-base region, an N-drift region, and an L-type drift region extension layer on the upper surface of the P-epitaxy layer; a source P+ region and a source P+ region are provided in the P-base region; a source metal is provided on the upper surface of the source P+ region and the source P+ region; a heavily doped N+ drain is provided in the L-type drift region extension layer; a drain metal field plate is provided on the upper surface of the heavily doped N+ drain; a gate oxide and field oxide layer are provided on the upper surface of the N-drift region; a gate polysilicon ramp field plate is provided in the gate oxide and field oxide layer; and a PNPN quadruple RESURF structure is provided in the N-drift region.

[0006] Furthermore, the PNPN quadruple RESURF structure includes a P-top buried layer, an N-top buried layer, a P-bottom buried layer, and an N-bottom buried layer stacked from top to bottom; the P-top buried layer is in contact with the lower surface of the gate oxide and field oxide layers; and the N-bottom buried layer is in contact with the upper surface of the P-epitaxial layer.

[0007] Furthermore, the lower P-layer and upper P-layer have two electric field peaks at their left and right ends, increasing the electric field peaks on the surface of the N-drift region and modulating the lateral electric field. The lower N-layer and lower N-layer provide a low-resistance conduction path for majority carriers, reducing the specific on-resistance of the device, and participate in the charge balance of the drift region. Together with the RESURF mechanism, they achieve electric field modulation and high breakdown voltage. The doped charges of the upper P-layer, upper N-layer, lower P-layer, and lower N-layer are mutually coupled and matched to form space charge complementarity and charge balance regulation, so that the N-drift region is completely depleted under reverse bias, satisfying the quadruple RESURF charge balance criterion and modulating the lateral and longitudinal electric field distribution of the device.

[0008] Furthermore, the source metal extends with a field plate, and the extended field plate of the source metal covers the upper surface of the field oxide layer.

[0009] Furthermore, the drain metal field plate extends with a field plate, and the extended field plate portion of the drain metal is located above the L-shaped drift region extension layer and the gate oxide and field oxide layers.

[0010] Furthermore, the gate polysilicon ramp field plate is located inside the gate oxide and field oxide layers, with its left end located above the P-base region and its right end located above the N-drift region.

[0011] Furthermore, the gate oxide and field oxide layers are located between the source field plate and the active region, isolating the gate polysilicon ramp field plate and the drain metal field plate.

[0012] The beneficial effects of this invention are as follows: Based on the traditional L-type drift region SiC LDMOS device, this invention adds a PNPN quadruple RESURF structure within the drift region of the device, reducing the peak electric field at the gate end and the peak electric field at the edge of the field plate, achieving a higher breakdown voltage within the same size, homogenizing the surface electric field, and using alternating P-type and N-type layers to form a quadruple charge balance structure, enabling more precise charge control in the drift region. Furthermore, the doping concentration of the L-type drift region structure is optimized, improving the longitudinal electric field distribution of the device and significantly increasing the breakdown voltage.

[0013] This invention significantly reduces the electric field at the SiC-SiO interface in the drift region through a quadruple RESURF structure, improving the high-voltage reliability of the device. The L-shaped extension layer reduces the specific on-resistance while maintaining a high breakdown voltage, improving the trade-off between breakdown voltage and on-resistance. In the vertical direction, the electric field peak, originally located at the drift region-substrate interface, is shifted to the interface between the extension layer and the substrate by the L-shaped extension layer. Compared to traditional SiC LMDOS devices, this invention provides a more uniform surface electric field distribution and a more dispersed vertical electric field, significantly improving the device's breakdown voltage capability.

[0014] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0015] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 This is a schematic diagram of the SiC LDMOS device based on the PNPN quadruple RESURF structure proposed in this invention; Figure 2 This is a diagram illustrating the key parameters of the device of the present invention; Figure 3 A comparison of the breakdown characteristic curves of the device of this invention and the L-type drift region SiC LDMOS device; Figure 4 A comparison of the longitudinal electric fields of the device of this invention and the L-type drift region SiC LDMOS device; Figure 5 A comparison of the lateral electric fields of the device of this invention and the L-type drift region SiC LDMOS device; Figure 6 With gate voltages of 10V, 11V, 12V, and 13V respectively, V DSA comparison of the output characteristic curves of the device of this invention and the conventional SiC LDMOS device during forward conduction, from 0 to 200V. Figure 7 A comparison of the on-resistance of the device of the present invention and the L-type drift region SiC LDMOS device under different gate voltages; Figure 8 In the middle (a) and (b), respectively, the L-type drift region SiC LDMOS (with applied voltage V) DS The device breaks down at 1211V (compared to the device of this invention (applied voltage V)). DS The distribution of the internal electric field with applied voltage in reverse blocking state when the device breaks down at 1491V; Figure 9 (a) and (b) show the collisional ionization rate distributions of the L-type drift region SiC LDMOS device and the device of this invention during breakdown, respectively. Figure reference numerals: 1. Source metal, 2. Gate polysilicon ramp field plate, 3. Drain metal field plate, 4. Field oxide layer, 5. Source P+ region, 6. Source N+ region, 7. P-base region, 8. N-drift region, 9. Drain N+ region, 10. L-type drift region extension layer, 11. P-epitaxial layer, 12. P+ substrate region, 13. P-buried layer on top, 14. N-buried layer on top, 15. P-buried layer on bottom, 16. N-buried layer on bottom. Detailed Implementation

[0016] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0017] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0018] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0019] Example 1: like Figure 1 As shown, this invention provides a SiC LDMOS device based on a PNPN quadruple RESURF structure, characterized in that: the device comprises: The bottommost P+ substrate region 12; The P-epitaxial layer 11 is located on the upper surface of the P+ substrate region 12. The top of the P-epitaxial layer 11 is in contact with the p-base region 7, the N-drift region 8 and the L-type drift region extension layer 10. The upper surface of the P-epitaxial layer 11 contacts the P-base region 7, and the right side of the P-base region contacts the N-drift region 8. P-Epipolar layer 11 contacts N-Drift region 8 on its upper surface; The source P+ region 5 is located inside the upper left of the P-base region 7, serving as the diffusion window of the P-base region 7.

[0020] The source N+ region 6 is in contact with the right side of the source P+5. The upper surfaces of the source P+5 and the source N+6 serve as the source input and are connected to the source metal 1 above. The L-type drift region extension layer 10 is in contact with the upper surface of the P-epitaxial layer 11, and the left side is in contact with the N-drift region 8 with a lower doping concentration. The heavily doped N+ drain 9 is located at the upper right corner of the L-type drift region extension layer 10. The drain N+ region 9 is located inside the L-type drift region extension layer 10 at the upper right, serving as a diffusion window for the N- drift region 8 and the L-type drift region extension layer 10; The source metal 1 is located at the top of the device, covering the upper surfaces of the source P+ region 5 and the source N+ region 6, and the field plate extended by the source metal covers the upper surface of the field oxide layer 4. The gate polysilicon ramp field plate 2 is located inside the gate oxide and field oxide layer 4, with the leftmost end located above the P-base region 7 and the rightmost end located in the N-drift region 8; The gate oxide and field oxide layer 4 is located between the source field plate and the active region, isolating the gate polysilicon ramp field plate 2 and the drain metal field plate 3, and is in contact with the upper surface of the buried layer 13 on P. The drain metal field plate 3 is located on the upper surface of the drain electrode, and the extended field plate portion is located above the L-shaped drift region extension layer 10. The N-under-buried layer 16 is located inside the N-drift region 8, and is in contact with the upper surface of the P-epipolar layer 11 and the lower surface of the P-under-buried layer 15. P-under-buried layer 15 is located inside N-drift region 8, and is in contact with the upper surface of N-under-buried layer 16 and the lower surface of N-under-buried layer 14. The N-upper buried layer 14 is located inside the N-drift region 8, and is in contact with the upper surface of the P-lower buried layer 15 and the lower surface of the P-upper buried layer 13. The P-buried layer 13 is located inside the N-drift region 8, in contact with the upper surface of the N-buried layer 14, and in contact with the area below the gate oxide and field oxide layers 4.

[0021] The N-drift region 8 contains a four-layer structure: an N-buried layer 16, a P-buried layer 15, an N-buried layer 14, and a P-buried layer 13. Two electric field peaks are introduced at the left and right ends of the P-buried layer 15 and the P-buried layer 13, increasing the electric field peaks on the surface of the N-drift region 8 and modulating the transverse electric field. The N-buried layer 16 and the N-buried layer 14 provide a low-resistance conduction path for majority carriers, reducing the device's specific on-resistance; they also participate in the charge balance of the drift region, working in conjunction with the RESURF mechanism to achieve electric field modulation and high breakdown voltage. The P-upper buried layer 13, N-upper buried layer 14, P-lower buried layer 15, and N-lower buried layer 16 are alternately arranged from top to bottom within the N-drift region 8. The doped charges of each layer are coupled and matched to form space charge complementarity and charge balance regulation, so that the N-drift region 8 is completely depleted under reverse bias, satisfying the quadruple RESURF charge balance criterion, effectively modulating the lateral and longitudinal electric field distribution of the device, reducing the peak electric field at the gate edge and field plate edge, suppressing the electric field concentration effect, and improving the breakdown voltage of the device.

[0022] Example 2: In this embodiment, for the device described in Example 1, when a positive voltage is applied to the gate, the upper surface of the P-base region between the source N+ region and the N- drift region will undergo inversion and form an electron conduction channel. When the drain-source voltage VDS > 0V, electrons can flow through this channel sequentially through the N- drift region, the upper and lower N-type buried layers and the drain L-shaped extension region, so that the device can be turned on.

[0023] Figure 2 The key parameters that determine the performance of the device in this invention are marked. Table 1 lists the specific values ​​of each key parameter in Figure 2. The performance parameter simulation analysis of the device in the following text is based on this set of parameters. Additionally, the following explanations are provided for some unmarked structural parameters: the gate field plate length is 2 μm, the gate oxide layer thickness is 0.5 μm, and the drain metal field plate length above the gate oxide layer is 2 μm. The source P+ region below the source metal has a length of 0.5 μm along the X-axis, a junction depth of 0.2 μm, and is doped with P-type boron (B) at a doping concentration of 1.0 × 10⁻⁶. 19 cm -3 The source N+ region to the right of the source P+ region has a length of 1.0 μm along the X-axis and a junction depth of 0.2 μm. It is doped with N-type nitrogen (N) impurity at a concentration of 1.0 × 10⁻⁶. 19 cm -3The junction depth of both the P-base region and the N-drift region is 1.0 μm, with the P-base region doped with P-type boron (B) impurity at a concentration of 1.0 × 10⁻⁶. 17 cm -3 The N-drift region has a length of 8.5 μm along the X-axis, corresponding to a region ranging from X=2.5 μm to X=11 μm. The P-type epitaxial layer below the N-drift region has a width of 10 μm along the Y-axis, ranging from Y=2 μm to Y=12 μm, and is doped with P-type boron (B) at a doping concentration of 3.0 × 10⁻⁶. 15 cm -3 The P+ substrate beneath the P-type epitaxial layer has a width of 1 μm along the Y-axis, ranging from Y=12 μm to Y=13 μm, and is doped with P-type boron (B) impurity at a doping concentration of 1.0 × 10⁻⁶. 19 cm -3 The overall length of the device along the X-axis is 14μm, and the total width along the Y-axis is 13μm.

[0024] Table 1

[0025] The following simulation analysis is performed on the SiC LDMOS device with PNPN quadruple RESURF proposed in this embodiment, and compared with the L-type drift region SiC LDMOS device.

[0026] Figure 3 A comparison of the breakdown characteristic curves of the device of this invention and the L-type drift region SiC LDMOS device shows that, compared with the L-type drift region SiC LDMOS device, the breakdown voltage of the device of this invention is increased to 1491V. The PNPN quadruple alternating doped RESURF structure can achieve precise charge balance compensation across the entire drift region, effectively optimize the lateral surface electric field and longitudinal bulk electric field distribution in the drift region, and suppress the local electric field concentration effect near the gate edge and drain field plate.

[0027] Figure 4Comparing the longitudinal electric field of the device of this invention with that of an L-type drift region SiC LDMOS device, the traditional L-type drift region device has an extremely low near-surface electric field strength, with a large amount of electric field concentrated deep within the drift region, exhibiting significant local peak concentration characteristics, which easily leads to premature avalanche breakdown in the bulk. The device of this invention, by synergistically optimizing the doping concentration of the L-type drift region and combining it with a PNPN quadruple alternating longitudinal charge compensation structure, effectively reconstructs the longitudinal electric field distribution of the device, significantly raising the electric field level in the near-surface region, while greatly suppressing the original concentrated peak of the electric field in the drift region, making the longitudinal electric field distribution more gentle and uniform along the depth direction, and achieving optimization of the electric field from local concentration in the bulk to longitudinal global dispersion.

[0028] Figure 5 Comparing the lateral electric field of the device of this invention with that of an L-type drift region SiC LDMOS device, the conventional L-type drift region device exhibits an uneven lateral electric field distribution, significant electric field distortion at the gate edge and the L-type extended region of the drain, and insufficient depletion in the L-type drift region, leading to local electric field concentration. The PNPN quadruple alternating vertical doping structure of this invention can significantly assist in the depletion of the L-type drift region. By compensating for alternating vertical charges, it improves the problem of incomplete depletion in the L-type region. At the same time, it can effectively suppress surface electric field spikes near the gate edge and drain field plate, optimize the overall lateral electric field distribution, and make the lateral electric field distribution in the entire drift region more uniform and smooth. This alleviates the phenomenon of local surface electric field concentration distortion in the conventional structure. Through the synergistic effect of suppressing strong surface electric fields and achieving full depletion of the L-type drift region, the breakdown voltage performance of the device is improved.

[0029] Figure 6 shows the forward output characteristic curves of the PNPN quadruple RESURF SiC LDMOS device of the present invention under gate voltages of 9V, 10V, 11V, and 12V. The drain current of the device first increases linearly and rapidly with the increase of drain-source voltage, and then tends to be stable and constant after entering the saturation range, showing the typical forward conduction law of SiC LDMOS device. At the same time, the higher the gate bias voltage, the greater the saturation conduction current of the device. The gate voltage has a stable and controllable modulation effect on the channel conduction current. The curves are free from distortion and abnormal fluctuations, indicating that while significantly improving the breakdown voltage performance, the forward conduction gate control characteristics of the device of the present invention remain normal and stable, and the conduction performance has not deteriorated.

[0030] Figure 7 A comparison of the specific on-resistance of the device of the present invention and the L-type drift region SiC LDMOS device under different gate voltages shows that the device of the present invention has a lower specific on-resistance under different gate voltages. The two additional heavily doped N-type layers in the drift region provide two conductive channels, which makes the present invention have a lower specific on-resistance than the L-type drift region SiC LDMOS.

[0031] Figure 8 The device of this invention (applied voltage V) DS =1491V Device breakdown) and L-type drift region SiC LDMOS (applied voltage V DS The diagram shows the distribution of the internal electric field as a function of the applied voltage in the reverse blocking state when the device breaks down at 1211V. Figure 8 (a) shows the internal electric field distribution of a traditional L-type drift region SiC LDMOS in reverse blocking state at a breakdown voltage of 1211V. The electric field of this device is highly concentrated at the edge of the drain L-type drift region and the field plate region on the gate-drain surface, forming an obvious local high field accumulation region. The electric field distribution in the drift region is uneven, and the potential voltage drop is accumulated in a large amount at a local position on the drain side. The electric field cannot be fully extended to the entire drift region. At a lower voltage, the critical breakdown field strength is reached, resulting in premature avalanche breakdown. Figure 8 Image (b) shows the bulk electric field distribution of the PNPN quadruple RESURF structure SiC LDMOS of this invention in reverse blocking state at a breakdown voltage of 1491V. Compared with the traditional structure, the local high-field region on the drain surface of the device of this invention is significantly shrunk, and the electric field distribution in the transverse and longitudinal directions of the drift region is more uniform and smooth. The high electric field is effectively dispersed throughout the entire drift region, and the electric field utilization efficiency is greatly improved. By introducing a PNPN quadruple longitudinal alternating RESURF doped buried layer structure, this invention can achieve precise charge balance compensation in the entire drift region. It can not only help the drain L-type drift region to be completely depleted and suppress the electric field spike distortion on the drain side surface, but also uniformly disperse the locally concentrated high electric field on the drain side to the entire longitudinal region of the drift region, optimizing the bulk electric field distribution. At the same time, it synergistically optimizes the doping concentration of the L-type drift region to suppress the impact ionization effect, ultimately greatly improving the breakdown voltage level of the device.

[0032] Figure 9 The diagram shows the impact ionization rate distribution during breakdown of the device of the present invention and the L-type drift region SiC LDMOS device. (a) is an L-type drift region device, where the strong impact ionization peak region is highly concentrated at the local edge of the drain L-type drift region, exhibiting extremely strong localized avalanche ionization characteristics. The severe impact ionization multiplication effect on the drain side directly causes the device to avalanche breakdown prematurely. (b) is the PNPN quadruple RESURF device of the present invention. The local strong ionization high value region of the device drain is significantly shrunken, and the high impact ionization region is uniformly dispersed to a wider range of the drift region, effectively suppressing the concentration of local avalanche ionization.

[0033] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A SiC LDMOS device based on a PNPN quadruple RESURF structure, characterized in that: The system includes a P+ substrate region, a P-epitaxial layer on the upper surface of the P+ substrate region, a P-base region, an N-drift region, and an L-type drift region extension layer on the upper surface of the P-epitaxial layer; a source P+ region and a source P+ region are provided in the P-base region; a source metal is provided on the upper surface of the source P+ region and the source P+ region; a heavily doped N+ drain is provided in the L-type drift region extension layer; a drain metal field plate is provided on the upper surface of the heavily doped N+ drain; a gate oxide and field oxide layer are provided on the upper surface of the N-drift region; a gate polysilicon ramp field plate is provided in the gate oxide and field oxide layer; and a PNPN quadruple RESURF structure is provided in the N-drift region.

2. The SiC LDMOS device based on the PNPN quadruple RESURF structure according to claim 1, characterized in that: The PNPN quadruple RESURF structure includes, from top to bottom, a P-up buried layer, an N-up buried layer, a P-down buried layer, and an N-down buried layer; the P-up buried layer is in contact with the lower surface of the gate oxide and field oxide layers; and the N-down buried layer is in contact with the upper surface of the P-epitaxial layer.

3. The SiC LDMOS device based on the PNPN quadruple RESURF structure according to claim 2, characterized in that: The lower P-layer and upper P-layer have two electric field peaks at their left and right ends, increasing the electric field peaks on the surface of the N-drift region and modulating the lateral electric field. The lower N-layer and lower N-layer provide a low-resistance conduction path for majority carriers, reducing the specific on-resistance of the device, and participate in the charge balance of the drift region. Together with the RESURF mechanism, they achieve electric field modulation and high breakdown voltage. The doped charges of the upper P-layer, upper N-layer, lower P-layer, and lower N-layer are mutually coupled and matched to form space charge complementarity and charge balance regulation, so that the N-drift region is completely depleted under reverse bias, satisfying the quadruple RESURF charge balance criterion and modulating the lateral and longitudinal electric field distribution of the device.

4. The SiC LDMOS device based on the PNPN quadruple RESURF structure according to claim 1, characterized in that: The source metal extends with a field plate, and the extended field plate of the source metal covers the upper surface of the field oxide layer.

5. The SiC LDMOS device based on a PNPN quadruple RESURF structure according to claim 1, characterized in that: The drain metal field plate extends with a field plate, and the extended field plate portion of the drain metal is located above the L-shaped drift region extension layer and the gate oxide and field oxide layers.

6. The SiC LDMOS device based on the PNPN quadruple RESURF structure according to claim 1, characterized in that: The gate polysilicon ramp field plate is located inside the gate oxide and field oxide layers, with its left end above the P-base region and its right end above the N-drift region.

7. The SiC LDMOS device based on a PNPN quadruple RESURF structure according to claim 1, characterized in that: The gate oxide and field oxide layers are located between the source field plate and the active region, isolating the gate polysilicon ramp field plate and the drain metal field plate.

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