semiconductor devices

Abstract

A semiconductor device includes a substrate, a first conductivity type semiconductor layer on a first surface of the substrate and penetrated by a first trench and a second trench, a gate electrode in the first trench and including a first side surface and a second side surface opposite to each other, a first gate insulating layer on the first side surface and a lower surface of the gate electrode, a second conductivity type doped layer on the first conductivity type semiconductor layer and covering a portion of the side surface of the first gate insulating layer, a first conductivity type doped region on the second conductivity type doped layer and covering another portion of the side surface of the first gate insulating layer, a source electrode on the first conductivity type doped region, a drain electrode on a second surface of the substrate, and a shielding pattern around the second trench.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] In modern society, semiconductor devices are closely related to our daily lives. In particular, the importance of power semiconductor devices is increasing in various fields such as transportation (e.g., electric vehicles, railways, and trams), renewable energy systems (e.g., solar and wind power), and mobile devices. Power semiconductor devices are semiconductor devices designed to handle high voltages or high currents and perform functions such as power conversion and control in high-power systems or high-power electronic devices. Power semiconductor devices have the ability and durability to handle high power, thus enabling them to withstand large currents and high voltages. For example, power semiconductor devices can handle voltages of hundreds to thousands of volts and currents of tens to thousands of amperes. Power semiconductor devices can improve the efficiency of electrical energy by minimizing power losses. Furthermore, power semiconductor devices can operate stably even in environments such as high temperatures.

[0003] These power semiconductor devices can be classified by material; for example, there are SiC power semiconductor devices and GaN power semiconductor devices. By using SiC or GaN instead of existing silicon wafers (Si wafers) to manufacture power semiconductor devices, the instability of silicon at high temperatures can be overcome. SiC power semiconductor devices are heat-resistant and have low power loss, making them suitable for electric vehicles and renewable energy systems. GaN power semiconductor devices are expensive but highly efficient in terms of speed, making them suitable for fast charging of mobile devices. Summary of the Invention

[0004] The embodiments are aimed at providing a semiconductor device with improved reliability.

[0005] A semiconductor device according to an embodiment includes: a substrate; a first conductivity type semiconductor layer on a first surface of the substrate and including a first trench and a second trench overlapping the first trench, the second trench being positioned on one side of the first trench and the first trench and the second trench each penetrating the first conductivity type semiconductor layer; a gate electrode in the first trench and including a first side surface and a second side surface opposite to the first side surface; a first gate insulating layer on the first side surface and a lower surface of the gate electrode; a second conductivity type doped layer on the first conductivity type semiconductor layer and covering at least a portion of the side surface of the first gate insulating layer; a first conductivity type doped region on the second conductivity type doped layer and covering at least another portion of the side surface of the first gate insulating layer; a source electrode on the first conductivity type doped region; a drain electrode on a second surface of the substrate; and a shielding pattern around the second trench.

[0006] A semiconductor device according to an embodiment includes: a substrate; a first conductivity type semiconductor layer on a first surface of the substrate and including a first trench and a second trench overlapping the first trench, the second trench being positioned on one side of the first trench and the first trench and the second trench each penetrating the first conductivity type semiconductor layer; a gate electrode in the first trench and including a first side surface and a second side surface opposite to the first side surface; a first gate insulating layer on the first side surface and a lower surface of the gate electrode; a second conductivity type doped layer on the first conductivity type semiconductor layer and covering at least a portion of the side surface of the first gate insulating layer; a first conductivity type doped region on the second conductivity type doped layer and covering at least another portion of the side surface of the first gate insulating layer; a source electrode on the first conductivity type doped region; a drain electrode on a second surface of the substrate; and an internal insulating pattern in the second trench. The bottom surface of the second trench is positioned closer to the drain electrode than the bottom surface of the first trench, wherein the internal insulating pattern comprises silicon oxide (SiO).

[0007] A semiconductor device according to an embodiment includes: a substrate; a first conductivity type semiconductor layer on a first surface of the substrate; a first trench and a second trench overlapping the first trench, the second trench being positioned on one side of the first trench, and the first trench and the second trench each penetrating the first conductivity type semiconductor layer; a gate electrode in the first trench and including a first side surface and a second side surface opposite to the first side surface; a first gate insulating layer conformally disposed on the bottom surface of the first trench and on a side surface of the first trench facing the first side surface of the gate electrode; an internal insulating pattern in the second trench having an upper surface at the same level as the upper surface of the gate electrode; a capping layer covering the upper surface of the gate electrode and the upper surface of the internal insulating pattern; and a second conductivity type. A doped layer is formed on a first conductivity type semiconductor layer and covers at least a portion of the side surface of a first gate insulating layer and a portion of the side surface of an internal insulating pattern; a first conductivity type doped region is formed on a second conductivity type doped layer and covers at least another portion of the side surface of the first gate insulating layer; a second conductivity type doped region is formed on a second conductivity type doped layer and covers at least a portion of the side surface of the internal insulating pattern; a source electrode is formed covering at least a portion of the upper surface of the first conductivity type doped region, the upper surface of the second conductivity type doped region, the upper surface of the internal insulating pattern, and the upper and side surfaces of a capping layer; a drain electrode is formed on a second surface of the substrate; and a shielding pattern is formed surrounding at least a portion of the side surface and the lower surface of the internal insulating pattern. At least a portion of the lower surface of the first gate insulating layer and the lower surface of the second conductivity type doped region is in contact with the shielding pattern, and the internal insulating pattern comprises silicon oxide (SiO).

[0008] According to the implementation method, a semiconductor device with improved reliability can be provided. Attached Figure Description

[0009] Figure 1 This is a cross-sectional view showing a semiconductor device according to an embodiment.

[0010] Figure 2 yes Figure 1 An enlarged cross-sectional view of region A in the image.

[0011] Figure 3 This is a cross-sectional view showing a semiconductor device according to an embodiment.

[0012] Figure 4 yes Figure 3 Enlarged cross-sectional view of region B.

[0013] Figure 5 This is a cross-sectional view showing a semiconductor device according to an embodiment.

[0014] Figure 6 This is a cross-sectional view showing a semiconductor device according to an embodiment.

[0015] Figure 7 This is a cross-sectional view showing a semiconductor device according to an embodiment.

[0016] Figure 8 This is a cross-sectional view showing a semiconductor device according to an embodiment.

[0017] Figure 9 This is a cross-sectional view showing a semiconductor device according to an embodiment.

[0018] Figures 10 to 18 It is a process cross-sectional view used to illustrate the manufacturing process of a semiconductor device according to an embodiment.

[0019] Figures 19 to 27 It is a process cross-sectional view used to illustrate the manufacturing process of a semiconductor device according to an embodiment. Detailed Implementation

[0020] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily implement the present disclosure. The present disclosure can be implemented in many different forms, and is not limited to the embodiments described herein.

[0021] For clarity of this disclosure, parts irrelevant to the description have been omitted, and identical or similar parts are assigned the same reference numerals throughout the specification.

[0022] Furthermore, for ease of explanation, the sizes and thicknesses of the components shown in the accompanying drawings are arbitrary, and therefore this disclosure is not necessarily limited to what is shown. In the drawings, the thicknesses of layers, films, panels, portions, etc., are exaggerated for clarity. In the drawings, the thicknesses of some layers and portions are exaggerated for ease of explanation.

[0023] It will be understood that when an element such as a layer, film, portion, or substrate is referred to as being "on" another element, it can be directly on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly on" another element, there are no intermediate elements present. Furthermore, being "on" or "above" a reference element means being positioned on or below the reference element, and does not necessarily mean being positioned "above" or "on" in a direction opposite to gravity.

[0024] Furthermore, unless explicitly stated otherwise, the word “including” and variations such as “comprising” or “containing…” will be understood to imply inclusion of the stated element but not exclusion of any other element.

[0025] Furthermore, throughout the instruction manual, when referring to a "plan view," it means the part of the object viewed from above, and when referring to a "section view," it means the vertically cut section of the part of the object viewed from the side.

[0026] In the following text, reference will be made to Figure 1 and Figure 2 Describes a semiconductor device according to an embodiment.

[0027] Reference Figure 1 and Figure 2 The semiconductor device according to the embodiment may include a substrate 110, a first conductivity type semiconductor layer 120 on a first surface of the substrate 110, a first trench 500, a second trench 600 located on one side of the first trench 500 and overlapping the first trench 500, a gate electrode 150 in the first trench 500, a first gate insulating layer 141 on the side surface and the lower surface of the gate electrode 150, a second conductivity type doped layer 133 on the first conductivity type semiconductor layer 120, a first conductivity type doped region 137 on the second conductivity type doped layer 133, a source electrode 173 on the first conductivity type doped region 137, a drain electrode 175 on a second surface of the substrate 110, and a shielding pattern 139 around the second trench 600.

[0028] Substrate 110 may be a semiconductor substrate including SiC. For example, substrate 110 may be made of 4H SiC substrate. In some cases, substrate 110 may be made of 3C SiC substrate, 6H SiC substrate, etc. Substrate 110 may be doped with n-type dopant. The resistivity of substrate 110 may be about 0.005 Ω·cm or greater and about 0.035 Ω·cm or less. The thickness of substrate 110 may be about 10 μm or greater and about 700 μm or less. The material, doping type, doping concentration, resistivity, thickness, etc. of substrate 110 are not limited thereto and can be modified in various ways. Substrate 110 may include a first surface and a second surface opposite to each other. The first surface of substrate 110 may be the upper surface, and the second surface of substrate 110 may be the lower surface.

[0029] A first conductivity type semiconductor layer 120 may be positioned on a first surface (i.e., the upper surface) of the substrate 110. The lower surface of the first conductivity type semiconductor layer 120 may contact the upper surface of the substrate 110. However, it is not limited to this; another layer may be positioned between the substrate 110 and the first conductivity type semiconductor layer 120. The first conductivity type semiconductor layer 120 may be an epitaxial layer formed from the substrate 110 using an epitaxial growth method. The first conductivity type semiconductor layer 120 may contain SiC. For example, the first conductivity type semiconductor layer 120 may contain 4H SiC. The first conductivity type semiconductor layer 120 may be doped to n-type. The first conductivity type semiconductor layer 120 may be lightly doped to n-type. The doping concentration of the first conductivity type semiconductor layer 120 may be lower than the doping concentration of the substrate 110. The doping concentration of the first conductivity type semiconductor layer 120 may be approximately 1.0 × 10⁻⁶. 15 cm -3 Or larger and approximately 1.0 × 10 17 cm -3 Or even smaller. The thickness of the first conductivity type semiconductor layer 120 can be about 1 μm or more and about 13 μm or less. The material, doping type, doping concentration, thickness, etc. of the first conductivity type semiconductor layer 120 are not limited to these and can be modified in various ways.

[0030] The first conductivity type semiconductor layer 120 may include a first trench 500 and a second trench 600 located on one side of the first trench 500. In an embodiment, each unit cell may include a first trench 500 and a second trench 600. A unit cell may be a minimal functional element that performs a specific function in response to a signal received from an external source. In an embodiment, a unit cell may be a switching element. Figure 1 and Figure 2In this context, the unit cell is described as having a trench-type MOSFET structure, but the structure of the unit cell is not limited to this. For example, the unit cell can have a planar MOSFET or a superjunction MOSFET structure. For example, the unit cell can have an IGBT structure.

[0031] Reference Figure 1 and Figure 2 Within a single unit cell, the second trench 600 may be located on one side of the first trench 500 and overlap with the first trench 500 in the first direction D1. Within a single unit cell, the first trench 500 and the second trench 600 may be integrally formed. Within a single unit cell, the first trench 500 and the second trench 600 may be continuously positioned in the first direction D1.

[0032] The first trench 500 can be formed to have a predetermined depth extending from the upper surface of the first conductivity type semiconductor layer 120. (Refer to...) Figure 1 and Figure 2 In one embodiment, the first trench 500 may include a bottom surface and a side surface extending from the bottom surface. One side surface of the first trench 500 may be defined by a first conductivity type semiconductor layer 120, a second conductivity type doped layer 133 (described later), and a first conductivity type doped region 137. The second trench 600 may be defined by the first conductivity type semiconductor layer 120 and a shielding pattern 139 (described later).

[0033] The second trench 600 can be formed to have a predetermined depth from the upper surface of the first conductivity type semiconductor layer 120. In an embodiment, the depth of the second trench 600 formed therein can be greater than the depth of the first trench 500 formed therein. In an embodiment, the level of the bottom surface of the second trench 600 can be lower than the level of the bottom surface of the first trench 500. In an embodiment, the bottom surface of the second trench 600 can be positioned closer to the drain electrode 175, which will be described later, compared to the bottom surface of the first trench 500.

[0034] In one embodiment, the distance between the bottom surface of the second trench 600 and the lower surface of the first conductive semiconductor layer 120 may be shorter than the distance between the bottom surface of the second trench 600 and the upper surface of the first conductive semiconductor layer 120.

[0035] and Figure 1 and Figure 2 As shown in the diagram, the depth of the second trench 600 formed therein can be substantially equal to or less than the depth of the first trench 500 formed therein.

[0036] Reference Figure 1 and Figure 2In one embodiment, the second trench 600 may include a bottom surface and two sidewalls extending from opposite ends of the bottom surface. One sidewall of the second trench 600 may include a portion of the sidewall of the first trench 500 facing in a direction opposite to the first direction D1. The other sidewall of the second trench 600 may face a portion of the sidewall of the second trench 600 in the first direction D1. The other sidewall of the second trench 600 may be located between the sidewall of the first trench 500 and the sidewall of the second trench 600. The sidewall of the second trench 600 may include a corresponding portion of the other sidewall of the second trench 600 and the sidewall of the first trench 500 facing in a direction opposite to the first direction D1.

[0037] Reference Figure 1 and Figure 2 The length of one sidewall of the second groove 600 extending along the second direction D2 can be longer than the length of the other sidewall of the second groove 600 extending along the second direction D2. In an embodiment, the length of one sidewall of the second groove 600 extending along the second direction D2 can be substantially equal to the combined length of the other sidewall of the second groove 600 extending along the second direction D2 and the length of one sidewall of the first groove 500 extending along the second direction D2.

[0038] One sidewall of the second trench 600 may be defined by a second conductivity type doped region 135 and a shielding pattern 139, which will be described later. The bottom surface of the second trench 600 and the other sidewall may be defined by the shielding pattern 139. Figure 1 and Figure 2 In the diagram, the angles of the two sidewalls of the second groove 600 relative to the bottom surface of the second groove 600 are shown as perpendicular, but are not limited thereto.

[0039] The gate electrode 150 can be positioned within a first trench 500 of the first conductivity type semiconductor layer 120. The gate electrode 150 can be spaced apart from the first conductivity type semiconductor layer 120. The distance between the gate electrode 150 and the first conductivity type semiconductor layer 120 can be substantially constant. However, not limited thereto, the distance between the gate electrode 150 and the first conductivity type semiconductor layer 120 can be position-dependent and non-uniform. The gate electrode 150 can have a cross-sectional shape similar to the cross-sectional shape of the first trench 500. Figure 1 and Figure 2 In the cross-sectional view, the gate electrode 150 is depicted as having an approximately rectangular shape, but is not limited thereto. For example, the gate electrode 150 may have a trapezoidal shape, wherein the width in the first direction D1 gradually narrows from top to bottom, and may also have various other shapes.

[0040] The gate electrode 150 may include a lower surface and side surfaces 150s1 and 150s2 extending from the lower surface. The lower surface and side surfaces 150s1 and 150s2 of the gate electrode 150 may form an approximately U-shaped profile in cross-section. The side surfaces 150s1 and 150s2 of the gate electrode 150 may extend in directions parallel to each other. The side surfaces 150s1 and 150s2 of the gate electrode 150 may extend in a second direction D2, but are not limited thereto.

[0041] The gate electrode 150 may further include an upper surface facing the lower surface, and the side surfaces 150s1 and 150s2 may connect the lower surface and the upper surface.

[0042] The lower surface of the gate electrode 150 may face the bottom surface of the first trench 500. The first side surface 150s1 of the gate electrode 150 may face a sidewall of the first trench 500. The first side surface 150s1 of the gate electrode 150 may include a portion overlapping with the first conductivity type doped region 137 and the second conductivity type doped layer 133, which will be described later, in the first direction D1. The second side surface 150s2 of the gate electrode 150 may face a sidewall of the second trench 600. The upper surface of the gate electrode 150 may contact the lower surface of the capping layer 142, which will be described later. The upper surface of the gate electrode 150 may be positioned at substantially the same level as the upper surfaces of the first conductivity type doped region 137 and the second conductivity type doped region 135, which will be described later.

[0043] In an implementation, the width of the gate electrode 150 in the horizontal direction (e.g., the first direction D1) may be narrower than the width of the first trench 500 in the horizontal direction.

[0044] The gate electrode 150 may comprise a conductive material. For example, the gate electrode 150 may comprise polycrystalline silicon doped with impurities. As another example, the gate electrode 150 may comprise a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, a conductive metal nitride, or a combination thereof. The gate electrode 150 may be formed of a single layer or multiple layers.

[0045] The semiconductor device according to an embodiment may further include an internal insulating pattern 143 filling the interior of the second trench 600. In an embodiment, the internal insulating pattern 143 may completely fill the interior of the second trench 600. The internal insulating pattern 143 may cover the bottom surface and two sidewalls of the second trench 600. The upper surface of the internal insulating pattern 143 may be positioned at substantially the same level as the upper surface of the gate electrode 150. The internal insulating pattern 143 may be surrounded by at least a portion of the shielding pattern 139. (Refer to...) Figure 1 and Figure 2At least a portion of the side surface and the lower surface of the internal insulating pattern 143 may be surrounded by the shielding pattern 139. The lower surface of the internal insulating pattern 143 may be covered by the shielding pattern 139. One side surface of the internal insulating pattern 143 may be covered by the second conductivity type doped region 135 and the shielding pattern 139. The other side surface of the internal insulating pattern 143 may be covered by the shielding pattern 139 and the first gate insulating layer 141 and the second gate insulating layer 144, which will be described later.

[0046] In one embodiment, the lower surface of the internal insulating pattern 143 may be positioned adjacent to the drain electrode 175 or the substrate 110. In another embodiment, the distance between the horizontal level of the lower surface of the internal insulating pattern 143 and the horizontal level of the lower surface of the first conductivity type semiconductor layer 120 may be shorter than the distance between the horizontal level of the lower surface of the internal insulating pattern 143 and the horizontal level of the upper surface of the first conductivity type semiconductor layer 120.

[0047] The internal insulating pattern 143 may comprise an insulating material. For example, the internal insulating pattern 143 may comprise silicon oxide (SiO). However, it is not limited to this, and the internal insulating pattern 143 may comprise various insulating materials. For example, the internal insulating pattern 143 may comprise silicon nitride (SiN), silicon oxide nitride (SiON), silicon carbon nitride (SiCN), or combinations thereof. The internal insulating pattern 143 may be formed from a single layer or multiple layers.

[0048] A first gate insulating layer 141 may surround at least a portion of the gate electrode 150. The first gate insulating layer 141 may be positioned on at least a portion of the gate electrode 150. In one embodiment, the first gate insulating layer 141 may be positioned on the bottom surface of the gate electrode 150 and on the first side surface 150s1 of the gate electrode 150. In another embodiment, the first gate insulating layer 141 may not be positioned on the second side surface 150s2 of the gate electrode 150.

[0049] The first gate insulating layer 141 may be positioned between the gate electrode 150 and the first conductivity type semiconductor layer 120. The first gate insulating layer 141 may also be positioned between the gate electrode 150 and the second conductivity type doped layer 133, which will be described later, and between the gate electrode 150 and the first conductivity type doped region 137.

[0050] The first gate insulating layer 141 may be positioned on the bottom surface and a sidewall of the first trench 500. The first gate insulating layer 141 may be positioned on the bottom surface and a sidewall of the first trench 500 with a substantially uniform thickness.

[0051] The first gate insulating layer 141 may comprise an insulating material. In one embodiment, the first gate insulating layer 141 may comprise a thermally oxidized layer formed by a thermal oxidation process. For example, the first gate insulating layer 141 may comprise silicon oxide (SiO) formed by a thermal oxidation process. However, it is not limited to this, and the material of the first gate insulating layer 141 may be modified in various ways. As another example, the first gate insulating layer 141 may comprise silicon nitride (SiN), silicon oxide nitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), or a combination thereof. The first gate insulating layer 141 may be formed as a single layer or multiple layers.

[0052] The semiconductor device according to the embodiment may further include a second gate insulating layer 144 positioned between the gate electrode 150 and the first gate insulating layer 141. The second gate insulating layer 144 may cover two side surfaces 150s1, 150s2 and a lower surface of the gate electrode 150. The second gate insulating layer 144 may be positioned between the first side surface 150s1 of the gate electrode 150 and the first gate insulating layer 141. The second gate insulating layer 144 may also be located between the lower surface of the gate electrode 150 and the first gate insulating layer 141.

[0053] Reference Figure 2 The second gate insulating layer 144 may also be positioned between the second side surface 150s2 of the gate electrode 150 and the internal insulating pattern 143. In an embodiment, the second gate insulating layer 144 may comprise an insulating material. The second gate insulating layer 144 may comprise silicon oxide (SiO). However, it is not limited thereto, and the internal insulating pattern 143 may comprise various insulating materials. For example, the internal insulating pattern 143 may comprise silicon nitride (SiN), silicon oxide nitride (SiON), silicon carbon nitride (SiCN), or a combination thereof. The internal insulating pattern 143 may be formed of a single layer or multiple layers.

[0054] In one embodiment, the second gate insulating layer 144 may comprise the same insulating material as the insulating material included in the inner insulating pattern 143. (See also...) Figure 2 The boundary between the second gate insulating layer 144 and the inner insulating pattern 143 is shown to be present, but if the second gate insulating layer 144 and the inner insulating pattern 143 contain the same insulating material, the boundary between them may be visually indistinguishable. Figure 2 In this design, the second gate insulating layer 144 and the internal insulating pattern 143 are depicted as separate structures, but the internal insulating pattern 143 and the second gate insulating layer 144 can be formed integrally. In an embodiment, the internal insulating pattern 143 and the second gate insulating layer 144 can be formed simultaneously in the same process.

[0055] The second conductivity type doped layer 133 may be located on the first conductivity type semiconductor layer 120. The second conductivity type doped layer 133 may be a region in which a channel is formed during ON operation of the semiconductor device according to the embodiment. During ON operation of the semiconductor device according to the embodiment, when a turn-on voltage is applied to the gate electrode 150, the channel may be formed in the second conductivity type doped layer 133. In this case, current can flow from the drain electrode 175 through the first conductivity type semiconductor layer 120, the second conductivity type doped layer 133, the first conductivity type doped region 137, and the second conductivity type doped region 135 to the source electrode 173.

[0056] The second conductivity type doped layer 133 may overlap with at least a portion of the gate electrode 150, at least a portion of the first gate insulating layer 141, and at least a portion of the second gate insulating layer 144 in the first direction D1. The second conductivity type doped layer 133 may face the gate electrode 150, with the first gate insulating layer 141 and the second gate insulating layer 144 interposed therebetween. The surface of the second conductivity type doped layer 133 facing the gate electrode 150 may be positioned on the same boundary line as one sidewall of the first trench 500. The second conductivity type doped layer 133 may cover at least a portion of the side surface of the first gate insulating layer 141 and the side surface of the inner insulating pattern 143. The shielding pattern 139, which will be described later, may be positioned between the second conductivity type doped layer 133 and the inner insulating pattern 143.

[0057] The second conductivity type doped layer 133 may be an epitaxial layer grown from the first conductivity type semiconductor layer 120 using an epitaxial growth method. Optionally, the second conductivity type doped layer 133 may be a doped region formed in the first conductivity type semiconductor layer 120 using an ion implantation (IIP) process.

[0058] The second conductivity type doped layer 133 may contain SiC. For example, the second conductivity type doped layer 133 may contain 4HSiC. The second conductivity type doped layer 133 may be doped with a p-type dopant. The second conductivity type doped layer 133 may be lightly doped with a p-type dopant. The doping concentration of the second conductivity type doped layer 133 may be approximately 1.0 × 10⁻⁶. 17 cm -3 Or larger and approximately 1.0 × 10 19 cm -3 Or even smaller. The material, doping type, doping concentration, and thickness of the second conductivity type doped layer 133 are not limited to this and can be modified in various ways.

[0059] The first conductivity type doped region 137 can be located on the second conductivity type doped layer 133. The first conductivity type doped region 137 can be located between the second conductivity type doped layer 133 and the source electrode 173, which will be described later.

[0060] The first conductivity type doped region 137 may cover at least a portion of the first gate insulating layer 141. The first conductivity type doped region 137 may face the gate electrode 150, and the first gate insulating layer 141 and the second gate insulating layer 144 are interposed therebetween. The surface of the first conductivity type doped region 137 facing the gate electrode 150 may be located on the same boundary line as the sidewall of the first trench 500. The upper surface of the first conductivity type doped region 137 may contact the source electrode 173, which will be described later. The lower surface of the first conductivity type doped region 137 may contact the second conductivity type doped layer 133. At least a portion of the upper surface of the first conductivity type doped region 137 may be covered by a capping layer 142, but is not limited thereto.

[0061] The first conductivity type doped region 137 can be a region formed in the first conductivity type semiconductor layer 120 using an ion implantation process. The first conductivity type doped region 137 can contain SiC. For example, the first conductivity type doped region 137 can contain 4H SiC. The first conductivity type doped region 137 can be doped with an n-type dopant. The first conductivity type doped region 137 can be heavily doped with an n-type dopant. The doping concentration of the first conductivity type doped region 137 can be approximately 1.0 × 10⁻⁶. 18 cm -3 Or larger and approximately 5.0 × 10 20 cm -3 Or smaller. The material, doping type, and doping concentration of the first conductivity type doped region 137 are not limited to this and can be modified in various ways.

[0062] The semiconductor device according to an embodiment may further include a second conductivity type doped region 135 positioned on a second conductivity type doped layer 133. In an embodiment, the second conductivity type doped region 135 may be positioned to one side of the first conductivity type doped region 137. The second conductivity type doped region 135 may be positioned at substantially the same level as the first conductivity type doped region 137. The upper surface of the second conductivity type doped region 135 may be positioned at substantially the same level as the upper surface of the first conductivity type doped region 137. The second conductivity type doped region 135 may have a side surface in contact with the first conductivity type doped region 137. The second conductivity type doped region 135 may have another side surface in contact with the internal insulating pattern 143.

[0063] The second conductivity type doped region 135 can be positioned between the second conductivity type doped layer 133 and the source electrode 173. The lower surface of the second conductivity type doped region 135 can contact the second conductivity type doped layer 133. At least a portion of the lower surface of the second conductivity type doped region 135 can contact the shielding pattern 139, which will be described later. The upper surface of the second conductivity type doped region 135 can contact the source electrode 173. The second conductivity type doped region 135 can form an ohmic contact with the source electrode 173.

[0064] The second conductivity type doped region 135 can be a region formed in the first conductivity type semiconductor layer 120 using an ion implantation process. The second conductivity type doped region 135 can contain SiC. For example, the second conductivity type doped region 135 can contain 4H SiC. The second conductivity type doped region 135 can be doped with a p-type dopant. The second conductivity type doped region 135 can be heavily doped with a p-type dopant. The doping concentration of the second conductivity type doped region 135 can be approximately 1.0 × 10⁻⁶. 18 cm -3 Or larger and approximately 5.0 × 10 20 cm -3 Or even smaller. The material, doping type, and doping concentration of the second conductivity type doped region 135 are not limited to this and can be modified in various ways.

[0065] The semiconductor device according to the embodiment may further include a capping layer 142 positioned above the gate electrode 150. The capping layer 142 may cover the upper surface of the gate electrode 150. Additionally, the capping layer 142 may cover at least a portion of the first gate insulating layer 141, the second gate insulating layer 144, and the first conductivity type doped region 137 adjacent to the gate electrode 150. The capping layer 142 may be surrounded by the source electrode 173, which will be described later. For example, the capping layer 142 may be positioned between adjacent source electrodes 173 in a first direction D1. The gate electrode 150 may be insulated from the source electrode 173 by the capping layer 142.

[0066] Cap layer 142 may comprise an insulating material. For example, cap layer 142 may comprise silicon oxide (SiO), silicon oxyphosphide (SiOP), silicon nitride (SiN), silicon nitride oxide (SiON), or combinations thereof. However, it is not limited thereto, and the material of cap layer 142 may be modified in various ways. Cap layer 142 may be formed of a single layer or multiple layers. Cap layer 142 may comprise the same material as the first gate insulating layer 141 or may comprise a different material. When cap layer 142 is formed of the same material as the first gate insulating layer 141, the boundary between cap layer 142 and the first gate insulating layer 141 may not be clearly distinguishable at the interface where they contact each other.

[0067] The source electrode 173 can be positioned on the first conductivity type semiconductor layer 120. The source electrode 173 can be positioned on the upper surface of the first conductivity type doped region 137 and the upper surface of the second conductivity type doped region 135.

[0068] The source electrode 173 may comprise a conductive material. For example, the source electrode 173 may comprise a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal nitride. For example, the source electrode 173 may comprise titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), and tantalum carbonitride (Ta... The source electrode 173 may be formed of a single layer or multiple layers, including, but not limited to, the following: CN, tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof.

[0069] Drain electrode 175 can be positioned on the second surface of substrate 110, that is, the lower surface. The upper surface of drain electrode 175 can contact the lower surface of substrate 110. Drain electrode 175 can have an ohmic contact with substrate 110. In substrate 110, the region in contact with drain electrode 175 can be doped at a relatively high concentration compared to other regions. However, this is not a limitation; another layer can be additionally positioned between drain electrode 175 and substrate 110.

[0070] The drain electrode 175 may comprise a conductive material. For example, the drain electrode 175 may comprise a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal nitride. The drain electrode 175 may be made of the same material as the source electrode 173, or it may be made of a different material. The drain electrode 175 may be formed as a single layer or multiple layers.

[0071] The shielding pattern 139 may be positioned around the second trench 600. The shielding pattern 139 in the semiconductor device according to the embodiment may be designed to reduce the electric field that may be concentrated around the first gate insulating layer 141 or the second gate insulating layer 144 and to improve the breakdown voltage.

[0072] The shielding pattern 139 may surround at least a portion of the second trench 600. The shielding pattern 139 may surround at least a portion of the bottom surface of the second trench 600 and the two sidewalls of the second trench 600. The shielding pattern 139 may surround at least a portion of the side and lower surfaces of the internal insulating pattern 143 that fills the interior of the second trench 600. The shielding pattern 139 may be positioned between the lower surface of the internal insulating pattern 143 and the first conductivity type semiconductor layer 120. The shielding pattern 139 may also be positioned between the side surfaces of the internal insulating pattern 143 and the first conductivity type semiconductor layer 120. At a level above the upper surface of the first conductivity type semiconductor layer 120, the shielding pattern 139 may also be positioned between the internal insulating pattern 143 and the second conductivity type doped layer 133.

[0073] The shielding pattern 139 can be formed with a predetermined width. (See reference...) Figure 1 and Figure 2 The width of the shielding pattern 139 located on the lower surface of the inner insulating pattern 143 in the second direction D2 may gradually decrease towards both ends of the lower surface of the inner insulating pattern 143, but is not limited thereto. The shielding pattern 139 located on the side surface of the inner insulating pattern 143 may have a uniform width in the first direction D1, but is not limited thereto.

[0074] In an embodiment, the length of the portion of the shielding pattern 139 located on one side surface of the inner insulating pattern 143 adjacent to the gate electrode 150 in the second direction D2 may be shorter than the length of the portion of the shielding pattern 139 located on the other side surface of the inner insulating pattern 143 in the second direction D2.

[0075] In one embodiment, the upper surface of a portion of the shielding pattern 139 located on a side surface of the inner insulating pattern 143 adjacent to the gate electrode 150 may cover at least a portion of the lower surface of the first gate insulating layer 141. (Refer to...) Figure 1 The shielding pattern 139 is shown to cover only a portion of the lower surface of the first gate insulating layer 141, but alternatively, the shielding pattern 139 may cover the entire lower surface of the first gate insulating layer 141.

[0076] In one embodiment, the upper surface of the portion of the shielding pattern 139 located on the other side surface of the internal insulating pattern 143 may cover at least a portion of the lower surface of the second conductivity type doped region 135, and the other side surface of the internal insulating pattern 143 faces a side surface of the internal insulating pattern 143 adjacent to the gate electrode 150.

[0077] The shielding pattern 139 can be a region formed in the first conductivity type semiconductor layer 120 using an ion implantation process. Specifically, the shielding pattern 139 can be a doped region formed by forming a second trench 600 in the first conductivity type semiconductor layer 120, and then implanting ions into the bottom surface and two sidewalls of the second trench 600 using an ion implantation process. The shielding pattern 139 can contain SiC. For example, the shielding pattern 139 can contain 4H SiC.

[0078] In embodiments, the shielding pattern 139 may also have a different conductivity type than that of the first conductivity type semiconductor layer 120. For example, the shielding pattern 139 may be doped with a p-type dopant. In embodiments, the shielding pattern 139 may be doped at a relatively high concentration compared to the first conductivity type semiconductor layer 120. Although in Figure 1 and Figure 2 It is not clearly shown, but in this case, the depletion region formed around the boundary between the first conductivity type semiconductor layer 120 and the shielding pattern 139 can extend wide and deep toward the first conductivity type semiconductor layer 120.

[0079] For example, the depletion region around the boundary between the portion of the shielding pattern 139 on the lower surface of the inner insulating pattern 143 and the first conductivity type semiconductor layer 120 can be formed to extend into the region adjacent to the upper surface of the substrate 110.

[0080] For example, the depletion region can be formed to overlap the entire lower surface of the first gate insulating layer 141 in the second direction D2. The depletion region is located around the boundary between a portion of the shielding pattern 139 and the first conductivity type semiconductor layer 120. This portion of the shielding pattern 139 is on a side surface of the inner insulating pattern 143 adjacent to the gate electrode 150.

[0081] According to the embodiment, since the shielding pattern 139 is positioned on the lower surface of the first gate insulating layer 141, the electric field concentrated around the first gate insulating layer 141 can be reduced, thereby improving the reliability of the semiconductor device.

[0082] The semiconductor device according to the embodiments may include a second trench 600, the second trench 600 being formed deeper than the first trench 500 and positioned on one side of the first trench 500 in the horizontal direction (e.g., Figure 1 The shielding pattern 139 overlaps with the first trench 500 in the first direction D1), and the shielding pattern 139 can be positioned around the second trench 600. According to this embodiment, the depletion region formed around the interface between the shielding pattern 139 and the first conductivity type semiconductor layer 120 can increase the breakdown voltage of the semiconductor device, thereby improving the reliability of the semiconductor device.

[0083] Figure 3 and Figure 4 This is a diagram used to illustrate a semiconductor device according to an embodiment. Specifically, Figure 3 This is a cross-sectional view showing a semiconductor device according to an embodiment. Figure 4 yes Figure 3 Enlarged cross-sectional view of region B. Figure 3 and Figure 4 The semiconductor device shown has many similarities to the previous embodiments, so the following description focuses mainly on the differences from the previous embodiments.

[0084] In the semiconductor device according to the embodiment, the internal insulating pattern 143 may include a first internal insulating pattern 143a and a second internal insulating pattern 143b.

[0085] In implementation, the first internal insulating pattern 143a and the second internal insulating pattern 143b can be formed in different processes. For example, the second internal insulating pattern 143b can be formed by first filling the entire interior of the second trench 600 with the first internal insulating pattern 143a, etching a portion of the first internal insulating pattern 143a, and then filling the etched portion with an insulating material.

[0086] The second internal insulating pattern 143b can be positioned between the gate electrode 150 and the first internal insulating pattern 143a. In one embodiment, the lower surface of the second internal insulating pattern 143b can be positioned at substantially the same level as the lower surface of the first gate insulating layer 141. A portion of the upper surface of the second internal insulating pattern 143b can be covered by the capping layer 142. One side surface and the lower surface of the second internal insulating pattern 143b can be covered by the first internal insulating pattern 143a.

[0087] The second internal insulating pattern 143b may comprise an insulating material. The second internal insulating pattern 143b may comprise silicon oxide (SiO). However, it is not limited to this; the second internal insulating pattern 143b may comprise various insulating materials. For example, the second internal insulating pattern 143b may comprise silicon nitride (SiN), silicon oxide nitride (SiON), silicon carbon nitride (SiCN), or combinations thereof. The second internal insulating pattern 143b may be formed from a single layer or multiple layers. In an embodiment, the second internal insulating pattern 143b may comprise the same insulating material as the first internal insulating pattern 143a. In this case, the boundary between the first internal insulating pattern 143a and the second internal insulating pattern 143b may not be discernible.

[0088] In one embodiment, the second gate insulating layer 144 may contain the same insulating material as the insulating material contained in the second internal insulating pattern 143b. (See also...) Figure 4 Although a boundary appears to exist between the second gate insulating layer 144 and the second internal insulating pattern 143b, this boundary can be visually indistinguishable when both layers contain the same insulating material. Figure 4 In this embodiment, the second gate insulating layer 144 and the second internal insulating pattern 143b are shown as separate components, but the second internal insulating pattern 143b and the second gate insulating layer 144 can be formed integrally. In another embodiment, the second internal insulating pattern 143b and the second gate insulating layer 144 can be formed simultaneously in the same process.

[0089] Figure 5 This is a cross-sectional view showing a semiconductor device according to an embodiment. Figure 5 The semiconductor device shown has many similarities to the previous embodiments; therefore, the following description focuses primarily on the differences from the previous embodiments. Specifically, Figure 5 The semiconductor device shown may have a source electrode 173 structure that is slightly different from the previous embodiment.

[0090] Reference Figure 5 In the semiconductor device according to the embodiment, in the portion where the source electrode 173 and the internal insulating pattern 143 overlap in the second direction D2, the source electrode 173 can extend to a predetermined depth in the internal insulating pattern 143. Figure 5 In this context, the lower surface of the source electrode 173 extending into the internal insulating pattern 143 can be positioned at substantially the same level as the lower surface of the second conductivity type doped region 135, but is not limited thereto. For example, the source electrode 173 can extend to a level below the lower surface of the second conductivity type doped region 135.

[0091] In this embodiment, one side of the second conductivity type doped region 135 may contact the source electrode 173. Unlike the previous example, the second conductivity type doped region 135 may contact the source electrode 173 at both its upper and side surfaces.

[0092] According to the embodiment, the contact area between the second conductivity type doped region 135 and the source electrode 173 can be increased, and the contact resistance between the second conductivity type doped region 135 and the source electrode 173 can be reduced, thereby improving the electrical characteristics of the semiconductor device according to the embodiment.

[0093] Figure 6 This is a cross-sectional view showing a semiconductor device according to an embodiment. Figure 6The semiconductor device shown has many similarities to the previous embodiments; therefore, the following description focuses on the differences from the previous embodiments. Specifically, Figure 6 The semiconductor device shown may differ from the aforementioned embodiments in that it further includes a dummy semiconductor pattern 138.

[0094] Reference Figure 6 The dummy semiconductor pattern 138 can be positioned inside the second trench 600. The dummy semiconductor pattern 138 can be formed by etching a portion of the internal insulating pattern 143 that fills the interior of the second trench 600, and then filling the etched portion with a semiconductor material.

[0095] The dummy semiconductor pattern 138 can extend in the second direction D2. (Refer to...) Figure 6 The upper surface of the dummy semiconductor pattern 138 can be positioned at substantially the same level as the upper surface of the second conductivity type doped layer 133. Figure 6 Unlike the example shown, the upper surface of the dummy semiconductor pattern 138 can be positioned at the same level as the upper surfaces of the gate electrode 150, the internal insulating pattern 143, the first conductivity type doped region 137, and / or the second conductivity type doped region 135.

[0096] The lower surface of the dummy semiconductor pattern 138 can be positioned at a higher level than the lower surface of the inner insulating pattern 143. However, it is not limited to this; the lower surface of the dummy semiconductor pattern 138 can be positioned at the same level as the lower surface of the inner insulating pattern 143.

[0097] The dummy semiconductor pattern 138 may comprise a semiconductor material. For example, the dummy semiconductor pattern 138 may comprise the same material as the gate electrode 150. For example, the dummy semiconductor pattern 138 may comprise polysilicon. In embodiments, the dummy semiconductor pattern 138 may be an undoped intrinsic semiconductor, but is not limited thereto.

[0098] Compared to silicon oxide (SiO), polycrystalline silicon can exhibit higher rigidity. Furthermore, compared to SiO, polycrystalline silicon can fill the interior of trenches more effectively without creating voids. According to an embodiment, the interior of the second trench 600 can be filled with a dummy semiconductor pattern 138 comprising polycrystalline silicon, thereby improving the reliability of the semiconductor device.

[0099] Figure 7 This is a cross-sectional view showing a semiconductor device according to an embodiment. Figure 7 The semiconductor device shown has many similarities to the previous embodiments; therefore, the following description focuses on the differences from the previous embodiments. Specifically, Figure 7The semiconductor device shown may differ in part from the aforementioned embodiments in terms of the structure and location of the gate electrode 150.

[0100] Reference Figure 7 In the semiconductor device according to the embodiment, the second gate insulating layer 144 may not be positioned between the first gate insulating layer 141 and the gate electrode 150. Specifically, in reference to... Figure 1 and Figure 2 In the described semiconductor device, the second gate insulating layer 144 is positioned between the first side surface 150s1 of the gate electrode 150 and the first gate insulating layer 141, and between the lower surface of the gate electrode 150 and the first gate insulating layer 141. In contrast, in the semiconductor device according to this embodiment, the second gate insulating layer 144 may not be positioned between the first side surface 150s1 of the gate electrode 150 and the first gate insulating layer 141, or between the lower surface of the gate electrode 150 and the first gate insulating layer 141.

[0101] In one embodiment, one side and the lower surface of the gate electrode 150 may contact the first gate insulating layer 141.

[0102] Figure 8 This is a cross-sectional view showing a semiconductor device according to an embodiment. Figure 8 The semiconductor device shown has many similarities to the previous embodiments; therefore, the following description focuses on the differences from the previous embodiments. Specifically, Figure 8 The shape of the gate electrode 150 in the semiconductor device shown may be partially different from the shape of the gate electrode 150 in the aforementioned embodiments.

[0103] In one embodiment, the gate electrode 150 may have a width that gradually decreases from top to bottom in the first direction D1. (Refer to...) Figure 8 In one embodiment, the side surface of the gate electrode 150 that contacts the first gate insulating layer 141 can extend parallel to the second direction D2. In another embodiment, the side surface of the gate electrode 150 that contacts the inner insulating pattern 143 can extend in a direction inclined relative to the second direction D2. In yet another embodiment, the side surface of the gate electrode 150 that contacts the inner insulating pattern 143 can extend in an inclined direction between the first direction D1 and the second direction D2.

[0104] In the region where the internal insulating pattern 143 overlaps with the gate electrode 150 in the first direction D1, the internal insulating pattern 143 may have a width that gradually increases from top to bottom in the first direction D1. (Refer to...) Figure 8In one embodiment, the side surface of the internal insulating pattern 143 that contacts the shielding pattern 139 and the second conductivity type doped region 135 may extend in the second direction D2. In another embodiment, one of the side surfaces of the internal insulating pattern 143 that contacts the gate electrode 150 may include a sloped region. In yet another embodiment, in the region of the internal insulating pattern 143 that overlaps with the gate electrode 150 in the first direction D1, the side surface of the internal insulating pattern 143 that contacts the gate electrode 150 may extend in a sloped direction between the first direction D1 and the second direction D2.

[0105] Reference Figure 8 The shapes of the described gate electrode 150 and internal insulating pattern 143 can be determined by the process of forming the first trench 500 (see [link]). Figure 22 and Figure 23 During this period, the difference in etching selectivity between silicon carbide (SiC) contained in the first conductivity type doped region 137, the second conductivity type doped layer 133, the first conductivity type semiconductor layer 120, and the shielding pattern 139 and silicon oxide (SiO) contained in the inner insulating pattern 143 arises.

[0106] Figure 9 This is a cross-sectional view showing a semiconductor device according to an embodiment. Figure 9 The semiconductor device shown has many similarities to the previous embodiments, therefore the following description focuses on the differences from the previous embodiments.

[0107] Reference Figure 9 A dummy semiconductor pattern 138 may be positioned within the second trench 600. In one embodiment, the entire interior region of the second trench 600, positioned below the level of the upper surface of the second conductivity type doped layer 133, may be filled with the dummy semiconductor pattern 138. The dummy semiconductor pattern 138 may cover the bottom surface and two sidewalls of the second trench 600. The upper surface of the dummy semiconductor pattern 138 may be positioned at substantially the same level as the upper surface of the second conductivity type doped layer 133. At least a portion of the lower surface and two side surfaces of the dummy semiconductor pattern 138 may be surrounded by a shielding pattern 139. In one embodiment, a portion of the upper surface of the dummy semiconductor pattern 138 may contact the source electrode 173. (Refer to...) Figure 9 The internal insulating pattern 143 can be positioned at a level above the upper surface of the second conductivity type doped layer 133 between the capping layer 142 and the dummy semiconductor pattern 138.

[0108] Figures 10 to 18 This is a cross-sectional view illustrating the manufacturing process of a semiconductor device according to an embodiment. Specifically, Figures 10 to 18 It is used for illustration and reference. Figure 1 and Figure 2 A cross-sectional view of the manufacturing process of the described semiconductor device.

[0109] like Figure 10 As shown, a second conductivity type doped layer 133, a first conductivity type doped region 137, and a second conductivity type doped region 135 can be sequentially formed on top of a first conductivity type semiconductor layer 120 positioned on a substrate 110.

[0110] Substrate 110 may be a semiconductor substrate containing SiC. For example, substrate 110 may be made of 4H SiC substrate. Substrate 110 may be heavily doped with an n-type dopant. Substrate 110 may include a first surface and a second surface facing each other. The first surface of substrate 110 may be the upper surface, and the second surface of substrate 110 may be the lower surface.

[0111] A first conductivity type semiconductor layer 120 can be formed on a first surface (i.e., the upper surface) of a substrate 110 using an epitaxial growth method. The first conductivity type semiconductor layer 120 can be formed directly on the substrate 110, or other predetermined layers can be formed on the substrate 110, and then the first conductivity type semiconductor layer 120 can be formed thereon. The first conductivity type semiconductor layer 120 may contain SiC. For example, the first conductivity type semiconductor layer 120 may contain 4H SiC. The first conductivity type semiconductor layer 120 may be lightly doped with an n-type dopant. The doping concentration of the first conductivity type semiconductor layer 120 may be lower than the doping concentration of the substrate 110. The doping type of the first conductivity type semiconductor layer 120 may be the same as the doping type of the substrate 110. The doping material of the first conductivity type semiconductor layer 120 may be the same as or different from the doping material of the substrate 110.

[0112] Next, a second conductivity type doped layer 133 can be formed in the upper region of the first conductivity type semiconductor layer 120. The second conductivity type doped layer 133 can be formed by an ion implantation process. The second conductivity type doped layer 133 can have a predetermined depth. At this time, the depth of the second conductivity type doped layer 133 can be determined by the number of implanted ions and / or the ion acceleration rate.

[0113] In this embodiment, the second conductivity type doped layer 133 may comprise SiC. For example, the second conductivity type doped layer 133 may comprise 4H SiC. The second conductivity type doped layer 133 may be doped with a p-type dopant. The second conductivity type doped layer 133 may be lightly doped with a p-type dopant. For example, the doping concentration of the second conductivity type doped layer 133 may be approximately 1.0 × 10⁻⁶. 17 cm -3 Or larger and approximately 1.0 × 10 19 cm -3Or even smaller. The material, doping type, doping concentration, etc. of the second conductivity type doped layer 133 are not limited to this, and various modifications can be made.

[0114] Next, ions can be implanted into the second conductivity type doped layer 133 to form a first conductivity type doped region 137. The first conductivity type doped region 137 can be formed within the second conductivity type doped layer 133 by an ion implantation process. The first conductivity type doped region 137 can be formed in at least a portion of the second conductivity type doped layer 133. First, a mask can be used to define a region on the second conductivity type doped layer 133 in which the first conductivity type doped region 137 will be formed. Thereafter, first conductivity type impurity ions can be implanted into this region. For example, the first conductivity type doped region 137 can be formed to a predetermined depth from the upper surface of the second conductivity type doped layer 133.

[0115] The first conductivity type doped region 137 may contain SiC. For example, the first conductivity type doped region 137 may contain 4HSiC. The first conductivity type doped region 137 may be heavily n-type doped. The doping type of the first conductivity type doped region 137 may be different from the doping type of the second conductivity type doped layer 133. The doping type of the first conductivity type doped region 137 may be the same as the doping type of the substrate 110 and the first conductivity type semiconductor layer 120. The doping concentration of the first conductivity type doped region 137 may be approximately 1.0 × 10⁻⁶. 18 cm -3 Or larger and approximately 5.0 × 10 20 cm -3 Or smaller. The material, doping type, doping concentration, etc. of the first conductivity type doped region 137 are not limited to this, and can be changed in various ways.

[0116] Subsequently, ions can be implanted into the second conductivity type doped layer 133 to further form the second conductivity type doped region 135. In an embodiment, the second conductivity type doped region 135 may be formed and positioned on one side of the first conductivity type doped region 137. The second conductivity type doped region 135 may be formed to be alternately arranged with the first conductivity type doped region 137 along the first direction D1 on the second conductivity type doped layer 133.

[0117] First, a mask can be used to define a region on the second conductivity type doped layer 133 in which the second conductivity type doped region 135 will be formed. The region where the second conductivity type doped region 135 will be formed can be defined as being located on one side of the first conductivity type doped region 137. In an embodiment, the depth of the second conductivity type doped region 135 can be substantially the same as the depth of the first conductivity type doped region 137. At least a portion of both side surfaces of the second conductivity type doped region 135 can be surrounded by the first conductivity type doped region 137.

[0118] The second conductivity type doped region 135 may contain SiC. For example, the second conductivity type doped region 135 may contain 4HSiC. The second conductivity type doped region 135 may be heavily doped with a p-type dopant. The doping type of the second conductivity type doped region 135 may be the same as the doping type of the second conductivity type doped layer 133. The doping material of the second conductivity type doped region 135 may be the same as or different from the doping material of the second conductivity type doped layer 133. The doping concentration of the second conductivity type doped region 135 may be higher than that of the second conductivity type doped layer 133.

[0119] like Figure 11 As shown, the first trench 500 can be formed by etching a portion of the first conductivity type semiconductor layer 120, a portion of the second conductivity type doped layer 133, a portion of the second conductivity type doped region 135, and a portion of the first conductivity type doped region 137.

[0120] First, a mask pattern with openings of a predetermined width can be formed over the first conductivity type doped region 137 and the second conductivity type doped region 135. At this time, the openings formed in the mask pattern can expose a portion of the first conductivity type doped region 137 and the second conductivity type doped region 135. Next, the first trench 500 can be formed by etching the first conductivity type doped region 137 and the second conductivity type doped region 135 exposed by the mask pattern, as well as portions of the second conductivity type doped layer 133 and the first conductivity type semiconductor layer 120 located below them. The first trench 500 can be formed by a dry etching process such as, for example, RIE (reactive ion etching) or ICP (inductively coupled plasma), but is not limited thereto.

[0121] In an embodiment, the first trench 500 may be formed to a predetermined depth. The first trench 500 may be formed in an approximately U-shape in cross-section. The first trench 500 may include a bottom surface and two sidewalls extending from the bottom surface. The bottom surface of the first trench 500 may be defined by a first conductivity type semiconductor layer 120. One sidewall of the first trench 500 may be defined by the first conductivity type semiconductor layer 120, a second conductivity type doped layer 133, and a first conductivity type doped region 137. The other sidewall of the first trench 500, opposite to one sidewall, may be defined by the first conductivity type semiconductor layer 120, the second conductivity type doped layer 133, and a second conductivity type doped region 135. The angles of one sidewall and the other sidewall relative to the bottom surface of the first trench 500 may be perpendicular, but are not limited thereto.

[0122] The bottom surface of the first trench 500 can be positioned at a level lower than the lower surface of the second conductivity type doped layer 133. The bottom surface of the first trench 500 can be positioned closer to the upper surface of the substrate 110 than the lower surface of the second conductivity type doped layer 133.

[0123] like Figure 12 As shown, a first gate insulating layer 141 can be conformally formed along the bottom surface and two sidewalls of the first trench 500. In an embodiment, the first gate insulating layer 141 can be formed by a high-temperature oxidation process. The process of forming the first gate insulating layer 141 can be performed, for example, by a dry oxidation process. However, it is not limited thereto, and the process of forming the first gate insulating layer 141 can also be performed by a wet oxidation process. By the oxidation process, the first gate insulating layer 141 can be formed on the surfaces of the first conductivity type semiconductor layer 120, the second conductivity type doped layer 133, the second conductivity type doped region 135, and the first conductivity type doped region 137 exposed in the first trench 500. In an embodiment, an oxide film can also be formed on the upper surfaces of the second conductivity type doped region 135 and the first conductivity type doped region 137. The oxide film formed on the upper surfaces of the second conductivity type doped region 135 and the first conductivity type doped region 137 can be removed, for example, by performing a chemical mechanical polishing (CMP) process.

[0124] Next, as Figure 13 As shown, a portion of the first conductivity type semiconductor layer 120, a portion of the second conductivity type doped layer 133, a portion of the second conductivity type doped region 135, and a portion of the first gate insulating layer 141 can be etched to form the second trench 600. In one embodiment, the second trench 600 can be formed on one side of the first trench 500 to partially overlap with the first trench 500. During the process of forming the second trench 600, a portion of the first gate insulating layer 141 located on one of the sidewalls of the first trench 500 can be removed.

[0125] To form the second trench 600, a photolithography process can be performed once, twice, or more. For example, a mask pattern including openings can first be formed on the upper surfaces of the second conductivity type doped region 135 and the first conductivity type doped region 137, exposing the area where the second trench 600 will be formed. In an embodiment, the mask pattern may also be positioned on at least a portion of the interior of the first trench 500. The mask pattern may cover a portion of the first gate insulating layer 141 formed on the bottom surface of the first trench 500. The mask pattern may cover a region of the first gate insulating layer 141 formed on a sidewall of the first trench 500, including the region defined by the first conductivity type doped region 137. Subsequently, the second trench 600 can be formed by etching a portion of the first gate insulating layer 141 and a portion of the second conductivity type doped region 135 exposed by the mask pattern, as well as portions of the underlying second conductivity type doped layer 133 and first conductivity type semiconductor layer 120. In this embodiment, the etching process of the first gate insulating layer 141, and the etching processes of the second conductivity type doped region 135, the second conductivity type doped layer 133, and the first conductivity type semiconductor layer 120 can be performed sequentially or simultaneously. The second trench 600 can be formed by a dry etching process such as, for example, RIE (reactive ion etching) or ICP (inductively coupled plasma), but is not limited thereto.

[0126] In one embodiment, the second trench 600 may be formed to a predetermined depth. The second trench 600 may be formed in an approximately U-shape in cross-section. The second trench 600 may include a bottom surface and two sidewalls extending from the bottom surface. The bottom surface of the second trench 600 may be defined by a first conductivity type semiconductor layer 120. One sidewall of the second trench 600 may be defined by the first conductivity type semiconductor layer 120 and a first gate insulating layer 141. The other sidewall of the second trench 600 facing one sidewall may be defined by the first conductivity type semiconductor layer 120, a second conductivity type doped layer 133, and a second conductivity type doped region 135. The angles of the first and second sidewalls relative to the bottom surface of the second trench 600 may be perpendicular, but are not limited thereto.

[0127] In one embodiment, the lower surface of the second trench 600 may be positioned at a lower level than the lower surface of the first trench 500. The lower surface of the second trench 600 may be positioned closer to the upper surface of the substrate 110 than the lower surface of the first trench 500. In another embodiment, the distance between the level of the lower surface of the second trench 600 and the level of the lower surface of the first conductivity type semiconductor layer 120 may be shorter than the distance between the level of the lower surface of the second trench 600 and the level of the upper surface of the first conductivity type semiconductor layer 120.

[0128] Next, as Figure 14As shown, a shielding pattern 139 can be formed around the bottom surface and sidewalls of the second trench 600. (Refer to...) Figure 14 The shielding pattern 139 can be formed from the bottom surface of the second trench 600 toward the first conductivity type semiconductor layer 120. The shielding pattern 139 can be formed from the two sidewalls of the second trench 600 toward the first conductivity type semiconductor layer 120.

[0129] In this embodiment, the shielding pattern 139 can be formed by an ion implantation process. For example, a p-type impurity can be implanted into the bottom surface and two sidewalls of the second trench 600 by an ion implantation process, thereby forming a shielding pattern 139 with a predetermined depth extending from the bottom surface and two sidewalls of the second trench 600 toward the first conductivity type semiconductor layer 120.

[0130] The shielding pattern 139 may comprise SiC. For example, the shielding pattern 139 may comprise 4H SiC. In an embodiment, the shielding pattern 139 may have a different conductivity type than the first conductivity type semiconductor layer 120. In an embodiment, the shielding pattern 139 may be doped at a relatively high concentration compared to the first conductivity type semiconductor layer 120. In an embodiment, the doping concentration of the shielding pattern 139 may be higher than the doping concentration of the second conductivity type doped layer 133. In an embodiment, the doping concentration of the shielding pattern 139 may be substantially the same as or lower than the doping concentration of the second conductivity type doped region 135, but is not limited thereto.

[0131] like Figure 15 As shown, an internal insulating pattern 143 can be formed to fill the interior of the second trench 600. The internal insulating pattern 143 can also be formed inside the first trench 500. The internal insulating pattern 143 can also be formed on the upper surface of the first conductivity type doped region 137, the upper surface of the second conductivity type doped region 135, and the upper surface of the first gate insulating layer 141. The internal insulating pattern 143 can contain an insulating material. The internal insulating pattern 143 can contain the same insulating material as the first gate insulating layer 141. For example, the internal insulating pattern 143 can contain silicon oxide (SiO), but is not limited thereto.

[0132] Next, as Figure 16 As shown, a gate electrode 150 can be formed in a portion of the interior of the first trench 500. First, an internal insulating pattern 143 is etched to fill a portion of the interior of the first trench 500. Then, a conductive material (e.g., impurity-doped polysilicon) is deposited on the etched portion to form the gate electrode 150. At this time, a second gate insulating layer 144 can be formed between the gate electrode 150 and the first gate insulating layer 141 (see...). Figure 2 ).

[0133] For example, the gate electrode 150 can be formed by depositing polysilicon over the entire upper surface of the semiconductor device according to the embodiment, and then removing the conductive material located above the area other than the etched area via an etch-back process. Alternatively, the gate electrode 150 can be formed by depositing conductive material over the entire upper surface of the semiconductor device according to the embodiment, and then removing the conductive material located above the level of the upper surfaces of the second conductivity type doped region 135 and the first conductivity type doped region 137 via a chemical mechanical polishing (CMP) process. In this case, the portion of the internal insulating pattern 143 located at a level higher than the upper surfaces of the second conductivity type doped region 135 and the first conductivity type doped region 137 can be removed together.

[0134] Next, as Figure 17 As shown, a capping layer 142 can be formed covering the upper surface of the gate electrode 150. First, a portion of the internal insulating pattern 143 located at a level higher than the upper surface of the gate electrode 150 can be removed by a chemical mechanical polishing process. Next, insulating material can be deposited on the upper surfaces of the gate electrode 150, the first gate insulating layer 141, the second conductivity type doped region 135, the first conductivity type doped region 137, and the internal insulating pattern 143, and then patterned to form the capping layer 142. The capping layer 142 can cover the upper surface of the gate electrode 150. The capping layer 142 can cover at least a portion of the first gate insulating layer 141, the first conductivity type doped region 137, and the internal insulating pattern 143 adjacent to the gate electrode 150.

[0135] The capping layer 142 may comprise an insulating material. For example, the capping layer 142 may comprise silicon oxide (SiO). However, it is not limited to this, and the material of the capping layer 142 can be changed in various ways. As another example, the capping layer 142 may comprise SiN, SiON, SiC, SiCN, or combinations thereof. The methods and materials used to form the capping layer 142 are not limited to this and can be modified in various ways.

[0136] Next, as Figure 18 As shown, a source electrode 173 can be formed. Specifically, conductive material can be deposited on the second conductivity type doped region 135, the first conductivity type doped region 137, the internal insulating pattern 143, and the capping layer 142 to form the source electrode 173. The source electrode 173 can be electrically insulated from the gate electrode 150 through the capping layer 142. The source electrode 173 can be in contact with at least a portion of the upper surface of the second conductivity type doped region 135, the first conductivity type doped region 137, and the internal insulating pattern 143.

[0137] Next, conductive material can be deposited on the second surface (i.e., the lower surface) of the substrate 110 to form the drain electrode 175 (see Figure 1The drain electrode 175 can contact the substrate 110.

[0138] Figures 19 to 27 This is a cross-sectional view illustrating the manufacturing process of a semiconductor device according to an embodiment. Specifically, Figures 19 to 27 It is used for illustration and reference. Figure 3 and Figure 4 A cross-sectional view of the manufacturing process of the described semiconductor device. In the following text, references will be omitted. Figures 10 to 18 The description of the manufacturing process is redundant, and the focus is placed on the differences.

[0139] like Figure 19 As shown, a second conductivity type doped layer 133, a first conductivity type doped region 137, and a second conductivity type doped region 135 can be sequentially formed on top of a first conductivity type semiconductor layer 120 positioned on a substrate 110.

[0140] First, a first conductivity type semiconductor layer 120 can be formed on the first surface (i.e., the upper surface) of the substrate 110 using an epitaxial growth method. The doping material of the first conductivity type semiconductor layer 120 can be the same as or different from the doping material of the substrate 110.

[0141] Next, a second conductivity type doped layer 133 can be formed in the upper region of the first conductivity type semiconductor layer 120. The second conductivity type doped layer 133 can be formed by an ion implantation process. The second conductivity type doped layer 133 can have a predetermined depth. At this time, the depth of the second conductivity type doped layer 133 can be determined by the number of implanted ions and / or the ion acceleration rate.

[0142] Next, ions can be implanted into the second conductivity type doped layer 133 to form a first conductivity type doped region 137. The first conductivity type doped region 137 can be formed within the second conductivity type doped layer 133 via an ion implantation process. The first conductivity type doped region 137 can be formed in at least a portion of the second conductivity type doped layer 133. For example, the first conductivity type doped region 137 can be formed to a predetermined depth from the upper surface of the second conductivity type doped layer 133.

[0143] Next, ions can be implanted into the second conductivity type doped layer 133 to further form the second conductivity type doped region 135. In an embodiment, the second conductivity type doped region 135 can be formed and positioned to one side of the first conductivity type doped region 137. The second conductivity type doped region 135 can be formed on the second conductivity type doped layer 133 to alternate with the first conductivity type doped region 137 along the first direction D1.

[0144] In one embodiment, the depth of the second conductivity type doped region 135 can be substantially the same as the depth of the first conductivity type doped region 137. At least a portion of the two side surfaces of the second conductivity type doped region 135 can be surrounded by the first conductivity type doped region 137.

[0145] like Figure 20 As shown, the second trench 600 can be formed by etching a portion of the first conductivity type semiconductor layer 120, a portion of the second conductivity type doped layer 133, a portion of the second conductivity type doped region 135, and a portion of the first conductivity type doped region 137.

[0146] First, a mask pattern including openings of a predetermined width can be formed on the first conductivity type doped region 137 and the second conductivity type doped region 135. At this time, the openings formed in the mask pattern can expose a portion of the first conductivity type doped region 137 and a portion of the second conductivity type doped region 135. Next, the second trench 600 can be formed by etching the first conductivity type doped region 137 and the second conductivity type doped region 135 exposed by the mask pattern, as well as portions of the underlying second conductivity type doped layer 133 and the first conductivity type semiconductor layer 120. The second trench 600 can be formed by a dry etching process such as, for example, RIE (reactive ion etching) or ICP (inductively coupled plasma), but is not limited thereto.

[0147] In one embodiment, the second trench 600 may be formed to a predetermined depth. The second trench 600 may be formed in an approximately U-shape in cross-section. The second trench 600 may include a bottom surface and two sidewalls extending from the bottom surface. The bottom surface of the second trench 600 may be defined by a first conductivity type semiconductor layer 120. One sidewall of the second trench 600 may be defined by the first conductivity type semiconductor layer 120, a second conductivity type doped layer 133, and a first conductivity type doped region 137. The other sidewall of the second trench 600, opposite to one sidewall, may be defined by the first conductivity type semiconductor layer 120, the second conductivity type doped layer 133, and a second conductivity type doped region 135.

[0148] Next, as Figure 21 As shown, a shielding pattern 139 can be formed around the bottom surface and sidewalls of the second trench 600. (Refer to...) Figure 21 The shielding pattern 139 can be formed from the bottom surface of the second trench 600 toward the first conductivity type semiconductor layer 120. The shielding pattern 139 can be formed from the two sidewalls of the second trench 600 toward the first conductivity type semiconductor layer 120, the second conductivity type doped layer 133 and / or the first conductivity type doped region 137.

[0149] In one embodiment, the shielding pattern 139 can be formed by an ion implantation process. In another embodiment, the shielding pattern 139 can be doped at a relatively high concentration compared to the first conductivity type semiconductor layer 120. In yet another embodiment, the doping concentration of the shielding pattern 139 can be higher than the doping concentration of the second conductivity type doped layer 133. In yet another embodiment, the doping concentration of the shielding pattern 139 can be substantially equal to or lower than the doping concentration of the second conductivity type doped region 135, but is not limited thereto.

[0150] like Figure 22 As shown, a first internal insulating pattern 143a can be formed to fill the interior of the second trench 600. The first internal insulating pattern 143a can also be formed on the upper surface of the first conductivity type doped region 137, the upper surface of the second conductivity type doped region 135, and the upper surface of the shielding pattern 139. The first internal insulating pattern 143a can contain an insulating material. The first internal insulating pattern 143a can contain the same insulating material as the first gate insulating layer 141. For example, the first internal insulating pattern 143a can contain silicon oxide (SiO), but is not limited thereto.

[0151] Next, as Figure 23 As shown, the first trench 500 can be formed by etching a portion of the first conductivity type semiconductor layer 120, a portion of the second conductivity type doped layer 133, a portion of the first conductivity type doped region 137, a portion of the shielding pattern 139, and a portion of the first internal insulating pattern 143a. In an embodiment, the first trench 500 can be formed on one side of the second trench 600 so as to partially overlap with the second trench 600. For example, the first trench 500 can be formed on one side of the second trench 600 so as to partially overlap with the second trench 600 in the first direction D1.

[0152] To form the first trench 500, a photolithography process can be performed once, twice, or more. For example, a mask pattern including openings can first be formed on the upper surface of the first internal insulating pattern 143a, exposing the area in which the first trench 500 is to be formed. Subsequently, the first trench 500 can be formed by etching a portion of the first internal insulating pattern 143a exposed by the mask pattern, as well as portions of the underlying first conductivity type doped region 137, second conductivity type doped layer 133, and shielding pattern 139. In embodiments, the process of etching the first internal insulating pattern 143a and the process of etching the first conductivity type doped region 137, second conductivity type doped layer 133, shielding pattern 139, and first conductivity type semiconductor layer 120 can be performed sequentially or simultaneously. The first trench 500 can be formed by dry etching processes such as reactive ion etching (RIE) or inductively coupled plasma (ICP), but is not limited to these.

[0153] In one embodiment, the first trench 500 may be formed to a predetermined depth. The first trench 500 may have a substantially U-shaped profile in cross-section. The first trench 500 may include a bottom surface and two sidewalls extending from the bottom surface. The bottom surface of the first trench 500 may be defined by a first conductivity type semiconductor layer 120, a shielding pattern 139, and a first internal insulating pattern 143a. One sidewall of the first trench 500 may be defined by the first conductivity type semiconductor layer 120, a second conductivity type doped layer 133, a first conductivity type doped region 137, and the first internal insulating pattern 143a. The other sidewall of the first trench 500, opposite to one sidewall, may be defined by the first internal insulating pattern 143a.

[0154] Reference Figure 23 The first groove 500 may have a rectangular shape in the cross section and a uniform width in the first direction D1.

[0155] In another embodiment, with Figure 23 As shown, at least one of the sidewalls of the first trench 500 may be inclined. For example, the width of the first trench 500 may gradually decrease from top to bottom in the first direction D1. In one embodiment, one sidewall of the first trench 500, whose entire area is defined by the first internal insulating pattern 143a, may extend in an inclined direction between the first direction D1 and the second direction D2. In another embodiment, the other sidewall of the first trench 500, defined by the first conductivity type semiconductor layer 120, the second conductivity type doped layer 133, and the first conductivity type doped region 137, may extend in a direction parallel to the second direction D2. This may be due to the difference in etch selectivity between the silicon carbide (SiC) contained in the first conductivity type doped region 137, the second conductivity type doped layer 133, the first conductivity type semiconductor layer 120, and the shielding pattern 139, and the silicon oxide (SiO) contained in the first internal insulating pattern 143a, during the process of forming the first trench 500. In this case, if the gate electrode 150 is formed directly inside the first trench 500 without the process of forming the second internal insulating pattern 143b, which will be described later, a pattern as shown in the reference can be formed. Figure 8 The gate electrode 150 is described in shape.

[0156] Next, as Figure 24As shown, a first gate insulating layer 141 can be formed along at least a portion of the bottom surface and one sidewall of the first trench 500. In an embodiment, the first gate insulating layer 141 may be formed only on the first conductivity type doped region 137, the second conductivity type doped layer 133, the first conductivity type semiconductor layer 120, and the shielding pattern 139 within the entire area of ​​the bottom surface and inner sidewall of the first trench 500. This can be attributed to the characteristics of the process in which the first gate insulating layer 141 is formed by an oxidation process. For example, the process of forming the first gate insulating layer 141 can be performed by a dry oxidation process. However, it is not limited to this, and the process of forming the first gate insulating layer 141 can also be performed by a wet oxidation process.

[0157] like Figure 25 As shown, a gate electrode 150 can be formed in some regions inside the first trench 500. First, a second internal insulating pattern 143b can be formed to fill the interior of the first trench 500. The second internal insulating pattern 143b can be formed on the entire upper surface of the semiconductor device according to the embodiment. For example, as... Figure 25 As shown, the second internal insulation pattern 143b can also be formed on the upper surface of the first internal insulation pattern 143a located outside the first trench 500.

[0158] Next, after etching a portion of the second internal insulating pattern 143b, a conductive material (e.g., impurity-doped polysilicon) can be deposited on the etched portion to form the gate electrode 150. At this time, a second gate insulating layer 144 can be formed between the gate electrode 150 and the first gate insulating layer 141 (see...). Figure 4 ).

[0159] The gate electrode 150 can be formed, for example, by depositing polysilicon over the entire upper surface of the semiconductor device according to the embodiment, and then removing the conductive material located over the area other than the etched area via an etch-back process.

[0160] In another embodiment, the gate electrode 150 can be formed by depositing a conductive material over the entire upper surface of the semiconductor device according to the embodiment, and then removing the conductive material located above the upper surfaces of the second conductivity type doped region 135 and the first conductivity type doped region 137 via a chemical mechanical polishing (CMP) process. At this time, portions of the first internal insulating pattern 143a and the second internal insulating pattern 143b located at a level higher than the upper surfaces of the second conductivity type doped region 135 and the first conductivity type doped region 137 can be removed together.

[0161] like Figure 26As shown, a capping layer 142 can be formed covering the upper surface of the gate electrode 150. First, portions of the first internal insulating pattern 143a and the second internal insulating pattern 143b positioned above the upper surface of the gate electrode 150 can be removed by a chemical mechanical polishing process. Next, insulating material can be deposited on the upper surfaces of the gate electrode 150, the first gate insulating layer 141, the second conductivity type doped region 135, the first conductivity type doped region 137, and the first and second internal insulating patterns 143a and 143b, and then patterned to form the capping layer 142. The capping layer 142 can cover the upper surface of the gate electrode 150. The capping layer 142 can cover at least a portion of the first gate insulating layer 141, the first conductivity type doped region 137, and the second internal insulating pattern 143b adjacent to the gate electrode 150.

[0162] Next, as Figure 27 As shown, a source electrode 173 can be formed. Specifically, conductive material can be deposited on the second conductivity type doped region 135, the first conductivity type doped region 137, the internal insulating pattern 143, and the capping layer 142 to form the source electrode 173. Next, conductive material can be deposited on the second surface (i.e., the lower surface) of the substrate 110 to form the drain electrode 175 (see Figure 143). Figure 3 The drain electrode 175 can contact the substrate 110.

[0163] A method for manufacturing a semiconductor device according to an embodiment includes: forming a first conductivity type semiconductor layer on a first surface of a substrate; forming a second conductivity type doped layer on the first conductivity type semiconductor layer; forming a first conductivity type doped region on the second conductivity type doped layer; forming a first trench by etching portions of the first conductivity type doped region, the second conductivity type doped layer, and the first conductivity type semiconductor layer; forming a first gate insulating layer on a bottom surface and a side surface of the first trench; forming a second trench located on one side of the first trench and overlapping the first trench; forming a shielding pattern around the second trench; forming a gate electrode in the first trench including a first side surface and a second side surface opposite to the first side surface; forming a source electrode on the first conductivity type doped region; and forming a drain electrode on a second surface of the substrate. The first gate insulating layer is positioned on a first side surface of the gate electrode and a lower surface of the gate electrode, the second conductivity type doped layer covers at least a portion of the side surface of the first gate insulating layer, and the first conductivity type doped region covers at least another portion of the side surface of the first gate insulating layer.

[0164] The method for manufacturing a semiconductor device according to an embodiment further includes filling an internal insulating pattern within a second trench. The shielding pattern surrounds at least a portion of the side and bottom surfaces of the internal insulating pattern.

[0165] In a method for manufacturing a semiconductor device according to an embodiment, forming a second trench includes forming a second trench such that the bottom surface of the second trench is positioned closer to the upper surface of the substrate compared to the bottom surface of the first trench.

[0166] In a method for manufacturing a semiconductor device according to an embodiment, forming a first gate insulating layer includes: forming a first gate insulating layer on the bottom surface and two side surfaces of a first trench, and removing the first gate insulating layer formed on one of the two side surfaces of the first trench during the formation of a second trench.

[0167] In a method for manufacturing a semiconductor device according to an embodiment, a shielding pattern covers a portion of the lower surface of a first gate insulating layer positioned on the bottom surface of a first trench.

[0168] In a method for manufacturing a semiconductor device according to an embodiment, forming a gate electrode includes forming a gate electrode such that a first side of the gate electrode and a lower surface of the gate electrode are in contact with a first gate insulating layer.

[0169] The method for manufacturing a semiconductor device according to an embodiment further includes: forming a dummy semiconductor pattern inside a second trench.

[0170] In a method for manufacturing a semiconductor device according to an embodiment, forming a dummy semiconductor pattern includes: removing a portion of an internal insulating pattern located inside a second trench, and filling the removed portion of the internal insulating pattern with a conductive material.

[0171] In the method for manufacturing a semiconductor device according to an embodiment, the dummy semiconductor pattern includes polycrystalline silicon doped with impurities.

[0172] In the method for manufacturing a semiconductor device according to an embodiment, a shielding pattern is doped with a p-type impurity.

[0173] Although the embodiments of this disclosure have been described in detail above, the scope of this disclosure is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of this disclosure as defined in the claims also fall within the scope of this disclosure.

[0174] Cross-references to related applications

[0175] This application claims priority and benefit to Korean Patent Application No. 10-2025-0018308, filed with the Korean Intellectual Property Office on February 12, 2025, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: Substrate; A semiconductor layer of a first conductivity type is disposed on a first surface of the substrate; A first trench and a second trench overlapping the first trench, the second trench being located on one side of the first trench, and the first trench and the second trench each penetrating the first conductivity type semiconductor layer; A gate electrode is located in the first trench and includes a first side surface and a second side surface opposite to the first side surface; A first gate insulating layer is provided on the first side surface and the lower surface of the gate electrode; A second conductivity type doped layer is placed on the first conductivity type semiconductor layer and covers at least a portion of the side surface of the first gate insulating layer; A first conductivity type doped region is located on the second conductivity type doped layer and covers at least another portion of the side surface of the first gate insulating layer; The source electrode is located on the doped region of the first conductivity type; Drain electrode, on the second surface of the substrate; as well as A shielding pattern is applied around the second trench.

2. The semiconductor device according to claim 1, in, The bottom surface of the second trench is positioned closer to the drain electrode than the bottom surface of the first trench.

3. The semiconductor device according to claim 1, in, The first gate insulating layer is on the bottom surface and sidewalls of the first trench, and the sidewalls of the first trench face the first side surface of the gate electrode.

4. The semiconductor device according to claim 3, in, The shielding pattern covers a portion of the lower surface of the first gate insulating layer on the bottom surface of the first trench.

5. The semiconductor device according to claim 1, in, Of the first side surface and the second side surface of the gate electrode, the first gate insulating layer is disposed only on the first side surface of the gate electrode.

6. The semiconductor device according to claim 1, further comprising: The internal insulation pattern in the second trench The shielding pattern surrounds at least a portion of the side surface and the lower surface of the inner insulating pattern.

7. The semiconductor device according to claim 6, further comprising: A second gate insulating layer between the gate electrode and the first gate insulating layer.

8. The semiconductor device according to claim 7, in, The second gate insulating layer includes a portion between the second side surface of the gate electrode and the internal insulating pattern.

9. The semiconductor device according to claim 7, in, The internal insulating pattern and the second gate insulating layer contain the same insulating material.

10. The semiconductor device according to claim 7, in, The first gate insulating layer and the second gate insulating layer contain different insulating materials.

11. The semiconductor device according to claim 6, in, The internal insulating pattern comprises silicon oxide.

12. The semiconductor device according to claim 1, in, The first side surface and the lower surface of the gate electrode are in contact with the first gate insulating layer.

13. The semiconductor device according to claim 1, further comprising: A dummy semiconductor pattern in the second trench.

14. The semiconductor device of claim 13, further comprising: The internal insulation pattern in the second trench The internal insulating pattern surrounds the side and bottom surfaces of the dummy semiconductor pattern.

15. The semiconductor device according to claim 1, in, The shielding pattern is doped with p-type impurities.

16. A semiconductor device, comprising: Substrate; A semiconductor layer of a first conductivity type is disposed on a first surface of the substrate; A first trench and a second trench overlapping the first trench, the second trench being located on one side of the first trench, and the first trench and the second trench each penetrating the first conductivity type semiconductor layer; A gate electrode is located in the first trench and includes a first side surface and a second side surface opposite to the first side surface; A first gate insulating layer is provided on the first side surface and the lower surface of the gate electrode; A second conductivity type doped layer is placed on the first conductivity type semiconductor layer and covers at least a portion of the side surface of the first gate insulating layer; A first conductivity type doped region is located on the second conductivity type doped layer and covers at least another portion of the side surface of the first gate insulating layer; The source electrode is located on the doped region of the first conductivity type; Drain electrode, on the second surface of the substrate; Internal insulating pattern, in the second trench; Wherein, the bottom surface of the second trench is positioned closer to the drain electrode than the bottom surface of the first trench; and The internal insulating pattern comprises silicon oxide.

17. The semiconductor device of claim 16, further comprising: A shielding pattern surrounding at least a portion of the side surface and the lower surface of the internal insulating pattern.

18. The semiconductor device of claim 16, further comprising: A second gate insulating layer is located between the gate electrode and the first gate insulating layer.

19. The semiconductor device of claim 16, further comprising: A dummy semiconductor pattern in the second trench.

20. A semiconductor device, comprising: Substrate; A semiconductor layer of a first conductivity type is disposed on a first surface of the substrate; A first trench and a second trench overlapping the first trench, the second trench being located on one side of the first trench, and the first trench and the second trench each penetrating the first conductivity type semiconductor layer; A gate electrode is located in the first trench and includes a first side surface and a second side surface opposite to the first side surface; A first gate insulating layer is conformally disposed on the bottom surface of the first trench and on the side surface of the first trench facing the first side surface of the gate electrode. The internal insulating pattern, in the second trench, has an upper surface at the same level as the upper surface of the gate electrode; A capping layer that covers the upper surface of the gate electrode and the upper surface of the internal insulating pattern; A second conductivity type doped layer is placed on the first conductivity type semiconductor layer and covers at least a portion of the side surface of the first gate insulating layer and a portion of the side surface of the internal insulating pattern. A first conductivity type doped region is located on the second conductivity type doped layer and covers at least another portion of the side surface of the first gate insulating layer; A second conductivity type doped region, on the second conductivity type doped layer and covering at least a portion of the side surface of the internal insulating pattern; The source electrode covers at least a portion of the upper surface of the first conductivity type doped region, the upper surface of the second conductivity type doped region, the upper surface of the internal insulating pattern, and the upper and side surfaces of the capping layer; Drain electrode, on the second surface of the substrate; as well as A shielding pattern surrounding at least another portion of the side surface and the lower surface of the inner insulating pattern. Wherein, at least a portion of the lower surface of the first gate insulating layer and the lower surface of the second conductivity type doped region are in contact with the shielding pattern, and The internal insulating pattern comprises silicon oxide.

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