Silicon carbide MOSFET structure and manufacturing method

Abstract

This specification provides embodiments of a silicon carbide MOSFET structure and its manufacturing method. By introducing an anti-parallel SBD region through the Schottky contact formed between the source metal and the MOSFET base region in the original scheme, a mutually separated P-type base region structure is set. The normally closed device is formed by the overlapping of the PN junction depletion layers of the left and right P+ injection regions and the N+ region between the P+ injection regions. Furthermore, the source metal electrode forms an ohmic contact with the semiconductor material, replacing the Schottky contact formed by the metal electrode and the epitaxial layer in the original parallel SBD or JBS Schottky barrier diode. This forms a field-controlled diode whose barrier height is only modulated by the PN junction depletion layers of the P+ injection region and the N+ region. By controlling the turn-on of this field-controlled diode, it has a lower diode forward voltage drop than the SBD or JBS diode, and can achieve a diode forward voltage drop of less than 1.0V.

Description

Technical Field

[0001] The embodiments in this specification relate to the field of semiconductor technology, and in particular to silicon carbide MOSFET structures. Background Technology

[0002] Silicon carbide (SiC), a third-generation semiconductor material, possesses characteristics such as a wide bandgap, high breakdown field strength, high thermal conductivity, high saturation electron mobility, and stable physicochemical properties, making it suitable for high-temperature, high-frequency, high-power, and extreme environments. SiC exhibits a wider bandgap and a higher critical breakdown field strength. Compared to silicon power devices under the same conditions, SiC devices have a voltage withstand capability approximately 10 times that of silicon. Furthermore, SiC devices have a higher electron saturation velocity, lower forward resistance, and lower power loss, making them suitable for high-current, high-power applications and reducing the requirements for heat dissipation equipment. Compared to other third-generation semiconductors (such as GaN), SiC can be more easily oxidized to form silicon dioxide through thermal oxidation. SiC possesses unique physical, chemical, and electrical properties, making it a semiconductor material with great development potential in extreme applications such as high temperature, high frequency, high power, and radiation resistance. SiC power MOS devices offer a series of advantages, including high input impedance, fast switching speed, high operating frequency, and high voltage withstand capability, and have been widely used in switching power supplies, high-frequency circuits, and power amplifiers.

[0003] MOSFETs made of silicon carbide (Si) can withstand higher voltages and switch faster than Si devices. For conventional Si MOSFETs, the body diode turn-on voltage is only about 0.7V, so they are commonly used as freewheeling channels under reverse bias. However, SiC has a wider bandgap, and the body diode turn-on voltage of SiC MOSFETs is too high, approximately 2.7V~4.0V, making it difficult to provide freewheeling protection for the MOSFET under reverse bias. In existing technologies, SiC MOSFETs are typically connected in anti-parallel with a Schottky diode (SBD) or a JBS diode. Because the Schottky diode's turn-on voltage is much lower than the body diode's, it can turn on with a relatively low voltage drop when the SiC MOSFET is in reverse, achieving a forward voltage drop of about 1.5V. However, due to the inherent characteristics of the Schottky barrier, there are problems such as degraded reverse blocking capability and excessive leakage current. Furthermore, the integrated parallel SBD or JBS diode solution is no longer sufficient to further reduce the forward voltage drop of the SiC MOSFET's body diode due to the Schottky barrier.

[0004] Therefore, a better solution is urgently needed. Summary of the Invention

[0005] In view of this, embodiments of this specification provide a silicon carbide MOSFET structure to address the technical deficiencies existing in the prior art.

[0006] According to a first aspect of the embodiments of this specification, a silicon carbide MOSFET structure is provided, comprising: silicon carbide substrate; Epitaxial layer, which is disposed on a silicon carbide substrate; P-type base regions are located in the epitaxial layer and are separated from each other; The N-type source region is located within the P-type base region; P+ type highly doped regions are disposed in the epitaxial layer between the P-type base regions, and a spacing is formed between the P+ type highly doped regions; The N-type JFET region is located in the epitaxial layer between the P+ type heavily doped regions. Gate oxide and gate polysilicon are disposed on the epitaxial layer; A dielectric oxide layer is disposed on the gate oxide layer and the gate polysilicon. The source metal electrode forms an ohmic contact with the semiconductor material. And a drain metal electrode, which is disposed below the silicon carbide substrate; A field-controlled diode in which the barrier height between the source metal electrode and the drain metal electrode is modulated by the depletion layer of the PN junction between the P+ type heavily doped region and the N type JFET region.

[0007] In one possible implementation, the N-type JFET region includes a first N-type JFET region and a second N-type JFET region; The first N-type JFET region is disposed in the epitaxial layer between the P+ type highly doped base regions; The second N-type JFET region is located on the wafer surface between the P+ type highly doped regions, and the doping concentration of the second N-type JFET region is higher than that of the first N-type JFET region.

[0008] In one possible implementation, the junction depth of the first N-type JFET region is 0.9~1.2um; The junction depth of the second N-type JFET region is 0.15~0.25um.

[0009] In one possible implementation, the spacing between the P+ type highly doped regions is 0.2~0.4 μm.

[0010] In one possible implementation, the junction depth of the P-type base region is 0.7~1.0 μm; The junction depth of the N-type source region is 0.2~0.3 μm; The junction depth of the P+ type highly doped region is 0.7~1.0 μm.

[0011] In one possible implementation, the doping concentration of the epitaxial layer is 2.0E15~1E16 cm⁻¹. - ³.

[0012] According to a second aspect of the embodiments of this specification, a method for manufacturing a silicon carbide MOSFET structure is provided, comprising: An epitaxial layer is formed on a silicon carbide substrate; A base region implantation shielding layer is formed on the epitaxial layer, and mutually separated P-type base regions are formed by ion implantation; The base region implantation shielding layer is oxidized to thicken it and form an isolation layer, and an N-type source region is formed by ion implantation. A P+ region implantation shielding layer is formed, and a P+ type highly doped region is formed by ion implantation, with spacing between the P+ type highly doped regions; Ion implantation is performed on the unit cell region to form an N-type JFET region located between the P+ type heavily doped regions; Perform annealing activation; Forming the gate oxide layer and the gate polysilicon; Deposit a dielectric oxide layer and form metal electrode contact holes; A metal layer is deposited and annealed to form a source ohmic contact metal layer, so that the source metal electrode and the semiconductor material form an ohmic contact. A drain metal electrode is formed on the lower surface of a silicon carbide substrate.

[0013] In one possible implementation, an N-type JFET region is formed, including: The first N-type JFET region is formed by ion implantation, with a junction depth of 0.9~1.2um; An implantation shielding layer is formed, and a second N-type JFET region is formed on the wafer surface between the P+ type highly doped regions through ion implantation. The junction depth is 0.15~0.25um, and the doping concentration of the second N-type JFET region is higher than that of the first N-type JFET region.

[0014] In one possible implementation, when forming P+ type highly doped regions, the spacing between the P+ type highly doped regions is 0.2~0.4 μm.

[0015] In one possible implementation, the source ohmic contact metal layer is formed, including: A Ni metal layer with a thickness of 100um-300nm is deposited and annealed at 900-1100 degrees Celsius for 2-3 minutes. Then, an AlCu alloy layer with a thickness of 3-6um is formed by metal deposition.

[0016] This specification provides embodiments of a silicon carbide MOSFET structure and its manufacturing method. By introducing an anti-parallel SBD region through a Schottky contact between the source metal and the MOSFET base region in the original design, a mutually separated P-type base region structure is set. The overlapping of the PN junction depletion layers of the left and right P+ injection regions and the N+ region between the P+ injection regions constitutes a normally closed device. Furthermore, an ohmic contact is formed between the source metal electrode and the semiconductor material, replacing the Schottky contact formed by the metal electrode and the epitaxial layer in the original parallel SBD or JBS Schottky barrier diode. This results in a field-controlled diode whose barrier height is modulated only by the P+ injection region and the N+ region PN junction depletion layer. Like SBD or JBS diodes, this field-controlled diode is a unipolar device. While achieving high reverse breakdown voltage characteristics similar to PiN diodes, it eliminates the limitation of the Schottky barrier height on the diode's forward conduction voltage drop. By controlling the contraction of the depletion layer using the drain-source voltage, the field-controlled diode is controlled to turn on, resulting in a lower diode forward voltage drop than SBD or JBS diodes, achieving a forward voltage drop of less than 1.0V. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a silicon carbide MOSFET structure provided in one embodiment of this specification; Figure 2 This is a flowchart illustrating a method for manufacturing a silicon carbide MOSFET structure according to one embodiment of this specification; Figure 3 This is a schematic diagram of a substrate for a silicon carbide MOSFET structure provided in one embodiment of this specification; Figure 4 This is a schematic diagram of the shielding polysilicon layer of a silicon carbide MOSFET structure provided in one embodiment of this specification; Figure 5 This is a schematic diagram of the N-type source region of a silicon carbide MOSFET structure provided in one embodiment of this specification; Figure 6 This is a schematic diagram of a P+ type highly doped region of a silicon carbide MOSFET structure provided in one embodiment of this specification; Figure 7 This is a schematic diagram of the JFET1 region of a silicon carbide MOSFET structure provided in one embodiment of this specification; Figure 8 This is a schematic diagram of the JFET2 region of a silicon carbide MOSFET structure provided in one embodiment of this specification; Figure 9 This is a schematic diagram of the carbon film of a silicon carbide MOSFET structure provided in one embodiment of this specification; Figure 10This is a schematic diagram of the gate oxide layer of a silicon carbide MOSFET structure provided in one embodiment of this specification; Figure 11 This is a schematic diagram of the front metal electrode of a silicon carbide MOSFET structure provided in one embodiment of this specification; Figure 12 This is a schematic diagram of the drain metal electrode of a silicon carbide MOSFET structure provided in one embodiment of this specification; Figure 13a This is a schematic diagram of the breakdown characteristic curve of a silicon carbide MOSFET structure provided in one embodiment of this specification; Figure 13b This is a schematic diagram of the depletion region distribution of the PN junction of a field-controlled diode in a silicon carbide MOSFET structure under zero bias, provided in one embodiment of this specification. Figure 13c This is a schematic diagram of the PN junction potential distribution of a field-controlled diode with zero bias in a silicon carbide MOSFET structure according to one embodiment of this specification; Figure 14a This is a schematic diagram of the depletion region distribution of the PN junction of a field-controlled diode under forward bias voltage according to an embodiment of this specification; Figure 14b This is a schematic diagram of the PN junction potential distribution of a field-controlled diode under forward bias voltage according to an embodiment of this specification of a silicon carbide MOSFET structure; Figure 15a This is a schematic diagram illustrating the simulated conduction characteristics of a silicon carbide MOSFET structure according to one embodiment of this specification; Figure 15b This is a schematic diagram of the simulated potential distribution of a silicon carbide MOSFET structure provided in one embodiment of this specification. Detailed Implementation

[0018] Many specific details are set forth in the following description to provide a full understanding of this specification. However, this specification can be implemented in many other ways than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this specification. Therefore, this specification is not limited to the specific implementations disclosed below.

[0019] The terminology used in one or more embodiments of this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the one or more embodiments of this specification. The singular forms “a” and “the” as used in one or more embodiments of this specification and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in one or more embodiments of this specification refers to and includes any or all possible combinations of one or more associated listed items.

[0020] It should be understood that although the terms first, second, etc., may be used to describe various information in one or more embodiments of this specification, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first may also be referred to as second without departing from the scope of one or more embodiments of this specification, and similarly, second may also be referred to as first. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to a determination."

[0021] This specification provides a silicon carbide MOSFET structure, which is described in detail in the following embodiments.

[0022] See Figure 1 , Figure 1 A schematic diagram of a silicon carbide MOSFET structure provided according to one embodiment of this specification is shown. Specifically, it includes: a silicon carbide substrate; an epitaxial layer disposed on the silicon carbide substrate; a P-type base region disposed in the epitaxial layer and separated from each other; an N-type source region disposed within the P-type base region; a P+ type heavily doped region disposed in the epitaxial layer between the P-type base regions and spaced apart; an N-type JFET region disposed in the epitaxial layer between the P+ type heavily doped regions; a gate oxide layer and a gate polysilicon layer disposed on the epitaxial layer; a dielectric oxide layer disposed on the gate oxide layer and the gate polysilicon layer; a source metal electrode forming an ohmic contact with the semiconductor material; and a drain metal electrode disposed below the silicon carbide substrate; a field-controlled diode formed between the source metal electrode and the drain metal electrode, the barrier height of which is modulated by the depletion layer of the PN junction between the P+ type heavily doped region and the N-type JFET region.

[0023] In this context, "silicon carbide substrate" refers to a substrate made of single-crystal silicon carbide material, used to support the epitaxial layer and device structure formed thereon. "Epitaxial layer" refers to a thin semiconductor layer formed on the substrate through epitaxial growth, serving as the drift region of the device. "P-type base region" refers to a P-type doped region formed in the epitaxial layer through ion implantation, used to form the channel region of a MOSFET. "N-type source region" refers to a region formed within the P-type base region through high-concentration N-type ion implantation, used to provide charge carriers. "P+ type highly doped region" refers to a region formed in the epitaxial layer between P-type base regions through high-concentration P-type ion implantation, used to form a depletion layer under reverse bias. "N-type JFET region" refers to an N-type doped region formed in the epitaxial layer between the P+ type highly doped regions, serving as the conductive channel of a field-controlled diode. "Gate oxide layer" refers to an insulating dielectric layer formed above the channel region, used to isolate the gate from the channel. "Gate polysilicon" refers to polysilicon material disposed on the gate oxide layer, used to form the gate electrode. The dielectric oxide layer can refer to the insulating layer covering the gate polysilicon, used to isolate the gate and source metals. The source metal electrode can refer to the metal layer forming an ohmic contact with the source region and the P-type base region, used to lead out the source. The drain metal electrode can refer to the metal layer disposed on the lower surface of the substrate, used to lead out the drain. An ohmic contact can refer to a low-resistance, non-rectified electrical contact between a metal and a semiconductor. A field-controlled diode can refer to a diode structure in which the forward voltage drop is modulated by the width of the PN junction depletion layer, and its metal-semiconductor contact is an ohmic contact rather than a Schottky contact.

[0024] The present application will be further described below through a detailed embodiment: This embodiment provides a silicon carbide MOSFET structure, specifically including a silicon carbide substrate, which is an N+ type silicon carbide monocrystalline wafer serving as the conductive path for the drain. An N-type epitaxial layer is grown on the upper surface of the silicon carbide substrate. This epitaxial layer serves as the drift region of the device, and its doping concentration is designed to balance on-resistance and breakdown voltage. Two separate P-type base regions are formed in the epitaxial layer through ion implantation. Each P-type base region serves as the channel region of the MOSFET, used to control on / off states. A high concentration of N-type impurities is further implanted into each P-type base region to form an N-type source region, used to provide electrons during conduction. Two highly doped P+ type regions are formed in the epitaxial layer between the two separate P-type base regions through ion implantation, with a certain spacing between them. An N-type JFET region is formed in the epitaxial layer between the two highly doped P+ type regions through ion implantation. This region serves as the conductive channel for the field-controlled diode. A gate oxide layer and a gate polysilicon layer are sequentially formed on the upper surface of the epitaxial layer. The gate oxide layer covers the channel region of the P-type base region, and the gate polysilicon layer is disposed on the gate oxide layer to apply a gate voltage to control the channel conduction. A dielectric oxide layer is deposited above the gate polysilicon layer to achieve electrical isolation between the gate and the source. Contact holes are formed in the dielectric oxide layer through photolithography and etching processes, and metal is deposited at the contact holes to form the source metal electrode. This source metal electrode forms an ohmic contact with the N-type source region, the P-type base region, and the P+-type heavily doped region simultaneously. Therefore, the contact between the source metal electrode and the semiconductor material is an ohmic contact rather than a Schottky contact. Metal is evaporated on the lower surface of the silicon carbide substrate to form the drain metal electrode. In this structure, the diode formed between the source metal electrode and the drain metal electrode is a field-controlled diode. Its barrier height during forward conduction is not determined by the metal-semiconductor Schottky barrier, but is modulated by the depletion layer of the PN junction formed between the P+-type heavily doped region and the N-type JFET region.

[0025] The beneficial effects of one of the embodiments in this specification include at least the following: by setting mutually separated P-type base region structures and forming N-type JFET regions between P+ type highly doped regions, while forming an ohmic contact between the source metal electrode and the semiconductor material, replacing the Schottky contact in traditional integrated SBD or JBS diodes, the diode barrier height formed between the source metal electrode and the drain metal electrode is only modulated by the PN junction depletion layer, thereby eliminating the limitation of the Schottky barrier on the forward conduction voltage drop and achieving a lower diode forward conduction voltage drop.

[0026] In one possible implementation, the N-type JFET region includes a first N-type JFET region and a second N-type JFET region; the first N-type JFET region is disposed in the epitaxial layer between the P+ type heavily doped regions; the second N-type JFET region is disposed on the wafer surface between the P+ type heavily doped regions, and the doping concentration of the second N-type JFET region is higher than that of the first N-type JFET region.

[0027] The first N-type JFET region can refer to a deeper N-type doped region located between the P+ type highly doped regions, used to withstand high voltage during reverse bias. The second N-type JFET region can refer to a highly doped N-type region located between the P+ type highly doped regions and close to the wafer surface, used to reduce contact resistance during forward conduction. The wafer surface can refer to the upper surface of the wafer after the aforementioned process steps are completed, i.e., the upper surface of the epitaxial layer.

[0028] Based on the aforementioned silicon carbide MOSFET structure, this embodiment further defines the N-type JFET region. Specifically, after forming the P+ type heavily doped region, a first N-type JFET region is formed in the epitaxial layer between the P+ type heavily doped regions through a high-energy ion implantation. This region has a relatively deep junction, which is used to extend the PN junction depletion layer formed with the adjacent P+ type heavily doped region into the N-type drift region to bear the reverse voltage when the device is turned off and withstands a high drain-source voltage. Subsequently, a second N-type JFET region is formed on the wafer surface between the P+ type heavily doped regions through a second ion implantation. The energy of this second implantation is lower, so that the second N-type JFET region is located in the near-surface region of the wafer, and its doping concentration is set to be higher than that of the first N-type JFET region. This setting allows the second N-type JFET region to serve as the surface part of the conductive channel of the field-controlled diode, which can effectively reduce the contact resistance between the source metal electrode and the conductive channel, thereby further reducing the forward voltage drop of the diode.

[0029] By setting the N-type JFET region as a two-layer structure with different depths and doping concentrations, the device is guaranteed to have sufficient withstand voltage when reverse biased, and the forward conduction resistance of the diode is reduced through the highly doped surface region, thus further optimizing the forward conduction characteristics of the device.

[0030] In one possible implementation, the junction depth of the first N-type JFET region is 0.9~1.2um; the junction depth of the second N-type JFET region is 0.15~0.25um.

[0031] Based on the aforementioned silicon carbide MOSFET structure, this embodiment optimizes and limits the junction depth of the first N-type JFET region and the second N-type JFET region. During fabrication, by controlling the ion implantation energy, the first N-type JFET region is implanted into a relatively deep location within the epitaxial layer, with its junction depth controlled between 0.9 and 1.2 micrometers. This depth allows the depletion layer extending from the P+ type heavily doped region to fully overlap with the first N-type JFET region when the device is turned off, effectively pinching off the conductive channel and achieving normally closed characteristics. Simultaneously, by controlling the energy of the second ion implantation, the second N-type JFET region is confined to a very shallow region near the wafer surface, with its junction depth controlled between 0.15 and 0.25 micrometers. This shallow junction depth design allows the second N-type JFET region to form a good low-resistance contact with the subsequently formed source ohmic contact metal layer, while not adversely affecting the breakdown voltage capability of the underlying first N-type JFET region. Through this layered junction depth design, a good balance between breakdown voltage and on-resistance is achieved.

[0032] By setting the junction depth of the first N-type JFET region to 0.9 to 1.2 micrometers, effective expansion of the depletion layer and reliable pinch-off of the channel are ensured during reverse bias. By setting the junction depth of the second N-type JFET region to 0.15 to 0.25 micrometers, low-resistance ohmic contact between the source metal and the conductive channel is achieved, thereby effectively reducing the forward conduction voltage drop while ensuring the device's withstand voltage capability.

[0033] In one possible implementation, the spacing between the P+ type highly doped regions is 0.2~0.4 μm.

[0034] The spacing between P+ type highly doped regions refers to the horizontal distance between two adjacent P+ type highly doped regions, and this spacing determines the width of the conductive channel of the field-controlled diode.

[0035] Based on the aforementioned silicon carbide MOSFET structure, this embodiment optimizes and limits the spacing between the P+ type highly doped regions. During the formation of the P+ type highly doped regions, a precise spacing is maintained between the two P+ type highly doped regions by controlling the pattern size on the photomask and the ion implantation shielding window. This spacing is set to 0.2 to 0.4 micrometers. This spacing setting is crucial: if the spacing is too large, the PN junction depletion layer formed by the two P+ type highly doped regions and the N-type JFET region under zero bias cannot completely overlap, and the channel cannot be effectively pinched off, causing the field-controlled diode to be in a conducting state without an applied voltage, failing to achieve its normally closed function; if the spacing is too small, the process becomes more difficult, and it may cause the PN junction depletion layer to shrink poorly during forward conduction, resulting in an excessively high turn-on voltage. Setting the spacing within the range of 0.2 to 0.4 micrometers ensures that the depletion layers of the PN junction overlap to form a barrier under zero bias, keeping the channel in a pinch-off state and achieving normally closed device characteristics. At the same time, after applying a forward voltage, the depletion layers can effectively shrink, making the channel conduct and achieving a low forward conduction voltage drop.

[0036] By setting the spacing between the P+ type highly doped regions to 0.2 to 0.4 micrometers, it is ensured that the PN junction depletion layers can overlap each other under zero bias voltage to form an effective channel barrier, enabling the integrated field-controlled diode to have normally closed characteristics and preventing the device from being turned on erroneously when there is no forward bias voltage.

[0037] In one possible implementation, the junction depth of the P-type base region is 0.7~1.0 μm; the junction depth of the N-type source region is 0.2~0.3 μm; and the junction depth of the P+ type highly doped region is 0.7~1.0 μm.

[0038] Based on the aforementioned silicon carbide MOSFET structure, this embodiment optimizes and limits the junction depth of the P-type base region, N-type source region, and P+-type heavily doped region. First, by controlling the ion implantation energy, the junction depth of the P-type base region is set between 0.7 and 1.0 micrometers. This depth ensures sufficient MOSFET channel length to effectively control channel current while avoiding short-channel effects. Second, the junction depth of the N-type source region is set between 0.2 and 0.3 micrometers. This shallow depth places the source region on the shallow surface of the P-type base region, facilitating subsequent ohmic contact formation and ensuring the PN junction formed between the source and P-type base regions is in a suitable position, which is beneficial for the device's switching characteristics. Finally, the junction depth of the P+-type heavily doped region is set to be similar to that of the P-type base region, i.e., 0.7 to 1.0 micrometers. This depth allows the P+-type heavily doped region to form a continuous P-type doped region with the P-type base region in the vertical direction, which is beneficial for forming a uniform depletion layer expansion during reverse bias and ensures effective modulation of the channel barrier during forward conduction.

[0039] By synergistically optimizing the junction depth of the P-type base region, N-type source region, and P+-type highly doped region, the channel length of the MOSFET, the source region location, and the depletion region distribution of the field-controlled diode are matched with each other, thereby optimizing the turn-on and turn-off performance of the integrated field-controlled diode while ensuring the basic switching characteristics of the MOSFET.

[0040] In one possible implementation, the doping concentration of the epitaxial layer is 2.0E15~1E16 cm⁻¹. - ³.

[0041] Based on the aforementioned silicon carbide MOSFET structure, this embodiment optimizes and limits the doping concentration of the epitaxial layer. During the growth of the epitaxial layer on the silicon carbide substrate, the doping concentration of the epitaxial layer is set to 2.0 × 10¹ by controlling the gas flow rate of the doping source. 5 Up to 1.0×10¹ 6 Within a range of cubic centimeters. This doping concentration range is set by comprehensively considering the trade-off between the device's breakdown voltage and on-resistance. If the doping concentration is too low, although it can increase the device's breakdown voltage, it will significantly increase the on-resistance and conduction losses; if the doping concentration is too high, the on-resistance will decrease, but the breakdown voltage will decrease. The epitaxial layer doping concentration is set at 2.0 × 10¹ 5 Up to 1.0×10¹ 6 Within a cubic centimeter range, it can achieve a low on-resistance while ensuring that the advantages of the high critical breakdown field strength of silicon carbide material are brought into play, making it suitable for medium and high voltage power switching applications.

[0042] By setting the doping concentration of the epitaxial layer to 2.0 × 10¹ 5 Up to 1.0×10¹ 6 Within each cubic centimeter, while utilizing the high breakdown field strength of silicon carbide material, the on-resistance of the drift region is effectively controlled, achieving a good balance between the device's withstand voltage and conduction loss.

[0043] See Figure 2 , Figure 2 A flowchart illustrating a method for manufacturing a silicon carbide MOSFET structure according to an embodiment of this specification is shown, specifically including the following steps.

[0044] Step 201: Form an epitaxial layer on a silicon carbide substrate; Step 202: Form a base region implantation shielding layer on the epitaxial layer, and form mutually separated P-type base regions by ion implantation; Step 203: Oxidize the base region implantation shielding layer to thicken it and form an isolation layer, and then form an N-type source region through ion implantation; Step 204: Form a P+ region implantation shielding layer, and form a P+ type highly doped region by ion implantation, with spacing between the P+ type highly doped regions; Step 205: Ion implantation is performed on the unit cell region to form an N-type JFET region located between the P+ type heavily doped regions; Step 206: Perform annealing activation; Step 207: Form the gate oxide layer and the gate polysilicon; Step 208: Deposit a dielectric oxide layer and form metal electrode contact holes; Step 209: Deposit a metal layer and anneal it to form a source ohmic contact metal layer, so that the source metal electrode and the semiconductor material form an ohmic contact; Step 210: Form a drain metal electrode on the lower surface of the silicon carbide substrate.

[0045] In this context, the base implantation shielding layer can refer to a masking layer formed before ion implantation, used to define the implantation region, such as a polysilicon layer. The isolation layer can refer to a structure formed by thermally oxidizing the base implantation shielding layer to thicken it, used to protect the underlying P-type base region during subsequent source implantation. The unit cell region can refer to the region in a device composed of multiple repeating units (unit cells), which is the core region for current conduction. Annealing activation refers to the thermal treatment of implanted impurity ions at high temperatures, causing them to enter their lattice positions and activate their electrical properties.

[0046] This embodiment provides a method for manufacturing a silicon carbide MOSFET structure, specifically including the following steps: First, an N+ type silicon carbide substrate is selected, and an N-type epitaxial layer is grown on the substrate using chemical vapor deposition. A polysilicon layer is deposited on the epitaxial layer, and a base region implantation shielding layer is formed using photolithography and etching processes. Using this shielding layer as a mask, P-type ion implantation is performed to form mutually separated P-type base regions. After completing the P-type base region implantation, the base region implantation shielding layer is thermally oxidized to increase its thickness and transform it into an isolation layer. Subsequently, using this thickened isolation layer as a mask, N-type ion implantation is performed to form an N-type source region. After removing the isolation layer, an oxide layer is deposited on the wafer surface, and a P+ region implantation shielding layer is formed using photolithography and etching. Using this shielding layer as a mask, high-dose P-type ion implantation is performed to form a P+ type heavily doped region, and by controlling the size of the implantation window, a certain spacing is maintained between the formed P+ type heavily doped regions. Then, through one or more ion implantations, an N-type JFET region is formed in the region between the P+ type heavily doped regions. After all implantation is complete, a carbon film is sputtered onto the wafer surface as a protective layer and annealed at high temperature to activate the implanted impurity ions electrically. After removing the carbon film, a gate oxide layer is grown using a dry oxidation process, and polysilicon is deposited. The gate polysilicon structure is formed by photolithography and etching. A dielectric oxide layer is deposited on the wafer, and metal electrode contact holes are formed using photolithography. A metal layer is deposited at the contact holes and annealed to form the source ohmic contact metal layer, which forms an ohmic contact with the semiconductor material. Finally, the lower surface of the silicon carbide substrate is thinned, and a metal layer is evaporated to form the drain metal electrode.

[0047] This manufacturing method enables the integration of field-controlled diode structures within the same process flow, avoiding the process complexity introduced by introducing additional Schottky diodes. Furthermore, by forming an ohmic contact between the source metal and the semiconductor, it lays the technological foundation for the subsequent formation of field-controlled diodes with low on-state voltage drop.

[0048] In one possible implementation, forming an N-type JFET region includes: forming a first N-type JFET region by ion implantation with a junction depth of 0.9~1.2um; forming an implantation shielding layer; and forming a second N-type JFET region located on the wafer surface between the P+ type heavily doped regions by ion implantation with a junction depth of 0.15~0.25um, wherein the doping concentration of the second N-type JFET region is higher than that of the first N-type JFET region.

[0049] The implantation shielding layer can refer to the masking oxide layer used to define the implantation region before the formation of the second N-type JFET region.

[0050] Based on the aforementioned silicon carbide MOSFET structure manufacturing method, this embodiment further specifies the steps for forming the N-type JFET region. Specifically, after completing the P+ type highly doped region implantation, a high-energy, low-dose N-type ion implantation is first performed to form the first N-type JFET region. By controlling the implantation energy, the junction depth of the first N-type JFET region reaches 0.9 to 1.2 micrometers. This region serves as the deep portion of the conductive channel of the field-controlled diode, used to withstand voltage during reverse bias. Subsequently, an oxide layer is deposited on the wafer surface, and a JFET2 implantation shielding layer is formed through photolithography and etching. This shielding layer opens the implantation window in the region between the P+ type highly doped regions. Next, a second N-type ion implantation is performed. This implantation uses lower energy and a higher dose, so that the implanted impurity ions are confined to a shallow region near the wafer surface, forming the second N-type JFET region. By controlling the implantation energy, the junction depth of the second N-type JFET region is controlled within the range of 0.15 to 0.25 micrometers, and its doping concentration is set to be higher than that of the first N-type JFET region. Through these two phased implantations, an N-type JFET region with a bilayer structure of high surface doping and low deep doping was finally formed.

[0051] By implanting the first N-type JFET region and the second N-type JFET region in stages, the doping concentration and junction depth of the conductive channel are controlled in layers. This ensures high breakdown voltage in the deep region and reduces the contact resistance of the source ohmic contact through the highly doped surface region, thereby optimizing the overall performance of the field-controlled diode.

[0052] In one possible implementation, when forming P+ type highly doped regions, the spacing between the P+ type highly doped regions is 0.2~0.4 μm.

[0053] The spacing between P+ type heavily doped regions can refer to the horizontal distance between two adjacent P+ type heavily doped regions formed by ion implantation.

[0054] Based on the aforementioned silicon carbide MOSFET structure manufacturing method, this embodiment optimizes and limits the critical dimensions during the formation of the P+ type heavily doped region. When forming the P+ region implantation shielding layer, the window size between the corresponding P+ type heavily doped regions on the mask is precisely controlled through photolithography. This ensures that a precise spacing is maintained between the two P+ type heavily doped regions after subsequent ion implantation; this spacing is set to 0.2 to 0.4 micrometers. This precise control of the spacing is achieved using high-precision photolithography equipment and optimized etching processes. This spacing ensures that after the subsequent formation of the N-type JFET region and completion of all high-temperature processes, the PN junction depletion layer formed by the P+ type heavily doped region and the N-type JFET region can overlap under zero bias, thereby clamping the conductive channel and keeping the integrated field-controlled diode in a normally closed state. Simultaneously, this spacing also provides sufficient space for the shrinkage of the depletion layer under forward bias, allowing the device to conduct at a lower forward voltage.

[0055] By precisely controlling the spacing between the P+ type highly doped regions to 0.2 to 0.4 micrometers, the depletion layers of the PN junction can be reliably overlapped under zero bias, realizing the normally closed characteristics of the field-controlled diode and avoiding deviation of device performance from the design target due to process fluctuations.

[0056] In one possible implementation, the source ohmic contact metal layer is formed by: depositing a Ni metal layer with a thickness of 100um-300nm, annealing it at 900-1100 degrees Celsius for 2-3 minutes, and then forming an AlCu alloy layer with a thickness of 3-6um by metal deposition.

[0057] The Ni metal layer can refer to the nickel layer used as a contact metal to form ohmic contacts with semiconductor materials. Annealing can refer to a heat treatment process that heats the wafer to a high temperature for a short time and then cools it rapidly to form low-resistance ohmic contacts at the metal-semiconductor interface. The AlCu alloy layer can refer to an aluminum-copper alloy layer, used as the main metal for the front electrode of the device to reduce resistance and improve reliability.

[0058] Based on the aforementioned silicon carbide MOSFET structure manufacturing method, this embodiment specifies the detailed process for forming the source ohmic contact metal layer. After completing the dielectric oxide layer and forming the metal electrode contact holes, a Ni metal layer is first deposited on the upper surface of the wafer using a physical vapor deposition process. The thickness of this Ni metal layer is controlled between 100 nm and 300 nm. After deposition, the wafer is placed in a rapid thermal annealing furnace for high-temperature rapid annealing under a nitrogen or argon protective atmosphere. The annealing temperature is set between 900 and 1100 degrees Celsius, and the annealing time is set between 2 and 3 minutes. During this process, Ni reacts with the exposed N-type source region, P-type base region, and P+-type highly doped region surface of the silicon carbide to form low-resistance metal silicides, thereby forming a high-quality ohmic contact. After annealing, metal deposition is performed again on the wafer to deposit an AlCu alloy layer, the thickness of which is controlled between 3 and 6 micrometers. The AlCu alloy layer, serving as the main metal of the source electrode, is patterned through photolithography and etching processes to form the final source metal electrode. This AlCu alloy layer not only exhibits low resistivity but also effectively suppresses electromigration, thereby improving device reliability.

[0059] By employing a Ni metal layer and performing high-temperature rapid annealing, a low-resistance ohmic contact is formed between the Ni metal layer and the silicon carbide semiconductor material, replacing the Schottky contact in the traditional process. This provides a key electrical contact foundation for achieving field-controlled diodes with low on-state voltage drop. At the same time, the thicker AlCu alloy layer serves as the electrode body, effectively reducing electrode resistance and improving the current carrying capacity and reliability of the device.

[0060] The following is in conjunction with the appendix Figures 3-12 Taking the application of the silicon carbide MOSFET structure provided in this specification in an N-channel SiC MOSFET as an example, the silicon carbide MOSFET structure will be further explained. Among other things, Figure 2 A flowchart illustrating the processing steps of a silicon carbide MOSFET structure according to an embodiment of this specification is shown, specifically including the following steps.

[0061] See Figure 3 An N+ type SiC substrate 1 was selected, and doping concentrations of 2.0E15~1E16 cm⁻¹ were deposited on the N+ type silicon substrate. -3 Epitaxial layer 2; See Figure 4 On the surface of the wafer with the epitaxial layer already deposited, a polysilicon deposition, photolithography, and etching process is used to etch and form a base region implantation shielding polysilicon layer 3. Then, a P-type base region implantation process is used, implanting impurity ions Al at an implantation energy of 30 keV to 600 keV and an implantation dose of 1E12 to 1E14 cm⁻¹. -2 ; Forms P-type base region 4, junction depth 0.7~1.0um; See Figure 5 After completing P-type base implantation, the base implantation shielding polysilicon layer is thermally oxidized to increase its thickness, forming a Spacer5 with a thickness of 0.3~0.6µm. The wafer forming the Spacer is then subjected to N-type source implantation, with N impurity ions implanted at an implantation energy of 30keV~200keV and an implantation dose of 4E14~4E15cm. -2 N-type source region 6 is formed, with a junction depth of 0.2~0.3 μm; See Figure 6 Through deposition, photolithography, and selective etching processes, a P+ region implantation shielding oxide layer 7 is formed on the wafer after N-type source region implantation. P+ implantation is then performed on the wafer through the implantation window formed by the P+ region implantation shielding oxide layer pattern to form a P+ type highly doped region 8. Impurity ions Al are implanted at an implantation energy of 100 keV to 600 keV and an implantation dose of 4E14 to 2E15 cm⁻¹. -2 The junction depth is 0.7~1.0um; a spacing of 0.2~0.4um is formed between the P+ type highly doped regions implanted in the left and right separated P type base regions; See Figure 7 N+ type impurity ion implantation was performed on the wafer unit cell region after P+ high doping region implantation, with N impurity ions implanted, implantation energy of 100keV~900keV, and implantation dose of 5E11~1E13cm-2; forming N+ type JFET1 region 9 with junction depth of 0.9~1.2um; See Figure 8 Through deposition, photolithography, and selective etching processes, a JFET2 implantation shielding oxide layer is formed on the wafer surface after the N+ type JFET1 region implantation is completed. Then, the wafer is implanted with N+ impurity ions again, with the implantation energy being 30keV~80keV and the implantation dose being 2E14~2E15cm-2. A highly doped N+ type JFET2 region 10 is formed on the wafer surface between the left and right separated P+ type highly doped regions, with a junction depth of 0.15~0.25um. See Figure 9 Remove the shielding oxide layer on the surface of the highly doped N+ type JFET 2 region implanted wafer and sputter a carbon film; then perform high-temperature annealing activation on the wafer after carbon film sputtering, with an annealing temperature of 1650~1750℃ and a time of 60~30min. See Figure 10 The carbon film on the surface of the high-temperature annealed wafer after impurity implantation is removed. A 300-500 μm thick oxide layer and a 0.5-1.0 μm thick gate polysilicon layer are formed on the upper surface of the wafer using dry oxidation and deposition processes, respectively. Then, the gate oxide layer 11 and gate polysilicon 12 structure are formed by photolithography and selective etching. See Figure 11A dielectric oxide layer 13 with a thickness of 1.0um-1.5um is deposited on a wafer with a gate oxide layer and a gate polysilicon structure. Then, metal electrode contact holes are formed on the dielectric layer by photolithography. Next, a Ni metal layer with a thickness of 100um-300nm is deposited on the upper surface of the wafer where the electrode contact holes are formed, and then annealed at a temperature of 900-1100 degrees Celsius for 2-3 minutes to form a source ohmic contact metal layer. Then, an AlCu alloy with a thickness of 3-6um is deposited by metal deposition to form the front metal electrode 14. See Figure 12 The lower surface of the SiC wafer substrate with the front metal electrode is thinned and a Ti / Ni / Ag metal layer is deposited by vapor deposition to form the drain metal electrode 15, thus completing the fabrication of the SiC MOSFET structure.

[0062] In the SiC MOSFET structure proposed in this application, an anti-parallel SBD region is introduced by forming a Schottky contact between the source metal and the MOSFET base region in the original scheme. A mutually separated P-type base region structure is set, and the overlapping of the PN junction depletion layers of the left and right P+ injection regions and the N+ region between the P+ injection regions constitutes a normally closed device. Furthermore, an ohmic contact is formed between the source metal electrode and the semiconductor material, replacing the original parallel SBD or JBS Schottky barrier diode. The Schottky contact formed between the metal electrode and the epitaxial layer creates a field-controlled diode whose barrier height is only modulated by the P+ injection region and the N+ region PN junction depletion layer. The beneficial effects are as follows: This application integrates a low-barrier field-controlled diode into the SiC MOSFET cell. Because the metal-semiconductor contact of this diode is an ohmic contact, there is no limitation of the Schottky barrier in existing integrated SBD or JBS diode technologies. This can further reduce the forward conduction voltage drop and further reduce switching losses when the MOSFET is turned off and performs reverse freewheeling.

[0063] Meanwhile, this field-controlled diode bears the high drain-source voltage when the MOS is turned off through the reverse bias barrier of the PN junction, and does not have the problems of degraded Schottky reverse blocking capability and excessive leakage current caused by the integrated SBD diode in the prior art.

[0064] In addition, since this field-controlled diode is a majority carrier device, it can avoid the bipolar degradation of SiC material caused by bipolar injection due to PiN parasitic diode conduction, thereby improving the reliability of the device.

[0065] When the MOS transistor is off, the integrated field-controlled diode operates in reverse. The PN junction depletion layer overlap region expands, entering the N-drift region and rapidly extending throughout the entire drift region. At this time, the integrated field-controlled diode in this application is similar to a PiN diode and operates on the same principle as JBS, achieving a relatively high reverse breakdown voltage, such as... Figure 13aThe figure shows the breakdown characteristic curve of a SiC MOSFET with integrated field-controlled diode.

[0066] The low-barrier field-controlled diode integrated in this application utilizes the overlapping of depletion layers of adjacent PN junctions on the conductive path to form a barrier. By designing the diode's structural dimensions and impurity doping, a suitable depletion region barrier height can be obtained, thereby achieving a lower forward voltage drop.

[0067] like Figure 13b and 13c The figure shows the depletion layer structure and potential distribution of the PN junction of the integrated field-controlled diode in this application at zero bias. As can be seen from the figure, when no voltage is applied to the diode anode and cathode, the depletion layers of the PN junction overlap under the influence of the built-in potential, causing the channel to be pinched off. A channel barrier exists in the pinched-off channel region. For electrons to pass through the channel region, they must overcome the barrier under the influence of an external voltage to potentially form an electron current.

[0068] When a forward voltage lower than the forward voltage drop is applied between the two terminals of a diode, electrons in the diode's channel and drift regions are influenced by the forward voltage and tend to drift towards the anode. However, due to the existence of the channel barrier, the potential energy of the electrons is lower than the height of the channel barrier, and they cannot cross the barrier to reach the diode's anode, thus preventing the formation of a forward current.

[0069] As the forward voltage applied to the anode of the diode increases, it affects the barrier height in the channel. As the forward voltage gradually increases, the depletion layer width of the PN junction shrinks under the influence of the forward bias, and the barrier height in the channel gradually decreases. When the shrinkage of the depletion layer reaches a certain level, and the reduction of the channel barrier reaches a certain level, resulting in a non-negligible number of electrons crossing the channel barrier, a forward current appears.

[0070] like Figure 14a and 14b As shown, when the forward voltage Ua of the diode increases to a certain extent, the PN junction depletion layer shrinks severely, and the overlapping region disappears. At this time, it is related to... Figure 13b and 13c In contrast, the barrier height Uh in the conductive channel has been significantly reduced, and a large number of electrons enter the conductive path from the drift region under the influence of the positive voltage, moving towards the anode region and forming a significant positive current.

[0071] The forward conduction characteristics of the field-controlled diode integrated in the SiC MOS of this application were simulated, such as... Figure 15a and 15b As can be seen, this application can achieve a diode forward voltage drop as low as 0.5V while ensuring normal leakage current.

[0072] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments in this specification are not limited to the described order of actions, because according to the embodiments in this specification, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the embodiments in this specification.

[0073] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0074] The preferred embodiments disclosed above are merely illustrative of this specification. The optional embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the embodiments described herein. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the embodiments, thereby enabling those skilled in the art to better understand and utilize this specification. This specification is limited only by the claims and their full scope and equivalents.

Claims

1. A silicon carbide MOSFET structure, characterized in that, include: silicon carbide substrate; An epitaxial layer disposed on the silicon carbide substrate; P-type base regions are disposed in the epitaxial layer and are separated from each other; The N-type source region is disposed within the P-type base region; The P+ type highly doped regions are disposed in the epitaxial layer between the P type base regions, and a spacing is formed between the P+ type highly doped regions. The N-type JFET region is disposed in the epitaxial layer between the P+ type heavily doped regions; A gate oxide layer and a gate polysilicon layer, wherein the gate oxide layer and the gate polysilicon layer are disposed on the epitaxial layer; A dielectric oxide layer is disposed on the gate oxide layer and the gate polysilicon; A source metal electrode, wherein the source metal electrode forms an ohmic contact with a semiconductor material; And a drain metal electrode, wherein the drain metal electrode is disposed below the silicon carbide substrate; A field-controlled diode is formed between the source metal electrode and the drain metal electrode, the barrier height of which is modulated by the depletion layer of the PN junction between the P+ type heavily doped region and the N type JFET region.

2. The silicon carbide MOSFET structure according to claim 1, characterized in that, The N-type JFET region includes a first N-type JFET region and a second N-type JFET region; The first N-type JFET region is disposed in the epitaxial layer between the P+ type highly doped regions; The second N-type JFET region is disposed on the wafer surface between the P+ type highly doped regions, and the doping concentration of the second N-type JFET region is higher than that of the first N-type JFET region.

3. The silicon carbide MOSFET structure according to claim 2, characterized in that, The junction depth of the first N-type JFET region is 0.9~1.2um; The junction depth of the second N-type JFET region is 0.15~0.25um.

4. The silicon carbide MOSFET structure according to claim 1, characterized in that, The spacing between the P+ type highly doped regions is 0.2~0.4 μm.

5. The silicon carbide MOSFET structure according to claim 1, characterized in that, The junction depth of the P-type base region is 0.7~1.0 μm; The junction depth of the N-type source region is 0.2~0.3 μm; The junction depth of the P+ type highly doped region is 0.7~1.0 μm.

6. The silicon carbide MOSFET structure according to claim 1, characterized in that, The doping concentration of the epitaxial layer is 2.0E15~1E16 cm⁻¹ - ³.

7. A method for manufacturing a silicon carbide MOSFET structure, characterized in that, include: An epitaxial layer is formed on a silicon carbide substrate; A base region implantation shielding layer is formed on the epitaxial layer, and mutually separated P-type base regions are formed by ion implantation; The base region implantation shielding layer is oxidized to thicken it and form an isolation layer, and an N-type source region is formed by ion implantation. A P+ region implantation shielding layer is formed, and a P+ type highly doped region is formed by ion implantation, with spacing formed between the P+ type highly doped regions; Ion implantation is performed on the unit cell region to form an N-type JFET region located between the P+ type heavily doped regions; Perform annealing activation; Forming the gate oxide layer and the gate polysilicon; Deposit a dielectric oxide layer and form metal electrode contact holes; A metal layer is deposited and annealed to form a source ohmic contact metal layer, so that the source metal electrode and the semiconductor material form an ohmic contact. A drain metal electrode is formed on the lower surface of the silicon carbide substrate.

8. The manufacturing method according to claim 7, characterized in that, Forming the N-type JFET region includes: The first N-type JFET region is formed by ion implantation, with a junction depth of 0.9~1.2um; An implantation shielding layer is formed, and a second N-type JFET region is formed on the wafer surface between the P+ type highly doped regions by ion implantation. The junction depth is 0.15~0.25um, and the doping concentration of the second N-type JFET region is higher than that of the first N-type JFET region.

9. The manufacturing method according to claim 7, characterized in that, When forming the P+ type highly doped region, the spacing between the P+ type highly doped regions is 0.2~0.4 μm.

10. The manufacturing method according to claim 7, characterized in that, Forming the source ohmic contact metal layer includes: A Ni metal layer with a thickness of 100um-300nm is deposited and annealed at 900-1100 degrees Celsius for 2-3 minutes. Then, an AlCu alloy layer with a thickness of 3-6um is formed by metal deposition.

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