A superjunction silicon VDMOS device with a high dielectric constant dielectric layer, a locally vertical superjunction buried layer, and non-uniform doping.

Abstract

This invention relates to a superjunction silicon VDMOS device with a high dielectric constant dielectric layer, a localized vertical superjunction buried layer, and non-uniform doping, belonging to the field of semiconductor power devices. Addressing the problems of concentrated bottom electric field, high peak interface electric field, and uneven vertical electric field distribution in existing superjunction devices, this device embeds horizontally alternating N+ and P+ buried layers within an N-buffer layer to form a localized vertical superjunction buried layer. A high dielectric constant dielectric layer is placed at the interface between the P-type and N-type pillars, and the P-type and N-type pillars are designed with a vertically non-uniformly doped structure. This approach effectively suppresses bottom electric field concentration, reduces the peak interface electric field, and homogenizes the vertical electric field distribution in the drift region. This results in improved breakdown voltage while reducing specific on-resistance, breaking through the performance limits of silicon materials and enhancing tolerance to manufacturing process deviations.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power devices and relates to a superjunction silicon vertical double-diffused metal-Oxide-Semiconductor field effect transistor (VDMOS) device having a high dielectric constant dielectric layer, a localized vertical superjunction buried layer, and non-uniform doping. Background Technology

[0002] Power metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used in high-power-density applications such as switching power supplies, motor drives, and new energy vehicles. The performance of traditional silicon-based vertical double-diffused metal-oxide-semiconductor field-effect transistors (VDMOS) is limited by the physical limitations of silicon, with an inherent trade-off between breakdown voltage and specific on-resistance. To improve the breakdown voltage, the doping concentration in the drift region needs to be reduced, but this significantly increases the on-resistance, limiting further optimization of high-voltage power devices.

[0003] Superjunction technology introduces alternating P-type and N-type pillars to form a superjunction drift region. Utilizing a lateral charge compensation mechanism, the N-type drift region can still be completely depleted even at high doping concentrations. This improves the relationship between breakdown voltage and specific on-resistance from a traditional high-power dependence to an approximately linear dependence, breaking the silicon limit. Commercially available superjunction VDMOS devices based on this principle have achieved a significant reduction in specific on-resistance.

[0004] However, existing superjunction VDMOS devices still have three main drawbacks. First, the electric field concentration at the junction of the bottom of the P-type and N-type pillars and the N-buffer layer is caused by a sudden charge change, and device breakdown often begins in this region, with the actual breakdown voltage lower than the theoretical value. Second, the lateral interface between the P-type and N-type pillars relies solely on the dielectric properties of silicon to constrain the electric field, resulting in a high peak value at the interface. This makes the interface highly sensitive to doping concentration deviations and prone to localized avalanche breakdown. Third, when the P-type and N-type pillars are uniformly doped, the longitudinal electric field distribution in the drift region is uneven due to the boundary effect between the top P-well and the bottom N-buffer layer. The voltage withstand capability is not fully exploited, leading to a higher specific on-resistance.

[0005] To address the aforementioned issues, the industry has proposed various improvement solutions, but most can only optimize a single performance aspect, failing to achieve a synergistic improvement in both breakdown voltage and specific on-resistance. Therefore, a novel superjunction structure that can simultaneously solve these three core problems is urgently needed to further enhance the performance limits of silicon-based power devices. Summary of the Invention

[0006] In view of this, the purpose of the present invention is to provide a superjunction silicon VDMOS device having a high dielectric constant dielectric layer, a localized vertical superjunction buried layer, and non-uniform doping.

[0007] To achieve the above objectives, the present invention provides the following technical solution: A superjunction silicon VDMOS device having a high dielectric constant dielectric layer, a localized vertical superjunction buried layer, and non-uniform doping, characterized in that it includes an N+ substrate 1, an N buffer layer 2, a P-type pillar 3, an N-type pillar 4, a high dielectric constant dielectric layer 5, a P-well 6, an N+ source region 7, a P+ body contact region 8, a gate oxide layer 9, a polysilicon gate 10, an N+ buried layer 11, a P+ buried layer 12, a source 13, and a drain 14; The N+ substrate 1 is located at the bottom of the device, and the drain 14 is disposed on the lower surface of the N+ substrate 1; The N-buffer layer 2 is disposed above the N+ substrate 1; the P-type pillars 3 and N-type pillars 4 are arranged alternately to form a superjunction pillar region, which is disposed above the N-buffer layer 2; The high dielectric constant dielectric layer 5 is sandwiched at the interface between the P-type pillar 3 and the N-type pillar 4, and extends longitudinally through the entire superjunction pillar region. The P-well 6 is located above the superstructure column region and covers the tops of the P-type column 3 and the N-type column 4; The N+ source region 7 and the P+ body contact region 8 are disposed above the P-well 6; The gate oxide layer 9 and the polysilicon gate 10 form a trench gate structure; The N+ buried layer 11 and P+ buried layer 12 are embedded inside the N buffer layer 2, and the N+ buried layer 11 is located above the P+ buried layer 12. The N+ buried layer 11 and P+ buried layer 12 are arranged periodically in the transverse direction to form a local longitudinal superjunction buried layer. The source electrode 13 is disposed above the N+ source region 7 and the P+ body contact region 8; The P-type pillar 3 and N-type pillar 4 are non-uniformly doped along the longitudinal direction, and the doping concentration of the P-type pillar 3 and N-type pillar 4 increases monotonically from the side closer to the P-well 6 to the side closer to the N-buffer layer 2.

[0008] Furthermore, the relative permittivity of the high dielectric layer 5 is greater than that of the silicon material.

[0009] Furthermore, the lateral arrangement period of the N+ buried layer 11 and the P+ buried layer 12 is the same as the lateral arrangement period of the P-type column 3 and the N-type column 4.

[0010] Furthermore, the non-uniform doping of the P-type pillar 3 and N-type pillar 4 is distributed in a stepped manner, divided into several segments along the longitudinal direction. The P-type pillar 3 and N-type pillar 4 at the same transverse position satisfy the transverse charge compensation balance in their respective segments.

[0011] Furthermore, the P+ body contact region 8 is shorted to the N+ source region 7 through the source electrode 13, clamping the potential of the P-well 6 to the source electrode potential.

[0012] Furthermore, the bottom of the grooved grid structure is provided with rounded corners.

[0013] Furthermore, the top corners of the N-shaped column 4 and the P-shaped column 3 adjacent to each other are provided with rounded corners.

[0014] Furthermore, the doping concentration of the N-buffer layer 2 is lower than the average doping concentration of the P-type pillar 3 and the N-type pillar 4. The N+ buried layer 11 and the P+ buried layer 12 are embedded in the middle position of the N-buffer layer 2, and background doping regions are left above the N+ buried layer 11 and below the P+ buried layer 12.

[0015] Furthermore, the material of the high dielectric constant dielectric layer 5 is a high dielectric constant oxide.

[0016] Furthermore, the N+ buried layer 11 and the P+ buried layer 12 are stacked vertically without contact along the longitudinal direction.

[0017] The beneficial effects of this invention are as follows: (1) By setting a localized longitudinal superjunction buried layer composed of N+ buried layer and P+ buried layer in the N buffer layer, a transverse depletion electric field is introduced inside the buffer layer, which is superimposed with the longitudinal depletion electric field of the main superjunction pillar region. This effectively eliminates the charge abrupt change and electric field concentration phenomenon at the bottom of the P-type pillar and N-type pillar and the junction of the N buffer layer, and transfers the device breakdown point from the fragile bottom interface to the middle of the drift region, significantly improving the actual breakdown voltage and making it closer to the theoretical limit.

[0018] (2) By inserting a high dielectric constant dielectric layer at the interface between P-type pillars and N-type pillars, the physical property that the electric displacement vector is normal continuous at the interface between the dielectric and silicon is utilized to force the high dielectric constant dielectric side to bear a higher electric field intensity, thereby significantly reducing the peak value of the interface electric field on the silicon side, delaying the triggering time of avalanche breakdown, and enhancing the process tolerance capability for the doping concentration deviation between P-type pillars and N-type pillars.

[0019] (3) By designing the P-type pillars and N-type pillars as vertically non-uniform doped structures, the gradient change of doping concentration is used to compensate for the suppression effect of the top P-well on the depletion region and the interference of the bottom N-buffer layer on the charge balance, making the vertical electric field distribution of the drift region more uniform, fully exploiting the overall pressure bearing capacity of the drift region, and simultaneously optimizing the breakdown voltage and specific on-resistance without increasing the device area.

[0020] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0021] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 This is a schematic diagram of a conventional VDMOS device structure; Figure 2 This is a schematic diagram of the half-cell cross-sectional structure of the superjunction silicon VDMOS device described in this invention.

[0022] Figure reference numerals: 1 is N+ substrate, 2 is N buffer layer, 3 is P-type pillar, 4 is N-type pillar, 5 is high dielectric constant dielectric layer, 6 is P-well, 7 is N+ source region, 8 is P+ bulk contact region, 9 is gate oxide layer, 10 is polysilicon gate, 11 is N+ buried layer, 12 is P+ buried layer, 13 is source, 14 is drain. Detailed Implementation

[0023] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0024] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0025] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0026] like Figure 1 As shown, a conventional vertical double-diffused metal-oxide-semiconductor field-effect transistor (VDMOS) device mainly consists of an N+ substrate, an N-buffer layer, a P-well, an N+ source region, a gate oxide layer, a polysilicon gate, a source, and a drain. This traditional structure is limited by the physical limitations of silicon, resulting in an irreconcilable contradiction between breakdown voltage and specific on-resistance, making it impossible to simultaneously optimize high voltage and low resistance.

[0027] like Figure 2 As shown, the present invention provides a VDMOS device with a high dielectric constant dielectric layer, a localized vertical superjunction buried layer, and non-uniform doping of a superjunction silicon vertical double-diffused metal-oxide-semiconductor field-effect transistor. Its semi-cell structure specifically includes an N+ substrate 1, an N buffer layer 2, a P-type pillar 3, an N-type pillar 4, a high dielectric constant dielectric layer 5, a P-well 6, an N+ source region 7, a P+ body contact region 8, a gate oxide layer 9, a polysilicon gate 10, an N+ buried layer 11, a P+ buried layer 12, a source 13, and a drain 14.

[0028] The N+ substrate 1 is located at the bottom of the device and is made of heavily doped N-type single-crystal silicon material. Its function is to provide a low-resistance drain current path for the device. The drain 14 is disposed on the lower surface of the N+ substrate 1 and forms a low-resistance ohmic contact with the N+ substrate 1 to reduce the contact resistance of the device.

[0029] N-buffer layer 2 is disposed above N+ substrate 1 and is made of lightly doped N-type silicon. The doping concentration of N-buffer layer 2 is lower than the average doping concentration of P-type pillars 3 and N-type pillars 4 in the superjunction structure above. A localized vertical superjunction buried layer structure is embedded within N-buffer layer 2, consisting of N+ buried layer 11 and P+ buried layer 12. N+ buried layer 11 and P+ buried layer 12 are arranged alternately in the lateral direction with the same arrangement period as the P-type pillars 3 and N-type pillars 4 above, with N+ buried layer 11 located above P+ buried layer 12, and the two are stacked without contact in the vertical direction. N+ buried layer 11 and P+ buried layer 12 are embedded in the middle of N-buffer layer 2, with a certain thickness of background doped region above and below them. This arrangement helps to smooth the electric field transition.

[0030] P-type pillars 3 and N-type pillars 4 are arranged alternately to form a superjunction pillar region, which is located above the N-buffer layer 2. The P-type pillars 3 and N-type pillars 4 employ a stepped, non-uniform doping distribution along the longitudinal direction (i.e., the current flow direction). Specifically, the doping concentration of the P-type pillars 3 and N-type pillars 4 increases monotonically in a stepped manner from the top side near the P-well 6 to the bottom side near the N-buffer layer 2. At the same lateral position, the P-type pillars 3 and N-type pillars 4 maintain a strict lateral charge compensation balance in each longitudinal segment, meaning the total charge per unit area is equal. Furthermore, the top corners of adjacent N-type pillars 4 and P-type pillars 3 are rounded; this geometric optimization aims to mitigate the electric field concentration effect in these sharp-angle regions.

[0031] A high-dielectric-constant dielectric layer 5 is sandwiched at the interface between the P-type pillar 3 and the N-type pillar 4, and extends longitudinally through the entire height of the superjunction pillar region. The high-dielectric-constant dielectric layer 5 is made of a high-dielectric-constant oxide with a relative dielectric constant significantly higher than that of silicon. Based on the principle of continuity of the electric displacement vector normal, the high-dielectric-constant characteristic of the high-dielectric-constant dielectric layer 5 can confine more electric field lines within the dielectric layer, thereby significantly reducing the peak electric field at the interface between the P-type pillar 3 and the N-type pillar 4 in the silicon material. Simultaneously, the thickness of the high-dielectric-constant dielectric layer 5 is controlled to be extremely thin to ensure that its impact on the effective conductive cross-sectional area of ​​the N-type pillar 4 is negligible, thus avoiding a significant increase in on-resistance.

[0032] P-well 6, located above the superjunction pillar region, is a P-type doped silicon region that covers and contacts the top regions of P-type pillar 3 and N-type pillar 4, serving as the device's channel region. The N+ source region 7 and the P+ body contact region 8 are arranged side-by-side on the upper surface of P-well 6. The P+ body contact region 8 is shorted to the N+ source region 7 via source 13, thereby forcibly clamping the potential of P-well 6 to the source potential. This eliminates the risk of the parasitic NPN bipolar transistor being turned on by the N+ source region 7, P-well 6, and the N-type drift region, improving device reliability.

[0033] The gate oxide layer 9 and the polysilicon gate 10 together form a trench gate structure, which extends into one side of the N-type pillar 4. The gate oxide layer 9 covers the inner wall of the trench, and the polysilicon gate 10 fills the inside of the trench. To prevent sharp-corner discharge, the bottom of the trench gate structure is also rounded, which effectively reduces the electric field strength at the trench corners and improves the long-term reliability of the gate oxide layer.

[0034] The source electrode 13 is located on the front side of the device, covering and contacting the N+ source region 7 and the P+ body contact region 8, thus enabling the electrode to be led out on the front side.

[0035] The working principle of this invention is as follows: In the off state, the gate voltage is lower than the threshold voltage, and a forward high voltage is applied to the drain 14. At this time, the lateral PN junction between the P-type pillar 3 and the N-type pillar 4 is reverse biased, and the superjunction pillar region is laterally depleted to withstand the voltage. During this process, the high dielectric constant dielectric layer 5 is responsible for reducing the peak value of the interface electric field, the localized vertical superjunction buried layer is responsible for eliminating the electric field abrupt change at the bottom of the pillar, and the non-uniform doping is responsible for flattening the vertical electric field distribution. The three work together to enable the device to withstand extremely high breakdown voltage. In the on state, the gate voltage is higher than the threshold voltage, and an inversion channel is formed at the interface between the P-well 6 and the gate oxide layer 9. Electrons are injected from the N+ source region 7 through the channel into the N-type pillar 4, and then flow sequentially through the N buffer layer 2 and the N+ substrate 1 to reach the drain 14. Since the superjunction structure allows the N-type pillar 4 to maintain a high doping concentration, the device exhibits an extremely low specific on-resistance.

[0036] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A superjunction silicon VDMOS device having a high dielectric constant dielectric layer, a locally longitudinal superjunction buried layer, and non-uniform doping, characterized in that: It includes an N+ substrate (1), an N-buffer layer (2), a P-type pillar (3), an N-type pillar (4), a high dielectric constant dielectric layer (5), a P-well (6), an N+ source region (7), a P+ bulk contact region (8), a gate oxide layer (9), a polysilicon gate (10), an N+ buried layer (11), a P+ buried layer (12), a source (13), and a drain (14). The N+ substrate (1) is located at the bottom of the device, and the drain (14) is disposed on the lower surface of the N+ substrate (1); The N buffer layer (2) is disposed above the N+ substrate (1); the P-type pillars (3) and N-type pillars (4) are arranged alternately to form a superjunction pillar region, which is disposed above the N buffer layer (2); The high dielectric constant dielectric layer (5) is sandwiched at the interface between the P-type pillar (3) and the N-type pillar (4), and extends longitudinally through the entire superjunction pillar region; The P-well (6) is located above the superstructure column region and covers the top of the P-type column (3) and the N-type column (4); The N+ source region (7) and the P+ body contact region (8) are disposed above the P-well (6); The gate oxide layer (9) and the polysilicon gate (10) form a trench gate structure; The N+ buried layer (11) and P+ buried layer (12) are embedded inside the N buffer layer (2), and the N+ buried layer (11) is located above the P+ buried layer (12). The N+ buried layer (11) and P+ buried layer (12) are arranged in a transverse periodic manner to form a local longitudinal superjunction buried layer. The source electrode (13) is disposed above the N+ source region (7) and the P+ body contact region (8); The P-type pillar (3) and N-type pillar (4) are non-uniformly doped along the longitudinal direction, and the doping concentration of the P-type pillar (3) and N-type pillar (4) increases monotonically from the side closer to the P-well (6) to the side closer to the N-buffer layer (2).

2. The superjunction silicon VDMOS device according to claim 1, characterized in that: The relative permittivity of the high dielectric layer (5) is greater than that of silicon.

3. The superjunction silicon VDMOS device according to claim 1, characterized in that: The lateral arrangement period of the N+ buried layer (11) and the P+ buried layer (12) is the same as that of the P-type column (3) and the N-type column (4).

4. The superjunction silicon VDMOS device according to claim 1, characterized in that: The non-uniform doping of the P-type pillar (3) and N-type pillar (4) is distributed in a stepped manner and divided into several sections along the longitudinal direction. The P-type pillar (3) and N-type pillar (4) at the same transverse position satisfy the transverse charge compensation balance in each corresponding section.

5. The superjunction silicon VDMOS device according to claim 1, characterized in that: The P+ body contact region (8) is short-circuited to the N+ source region (7) through the source electrode (13), clamping the potential of the P-well (6) at the source electrode potential.

6. The superjunction silicon VDMOS device according to claim 1, characterized in that: The bottom of the trench grid structure has rounded corners.

7. The superjunction silicon VDMOS device according to claim 1, characterized in that: The top corners of the N-type column (4) and the P-type column (3) are rounded.

8. The superjunction silicon VDMOS device according to any one of claims 1 to 7, characterized in that: The doping concentration of the N buffer layer (2) is lower than the average doping concentration of the P-type pillar (3) and the N-type pillar (4). The N+ buried layer (11) and the P+ buried layer (12) are embedded in the middle of the N buffer layer (2), and background doping regions are left above the N+ buried layer (11) and below the P+ buried layer (12).

9. The superjunction silicon VDMOS device according to claim 1, characterized in that: The material of the high dielectric constant dielectric layer (5) is a high dielectric constant oxide.

10. The superjunction silicon VDMOS device according to claim 1, characterized in that: The N+ buried layer (11) and P+ buried layer (12) are stacked vertically without contact along the longitudinal direction.

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