Semiconductor devices and their fabrication methods

Abstract

This invention discloses a semiconductor device and its fabrication method. The semiconductor device includes: a semiconductor substrate; a well region of a first conductivity type located in the semiconductor substrate; a plurality of trench gate structures located within the well region and spaced apart, each trench gate structure including: a trench located within the semiconductor substrate, the trench extending from the surface of the semiconductor substrate into the semiconductor substrate and beyond the well region; a first gate and a second gate located within the trench; a dielectric layer; a first output electrode and a second output electrode located on the surface of the well region; and a semiconductor layer located within the well region, wherein the semiconductor layer is of a second conductivity type, and the first conductivity type is opposite to the second conductivity type. This invention, by setting the P-type filling region to a corresponding doping concentration range, can effectively deplete the free carriers in the N-type well region, thereby ensuring that while improving the breakdown voltage capability of the semiconductor device, it also improves the current capability, thus better balancing the requirements of high breakdown voltage and low on-resistance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor device and its fabrication method. Background Technology

[0002] Power MOSFETs are widely used in power control due to their advantages such as low on-state voltage drop, high frequency operation capability, simple drive control, high power density, and easy parallel connection. They are one of the mainstream power devices at present.

[0003] In low-voltage power control and voltage conversion applications, such as Applications such as converters and battery charging and discharging often require power devices to have bidirectional voltage withstand capability and current conduction capability. Therefore, it is necessary to design power devices with bidirectional conduction and voltage withstand capability to meet the needs of bidirectional conduction application scenarios. For power MOSFETs, it is often difficult to achieve both voltage withstand capability and low on-resistance. For example, in order to reduce the on-resistance of the device, the drift region needs to use a higher doping concentration as much as possible, which is conducive to current flow. However, if the doping concentration is too high, an effective depletion region cannot be formed, which affects the voltage withstand capability of the device. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its fabrication method, which improves the voltage withstand capability and current conduction capability of a bidirectional power MOSFET device.

[0005] The first aspect of the present invention provides a semiconductor device, comprising: Semiconductor substrate; A well region of a first conductivity type located in the semiconductor substrate; A plurality of trench gate structures are located within the well region and spaced apart. Each trench gate structure includes: a trench located within the semiconductor substrate, the trench extending from the surface of the semiconductor substrate into the semiconductor substrate and beyond the well region; a first gate and a second gate located within the trench; and a dielectric layer isolating the first gate from the second gate, the first gate from the semiconductor substrate, and the second gate from the semiconductor substrate. The first and second output electrodes are located on the surface of the well region; A semiconductor layer located within the well region, wherein the semiconductor layer is of a second conductivity type, and the first conductivity type is opposite to the second conductivity type.

[0006] Preferably, the semiconductor device includes a bidirectional trench gate power MOSFET device, wherein the semiconductor substrate and the semiconductor layer include P-type semiconductors; and the well region includes N-type semiconductors.

[0007] Preferably, the semiconductor layer and the well region form a local superjunction structure for assisting in the depletion of free carriers in the well region, wherein the doping concentration of the semiconductor layer matches the doping concentration of the well region.

[0008] Preferably, the doping concentration range of the well region is: .

[0009] Preferably, the system further includes a filling trench located between two adjacent trenches, wherein the bottom longitudinal depth of the filling trench is less than the bottom longitudinal depth of the well region.

[0010] Preferably, the first gate is located near the top of the trench, and the second gate is located near the bottom of the trench.

[0011] Preferably, the first gate includes a field plate electrode that functions as a field plate, and the second gate includes a control electrode for a current-controlled switch.

[0012] Preferably, it further includes a heavily doped semiconductor layer for generating the first output electrode or the second output electrode.

[0013] Preferably, when the second output electrode is shorted to the semiconductor substrate and the second gate is turned on, the current flows from the first output electrode to the second output electrode; when the first output electrode is shorted to the semiconductor substrate and the second gate is turned on, the current flows from the second output electrode to the first output electrode.

[0014] A second aspect of the present invention also provides a method for fabricating a semiconductor device, the method comprising: A semiconductor substrate is provided, and a well region of a first conductivity type is formed in the semiconductor substrate; At least one filling trench is formed in the well region; A semiconductor material of a second conductivity type is filled into the filling trench to form a semiconductor layer, such that the semiconductor layer and the well region constitute a local superjunction structure. A trench gate structure is formed in a semiconductor substrate, the trench gate structure comprising: a trench located in the semiconductor substrate; a first gate and a second gate located in the trench; and a dielectric layer located between the first gate and the second gate, the first gate and the inner wall of the trench, and the second gate and the inner wall of the trench. The first and second output electrodes are generated on the surface of the well region through a heavily doped semiconductor layer.

[0015] The semiconductor device and its fabrication method disclosed in this invention have the following beneficial effects: it can improve the withstand voltage of a bidirectional conducting device while further reducing the on-resistance of the semiconductor device, thereby optimizing the electrical performance. In addition, by adding P-type filling to the N-type well region and utilizing the superjunction depletion principle, this invention can further improve the withstand voltage of the semiconductor device while increasing the conduction current capability, thereby optimizing the performance of the semiconductor device. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a typical bidirectional trench gate power MOSFET device. Figure 2 A schematic diagram of the structure of a semiconductor device according to the present invention is shown.

[0017] Component designation 1 Semiconductor substrate 2. Tunnel 3 First gate 4 Second gate 5 Semiconductor layer 6. Heavily doped semiconductor layer D1 First Output Terminal D2 Second Output Terminal Detailed Implementation

[0018] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments of the present invention and the features thereof can be combined with each other.

[0019] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0020] An existing bidirectional trench gate power MOSFET uses a split-gate structure, such as Figure 1 As shown, a typical bidirectional trench-gate power MOSFET device uses the sources of adjacent power MOSFETs connected in a back-to-back mode. Figure 1Both "Drain 1" and "Drain 2" are on the device surface. The device gate design adopts a split-gate design structure. "Gate 2" is a channel control gate. A control channel is formed at the bottom of "Gate 2" in the bottom region of the trench to control the switching of the device. "Gate 1" near the top of the trench is a source gate (grounded) with field plate function. Through the field plate depletion effect of "Gate 1", it assists the breakdown voltage of the PN junction formed by the N well and P substrate. When the device is in operation, when the device is turned on, "gate 2" controls the opening and closing of the channel at the bottom of the gate, so that the current flows from "drain 1" to "drain 2" or from "drain 2" to "drain 1", satisfying the bidirectional current flow requirement. When the device is turned off, the device breakdown voltage is borne by the P substrate and N well. By selecting appropriate P substrate material resistivity and N well concentration design, the breakdown voltage requirement of typical bidirectional conduction devices is met, usually 30-50V. At the same time, in order to achieve low on-resistance characteristics, the gate structure of the device adopts a split-gate structure design, in which "gate 1" is connected to the source gate (grounded), realizing the field plate depletion effect of the "N well" drift region. In this way, even when the N well uses a high doping concentration, the expected breakdown voltage can still be maintained.

[0021] However, for power MOSFETs, there is an inherent contradiction between breakdown voltage and low on-resistance: reducing on-resistance requires increasing the doping concentration of the drift region (i.e., N-well) to facilitate current flow, but excessive doping concentration will prevent the depletion region from widening sufficiently, weakening the breakdown voltage of the device. Existing split-gate structures rely solely on the unilateral depletion effect of the source gate on the drift region to alleviate this contradiction, with limited depletion effect, making it difficult to maintain sufficient breakdown voltage margin while further increasing the doping concentration of the drift region.

[0022] Therefore, there is a need for a device structure that can simultaneously improve the breakdown voltage and reduce the on-resistance in a bidirectional power MOSFET. Based on the above structure, this invention fully considers the design requirements of on-resistance and breakdown voltage. It adopts a P-type epitaxial filling structure added to the N-type drift region. By locally grooving and realizing the epitaxial P-type filling design, a P-type structure region is added to the N-type drift region. This region effectively depletes the highly doped N-type drift region, which can further increase the doping concentration of the N-type drift region. At the same time, the P-type structure region is used to realize the effect of local superjunction design, which can further reduce the device on-resistance and improve the breakdown voltage.

[0023] First Embodiment

[0024] like Figure 2 As shown, an embodiment of the present invention discloses a semiconductor device, comprising: Semiconductor substrate 1; A well region 2 of the first conductivity type is located in the semiconductor substrate 1; A plurality of trench gate structures are located within a well region 2 and spaced apart. The trench gate structure includes: a trench located within a semiconductor substrate, the trench extending from the surface of the semiconductor substrate 1 into the semiconductor substrate 1 and beyond the well region 2; a first gate 3 and a second gate 4 located within the trench, wherein the first gate 3 is near the top of the trench and the second gate is near the bottom of the trench; and a dielectric layer isolating the first gate 3 from the second gate 4, the first gate 3 from the semiconductor substrate 1, and the second gate 4 from the semiconductor substrate 1. The first output electrode D1 and the second output electrode D2 are located on the surface of well region 2; The semiconductor layer 5 is located within the well region 2. The semiconductor layer 5 is of the second conductivity type, and the first conductivity type is the opposite of the second conductivity type.

[0025] It should be noted that in the bidirectional trench gate power MOSFET device provided in this embodiment, both the semiconductor substrate 1 and the semiconductor layer 5 are P-type doped; the well region 2 is an N-type semiconductor.

[0026] Specifically, the semiconductor substrate 1 is a P-type substrate, and an N-type well region 2, i.e. an N-type drift region, is formed in the semiconductor substrate 1 through processes such as diffusion.

[0027] Furthermore, in this embodiment, the first gate 3 and the second gate 4 form a split gate structure, wherein the first gate 3 is used as a field plate and the second gate 4 is used as a control switch; electrically, the first gate 3 is connected to the ground terminal to exert the field plate effect in the high voltage cut-off state; the bottom of the second gate 4 extends into the region of the semiconductor substrate 1 where the well region 2 is not provided, and there is a longitudinal spatial overlap region with the semiconductor substrate 1.

[0028] Furthermore, in this embodiment, a first output electrode D1 and a second output electrode D2 are provided on the outermost layer of the well region 2. Below the metal contact area of ​​D1 and D2, a surface high-concentration doped layer region is specially created by high-dose ion implantation, which corresponds to the semiconductor heavily doped layer 6. The doping concentration of the semiconductor heavily doped layer 6 region is extremely high, which can make the barrier at the metal-semiconductor contact interface extremely thin. Electrons can achieve ultra-low impedance bidirectional ohmic contact through the tunneling effect, effectively reducing the lead-out resistance. In this way, low resistance and completely symmetrical bidirectional unobstructed conduction are achieved between the metal and the semiconductor.

[0029] Furthermore, in this embodiment, the second conductivity type semiconductor layer 5 located in the filling trench (not shown) is specifically filled with, for example, P-type silicon material, wherein the filling trench is located between two adjacent trenches, and the bottom longitudinal depth of the filling trench is less than the bottom longitudinal depth of the well region 2.

[0030] Furthermore, in this embodiment, the first gate 3 and the well region 2 are arranged laterally, and the second gate 4 overlaps with the semiconductor substrate 1 to form a control channel for bidirectional flow of control current in the overlapping area of ​​the semiconductor substrate 1.

[0031] It should be noted that, in this embodiment, the first gate 3 faces the well region 2 laterally to exert the field plate effect in the off state of the semiconductor device, so as to cooperate with the semiconductor layer 5 to deplete the charge in the well region 2 laterally; the bottom of the second gate 4 overlaps with the semiconductor substrate 1, so as to form a longitudinal control channel in the overlapping area of ​​the semiconductor substrate 1 in the on state, so as to control the bidirectional current between the first output electrode D1 and the second output electrode D2 of the device.

[0032] According to an embodiment of the present invention, the semiconductor layer 5 and the well region 2 constitute a local superjunction structure for assisting in the depletion of the well region 2, wherein the doping concentration of the semiconductor layer 5 is matched with the doping concentration of the well region 2.

[0033] It should be noted that, in this embodiment, the doping concentration range of the well region 2 is [range missing]. .

[0034] It should be noted that, in this embodiment, when the second output electrode D2 is shorted to the semiconductor substrate 1 and the second gate 4 is turned on, the current flows from the first output electrode D1 to the second output electrode D2; when the first output electrode D1 is shorted to the semiconductor substrate 1 and the second gate 4 is turned on, the current flows from the second output electrode D2 to the first output electrode D1.

[0035] Specifically, in one embodiment of the invention, the bidirectional trench gate power MOSFET structure operates as follows in the on and off states: In the on state, a gate voltage higher than the threshold voltage is applied to the second gate 4. A conductive channel is formed in the region of the semiconductor substrate 1 adjacent to the sidewall of the dielectric layer of the second gate 4, connecting the two well regions 2. Current flows from the first output electrode D1 into one well region 2, through the channel into the other well region 2, and finally flows out from the second output electrode D2. In the reverse conduction state, the current path is reversed, which will not be described in detail. In the on state, the semiconductor layer 5 in the well region 2 does not participate in current transport. The current flows along the region of the well region 2 except for the semiconductor layer 5. Since the well region 2 uses a high doping concentration, the carrier concentration in the current channel is high and the on resistance is low.

[0036] In the off state, the gate voltage of the second gate 4 is lower than the threshold voltage or zero, the conductive channel disappears, and the current path between the two well regions 2 is broken. At this time, if an external voltage is applied between the first output electrode D1 and the second output electrode D2, the PN junction between the well region 2 and the semiconductor substrate 1 is reverse biased, and the depletion region expands from the PN junction interface to both sides to bear the external voltage. At the same time, the gate conductor of the first gate 3 is at the source potential, which applies a field plate depletion effect to the adjacent well region 2, and assists in the depletion of carriers in the well region 2.

[0037] In the off state, the PN junction between the semiconductor layer 5 and the well region 2 is also in a reverse bias state. The depletion region extends from the PN junction interface into the well region 2 and the interior of the semiconductor layer 5. The depletion effect of the semiconductor layer 5 on the well region 2 is superimposed on the depletion effect of the first gate 3, so that the high-concentration N-type doped carriers in the well region 2 are more fully depleted. Under the action of superjunction charge compensation, the N-type space charge in the well region 2 and the P-type space charge in the semiconductor layer 5 compensate each other. The depletion region can penetrate most of the well region 2, so that the device can still maintain the expected breakdown voltage under the condition of high doping concentration in the well region 2.

[0038] In some embodiments, with multiple semiconductor layers 5 disposed in each well region 2, the depletion regions of multiple PN junction interfaces in the cutoff state are interconnected, the depletion regions are more uniformly distributed in the lateral range of the well region 2, the uniformity of the electric field distribution is improved, and the withstand voltage capability of the device is further enhanced.

[0039] In this embodiment, a semiconductor layer 5 is introduced inside the well region 2 of the bidirectional trench gate power MOSFET. The semiconductor layer 5 and the well region 2 form a PN junction interface, constituting an approximate superjunction structure.

[0040] In the device cutoff state, the PN junction between semiconductor layer 5 and well region 2 is reverse biased, and the depletion region extends from the PN junction interface into the interior of well region 2. Together with the depletion effect of the first gate 3, it depletes well region 2. Because the superjunction structure utilizes the charge compensation principle of alternating lateral PN junctions, the P-type space charge in semiconductor layer 5 compensates for the N-type space charge in well region 2. Therefore, even if well region 2 uses a high doping concentration, the depletion region can still be sufficiently widened to withstand the applied voltage, and the device's withstand voltage capability is improved.

[0041] In the on-state of the device, because the doping concentration of well region 2 can be further increased without affecting the breakdown voltage, the carrier concentration in the current channel increases, the drift region resistance decreases, and the on-resistance of the device decreases.

[0042] Therefore, this embodiment overcomes the shortcomings of existing crack gate structures that rely solely on field plate depletion to maintain sufficient voltage margin under high-doped drift region conditions by setting an approximate superjunction structure with P-type silicon material filling in the N-type well region. It improves the current conduction capability while further enhancing the device's voltage withstand capability, achieving a balance between low on-resistance and high voltage withstand capability.

[0043] Second Embodiment

[0044] This embodiment specifically illustrates the fabrication method of the above-mentioned semiconductor device, including the following steps: A semiconductor substrate is provided, and a well region of a first conductivity type is formed in the semiconductor substrate; At least one filling trench is formed in the well region; A semiconductor material of a second conductivity type is filled into the filling trench to form a semiconductor layer, thereby forming a local superjunction structure between the semiconductor layer and the well region. A trench gate structure is formed in a semiconductor substrate. The trench gate structure includes: a trench located in the semiconductor substrate; a first gate and a second gate located in the trench, wherein the first gate is near the top of the trench and the second gate is near the bottom of the trench; and a dielectric layer located between the first gate and the second gate, the first gate and the inner wall of the trench, and the second gate and the inner wall of the trench. The first and second output electrodes are generated on the surface of the well region through a heavily doped semiconductor layer.

[0045] In this embodiment, a single-crystal silicon P-type semiconductor substrate can be selected. A thermally oxidized protective layer is formed on the surface of the P-type substrate. A photomask is used to locate the well region window to implant ions into the substrate, thereby forming a doping concentration range of [range missing]. N-type semiconductor.

[0046] Furthermore, the semiconductor substrate is etched to obtain trenches, and then a second gate, an isolation dielectric layer, and a first gate are formed within the trenches. The specific formation process can refer to the fabrication process commonly used in existing split-gate structures. In addition, the core innovation of this invention is that it also requires the creation of filling trenches to fill the semiconductor material of the second conductivity type, namely P-type silicon material. Since the first conductivity type is opposite to the second conductivity type, the semiconductor layer of the second conductivity type and the well region of the first conductivity type form a superjunction-like structure. This ensures that when the device is subjected to high voltage in reverse cutoff, the P-type filling region and the surrounding N-type well region can be completely drained laterally from each other based on the superjunction depletion principle, transforming into a fully depleted state.

[0047] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor substrate; A well region of a first conductivity type located in the semiconductor substrate; A plurality of trench gate structures are located within the well region and spaced apart. Each trench gate structure includes: a trench located within the semiconductor substrate, the trench extending from the surface of the semiconductor substrate into the semiconductor substrate and beyond the well region; a first gate and a second gate located within the trench; and a dielectric layer isolating the first gate from the second gate, the first gate from the semiconductor substrate, and the second gate from the semiconductor substrate. The first and second output electrodes are located on the surface of the well region; A semiconductor layer located within the well region, wherein the semiconductor layer is of a second conductivity type, and the first conductivity type is opposite to the second conductivity type.

2. A semiconductor device according to claim 1, characterized in that, The semiconductor device includes a bidirectional trench gate power MOSFET device, wherein the semiconductor substrate and the semiconductor layer include P-type semiconductors; and the well region includes N-type semiconductors.

3. A semiconductor device according to claim 1, characterized in that, The semiconductor layer and the well region constitute a local superjunction structure for assisting in the depletion of free carriers in the well region, wherein the doping concentration of the semiconductor layer matches the doping concentration of the well region.

4. A semiconductor device according to claim 3, characterized in that, The doping concentration range of the well region is: .

5. A semiconductor device according to claim 1, characterized in that, It also includes a filling trench located between two adjacent trenches, wherein the bottom longitudinal depth of the filling trench is less than the bottom longitudinal depth of the well region.

6. A semiconductor device according to claim 1, characterized in that, The first gate is located near the top of the trench, and the second gate is located near the bottom of the trench.

7. A semiconductor device according to claim 1, characterized in that, The first gate includes a field plate electrode that functions as a field plate, and the second gate includes a control electrode for a current-controlled switch.

8. A semiconductor device according to claim 1, characterized in that, It also includes a heavily doped semiconductor layer for generating the first output electrode or the second output electrode.

9. A semiconductor device according to claim 1, characterized in that, When the second output electrode is shorted to the semiconductor substrate and the second gate is turned on, current flows from the first output electrode to the second output electrode; when the first output electrode is shorted to the semiconductor substrate and the second gate is turned on, current flows from the second output electrode to the first output electrode.

10. A method for fabricating a semiconductor device, characterized in that, The method includes: A semiconductor substrate is provided, and a well region of a first conductivity type is formed in the semiconductor substrate; At least one filling trench is formed in the well region; A semiconductor material of a second conductivity type is filled into the filling trench to form a semiconductor layer, such that the semiconductor layer and the well region constitute a local superjunction structure. A trench gate structure is formed in a semiconductor substrate, the trench gate structure comprising: a trench located in the semiconductor substrate; a first gate and a second gate located in the trench; and a dielectric layer located between the first gate and the second gate, the first gate and the inner wall of the trench, and the second gate and the inner wall of the trench. The first and second output electrodes are generated on the surface of the well region through a heavily doped semiconductor layer.

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