A silicon carbide power device and chip with a grid-like cell sloping P-well region.

Abstract

This application belongs to the field of semiconductor technology and provides a silicon carbide power device and chip with a grid-like cell inclined P-well region. Multiple first junction field-effect regions and second junction field-effect regions are formed on the N-type drift region. The multiple first junction field-effect regions are arranged sequentially according to a first direction, and the multiple second junction field-effect regions are arranged sequentially according to a second direction. The first direction is perpendicular to the second direction, so that the interface between the inclined P-well region and the second junction field-effect region is a continuous inclined surface, thereby forming a grid-like cell inclined P-well region. This makes the edge of the inclined P-well region no longer a single-depth straight wall corner, but presents an effective large curvature radius transition with spatial expansion. The inclined interface bears the electric field, reducing the peak electric field of the gate dielectric layer and the device, and improving the reliability of the device.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a silicon carbide power device and chip with a grid-like cell inclined P-well region. Background Technology

[0002] Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have become core devices in high-voltage power electronic systems due to their excellent material properties (such as high critical breakdown electric field, high thermal conductivity, and high saturated electron drift velocity). Traditional planar gate devices have mature manufacturing processes, with the gate oxide layer located on a flat surface, resulting in a relatively uniform electric field distribution and good reliability. However, the JFET region between the P-wells exhibits a significant current contraction effect, leading to a higher specific on-resistance. Furthermore, the right-angled PN junction formed by the vertical sidewalls and bottom of the P-wells generates electric field concentration during reverse blocking, limiting further improvements in breakdown voltage. In contrast, trench gate devices, by embedding the gate within the SiC bulk, achieve smaller cell spacing and lower on-resistance.

[0003] However, the extremely high electric fields at the bottom and sharp corners of the trench in trench gate power devices pose a severe long-term reliability challenge to the gate oxide layer. The lack of overall design between the cell layout and the beveled profile of the P-well and the shape of the shallow source trench limits the improvement of power density and heat dissipation efficiency. Furthermore, the complex etching process results in high cost and low yield. Summary of the Invention

[0004] To address the aforementioned technical problems, this application aims to provide a silicon carbide power device with a grid-like cell inclined P-well region.

[0005] A first aspect of this application provides a silicon carbide power device with a grid-like cell inclined P-well region, the silicon carbide power device comprising: silicon carbide substrate; An N-type drift region is formed on the front side of the silicon carbide substrate; Multiple first junction field-effect regions and second junction field-effect regions are formed on the N-type drift region; wherein, the multiple first junction field-effect regions are arranged sequentially according to a first direction, and the multiple second junction field-effect regions are arranged sequentially according to a second direction, wherein the first direction is perpendicular to the second direction; A P-type heavily doped region is formed on the N-type drift region; A sloping P-type well region is formed on the N-type drift region, wherein the interface between the sloping P-type well region and the first junction field-effect region and the second junction field-effect region is a continuous sloping surface, and the sloping P-type well region is arranged around the P-type heavily doped region to form a grid-like cellular sloping P-well region. A gate dielectric layer, a gate polysilicon layer, and an interlayer dielectric layer are formed on the first junction field-effect region, the second junction field-effect region, the inclined P-type well region, and the N-type drift region, wherein the gate dielectric layer and the interlayer dielectric layer form a cavity structure to enclose the gate polysilicon layer and form a planar gate stack structure. A first electrode formed on the back side of the silicon carbide substrate; A second electrode is formed on the interlayer dielectric layer and the P-type heavily doped region, and the protrusion of the second electrode extends into the P-type heavily doped region; An N-type heavily doped region is formed within the sloping P-type well region and surrounds the protrusion of the second electrode, wherein the N-type heavily doped region and the second electrode are in an ohmic contact.

[0006] In some embodiments, the intersection region of the first direction and the second direction is the protrusion of the N-type drift region, the two first junction field-effect regions disposed opposite to each other in the first direction are isolated by the protrusion, and the two second junction field-effect regions disposed opposite to each other in the second direction are isolated by the protrusion.

[0007] In some embodiments, the intersection region of the first direction and the second direction is the P-type heavily doped region.

[0008] In some embodiments, the silicon carbide power device further includes a P-pillar formed below the sloping P-type well region and extending into the N-type drift region.

[0009] In some embodiments, the first junction field-effect region and the second junction field-effect region are portions of the N-type drift region, the P-pillars extend to the surface of the silicon carbide substrate, the P-pillars divide the N-type drift region into a plurality of N-pillars, and the N-pillars and the P-pillars are alternately arranged in the first direction or the second direction.

[0010] In some embodiments, a P-type blocking region is further provided at the intersection of the first junctional field-effect region arranged along the first direction and the second junctional field-effect region arranged along the second direction on the horizontal cross section.

[0011] In some embodiments, the interface between the inclined P-well region and the second junction field-effect region is any one of a linear inclined plane, a continuous inclined plane, a continuous curved inclined plane, or a continuous irregular inclined plane.

[0012] In some embodiments, the doping concentration of the sloping P-well region gradually increases from the side away from the heavily doped P-type region to the side closer to the heavily doped P-type region.

[0013] In some embodiments, the doping concentration of the sloped P-well region gradually decreases from the direction near the slope to the direction away from the slope.

[0014] A second aspect of this application also provides a chip, including a silicon carbide power device with a grid-like cell sloped P-well region as described in any of the preceding claims.

[0015] The beneficial effects of this application embodiment compared with the prior art are as follows: multiple first junction field-effect regions and second junction field-effect regions are formed on the N-type drift region. The multiple first junction field-effect regions are arranged sequentially according to a first direction, and the multiple second junction field-effect regions are arranged sequentially according to a second direction. The first direction is perpendicular to the second direction, so that the interface between the inclined P-type well region and the second junction field-effect region is a continuous inclined surface, thereby forming a grid-like cell inclined P-well region. This makes the edge of the inclined P-type well region no longer a single-depth straight wall corner, but presents an effective large curvature radius transition with spatial expansion. The inclined interface bears the electric field, reducing the overall electric field peak of the gate dielectric layer and the device, and improving the reliability of the device. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of a silicon carbide power device with a grid-like cell sloped P-well region provided in one embodiment of this application. Figure 1 ; Figure 2 This is a schematic diagram of the structure of a silicon carbide power device with a grid-like cell sloped P-well region provided in one embodiment of this application. Figure 2 ; Figure 3 This is a schematic diagram of the structure of a silicon carbide power device with a grid-like cell sloped P-well region provided in one embodiment of this application. Figure 3 ; Figure 4 This is a schematic diagram of the structure of a silicon carbide power device with a grid-like cell sloped P-well region provided in one embodiment of this application. Figure 4 ; Figure 5 This is a schematic diagram of the structure of a silicon carbide power device with a grid-like cell sloped P-well region provided in one embodiment of this application. Figure 5 ; Figure 6 This is a schematic diagram of the structure of a silicon carbide power device with a grid-like cell sloped P-well region provided in one embodiment of this application. Figure 6 ; Figure 7a This is a schematic diagram (7) of the structure of a silicon carbide power device with a grid-like cell inclined P-well region provided in one embodiment of this application; Figure 7b This is a schematic diagram of the structure of a silicon carbide power device with a grid-like cell sloped P-well region provided in one embodiment of this application. Figure 8 ; Figure 7c This is a schematic diagram of the structure of a silicon carbide power device with a grid-like cell sloped P-well region provided in one embodiment of this application. Figure 9 ; Figure 8 This is a schematic diagram of the doping concentration distribution of a silicon carbide power device with a P-type well region formed by planar implantation and a silicon carbide power device with a P-type well region formed by tilted implantation, provided in one embodiment of this application. Figure 9 This is a schematic diagram of the electric field distribution of a silicon carbide power device with a P-type well region formed by planar implantation and a silicon carbide power device with a P-type well region formed by tilted implantation, provided in one embodiment of this application. Figure 10 This is a schematic diagram of the breakdown voltage curves of a silicon carbide power device with a P-type well region formed by tilted injection and a P-type well region formed by planar injection, according to an embodiment of this application. Figure 11a This is a schematic diagram of the electric field peak of the gate dielectric layer of a silicon carbide power device with a P-type well region formed by planar implantation according to an embodiment of this application; Figure 11b This is a schematic diagram of the electric field peak of the gate dielectric layer of a silicon carbide power device with a P-type well region formed by tilted injection, provided in one embodiment of this application. Detailed Implementation

[0017] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0018] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0019] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means one or more, unless otherwise explicitly specified.

[0021] In this specification, references to "one embodiment," "some embodiments," or simply "embodiment" mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," "in a particular embodiment," and "in a particular application," appearing in various parts of this specification, do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, specific features, structures, or characteristics may be combined in any suitable manner.

[0022] While traditional trench MOSFETs reduce on-resistance, they introduce more severe reliability challenges. For example, the electric field strength at the corners of the trench bottom is much higher than that of a planar gate, causing the gate oxide to experience significant voltage stress. To alleviate this problem, a double-trench structure is usually required. Although the double-trench structure alleviates the gate oxide electric field, it increases the process complexity, and the deeper source trench can easily introduce new leakage paths. However, regardless of the form factor, when the device is off-state, significant electric field concentration occurs near the gate oxide / semiconductor interface, as well as at the edges and corners of the PN junctions of P-well and N-drift.

[0023] To address the aforementioned technical problems, embodiments of this application provide a silicon carbide power device with a grid-like cell inclined P-well region. Figure 1 The schematic structure (a) in the diagram is a schematic structure of the horizontal cross-section of a silicon carbide power device. Figure 1 The schematic structure (b) in the diagram is a schematic structure of section A. Figure 1 The schematic structure (c) in the diagram is a schematic structure of section B. See [link / reference]. Figure 1As shown, the silicon carbide power device in this embodiment includes: a silicon carbide substrate 110, an N-type drift region 210, a first junction field-effect region 221, a second junction field-effect region 222, a heavily doped P-type region 310, a sloped P-type well region 410, a heavily doped N-type region 510, a gate dielectric layer 611, an interlayer dielectric layer 612, a gate polysilicon layer 620, a first electrode 710, and a second electrode 720.

[0024] An N-type drift region 210 is formed on the front side of a silicon carbide substrate 110. Multiple first junction field-effect regions 221 and second junction field-effect regions 222 are formed on the N-type drift region 210. The multiple first junction field-effect regions 221 are arranged sequentially along a first direction, and the multiple second junction field-effect regions 222 are arranged sequentially along a second direction, with the first direction perpendicular to the second direction. A sloped P-type well region 410 is formed on the N-type drift region, and the interface between the sloped P-type well region 410 and the second junction field-effect regions 222 is a continuous sloped surface. A heavily doped P-type region 310 is formed on the N-type drift region 210, and the heavily doped P-type region 310 is disposed adjacent to the sloped P-type well region 410. The interface between the sloping P-type well region 410 and the first junction field-effect region 221 and the second junction field-effect region 222 is a continuous sloping surface. The sloping P-type well region 410 is arranged around the P-type heavily doped region 310 to form a grid-like cellular sloping P-well region.

[0025] A gate dielectric layer 611 and a gate polysilicon layer 620 are formed on a first junction field-effect region 221, a second junction field-effect region 222, a sloped P-type well region 410, and an N-type drift region 210. The gate dielectric layer 611 and the interlayer dielectric layer 612 form a cavity structure to enclose the gate polysilicon layer 620, thus forming a planar gate stack structure on the channel region within the sloped P-type well region 410. A first electrode 710 is formed on the back side of the silicon carbide substrate 110, and a second electrode 720 is formed on the interlayer dielectric layer 612 and the heavily doped P-type region 310, with the protrusion of the second electrode 720 extending into the heavily doped P-type region 310. An heavily doped N-type region 510 is formed within the sloped P-type well region 410 and surrounds the protrusion of the second electrode 720, with an ohmic contact between the heavily doped N-type region 510 and the second electrode 720.

[0026] In this embodiment, multiple first junction field-effect regions 221 are arranged sequentially along a first direction, and multiple second junction field-effect regions 222 are arranged sequentially along a second direction. The first direction is perpendicular to the second direction, so the interface between the inclined P-type well region 410 and the second junction field-effect region 222 is a continuous inclined surface, thus forming a grid-like cell inclined P-type well region 410. This makes the edge of the inclined P-type well region no longer a single-depth straight wall corner, but presents an effective large radius of curvature transition with spatial expansion, and the electric field is borne by its inclined interface. Since N-type junction field-effect regions (first junction field-effect region 221, second junction field-effect region 222) are arranged between the inclined P-type well regions 410 of adjacent grid-like cells, the junction field-effect region injection (JFET IMP) forms a low-resistance current flow channel. The inclined P-type well region 410 and the JFET injection region work together to ensure good channel pinch-off characteristics and reduce on-resistance. Thus, by utilizing the sloping P-type well region 410, a severe electric field concentration occurs at the corner position under blocking voltage, which reduces the device breakdown voltage. Furthermore, under short-circuit and UIS avalanche conditions, the sloping P-type well region 410 leads to concentrated collisional ionization and heat generation at the corner. Compared to the stepped P-well structure, the grid-like cellular sloping P-type well region 410 in this embodiment helps reduce the overall electric field peak of the gate dielectric layer and the device, thereby improving device reliability.

[0027] In some embodiments, the thickness of the second junction field-effect region 222 gradually decreases from the side away from the heavily doped p-type region 310 to the side closer to the heavily doped p-type region 310. Figure 1 As shown in the schematic structure (b), the second junction field-effect region 222 includes a vertical portion and an inclined portion. The thickness of the inclined portion gradually decreases from the side away from the heavily doped P-type region 310 to the side closer to the heavily doped P-type region 310. The lower surface of the vertical portion contacts the N-type drift region 210, and the upper surface of the vertical portion contacts the gate dielectric layer 611. The contact surface between the inclined portion and the inclined P-type well region 410 is an inclined surface. By setting this inclined P-type well region 410, it serves as an "electric field venting channel" for the entire device structure. When a blocking voltage is applied, the high potential of the second electrode 720 splits and shunts in both the vertical and horizontal directions along the inclined surface, completely changing the slope of the equipotential line and cutting off the risk of electric field breakdown at the sharp corner of the dielectric layer from the source.

[0028] In this embodiment, the inclined P-type well region 410 with a sloping structure and shallow trench structure are combined with a planar gate structure, and the inclined P-type well region 410 with a sloping structure is used as an "electric field drainage channel" for the entire device structure. Since the second electrode 720 extends along the top and side of the interlayer dielectric layer 612 to the heavily doped P-type region 310 and contacts the heavily doped N-type region 510, when a blocking voltage is applied, the high potential of the first electrode 710 splits and shunts the current in both the up and down directions along the sloping surface, completely changing the slope of the equipotential line and cutting off the risk of electric field breakdown at the sharp corner of the dielectric layer from the source.

[0029] In some embodiments, the intersection of the first direction and the second direction is a protrusion of the N-type drift region 210.

[0030] In this embodiment, combined with Figure 1 As shown in the schematic structure (a), the first junction field-effect region 221 and the second junction field-effect region 222 are rectangular in horizontal cross-section. The long side of the first junction field-effect region 221 is horizontally aligned with the first direction, and the long side of the second junction field-effect region 222 is horizontally aligned with the second direction. A protrusion of the N-type drift region 210 is located between two opposing first junction field-effect regions 221 in the first direction, and a protrusion of the N-type drift region 210 is located between two opposing second junction field-effect regions 222 in the second direction. This allows the active region cell to... The arrangement is set as a continuous grid of cells, forming a conductive channel within the open window enclosed by each grid, and the P-well region within the window is constructed as a sloping P-type well region 410. In the top view, the junction depth / doping concentration surface of the sloping P-type well region 410 changes continuously or stepwise-approximately continuously with the radial / diagonal distance from the center of the window (or from the open axis of the JFET), forming a "slope" from the window side outward, so that the edge of the sloping P-type well region 410 is no longer a single-depth straight wall corner, but presents an effective large curvature radius transition of spatial expansion.

[0031] In some embodiments, combined with Figure 1 As shown in schematic structures (b) and (c), the first junction field-effect region 221 has a cross-sectional shape that is narrower at the top and wider at the bottom in the second direction, and the second junction field-effect region 222 has a cross-sectional shape that is narrower at the top and wider at the bottom in the first direction. Since the P-type well region is divided into four parts by the first junction field-effect region 221 and the second junction field-effect region 222, the inclined P-type well region 410 is adjacent to the first junction field-effect region 221 and the second junction field-effect region 222. Thus, the inclined P-type well region 410 has a shape that is wider at the top and narrower at the bottom.

[0032] In this embodiment, through an innovative layout structure and P-type well region design, multiple cells are arranged in a grid array, rather than the traditional strip or single-cell structure. This layout significantly increases the channel width per unit area, thereby improving current density. While maintaining the advantages of planar gate technology, it effectively improves the electric field distribution, reduces on-resistance, and enhances device reliability and current handling capability.

[0033] In some embodiments, the P-well region of each cell has sloping sidewalls, combined with Figure 1 As shown in schematic structures (b) and (c), the interface between the sloping P-well region 410 and the junction field-effect region (JFET region) is sloping. This structure can smooth the electric field spike at the bottom of the P-well region, reduce the maximum electric field strength borne by the gate oxide layer, and thus improve the breakdown voltage and long-term reliability of the device. Furthermore, a grid-like cell layout is formed using the first JFET region 221 and the second JFET region 222. The grid structure provides more parallel current paths, enabling the device to carry a larger current in the same chip area, increasing the channel density. At the same time, combined with the sloping P-well region, the current diffusion path is optimized, effectively reducing the JFET region resistance and the overall on-resistance. Thus, by optimizing the electric field distribution and lowering the parasitic capacitance (Cgd), a faster switching speed can be achieved, thereby reducing switching losses.

[0034] In some embodiments, Figure 2 The schematic structure (a) in the diagram is a schematic structure of the horizontal cross-section of a silicon carbide power device. Figure 2 The schematic structure (b) in the diagram is a schematic structure of section A. Figure 2 The schematic structure (c) in the diagram is a schematic structure of section B. See [link / reference]. Figure 2 As shown, the intersection of the first direction and the second direction is the inclined P-type well region 410. The inclined P-type well region 410 extends along the upper second junction field-effect region 222 to the lower second junction field-effect region 222 in the second direction. In the first direction, the interface between the inclined P-type well region 410 and the adjacent second junction field-effect region 222 or the first junction field-effect region 221 is an inclined surface.

[0035] In this embodiment, combined with Figure 2 In the schematic structure (c), the intersection area of ​​the first direction and the second direction is set as a sloping P-type well region 410. Furthermore, in the four directions of the horizontal plane, the sloping P-type well region 410 has the characteristic of being wider at the top and narrower at the bottom. By using the sloping P-type well region 410 at the intersection area, the two first junction field-effect regions 221 arranged opposite to each other in the first direction can be isolated, and the two second junction field-effect regions 222 arranged opposite to each other in the second direction can also be isolated.

[0036] In some embodiments, Figure 3The schematic structure (a) in the diagram is a schematic structure of the horizontal cross-section of a silicon carbide power device. Figure 3 The schematic structure (b) in the diagram is a schematic structure of section A. Figure 3 The schematic structure (c) in the diagram is a schematic structure of section B. See [link / reference]. Figure 3 As shown, the silicon carbide power device also includes a P-pillar 400 formed below the sloping P-type well region 410 and extending into the N-type drift region 210.

[0037] In this embodiment, combined with Figure 3 As shown in the schematic structure (c), the sloping P-type well region 410 has a wider top and narrower bottom. Utilizing the sloping P-type well region 410 at the intersection, two first junction field-effect regions 221 arranged opposite each other in the first direction can be isolated, as can two second junction field-effect regions 222 arranged opposite each other in the second direction. The depth of the heavily doped P-type region 310 is the same as the depth of the junction field-effect region. The heavily doped P-type region 310 also forms P-pillars 400, which extend into the N-type drift region 210. Thus, by forming the P-pillars 400 of the semi-superjunction through high-energy ion implantation, and combining the sloping P-type well region 410 with the superjunction structure, a higher breakdown voltage can be achieved while maintaining a lower on-resistance.

[0038] In some embodiments, Figure 4 The schematic structure (a) in the diagram is a schematic structure of the horizontal cross-section of a silicon carbide power device. Figure 4 The schematic structure (b) in the diagram is a schematic structure of section A. Figure 4 The schematic structure (c) in the diagram is the schematic structure of section B. Figure 4 The schematic structure (d) in the diagram is a schematic structure of section C. See [link / reference]. Figure 4 As shown, the intersection region of the first direction and the second direction is the P-type heavily doped region 310.

[0039] In this embodiment, the second electrode 720 covers the entire upper surface of the device. A portion of the protrusion of the second electrode 720 extends into the P-type heavily doped region 310, and another portion extends into the N-type heavily doped region 510. The P-type heavily doped region 310, together with the first junction field-effect region 221 and the second junction field-effect region 222, divides the P-well into a grid-like inclined P-type well region 410. The junction depth / effective doping boundary of the inclined P-type well region 410 has a slope that varies with position in the top view. Through the smooth slope structure, the electric field transitions smoothly from the high-voltage region to the low-voltage region.

[0040] In some embodiments, Figure 5 The schematic structure (a) in the diagram is a schematic structure of the horizontal cross-section of a silicon carbide power device. Figure 5 The schematic structure (b) in the diagram is a schematic structure of section A. Figure 5The schematic structure (c) in the diagram is a schematic structure of section B. See [link / reference]. Figure 5 As shown, the second electrode 720 covers the entire upper surface of the device. The first junction field-effect region 221 and the second junction field-effect region 222 divide the P-well into a grid of inclined P-type well regions 410. In each grid of the inclined P-type well region 410, a heavily doped P-type region 310 and a heavily doped N-type region 510 are formed within the inclined P-type well region 410. A portion of the protrusion of the second electrode 720 extends into the heavily doped P-type region 310, and this portion of the protrusion of the second electrode 720 extends into the heavily doped N-type region 510, such that the heavily doped N-type region 510 surrounds the protrusion of the second electrode 720. The first junction field-effect region 221 and the second junction field-effect region 222 are portions of the N-type drift layer. The P-pillars 400 extend to the surface of the silicon carbide substrate 110, and the P-pillars 400 divide the N-type drift layer into multiple N-pillars 200. The N-pillars 200 and the P-pillars 400 are alternately arranged in a first direction or a second direction.

[0041] In this embodiment, alternating P-pillars and N-pillars (superjunction structure) are formed in the drift layer using multiple epitaxial or trench backfilling techniques. By combining the sloping P-type well region 410 with the superjunction structure, a higher breakdown voltage can be achieved while maintaining a lower on-resistance.

[0042] In some embodiments, Figure 6 The schematic structure (a) in the diagram is a schematic structure of the horizontal cross-section of a silicon carbide power device. Figure 6 The schematic structure (b) in the diagram is a schematic structure of section A. Figure 6 The schematic structure (c) in the diagram is the schematic structure of section B. Figure 6 The schematic structure (d) in the diagram is a schematic structure of section C. See [link / reference]. Figure 6 As shown, the second electrode 720 covers the entire upper surface of the device. A portion of the protrusion of the second electrode 720 extends into the heavily doped P-type region 310. The heavily doped P-type region 310, together with the first junction field-effect region 221 and the second junction field-effect region 222, divides the P-well into a grid-like sloping P-type well region 410. A portion of the protrusion of the second electrode 720 extends into the heavily doped P-type region 310, and an N-type heavily doped region 510 is formed in each grid of the sloping P-type well region 410. The P-pillars 400 extend to the surface of the silicon carbide substrate 110. The P-pillars 400 divide the N-type drift layer into multiple N-pillars 200. The N-pillars and P-pillars 400 are alternately arranged in the first direction or the second direction.

[0043] In some embodiments, a P-type blocking region is further provided at the intersection of the first junction field-effect region 221 arranged along the first direction and the second junction field-effect region 222 arranged along the second direction on the horizontal cross section.

[0044] In this embodiment, within the grid-like cells, the sloping P-type well region 410 of each cell can be formed through two or more ion implantations with different energies and doses, combined with a self-aligned sidewall process to form sloping sidewalls. A highly doped P-type blocking region (Block P) is introduced at or around the bottom of the sloping P-type well region 410, forming a three-tiered step-like doping distribution, thereby further enhancing the shielding effect of the P-well bottom on the electric field, suitable for high-voltage applications.

[0045] In some embodiments, combined with Figure 2 As shown, the doping concentration of the first junction field-effect region 221 and the second junction field-effect region 222 is greater than the doping concentration of the N-type drift region 210.

[0046] In some embodiments, the doping concentration of the portion of the first junction field-effect region 221 and the second junction field-effect region 222 near the gate dielectric layer 611 is greater than the doping concentration of the portion of the second junction field-effect region 222 far from the gate dielectric layer 611. In this case, the portion of the first junction field-effect region 221 and the second junction field-effect region 222 near the gate dielectric layer 611 can be a current spreading region.

[0047] In some embodiments, combined with Figure 2 As shown, the first junction field effect region 221 and the second junction field effect region 222 and the N-type drift region 210 can be integrally formed, and the first junction field effect region 221, the second junction field effect region 222 and the N-type drift region 210 are all part of the N-type drift layer.

[0048] In some embodiments, a second junction field-effect region 222 and a P-type heavily doped region 310 are formed on an N-type drift region 210. The P-type heavily doped region 310 is disposed adjacent to the second junction field-effect region 222, and the thickness of the second junction field-effect region 222 gradually decreases from the side away from the P-type heavily doped region 310 to the side closer to the P-type heavily doped region 310.

[0049] In some embodiments, see Figure 1 As shown, the second junction field-effect region 222 includes a vertical portion and an inclined portion. The vertical portion is located on the inclined portion. The inclined portion between adjacent inclined P-type well regions 410 has a cross-sectional structure that is narrower at the top and wider at the bottom. The thickness of the inclined portion gradually decreases from the side away from the heavily doped P-type region 310 to the side closer to the heavily doped P-type region 310. The lower surface of the vertical portion contacts the N-type drift region 210, and the upper surface of the vertical portion contacts the gate dielectric layer 611. The contact surface between the inclined portion and the inclined P-type well region 410 is an inclined surface. By setting this inclined P-type well region 410, it serves as an "electric field venting channel" for the entire device structure. When a blocking voltage is applied, the high potential of the first electrode 710 splits and shunts the current in both the vertical and horizontal directions along the inclined surface, completely changing the slope of the equipotential line and cutting off the risk of electric field breakdown at the sharp corner of the dielectric layer from the source.

[0050] In some embodiments, the second electrode 720 is the source electrode, the first electrode 710 is the drain electrode, and the gate dielectric layer 611 is a silicon oxide layer.

[0051] In this embodiment, the electric field of the device is mainly concentrated at the corner of the sloping P-type well region 410. In this embodiment, by forming a contact surface with an inclined angle at the interface between the sloping P-type well region 410 and the N-type drift layer, it is equivalent to turning the vertical blocking wall into a gentle slope. When the blocking voltage is applied, the high potential of the drain is bifurcated along the sloping surface in both the up and down directions, reducing the risk of electric field breakdown at the sharp corner of the gate dielectric layer 611.

[0052] In some embodiments, a sloped P-type well region 410 is formed on the second junction field-effect region 222, and an N-type heavily doped region 510 is formed on the sloped P-type well region 410. In this embodiment, the N-type heavily doped region 510 can be formed by implanting N-type dopant ions into the side of the sloped P-type well region 410 close to the P-type heavily doped region 310, and the concentration of N-type dopant ions in the N-type heavily doped region 510 is greater than the concentration of P-type dopant ions in the sloped P-type well region 410. The gate polysilicon layer 620 is disposed opposite to the sloped P-type well region 410.

[0053] In some embodiments, the second electrode 720 is formed on the gate dielectric layer 611 and the P-type heavily doped region 310, and the second electrode 720 has an L-shaped structure. The first electrode 710 is formed on the back side of the silicon carbide substrate 110.

[0054] In this embodiment, the second electrode 720 has an L-shaped structure. The horizontal portion of the second electrode 720 covers the gate dielectric layer 611, and the vertical portion of the second electrode 720 extends to the side of the gate dielectric layer 611 and contacts the P-type heavily doped region 310. The N-type heavily doped region 510 is located in the space formed by the inclined P-type well region 410, the second electrode 720, and the gate dielectric layer 611. By forming adjacent second junction field-effect regions 222 and P-type heavily doped regions 310 on the N-type drift region 210, and setting the thickness of the second junction field-effect region 222 to gradually decrease from the side away from the P-type heavily doped region 310 to the side closer to the P-type heavily doped region 310, a sloping P-type well region 410 is formed on the second junction field-effect region 222, thereby forming a sloping P-type well region 410 with a sloping interface. This allows the sloping interface of the sloping P-type well region 410 to bear the electric field, reducing the peak electric field of the gate dielectric layer 611 and the device, and improving the reliability of the device. Furthermore, by setting the second electrode 720 on its interlayer dielectric layer 612 to an L-shaped structure, the specific on-resistance of the device is reduced, thereby reducing its on-resistance at high temperatures while optimizing the current spread capability of the device.

[0055] In some embodiments, the thickness of the gate dielectric layer 611 between the gate polysilicon layer 620 and the second junction field-effect region 222 is less than the thickness of the interlayer dielectric layer 612 between the gate polysilicon layer 620 and the first electrode 710.

[0056] In this embodiment, the second electrode 720 extends through a channel to the heavily doped P-type region 310. The width of the vertical portion of the second electrode 720 is the same as the width of the heavily doped P-type region 310, but smaller than the width of the sloping P-type well region 410. Because the trench depth is strictly limited to less than 1 μm, the planar area required for a single cell is significantly reduced while ensuring good ohmic contact. This directly results in an extremely narrow cell pitch of ≤5 μm. Within this confined space, the JFET spacing of the device is reduced to <1.5 μm, greatly reducing the overall specific on-resistance of the device.

[0057] In some embodiments, the depth of the vertical portion of the second electrode 720 is less than 1 μm, and its depth range can be set to 0.2-0.8 μm.

[0058] In some embodiments, the upper surface of the N-type heavily doped region 510 is higher than the upper surface of the P-type heavily doped region 310, the gate dielectric layer 611 covers a portion of the N-type heavily doped region 510, the vertical portion of the second electrode 720 has a stepped structure, the horizontal portion of the second electrode 720 covers the interlayer dielectric layer 612, and the second electrode 720 extends stepwise from the upper surface and side surface of the interlayer dielectric layer 612 and the upper surface of the N-type heavily doped region 510 to the P-type heavily doped region 310.

[0059] In this embodiment, the vertical portion of the second electrode 720 has a stepped structure. The width of the gate dielectric layer 611 is less than the sum of the width of the second junction field-effect region 222 and the width of the inclined P-type well region 410. The height of the upper surface of the heavily doped P-type region 310 gradually increases from the upper surface of the interlayer dielectric layer 612, so that the vertical portion of the second electrode 720 has a stepped structure.

[0060] In some embodiments, the sloping P-type well region 410 is inclined, with an inclination angle between 1 and 30°. The total depth of the sloping P-type well region 410 is 1.2-2.5 μm, and the doping concentration of the sloping P-type well region 410 exhibits a gradient distribution, with the doping concentration near the channel being lower than the high concentration at the bottom. Thus, the geometry of the PN junction can be altered using the sloping structure, transforming the traditional vertical electric field distribution into an oblique electric field distributed along the sloping surface.

[0061] In some embodiments, the sloping P-type well region 410 is located between the vertical portion of the second junction field-effect region 222 and the heavily doped P-type region 310. The sloping P-type well region 410 includes a plurality of sub-well regions, and the doping concentration of the plurality of sub-well regions gradually increases from the second junction field-effect region 222 to the heavily doped P-type region 310.

[0062] In this embodiment, combined with Figure 7a As shown, the sloping P-type well region 410 includes a first sub-well region 411, a second sub-well region 412, and a third sub-well region 413. These three sub-well regions are arranged side-by-side in the vertical direction. The doping concentration of the second sub-well region 412 is lower than that of the first sub-well region 411, and the doping concentration of the third sub-well region 413 is lower than that of the second sub-well region 412. The third sub-well region 413 is located near the vertical portion of the second junction field-effect region 222, while the first sub-well region 411 is located near the heavily doped P-type region 310. This forms a three-tiered, stepped doping distribution. This structure further enhances the shielding effect of the P-well on the electric field. Especially in high-voltage applications, the first sub-well region 411 can serve as the main discharge channel. When the high voltage is interrupted, the first sub-well region 411 is depleted first, undertaking the main longitudinal withstand voltage task. In this way, the high electric field region can be transferred from the sensitive channel region to the depth of the device, protecting the channel from high field stress. The deep P-well structure provides a larger avalanche current distribution volume, improving the device's UIS (non-clamped inductive load switch) capability.

[0063] In some embodiments, the sloping P-type well region 410 is located between the vertical portion of the second junction field-effect region 222 and the heavily doped P-type region 310, and the doping concentration of the sloping P-type well region 410 gradually decreases from the N-type drift region 210 toward the heavily doped N-type region 510.

[0064] In some embodiments, the depth of the heavily doped P-type region 310 is greater than the depth of the sloping P-type well region 410. The doping concentration of the sloping P-type well region 410 gradually decreases from the N-type drift region 210 to the heavily doped N-type region 510. Its doping concentration is non-uniformly distributed, which realizes a smooth transition of the electric field from the high-voltage region to the low-voltage region. In this way, electric field spikes caused by abrupt changes in depth can be prevented, and the electric field can be balanced and managed. Moreover, gradient doping reduces interface states and lowers the reverse leakage current at high temperatures.

[0065] In this embodiment, combined with Figure 7bAs shown, the sloping P-type well region 410 includes a fourth sub-well region 414, a fifth sub-well region 415, and a sixth sub-well region 416. These sub-well regions 414, 415, and 416 are arranged sequentially along the sloping direction and are parallel to each other. The doping concentration of the fifth sub-well region 415 is lower than that of the fourth sub-well region 414, and the doping concentration of the sixth sub-well region 416 is lower than that of the fifth sub-well region 415. The fourth sub-well region 414 is close to the second junction field-effect region 222, forming an inclined interface between them. The sixth sub-well region 416 is close to the heavily doped N-type region 510. Thus, a three-level inclined doping distribution is formed. This structure further enhances the shielding effect of the P-well on the electric field. Especially in high-voltage applications, the fourth sub-well region 414 can serve as the main discharge channel. When the high voltage is interrupted, the fourth sub-well region 414 is depleted first, undertaking the main longitudinal withstand voltage task. In this way, the high electric field region can be transferred from the sensitive channel region to the depth of the device, protecting the channel from high field stress. The deep P-well structure provides a larger avalanche current distribution volume, improving the device's UIS (unclamped inductive load switch) capability.

[0066] In some embodiments, combined with Figure 7c As shown, the silicon carbide power device with a grid-like cell and sloping P-well region includes four cells, each cell comprising a sloping P-type well region 410. In the silicon carbide power device, the first and third sloping P-type well regions 410 include a first sub-well region 411, a second sub-well region 412, and a third sub-well region 413. The first and third sloping P-type well regions 410 are axially symmetrically arranged with the intersection of the first and second directions as the central symmetry point. The second and fourth sloping P-type well regions 410 include a fourth sub-well region 414, a fifth sub-well region 415, and a sixth sub-well region 416. The second and fourth sloping P-type well regions 410 are also axially symmetrically arranged with the intersection of the first and second directions as the central symmetry point. Utilizing this symmetrical structure, when a positive voltage is applied to the gate, an inversion channel is formed on the surface of the P-well of all cells. Electrons originate from the source, pass through the channel of each cell, and enter the drift layer below. Because the cells are arranged in a grid pattern, current can converge from all directions to the central drain, effectively creating a network of countless tiny MOSFETs operating in parallel. Due to the symmetrical doping arrangement of the sloping P-type well region 410, the electric field peak, which would otherwise be concentrated at a single point, can be dispersed over a larger area. This "flattens" the electric field distribution, significantly reducing the peak electric field intensity. This means that, for the same breakdown voltage design, a higher doping concentration drift layer can be used, further reducing the on-resistance.

[0067] In some embodiments, the interface between the inclined P-type well region 410 and the second junction field-effect region 222 is any one of a linear inclined surface, a continuous inclined surface, a continuous curved inclined surface, or a continuous irregular inclined surface.

[0068] In this embodiment, by setting the interface between the inclined P-type well region 410 and the second junction field-effect region 222 to any one of a linear inclined surface, a continuous inclined surface, a continuous curved inclined surface, or a continuous irregular inclined surface, a buffered slope structure can be formed. The interface between the inclined P-type well region 410 and the second junction field-effect region 222 extends slowly from the lower surface of the heavily doped P-type region 310 to the vertical part of the second junction field-effect region 222. The continuously inclined interface of the inclined P-type well region 410 can reduce the interface electric field spikes, so that the electric field transitions smoothly from the high-voltage region to the low-voltage region.

[0069] In some embodiments, the lower surface of the inclined P-type well region 410 is a continuous curved surface, which can be a regular curved surface or an irregular curved surface.

[0070] In this embodiment, by setting the lower surface of the sloping P-type well region 410 to be curved, a buffered slope structure can be formed. The lower surface of the sloping P-type well region 410 extends slowly from the lower left corner of the heavily doped P-type region 310 to the junction field-effect region. The continuously sloping interface of the sloping P-type well region 410 can reduce the interface electric field spikes, so that the electric field transitions smoothly from the high-voltage region to the low-voltage region.

[0071] In some embodiments, the interface between the inclined P-type well region 410 and the second junction field-effect region 222 is an arc surface, the thickness of the inclined P-type well region 410 is the same as the thickness of the second junction field-effect region 222, and the height of the arc surface between the inclined P-type well region 410 and the second junction field-effect region 222 is greater than half the thickness of the second junction field-effect region 222.

[0072] In this embodiment, the interface between the inclined P-type well region 410 and the second junction field-effect region 222 is an arc surface. The arc-shaped interface between the inclined P-type well region 410 and the second junction field-effect region 222 extends from the lower surface of the heavily doped P-type region 310 to the vertical portion of the second junction field-effect region 222. The interface between the vertical portion of the second junction field-effect region 222 and the inclined P-type well region 410 is linear. In this way, the continuously inclined P-type well region 410 interface can reduce the interface electric field spikes, so that the electric field transitions smoothly from the high-voltage region to the low-voltage region.

[0073] In some embodiments, the interface shape between the sloping P-type well region 410 and the second junction field-effect region 222 is a series of continuous arcs. The multiple arc interfaces are connected and extend from the lower surface of the heavily doped P-type region 310 to the vertical portion of the second junction field-effect region 222. The interface between the vertical portion of the second junction field-effect region 222 and the sloping P-type well region 410 is linear. In this way, the lower surface of the sloping P-type well region 410 is a stepped, continuously inclined arc interface, which can reduce the interface electric field peaks, balance the distribution of the internal electric field, and make the electric field transition smoothly from the high-voltage region to the low-voltage region.

[0074] In some embodiments, the thickness of the sloping P-type well region 410 is less than the thickness of the second junction field-effect region 222, and the interface depth between the heavily doped P-type region 310 and the second junction field-effect region 222 is greater than half the thickness of the heavily doped P-type region 310.

[0075] In this embodiment, the thickness of the sloping P-type well region 410 is less than the thickness of the second junction field-effect region 222. The sloping P-type well region 410 and the second junction field-effect region 222 are at an inclined interface. The inclined interface extends from a region at a depth higher than half the depth of the heavily doped P-type region 310 to the vertical part of the second junction field-effect region 222. Through gradient doping, the distribution of the internal electric field can be balanced, so that the electric field can smoothly transition from the high-voltage region to the low-voltage region.

[0076] In some embodiments, the thickness of the P-type heavily doped region 310 is greater than 2.5 μm.

[0077] In some embodiments, both the second junction field-effect region 222 and the N-type drift region 210 are N-type doped, and the second junction field-effect region 222 and the N-type drift region 210 are integrally formed. The heavily doped P-type region 310 extends from the silicon carbide substrate 110 to the second electrode 720. The first sub-well region 411 and the second sub-well region 412 of the inclined P-type well region 410 form a transverse trapezoidal structure, forming a superjunction structure. The interface between the inclined P-type well region 410 and the second junction field-effect region 222 is a continuous linear inclined plane with steps, thus forming a buffered slope structure. The interface between the inclined P-type well region 410 and the second junction field-effect region 222 extends stepwise from the lower surface of the gate dielectric layer 611 to the silicon carbide substrate 110. The continuously inclined P-type interface can reduce the interface electric field spikes, so that the electric field transitions smoothly from the high-voltage region to the low-voltage region.

[0078] In some embodiments, the silicon carbide substrate 110 is p-type doped, the second electrode 720 is the emitter, and the first electrode 710 is the collector.

[0079] In some embodiments, Figure 8This is a schematic diagram showing the doping concentration distribution of a silicon carbide power device with a P-type well region formed by planar implantation (schematic structure (a)) and a silicon carbide power device with a P-type well region formed by tilted implantation (schematic structure (b)) according to an embodiment of this application. Figure 8 As shown in the schematic structure (b), the lower surface of the inclined P-type well region 410 formed by the inclined injection angle is inclined, and the doping concentration of the inclined P-type well region 410 is gradient distributed, with the doping concentration near the channel being lower than the high concentration at the bottom.

[0080] In some embodiments, Figure 9 This is a schematic diagram of the electric field distribution of a silicon carbide power device with a P-type well region formed by planar implantation (schematic structure (a)) and a silicon carbide power device with a P-type well region formed by tilted implantation (schematic structure (b)) according to an embodiment of this application. Figure 10 This is a schematic diagram of the breakdown voltage curves of a silicon carbide power device with a P-type well region formed by tilted implantation and a P-type well region formed by planar implantation, provided in one embodiment of this application. Figure 9 and Figure 10 As shown, the silicon carbide power device in this embodiment has a sloping P-type well region 410 with an inclined shape. According to simulation results, under the same cell size, Figure 1 In the schematic structure (a), the voltage is borne by the P-type well region and the heavily doped P-type region, and its breakdown voltage (BVDSS) is 1551V (e.g., Figure 10 Curve a) in the figure has a threshold voltage of 2.85V and a specific on-resistance of 2.598 milliohms per square centimeter (mΩ·cm²). In this embodiment, through the inclined surface of the P-type well region 410, its breakdown voltage (BVDSS) is 1647V (e.g., ...). Figure 10 Curve b in the figure shows that the threshold voltage is 2.795V and the specific on-resistance is 2.3892 milliohms per square centimeter (mΩ·cm²). Compared with silicon carbide power devices with P-type well regions formed by planar implantation, the breakdown voltage and specific on-resistance of the device are slightly improved after tilted implantation.

[0081] Figure 11a This is a schematic diagram of the electric field peak of the gate dielectric layer of a silicon carbide power device with a P-type well region formed by planar implantation according to an embodiment of this application. Figure 11b This is a schematic diagram of the electric field peak of the gate dielectric layer of a silicon carbide power device with a P-type well region formed by tilted injection according to an embodiment of this application. The vertical axis X represents the vertical direction, and the horizontal axis Y represents the horizontal direction, with the unit being micrometers. Figure 11a and Figure 11bSimulation results show that the peak electric field of the gate dielectric layer of the silicon carbide power device with P-type well region formed by planar injection is 2.97MV / cm, while the peak electric field of the gate dielectric layer of the silicon carbide power device with P-type well region formed by tilted injection is 2.36MV / cm.

[0082] This application also provides a chip, including a silicon carbide power device as described in any of the above embodiments.

[0083] In some embodiments, the chip includes a chip substrate on which one or more silicon carbide device structures are disposed, the silicon carbide device structures including the silicon carbide device structures of any of the above embodiments.

[0084] In one specific application embodiment, when the silicon carbide substrate 110 is N-type doped, the silicon carbide device structure can be a MOS structure, with the second electrode 720 as the source and the first electrode 710 as the drain. When the silicon carbide substrate 110 is P-type doped, the silicon carbide device structure can be an IGBT structure, with the second electrode 720 as the emitter and the first electrode 710 as the collector.

[0085] Other related semiconductor devices, as well as MOSFETs, can be integrated on the chip substrate to form an integrated circuit.

[0086] In one specific application embodiment, the chip can be a switch chip or a driver chip.

[0087] In this embodiment, the silicon carbide power device includes a grid-like cell inclined P-well region within the chip. Multiple first junction field-effect regions and second junction field-effect regions are formed on the N-type drift region. The multiple first junction field-effect regions are arranged sequentially according to a first direction, and the multiple second junction field-effect regions are arranged sequentially according to a second direction. The first direction is perpendicular to the second direction, thus the interface between the inclined P-well region and the second junction field-effect region is a continuous inclined surface, forming a grid-like cell inclined P-well region. This makes the edge of the inclined P-well region no longer a single-depth straight-wall corner, but presents an effective large radius of curvature transition with spatial expansion. The inclined interface bears the electric field, reducing the overall electric field peak of the gate dielectric layer and the device, and improving the reliability of the device.

[0088] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0089] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A silicon carbide power device with a grid-like cell inclined P-well region, characterized in that, The silicon carbide power device includes: silicon carbide substrate; An N-type drift region is formed on the front side of the silicon carbide substrate; Multiple first junction field-effect regions and second junction field-effect regions are formed on the N-type drift region; wherein, the multiple first junction field-effect regions are arranged sequentially according to a first direction, and the multiple second junction field-effect regions are arranged sequentially according to a second direction, wherein the first direction is perpendicular to the second direction; A P-type heavily doped region is formed on the N-type drift region; A sloping P-type well region is formed on the N-type drift region; wherein the interface between the sloping P-type well region and the first junction field-effect region and the second junction field-effect region is a continuous sloping surface, and the sloping P-type well region is arranged around the P-type heavily doped region to form a grid-like cellular sloping P-well region. A gate dielectric layer, a gate polysilicon layer, and an interlayer dielectric layer are formed on the first junction field-effect region, the second junction field-effect region, the inclined P-type well region, and the N-type drift region, wherein the gate dielectric layer and the interlayer dielectric layer form a cavity structure to enclose the gate polysilicon layer and form a planar gate stack structure. A first electrode formed on the back side of the silicon carbide substrate; A second electrode is formed on the interlayer dielectric layer and the P-type heavily doped region, and the protrusion of the second electrode extends into the P-type heavily doped region; An N-type heavily doped region is formed within the sloping P-type well region and surrounds the protrusion of the second electrode, wherein the N-type heavily doped region and the second electrode are in an ohmic contact.

2. The silicon carbide power device with a grid-like cell inclined P-well region as described in claim 1, characterized in that, The intersection area of ​​the first direction and the second direction is the protrusion of the N-type drift region. The two first junction field-effect regions arranged opposite each other in the first direction are isolated by the protrusion, and the two second junction field-effect regions arranged opposite each other in the second direction are isolated by the protrusion.

3. The silicon carbide power device with a grid-like cell inclined P-well region as described in claim 1, characterized in that, The intersection region of the first direction and the second direction is the P-type heavily doped region.

4. The silicon carbide power device with a grid-like cell inclined P-well region as described in claim 1, characterized in that, The silicon carbide power device further includes a P-pillar formed below the sloped P-type well region and extending into the N-type drift region.

5. The silicon carbide power device with a grid-like cell inclined P-well region as described in claim 4, characterized in that, The first junction field-effect region and the second junction field-effect region are portions of the N-type drift region. The P-pillars extend to the surface of the silicon carbide substrate. The P-pillars divide the N-type drift region into multiple N-pillars. The N-pillars and the P-pillars are alternately arranged in the first direction or the second direction.

6. The silicon carbide power device with a grid-like cell inclined P-well region as described in claim 1, characterized in that, On the horizontal cross section, a P-type blocking region is also provided at the intersection of the first junction field-effect region arranged along the first direction and the second junction field-effect region arranged along the second direction.

7. The silicon carbide power device with a grid-like cell inclined P-well region as described in claim 1, characterized in that, The interface between the inclined P-well region and the second junction field-effect region can be any one of a linear inclined plane, a continuous inclined plane, a continuous curved inclined plane, or a continuous irregular inclined plane.

8. The silicon carbide power device with a grid-like cell inclined P-well region as described in claim 1, characterized in that, The doping concentration of the sloping P-well region gradually increases from the side away from the heavily doped P-type region to the side closer to the heavily doped P-type region.

9. The silicon carbide power device with a grid-like cell inclined P-well region as described in claim 1, characterized in that, The doping concentration of the sloped P-well region gradually decreases from the direction near the slope to the direction away from the slope.

10. A chip, characterized in that, The silicon carbide power device includes the grid-like cell inclined P-well region as described in any one of claims 1-9.

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