Transistor substrate, electronic device, and method for manufacturing transistor substrate

Abstract

A transistor substrate, an electronic device, and a method for manufacturing the transistor substrate are disclosed. The transistor substrate includes: a substrate; and a first active pattern disposed on the substrate. The first active pattern includes: a lower layer comprising an amorphous oxide semiconductor and having a first conductive region, a second conductive region, and a first channel region positioned between the first conductive region and the second conductive region; and an upper layer disposed on the lower layer and comprising a crystalline oxide semiconductor. The transistor substrate further includes: a first gate electrode disposed on the first active pattern and overlapping the first channel region in a plan view; a first connection electrode contacting the first conductive region; and a second connection electrode contacting the second conductive region. The first gate electrode and the first active pattern form a first transistor.

Description

Technical Field

[0001] Embodiments of this disclosure relate to transistor substrates. More specifically, embodiments of this disclosure relate to transistor substrates, electronic devices including transistor substrates, and methods of manufacturing transistor substrates. Background Technology

[0002] With the advancement of information technology, display devices, which serve as communication interfaces between users and digital information, have become increasingly important. As a result, the adoption of various types of display devices, such as liquid crystal displays (LCDs), organic light-emitting diode (OLED) displays, and plasma display panels, continues to increase.

[0003] Display devices typically include multiple pixels, and each pixel may include at least one thin-film transistor (TFT), at least one capacitor, and at least one light-emitting element. For example, the active pattern of the TFT can be formed using amorphous silicon or polycrystalline silicon. Recently, thin-film transistors using metal-oxide-semiconductor (MOS) semiconductors have been actively studied due to, for example, higher charge carrier mobility compared to amorphous silicon, lower manufacturing cost compared to polycrystalline silicon, and better uniformity across the substrate. Summary of the Invention

[0004] The various embodiments provide transistor substrates that can improve the characteristics of the driving transistors.

[0005] Various embodiments provide electronic devices including transistor substrates.

[0006] The embodiments provide methods for manufacturing transistor substrates.

[0007] A transistor substrate according to an embodiment of the present disclosure includes: a substrate; and a first active pattern disposed on the substrate and including: a lower layer comprising an amorphous oxide semiconductor and having a first conductive region, a second conductive region, and a first channel region positioned between the first conductive region and the second conductive region; and an upper layer disposed on the lower layer and comprising a crystalline oxide semiconductor. The transistor substrate further includes: a first gate electrode disposed on the first active pattern and overlapping the first channel region in a plan view, and forming a first transistor together with the first active pattern; a first connection electrode contacting the first conductive region; and a second connection electrode contacting the second conductive region.

[0008] In one embodiment, a first-first hole surrounded by a first conductive region and a second-first hole surrounded by a second conductive region may be defined in a lower layer, and a first-second hole exposing the first-first hole and a second-second hole exposing the second-first hole may be defined in an upper layer. The width of the first-first hole may be smaller than the width of the first-second hole, and the width of the second-first hole may be smaller than the width of the second-second hole.

[0009] In one embodiment, the first connecting electrode can contact the first conductive region through the first-second hole and can be non-overlapping with the first-first hole in a plan view. The second connecting electrode can contact the second conductive region through the second-second hole and can be non-overlapping with the second-first hole in a plan view.

[0010] In an embodiment, the first connecting electrode may face the second connecting electrode in one direction, and the length of the lower layer in one direction may be approximately equal to the length of the upper layer in one direction.

[0011] In an embodiment, the upper layer may include: a third conductive region that at least partially overlaps with the first conductive region in a plan view; a fourth conductive region that at least partially overlaps with the second conductive region in a plan view; and a second channel region that overlaps with the first channel region in a plan view.

[0012] In an embodiment, the transistor substrate may further include a gate insulating layer disposed between the first active pattern and the first gate electrode. A first opening exposing the third conductive region, the first-first via, and the first-second via, and a second opening exposing the fourth conductive region, the second-first via, and the second-second via may be defined within the gate insulating layer.

[0013] In this embodiment, the thickness of the upper layer can be less than approximately Within a certain range, and the thickness of the lower layer can be greater than approximately And less than approximately Within the range.

[0014] In an embodiment, the transistor substrate may further include: a second active pattern disposed on the substrate, comprising an amorphous oxide semiconductor and having a conductive region and a channel region; and a second gate electrode disposed on the second active pattern, overlapping the channel region in a planar view, and the second gate electrode together with the second active pattern constitutes a second transistor.

[0015] In an embodiment, the upper layer may include: a third conductive region that at least partially overlaps with the first conductive region in a plan view; a fourth conductive region that at least partially overlaps with the second conductive region in a plan view; and a second channel region that overlaps with the first channel region in a plan view.

[0016] In an embodiment, a first hole surrounded by a first conductive region and a second hole surrounded by a second conductive region may be defined in a lower layer, and a third hole surrounded by a conductive region may be defined in a second active pattern.

[0017] In one embodiment, a first step may exist between the end of the upper layer facing the first connecting electrode and the end of the first conductive region exposed by the first hole and facing the first connecting electrode. A second step may exist between the end of the upper layer facing the second connecting electrode and the end of the second conductive region exposed by the second hole and facing the second connecting electrode.

[0018] An electronic device according to an embodiment of the present disclosure includes: a display device; a power supply for supplying power to the display device; and a processor for controlling the display device. The display device includes: a substrate; a first active pattern disposed on the substrate and including: a lower layer comprising an amorphous oxide semiconductor and having a first conductive region, a second conductive region, and a first channel region positioned between the first conductive region and the second conductive region; and an upper layer disposed on the lower layer and comprising a crystalline oxide semiconductor; a first gate electrode disposed on the first active pattern, overlapping the first channel region in a plan view, and forming a first transistor together with the first active pattern; a first connection electrode contacting the first conductive region; and a second connection electrode contacting the second conductive region.

[0019] A method for manufacturing a transistor substrate according to an embodiment of the present disclosure includes: forming a first active pattern on a substrate, the first active pattern including a lower layer and an upper layer, the lower layer including an amorphous oxide semiconductor and having a first conductive region, a second conductive region and a first channel region positioned between the first conductive region and the second conductive region, the upper layer being disposed on the lower layer and including a crystalline oxide semiconductor; forming a first gate electrode on the first active pattern, overlapping the first channel region in a plan view and constituting a first transistor together with the first active pattern; and forming a first connection electrode contacting the first conductive region and a second connection electrode contacting the second conductive region.

[0020] In an embodiment, forming a first active pattern may include: forming a lower layer on a substrate and forming an upper layer on the lower layer; performing a thermal processing on the upper layer; forming a gate insulating layer covering the lower and upper layers; removing a portion of the gate insulating layer to form a first-second via and a second-second via that exposes at least a portion of the lower layer to the upper layer; forming a conductive layer on the gate insulating layer that fills the first-second via and the second-second via; and forming a photoresist pattern on the conductive layer. When the first-second via and the second-second via are formed, the portion of the lower layer exposed by the first-second via can become a first conductive region, and the portion of the lower layer exposed by the second-second via can become a second conductive region.

[0021] In an embodiment, after forming the conductive layer, the method may further include: using a photoresist pattern as a mask to remove a portion of each of the conductive layer, the first conductive region, and the second conductive region to form a first-first via exposed by the first-second via and a second-first via exposed by the second-second via in the lower layer; using the photoresist pattern as a mask to remove a first portion and a second portion of the gate insulating layer that overlaps with the first active pattern in a planar view; and removing the photoresist pattern. When the first portion and the second portion are removed, the portions of the lower layer that overlap with the first portion and the second portion in a planar view may respectively become the first conductive region and the second conductive region, and the portions of the upper layer that overlap with the first portion and the second portion in a planar view may respectively become the third conductive region and the fourth conductive region.

[0022] In an embodiment, the method may further include: forming a second active pattern on a substrate, the second active pattern comprising an amorphous oxide semiconductor and having a conductive region and a channel region; and forming a second gate electrode on the second active pattern, overlapping the channel region in a planar view, and together with the second active pattern constituting a second transistor.

[0023] In an embodiment, forming the second active pattern may include: forming a preliminary lower layer on a substrate; forming a preliminary upper layer on the preliminary lower layer; removing a portion of the preliminary lower layer to form the lower layer and the second active pattern, and simultaneously removing a portion of the preliminary upper layer to form an upper layer and a residual layer on the second active pattern; removing a portion and the entire residual layer of the upper layer; performing a thermal processing process on the upper layer; forming a gate insulating layer covering the lower layer, the upper layer, and the second active pattern; removing a portion of the gate insulating layer to expose a portion of the lower layer and a portion of the second active pattern; forming a conductive layer on the gate insulating layer; and forming a third photoresist pattern on the conductive layer. When a portion of the lower layer and a portion of the second active pattern are exposed, the exposed portion of the lower layer may become a first conductive region and a second conductive region, and the exposed portion of the second active pattern may become a conductive region.

[0024] In an embodiment, forming a lower layer, a second active pattern, an upper layer, and a residual layer may include: forming a photosensitive organic layer on a preliminary upper layer; exposing and developing the photosensitive organic layer using a halftone mask to form a first photoresist pattern and a second photoresist pattern with different thicknesses; using the first and second photoresist patterns as masks to remove a portion of each of the preliminary lower layer and the preliminary upper layer to form the lower layer, the second active pattern, the upper layer, and the residual layer; and removing a portion of the first photoresist pattern and the entire second photoresist pattern by an ashing process. Removing a portion of the upper layer and the entire residual layer may include: using the first photoresist pattern as a mask to remove a portion of the upper layer and the entire residual layer; and removing the first photoresist pattern. The first photoresist pattern may be formed in a region overlapping the lower and upper layers in a planar view, and the second photoresist pattern may be formed in a region overlapping the second active pattern and the residual layer in a planar view.

[0025] In an embodiment, after forming the conductive layer, the method may further include: using a third photoresist pattern as a mask to remove a portion of each of the conductive layer, the first conductive region, and the second conductive region to form a first via and a second via in the underlying layer, and a third via in the second active pattern; using the third photoresist pattern as a mask to remove a first portion and a second portion of the gate insulating layer that overlaps with the first active pattern in a plan view, and a portion of the gate insulating layer that overlaps with the second active pattern in a plan view; and removing the third photoresist pattern. During the formation of the first via, the second via, and the third via, the first via can be formed by removing a portion of the first conductive region, the second via by removing a portion of the second conductive region, and the third via by removing a portion of the conductive region.

[0026] In the embodiment, during the removal of the first part and the second part, the portions of the lower layer that overlap with the first part and the second part in the plan view can respectively become the first conductive region and the second conductive region, and the portions of the second active pattern that overlap with the gate insulating layer in the plan view can become conductive regions.

[0027] In embodiments of this disclosure, the transistors on the transistor substrate disposed in the display area may include active patterns comprising a lower layer containing amorphous oxide semiconductor and an upper layer containing crystalline oxide semiconductor. In this case, both the driving transistor and the switching transistor of the transistor substrate may have the same structure as the transistor. In embodiments of this disclosure, the first transistor on the transistor substrate disposed in the display area may include a first active pattern comprising a lower layer containing amorphous oxide semiconductor and an upper layer containing crystalline oxide semiconductor, and the second transistor may include a second active pattern having a single-layer structure containing amorphous oxide semiconductor. In this case, the driving transistor of the transistor substrate may have the same structure as the first transistor, and the switching transistor may have the same structure as the second transistor. Therefore, the driving range of the driving transistor can be expanded. Attached Figure Description

[0028] The above and other features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0029] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0030] Figure 2 It is shown Figure 1 A circuit diagram of a pixel included in a display device.

[0031] Figure 3 It shows along Figure 1 A cross-sectional view of an example section taken by line I-I'.

[0032] Figure 4 It is shown Figure 3 A plan view of the transistor substrate.

[0033] Figures 5 to 13 It shows the manufacturing process. Figure 3 A cross-sectional view of the method for using a transistor substrate.

[0034] Figure 14 It shows along Figure 1 A cross-sectional view of an example section taken by line I-I'.

[0035] Figures 15 to 29 It shows the manufacturing process. Figure 14 A cross-sectional view of the method for using a transistor substrate.

[0036] Figure 30 It shows along Figure 1 A cross-sectional view of an example section taken by line I-I'.

[0037] Figure 31It shows including Figure 1 A block diagram of the electronic device for displaying the device.

[0038] Figure 32 It is shown Figure 31 The electronic device is implemented as an example view of a television set.

[0039] Figure 33 It is shown Figure 31 The electronic device is implemented as an example view of a smartphone. Detailed Implementation

[0040] In the following description, embodiments of the present disclosure will be described more fully with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may refer to the same elements.

[0041] It will be further understood that when terms such as “comprising,” “including,” and “having” are used herein, it indicates the presence of the stated features, wholes, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0042] It will be understood that the terms “first,” “second,” “third,” etc., are used herein to distinguish one element from another, and these elements are not limited by these terms. Thus, a “first” element in one embodiment may be described as a “second” element in another embodiment.

[0043] It should be understood that, unless the context clearly indicates otherwise, the description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments.

[0044] Unless the context clearly indicates otherwise, the singular forms “a,” “one,” and “the” as used herein are also intended to include the plural forms.

[0045] For ease of description, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” and “above” may be used herein to describe the relationship of one element or feature to another element (or more elements) or feature (or more features) as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. For example, if the device in the drawings is flipped, an element described as “below,” “below,” or “below” other elements or features will subsequently be oriented “above” other elements or features. Thus, the example terms “below” and “below” can cover both above and below orientations.

[0046] It will be understood that when a component is referred to as being "on" another component, "connected to" another component, "coupled to" another component, or "adjacent to" another component, the component may be directly on, directly connected to, directly coupled to, or directly adjacent to the other component, or there may be intermediary components. It will also be understood that when a component is referred to as being "between" two components, the component may be the only component between the two components, or there may be one or more intermediary components. It will also be understood that when a component is referred to as "covering" another component, the component may be the only component covering the other component, or one or more intermediary components may also cover the other component. Other terms used to describe relationships between components should be interpreted in the same manner.

[0047] In this document, when two or more elements or values ​​are described as substantially the same or approximately equal to each other, it should be understood that these elements or values ​​are equivalent to each other, are equal to each other within measurement error, or, as will be understood by those skilled in the art, are sufficiently close in value to be functionally equal to each other if they are measurably unequal. For example, taking into account the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), the term “approximately” as used herein includes the stated value and means within an acceptable range of deviation for a particular value as determined by those skilled in the art. For example, “approximately” may mean within one or more standard deviations as understood by those skilled in the art, such as ±30%, ±20%, ±10%, or ±5% of the stated value. Furthermore, it should be understood that while a parameter may be described herein as having “approximately” a certain value, according to embodiments, as will be understood by those skilled in the art, the parameter may be exactly that value or approximate that value within measurement error. These terms, and other uses of similar terms, used to describe relationships between components, should be interpreted in the same manner.

[0048] Embodiments of this disclosure relate to thin-film transistors and display devices incorporating thin-film transistors, and more specifically, to novel active patterning structures configured to improve electrical performance and manufacturing uniformity.

[0049] In one embodiment, the active pattern of the thin-film transistor includes a lower layer formed of amorphous oxide semiconductor and an upper layer formed of crystalline oxide semiconductor. These layers are vertically stacked in a stacked configuration, allowing for the selective formation of conductive and channel regions in each layer through controlled hydrogen doping. This layered structure enables the lower layer to provide stable baseline conductivity, while the upper layer exhibits higher mobility due to its crystallinity, which is beneficial for improving the driving characteristics of the display device.

[0050] By separating the conductive region and the channel region across two oxide semiconductor layers of different crystallinity, the structure according to the embodiment can mitigate threshold voltage variations, increase current drive capability, and reduce image artifacts. The resulting improvements in transistor characteristics can enhance the performance of high-resolution displays (display devices) while maintaining compatibility with scalable and cost-effective manufacturing processes.

[0051] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0052] refer to Figure 1 According to embodiments of the present disclosure, the display device DD may include a substrate SUB, a plurality of pixels PX, a data line DL, a gate line GL, a gate driver GDV, and a data driver DDV.

[0053] The substrate SUB may include a display area DA and a peripheral area PA. The display area DA may be an area capable of displaying an image by generating light or by controlling the transmittance of light supplied from an external light source. The peripheral area PA may be an area where no image is displayed. The peripheral area PA may be positioned around the display area DA. For example, the peripheral area PA may completely surround the display area DA.

[0054] Multiple pixels PX can be set in the display area DA on the substrate SUB. The multiple pixels PX can be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1.

[0055] Each of the plurality of pixels PX may include a driving element (e.g., a driving thin-film transistor) that generates a driving current and a light-emitting element electrically connected to the driving element and generating light based on the driving current. Therefore, each of the plurality of pixels PX can emit light according to the driving current.

[0056] Drivers that drive multiple pixels (PX) can be located in the peripheral region (PA) on the substrate (SUB). For example, the drivers may include a gate driver (GDV) and a data driver (DDV).

[0057] The gate line GL can be electrically connected to the gate driver GDV and can extend along the first direction DR1. The gate line GL can receive scan signals from the gate driver GDV and transmit the scan signals to multiple pixels PX.

[0058] The data line DL can be electrically connected to the data driver DDV and can extend along the second direction DR2. The data line DL can receive data voltage from the data driver DDV and transmit the data voltage to multiple pixels PX.

[0059] For example, such as Figure 1As shown, in one embodiment, the data driver DDV can be directly disposed on the substrate SUB. In another embodiment, the data driver DDV can be disposed on a circuit board (e.g., a printed circuit board (PCB) or a flexible printed circuit board (FPCB)) that is electrically connected to pad electrodes disposed on one side of the peripheral region PA.

[0060] In this specification, a plane may be defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the first direction DR1 and the second direction DR2 may be perpendicular to each other. Furthermore, a third direction DR3 may be perpendicular to the plane.

[0061] Figure 2 It is shown Figure 1 A circuit diagram of a pixel included in a display device.

[0062] refer to Figure 2 Each pixel PX may include a pixel driving circuit section PC and a light-emitting element LED electrically connected to the pixel driving circuit section PC. The pixel driving circuit section PC can generate a driving current, and the light-emitting element LED can generate light based on the driving current.

[0063] The pixel driving circuit PC may include a first transistor T1, a second transistor T2 and a third transistor T3, a storage capacitor CST and a light-emitting capacitor CLED.

[0064] In this embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 may all be NMOS transistors. However, the embodiments of this disclosure are not necessarily limited thereto, and at least one of the first transistor T1, the second transistor T2, and the third transistor T3 may be a PMOS transistor, and the remaining transistors may be NMOS transistors.

[0065] In the case where the pixel driving circuit PC includes both NMOS transistors and PMOS transistors, the active pattern of the NMOS transistor may include oxide semiconductor, and the active pattern of the PMOS transistor may include silicon semiconductor. However, the embodiments of this disclosure are not necessarily limited thereto, and the active pattern of the NMOS transistor may include silicon semiconductor, and the active pattern of the PMOS transistor may include oxide semiconductor.

[0066] The first transistor T1 may include a first electrode, a gate electrode, and a second electrode. The gate electrode of the first transistor T1 may be connected to a first node N1. A drive voltage ELVDD may be applied to the first electrode of the first transistor T1. The second electrode of the first transistor T1 may be connected to a second node N2. The first transistor T1 may receive the drive voltage ELVDD from the drive voltage line in response to the voltage of the first node N1 and supply drive current to the light-emitting element LED. For example, the first transistor T1 may be a drive transistor for driving the light-emitting element LED.

[0067] The second transistor T2 may include a first electrode, a gate electrode, and a second electrode. A first scan signal SC may be applied to the gate electrode of the second transistor T2. A data voltage VDATA may be applied to the first electrode of the second transistor T2. The second electrode of the second transistor T2 may be connected to the first node N1. The second transistor T2 may be turned on by the first scan signal SC to electrically connect the data line providing the data voltage VDATA to the first node N1.

[0068] The third transistor T3 may include a first electrode, a gate electrode, and a second electrode. A second scan signal SS may be applied to the gate electrode of the third transistor T3. An initialization voltage VINT may be applied to the first electrode of the third transistor T3. The second electrode of the third transistor T3 may be connected to the second node N2. The third transistor T3 may be turned on by the second scan signal SS to electrically connect the initialization voltage line providing the initialization voltage VINT to the second node N2.

[0069] For example, each of the second transistor T2 and the third transistor T3 can be a switching transistor.

[0070] In an embodiment, the first electrode of each of the first transistor T1, the second transistor T2, and the third transistor T3 may be the drain electrode, and the second electrode of each of the first transistor T1, the second transistor T2, and the third transistor T3 may be the source electrode. However, the embodiments of this disclosure are not necessarily limited thereto, and the first electrode of at least one of the first transistor T1, the second transistor T2, and the third transistor T3 may be the source electrode, and the first electrodes of the remaining transistors of the first transistor T1, the second transistor T2, and the third transistor T3 may be the drain electrodes.

[0071] The storage capacitor CST may include a first electrode and a second electrode. The first electrode of the storage capacitor CST may be connected to a first node N1. The second electrode of the storage capacitor CST may be connected to a second node N2. The storage capacitor CST may store the differential voltage between the gate voltage and the source voltage of the first transistor T1.

[0072] The light-emitting capacitor CLED may include a first electrode and a second electrode. The first electrode of the light-emitting capacitor CLED may be connected to a second node N2. The second electrode of the light-emitting capacitor CLED may be connected to the cathode electrode of the light-emitting element LED. The light-emitting capacitor CLED enables the voltage across the light-emitting element LED to remain constant, thereby allowing the light-emitting element LED to display a constant brightness. In an embodiment, the light-emitting capacitor CLED may be omitted.

[0073] The light-emitting element (LED) may include an anode electrode and a cathode electrode. The anode electrode of the LED may be connected to a second node N2. A common voltage ELVSS may be applied to the cathode electrode of the LED. The common voltage ELVSS may have a voltage level lower than the driving voltage ELVDD. The LED may emit light with a brightness corresponding to the driving current supplied from the pixel driving circuit PC.

[0074] exist Figure 2 In the diagram, the pixel driving circuit PC is shown to include three transistors and two capacitors, but embodiments of this disclosure are not necessarily limited thereto.

[0075] Figure 3 It shows along Figure 1 A cross-sectional view of an example section taken by line I-I'. Figure 4 It is shown Figure 3 A plan view of the transistor substrate. For example, Figure 3 It is shown Figure 1 A cross-sectional view of a portion of the display area DA.

[0076] refer to Figure 3 and Figure 4 The display device DD according to embodiments of the present disclosure may include a transistor substrate TS, a pixel defining layer PDL, a light-emitting element LED, and an encapsulation layer ENC.

[0077] The transistor substrate TS may include a substrate SUB, a voltage line VL, a lower metal layer BML, a buffer layer BUF, a gate insulating layer GI, a transistor TR, a first connection electrode CNE1 and a second connection electrode CNE2, a passivation layer PVX, and a via insulating layer VIA. Here, the transistor TR may include an active pattern ACT and a gate electrode GE. Furthermore, the light-emitting element LED may include a pixel electrode PE, a light-emitting layer EML, and a common electrode CE.

[0078] The substrate SUB can be, for example, a glass substrate, a metal substrate, or a polymer substrate. In some embodiments, the substrate SUB can be a flexible polymer substrate. However, the embodiments of this disclosure are not necessarily limited thereto, and the substrate SUB can be an inorganic layer, an organic layer, or a composite material layer.

[0079] The lower metal layer (BML) can be disposed on the substrate (SUB). The lower metal layer (BML) can block external light incident on the transistor (TR). The lower metal layer (BML) can transmit signals and / or voltages to the transistor (TR). For example, the lower metal layer (BML) can include metals, alloys, metal nitrides, conductive metal oxides, and transparent conductive materials. These materials can be used alone or in combination with each other.

[0080] Voltage lines VL can be disposed on the substrate SUB. Voltage lines VL can be disposed in the same layer as the underlying metal layer BML. That is, voltage lines VL and the underlying metal layer BML can comprise the same material and can be formed by the same process. Various voltages (e.g., Figure 2 The drive voltage ELVDD or data voltage VDATA shown can be applied to the voltage line VL.

[0081] A buffer layer (BUF) can be disposed on the substrate SUB. The buffer layer BUF can cover the underlying metal layer (BML) and the voltage line (VL). The buffer layer BUF prevents metal atoms or impurities from diffusing from the substrate SUB into the transistor TR. Furthermore, if the surface of the substrate SUB is uneven, the buffer layer BUF can improve the flatness of the substrate SUB surface. For example, the buffer layer BUF can include silicon compounds, such as silicon oxide (SiO₂). x ), silicon nitride (SiN) x ) and silicon oxynitride (SiO) x N y These materials can be used individually or in combination with each other.

[0082] An active pattern ACT can be disposed on a buffer layer BUF. The active pattern ACT may include a metal-oxide-semiconductor (MODS). In an embodiment, the active pattern ACT may include a lower layer LL and an upper layer UL, the lower layer LL comprising an amorphous oxide semiconductor, and the upper layer UL disposed on the lower layer LL and comprising a crystalline oxide semiconductor. Therefore, a driving transistor (e.g., Figure 2 The driving range of the first transistor T1 in the process can be expanded.

[0083] In this configuration, in this embodiment, the lower LL layer comprising an amorphous oxide semiconductor can provide manufacturing benefits due to its relatively low processing temperature and good uniformity across a large substrate. The upper UL layer formed of a crystalline oxide semiconductor can contribute to improved charge mobility and improved transistor electrical performance. Integrating these two layers into a stacked active pattern ACT can, for example, enable the transistor to benefit from both process stability and improved operating characteristics when used as a drive transistor in an active matrix display.

[0084] For example, the amorphous oxide semiconductor of the lower LL layer may include zinc oxide (ZnO) containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), and magnesium (Mg). x Gallium oxide (GaO) x ), Tin oxide (SnO) x Indium oxide (InO) x Indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), indium zinc tin oxide (IZTO), and indium gallium zinc oxide (IGZO), etc. These materials can be used alone or in combination with each other. In an embodiment, the amorphous oxide semiconductor of the lower LL layer may include indium gallium zinc oxide (IGZO). However, the embodiments of this disclosure are not necessarily limited thereto.

[0085] Similarly, for example, the crystalline oxide semiconductor of the upper UL may include zinc oxide (ZnO) containing elements such as indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), and magnesium (Mg). x Gallium oxide (GaO) x ), Tin oxide (SnO) x Indium oxide (InO) x Indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), indium zinc tin oxide (IZTO), and indium gallium zinc oxide (IGZO), etc. These materials can be used alone or in combination with each other. In an embodiment, the crystalline oxide semiconductor of the upper UL may include indium gallium oxide (IGO). However, embodiments of this disclosure are not necessarily limited thereto.

[0086] The lower layer LL may have a first channel region CH1, a first conductive region CD1, and a second conductive region CD2. The first channel region CH1 may be located between the first conductive region CD1 and the second conductive region CD2. For example, the first conductive region CD1 and the second conductive region CD2 may be regions that are n+ type conductive. However, the embodiments of this disclosure are not necessarily limited to this. The first channel region CH1 may be a non-conductive region.

[0087] The upper UL layer may have a second channel region CH2, a third conductive region CD3, and a fourth conductive region CD4. The second channel region CH2 may be located between the third conductive region CD3 and the fourth conductive region CD4. The second channel region CH2 may overlap with the first channel region CH1 in a plan view, and the third conductive region CD3 and the fourth conductive region CD4 may at least partially overlap with the first conductive region CD1 and the second conductive region CD2, respectively, in a plan view. For example, the third conductive region CD3 and the fourth conductive region CD4 may be regions that are n+ type conductive. However, embodiments of this disclosure are not necessarily limited to this. The second channel region CH2 may be a non-conductive region.

[0088] In this embodiment, by vertically aligning the first channel region CH1 and the second channel region CH2, and configuring the third conductive region CD3 and the fourth conductive region CD4 in the upper UL layer to at least partially overlap with the lower first conductive region CD1 and the second conductive region CD2, the resulting structure can suppress parasitic resistance and improve carrier injection efficiency. This alignment can help stabilize the threshold voltage and facilitate consistent operation of the drive transistors under varying load conditions in the display.

[0089] In this embodiment, the width of the lower layer LL can be substantially the same as the width of the upper layer UL. Here, width refers to the length in the first direction DR1. That is, the end of the lower layer LL facing the first direction DR1 can coincide with the end of the upper layer UL facing the first direction DR1.

[0090] At least a portion of the upper surface of the exposed buffer layer BUF, including a first-first-hole H11 and a second-first-hole H21, may be defined in the lower layer LL. The first-first-hole H11 may be surrounded by a first conductive region CD1, and the second-first-hole H21 may be surrounded by a second conductive region CD2. That is, the first conductive region CD1 may have a planar shape surrounding the first-first-hole H11, and the second conductive region CD2 may have a planar shape surrounding the second-first-hole H21.

[0091] A first-second hole H12 connected to a first-first hole H11 and a second-second hole H22 connected to a second-first hole H21 can be defined in the upper UL layer. The first-second hole H12 can expose a portion of a first conductive region CD1 and the first-first hole H11, and the second-second hole H22 can expose a portion of a second conductive region CD2 and the second-first hole H21. The first-first hole H11 and the first-second hole H12 can define a first hole H1, and the second-first hole H21 and the second-second hole H22 can define a second hole H2.

[0092] In this embodiment, the width of the first-second hole H12 can be greater than the width of the first-first hole H11, and the width of the second-second hole H22 can be greater than the width of the second-first hole H21. That is, the first-second hole H12 can expose the entire first-first hole H11, and the second-second hole H22 can expose the entire second-first hole H21. Here, width refers to the length in the first direction DR1.

[0093] The thickness TH1 of the lower LL layer can be greater than approximately For example, the thickness TH1 of the lower layer LL can be greater than approximately And less than approximately Within the range. If the thickness TH1 of the lower layer LL is less than or equal to approximately Etching the lower LL layer may not be easy. In this case, it may be difficult to form the active pattern ACT. If the thickness TH1 of the lower LL layer is greater than or equal to approximately The process characteristics may then deteriorate.

[0094] In this embodiment, the thickness TH2 of the upper UL layer can be less than approximately For example, the thickness TH2 of the upper UL layer can be greater than approximately And less than approximately Within the range. If the thickness TH2 of the upper UL layer is less than or equal to approximately Crystal growth may not proceed smoothly, and the current flowing through the upper UL layer may be disrupted. If the thickness TH2 of the upper UL layer is greater than approximately The process characteristics may then deteriorate.

[0095] In this embodiment, the relative thicknesses of the upper and lower layers are chosen to improve the balance between carrier mobility and uniform film deposition. A thinner upper UL layer can promote efficient crystallization during annealing and maintain low leakage current, while a slightly thicker lower LL layer can provide structural stability and compatibility with standard backplane processes. These parameters can collectively contribute to supporting improved electrical characteristics and scalable manufacturing of transistor configurations for both.

[0096] A gate insulating layer GI can be disposed on a buffer layer BUF and an active pattern ACT. The gate insulating layer GI can cover at least a portion of the active pattern ACT. A first opening OP1 connected to a first via H1 and a second opening OP2 connected to a second via H2 can be defined in the gate insulating layer GI. For example, the first opening OP1 can expose the first via H1 and a third conductive region CD3, and the second opening OP2 can expose the second via H2 and a fourth conductive region CD4.

[0097] For example, the gate insulating layer GI may include silicon compounds, such as silicon oxide (SiO2). x), silicon nitride (SiN) x ) and silicon oxynitride (SiO) x N y These materials can be used individually or in combination with each other.

[0098] The gate electrode GE can be disposed on the gate insulating layer GI. The gate electrode GE can overlap with the first channel region CH1 and the second channel region CH2 in a planar view. For example, the gate electrode GE can include metals, alloys, metal nitrides, conductive metal oxides, and transparent conductive materials. Examples of metals include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), and scandium (Sc). Examples of conductive metal oxides include indium tin oxide and indium zinc oxide. Examples of metal nitrides include aluminum nitride (AlN). x ), Tungsten nitride (WN) x ) and chromium nitride (CrN) x These materials can be used individually or in combination with each other.

[0099] The first connecting electrode CNE1 and the second connecting electrode CNE2 can be disposed on the gate insulating layer GI. The first connecting electrode CNE1 and the second connecting electrode CNE2 can face each other in the first direction DR1.

[0100] The first connection electrode CNE1 can be connected (or contacted) to the lower metal layer BML through the first contact hole CNT1 that penetrates the buffer layer BUF and the gate insulating layer GI, and the second connection electrode CNE2 can be connected (or contacted) to the voltage line VL through the second contact hole CNT2 that penetrates the buffer layer BUF and the gate insulating layer GI.

[0101] The first connecting electrode CNE1 can be connected (or contacted) to the first conductive region CD1 through the first opening OP1 and the first-second hole H12, and does not overlap with the first-first hole H11 in the plan view. Similarly, the second connecting electrode CNE2 can be connected (or contacted) to the second conductive region CD2 through the second opening OP2 and the second-second hole H22, and does not overlap with the second-first hole H21 in the plan view. In other words, the first connecting electrode CNE1 can extend into the first opening OP1 and the first-second hole H12, but may not extend into the first-first hole H11. The second connecting electrode CNE2 can extend into the second opening OP2 and the second-second hole H22, but may not extend into the second-first hole H21. In this configuration, the first connecting electrode CNE1 can contact the upper UL inside the first-second hole H12, and the second connecting electrode CNE2 can contact the upper UL inside the second-second hole H22.

[0102] Therefore, the first connecting electrode CNE1 can electrically connect the lower metal layer BML and the active pattern ACT, and the second connecting electrode CNE2 can electrically connect the voltage line VL and the active pattern ACT.

[0103] In this embodiment, the first connection electrode CNE1 and the second connection electrode CNE2 may be disposed in the same layer as the gate electrode GE. That is, the first connection electrode CNE1 and the second connection electrode CNE2 may comprise the same material as the gate electrode GE and may be formed by the same process.

[0104] In this embodiment, transistor TR may correspond to Figure 2 The first transistor T1, the second transistor T2, and the third transistor T3. That is to say, Figure 2 The first transistor T1, the second transistor T2, and the third transistor T3 may all have the structure of transistor TR. However, the embodiments disclosed herein are not necessarily limited thereto.

[0105] The passivation layer PVX can be disposed on the gate insulating layer GI, the gate electrode GE, the first connection electrode CNE1, and the second connection electrode CNE2. The passivation layer PVX can cover the gate insulating layer GI, the gate electrode GE, the first connection electrode CNE1, and the second connection electrode CNE2, and can fill the first hole H1 and the second hole H2, as well as the first opening OP1 and the second opening OP2. For example, the passivation layer PVX can include a silicon compound, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ) and silicon oxynitride (SiO) x N y These materials can be used individually or in combination with each other.

[0106] The via insulating layer (VIA) can be disposed on the passivation layer (PVX). The via insulating layer (VIA) can have a substantially flat upper surface. The via insulating layer (VIA) can include organic materials. For example, the via insulating layer (VIA) can include organic materials such as phenolic resin, polyacrylate resin, polyimide resin, polyamide resin, silicone resin, and epoxy resin. These materials can be used alone or in combination with each other.

[0107] The pixel electrode PE can be disposed on the via insulating layer VIA. If the transistor TR corresponds to Figure 2If the first transistor T1 is connected, the pixel electrode PE can be connected to the first connection electrode CNE1 through a contact hole penetrating the via insulating layer VIA. For example, the pixel electrode PE may include metals, alloys, metal nitrides, conductive metal oxides, and transparent conductive materials. These materials can be used alone or in combination. In embodiments, the pixel electrode PE may have a stacked structure including ITO / Ag / ITO. However, embodiments of this disclosure are not necessarily limited to this. The pixel electrode PE may be an anode electrode.

[0108] A pixel defining layer (PDL) may be disposed on a via insulating layer (VIA). The PDL may cover the edge of the pixel electrode (PE). The PDL may define an opening exposing at least a portion of the upper surface of the pixel electrode (PE). For example, the PDL may comprise inorganic or organic materials. In embodiments, the PDL may comprise organic materials such as epoxy resins and silicone resins. These materials may be used alone or in combination with each other. In embodiments, the PDL may comprise inorganic and / or organic materials containing light-blocking materials such as black pigments and black dyes.

[0109] The emissive layer (EML) can be disposed on the pixel electrode (PE). For example, the emissive layer (EML) can be disposed in an opening of the pixel limiting layer (PDL). The emissive layer (EML) may include a light-emitting material that emits light of a preset color. For example, the emissive layer (EML) may include a light-emitting material that emits red, green, or blue light.

[0110] The common electrode CE can be disposed on the pixel limiting layer (PDL) and the light-emitting layer (EML). For example, the common electrode CE can include metals, alloys, metal nitrides, conductive metal oxides, and transparent conductive materials. These materials can be used individually or in combination with each other. The common electrode CE can be a cathode electrode.

[0111] Therefore, the light-emitting element (LED), including the pixel electrode (PE), the light-emitting layer (EML), and the common electrode (CE), can be formed on the substrate (SUB) in the display area (DA) (see...). Figure 1 In this context, the light-emitting element (LED) can be electrically connected to the transistor TR. Therefore, the LED can receive a drive signal from the transistor TR and generate light based on the drive signal.

[0112] The encapsulation layer ENC can be disposed on the common electrode CE. The encapsulation layer ENC can protect the light-emitting element (LED) from foreign matter such as moisture and oxygen. For example, the encapsulation layer ENC may include at least one inorganic layer and at least one organic layer. In embodiments, the encapsulation layer ENC may have a stacked structure of a first inorganic layer, an organic layer, and a second inorganic layer. However, embodiments of this disclosure are not necessarily limited thereto.

[0113] Figures 5 to 13 It shows the manufacturing process. Figure 3 A cross-sectional view of the method for using a transistor substrate. In the following text, references will be omitted or simplified. Figure 3 and Figure 4 The description of the transistor substrate TS is repeated.

[0114] refer to Figure 5 The lower metal layer BML and voltage lines VL can be formed on the substrate SUB. The lower metal layer BML and voltage lines VL can be formed simultaneously using the same process.

[0115] refer to Figure 6 A buffer layer (BUF) can be formed on the substrate (SUB). The buffer layer (BUF) can cover the underlying metal layer (BML) and the voltage line (VL). For example, the buffer layer (BUF) can be formed using silicon compounds.

[0116] An active pattern ACT can be formed on the buffer layer BUF. The active pattern ACT may include a lower layer LL disposed on the buffer layer BUF and an upper layer UL disposed on the lower layer LL. For example, a semiconductor layer can be completely formed on the buffer layer BUF, and the active pattern ACT can be formed by patterning the semiconductor layer. In an embodiment, each of the lower layer LL and the upper layer UL can be formed using a metal oxide semiconductor. For example, the lower layer LL can be formed using indium gallium zinc oxide (IGZO), and the upper layer UL can be formed using indium gallium oxide (IGO).

[0117] After forming the active pattern ACT, a thermal processing process can be performed on the upper UL layer of the active pattern ACT. Therefore, the upper UL layer can have a crystalline structure. That is, the upper UL layer can include a crystalline oxide semiconductor. In contrast, the lower LL layer can include an amorphous oxide semiconductor.

[0118] A gate insulating layer GI can be formed on the buffer layer BUF. The gate insulating layer GI can cover the active pattern ACT. For example, the gate insulating layer GI can be formed using a silicon compound.

[0119] refer to Figure 7 A portion of each of the buffer layer BUF, gate insulating layer GI, and upper UL can be removed by a first etching process. Therefore, a first contact via CNT1 exposing at least a portion of the lower metal layer BML and a second contact via CNT2 exposing at least a portion of the voltage line VL can be formed in the buffer layer BUF and the gate insulating layer GI. Essentially simultaneously, a first-second via H12 and a second-second via H22 can be formed in the upper UL, and a first opening OP1 overlapping the first-second via H12 and a second opening OP2 overlapping the second-second via H22 can be formed in the gate insulating layer GI.

[0120] For example, the first etching process can be a dry etching process. However, the embodiments of this disclosure are not necessarily limited to this.

[0121] During the process of removing the portion of the gate insulating layer GI by a first etching process, hydrogen contained in the gate insulating layer GI can flow into the underlying layer LL. The portion of the underlying layer LL from which hydrogen is introduced from the gate insulating layer GI can have a high carrier concentration due to the introduced hydrogen, thereby becoming conductive, and thus can become the first conductive region CD1 and the second conductive region CD2. The first conductive region CD1 can be exposed by the first-second via H12, and the second conductive region CD2 can be exposed by the second-second via H22.

[0122] refer to Figure 8 A conductive layer CL can be completely formed on the gate insulating layer GI. The conductive layer CL can fill the first contact hole CNT1 and the second contact hole CNT2, the first opening OP1 and the second opening OP2, and the first-second hole H12 and the second-second hole H22. For example, the conductive layer CL can be formed using metals, alloys, metal nitrides, conductive metal oxides, and transparent conductive materials.

[0123] refer to Figure 9 and Figure 10 A photosensitive organic layer can be formed on the conductive layer CL. Multiple photoresist patterns PRP can be formed by exposing and developing the photosensitive organic layer. The multiple photoresist patterns PRP can overlap with the regions where the first connection electrode CNE1, the gate electrode GE, and the second connection electrode CNE2 will be formed, respectively.

[0124] For example, in one embodiment, the photoresist pattern PRP may include a positive photoresist. In another embodiment, the photoresist pattern PRP may include a negative photoresist.

[0125] A portion of the first conductive region CD1, a portion of the second conductive region CD2, and a portion of the conductive layer CL can be removed by a second etching process using a photoresist pattern PRP as a mask. For example, the portion of the first conductive region CD1 that does not overlap with the photoresist pattern PRP, the portion of the second conductive region CD2 that does not overlap with the photoresist pattern PRP, and the portion of the conductive layer CL that does not overlap with the photoresist pattern PRP can be removed by the second etching process.

[0126] In an embodiment, a second etching process that removes the exposed portions of the conductive layer CL and the underlying first conductive region CD1 and second conductive region CD2 can facilitate the formation of a stacked via structure. For example, this operation can facilitate the formation of a first-first via H11 within the first conductive region CD1 and a second-first via H21 within the second conductive region CD2, respectively. These stacked vias allow subsequent electrical connections to be selectively formed within the upper UL layer, while providing partial electrical isolation to the lower LL layer, which serves as a channel region. This spatial separation between conductive and non-conductive regions within a vertically stacked semiconductor structure can lead to improved device reliability.

[0127] Therefore, a first connection electrode CNE1 filling the first contact hole CNT1 and connected to the first conductive region CD1, a gate electrode GE overlapping the center portion of the active pattern ACT in the plan view, and a second connection electrode CNE2 filling the second contact hole CNT2 and connected to the second conductive region CD2 can be formed simultaneously. Essentially simultaneously, the portion of the first conductive region CD1 that does not overlap with the photoresist pattern PRP can be removed to form a first-first hole H11, and the portion of the second conductive region CD2 that does not overlap with the photoresist pattern PRP can be removed to form a second-first hole H21.

[0128] In this embodiment, by patterning the first connection electrode CNE1, the gate electrode GE, and the second connection electrode CNE2 in a single process using the same conductive layer CL, the manufacturing sequence avoids additional alignment operations, thus improving process integration and yield. Furthermore, simultaneously forming vertically aligned via structures and connection electrodes allows for close registration between the center of the gate electrode GE and the center of the active pattern ACT. This alignment improves electrostatic control of the dual-channel configuration formed in the active pattern ACT and supports improved subthreshold characteristics in the resulting transistor TR.

[0129] For example, the second etching process can be a wet etching process. However, the embodiments of this disclosure are not necessarily limited thereto.

[0130] refer to Figure 10 and Figure 11 A portion of the gate insulating layer GI can be removed using a third etching process that uses a photoresist pattern PRP as a mask. For example, the first and second portions of the gate insulating layer GI that do not overlap with the photoresist pattern PRP but overlap with the active pattern ACT in the planar view can be removed by the third etching process. Therefore, the width of each of the first opening OP1 and the second opening OP2 can be increased.

[0131] In this embodiment, expanding the first opening OP1 and the second opening OP2 through a third etching process increases the surface area through which hydrogen from the gate insulating layer GI can diffuse into the active pattern ACT. This allows for a wider and more uniform distribution of dopant species within both the lower LL and upper UL layers. Consequently, the third etching operation not only supports further geometric optimization of the aperture structure but also contributes to the modulation of electrical properties in the conductive and channel regions of the transistor TR.

[0132] For example, the third etching process can be a dry etching process. However, the embodiments of this disclosure are not necessarily limited thereto.

[0133] During the process of removing the aforementioned portion of the gate insulating layer GI by the third etching process, hydrogen contained in the gate insulating layer GI can flow into the lower layer LL and the upper layer UL. The portion of the lower layer LL from which hydrogen is introduced from the gate insulating layer GI can have a high carrier concentration due to the introduced hydrogen, thereby becoming conductive, and thus can become the first conductive region CD1 and the second conductive region CD2. Similarly, the portion of the upper layer UL from which hydrogen is introduced from the gate insulating layer GI can have a high carrier concentration due to the introduced hydrogen, thereby becoming conductive, and thus can become the third conductive region CD3 and the fourth conductive region CD4. That is, after performing the third etching process, the portions of the lower layer LL that overlap with the first and second portions of the gate insulating layer GI in the plan view can become the first conductive region CD1 and the second conductive region CD2, respectively, and the portions of the upper layer UL that overlap with the first and second portions of the gate insulating layer GI in the plan view can become the third conductive region CD3 and the fourth conductive region CD4, respectively.

[0134] In this embodiment, in addition to the first conductive region CD1 and the second conductive region CD2 within the lower layer LL, forming a third conductive region CD3 and a fourth conductive region CD4 within the upper layer UL can result in a complex vertical structure in which both the crystalline and amorphous regions of the oxide semiconductor can participate in electrical conduction. This vertically distributed doping profile supports the use of stacked contact geometries while also reducing the likelihood of contact resistance at the electrode interfaces. Furthermore, this configuration vertically confines the channel conduction path between the selectively doped conductive regions, thereby providing improved isolation and control over short-channel effects.

[0135] Therefore, the first conductive region CD1 can be formed around the first-first hole H11, and the second conductive region CD2 can be formed around the second-first hole H21.

[0136] In this embodiment, the configuration of the first conductive region CD1 and the second conductive region CD2 surrounding the first-first hole H11 and the second-first hole H21 respectively allows the connecting electrodes CNE1 and CNE2 to have an interface with the upper UL layer while maintaining electrical isolation from the adjacent portions of the lower LL layer. This structural arrangement can reduce lateral current leakage across the active pattern ACT and support high field-effect mobility within the channel region. Furthermore, this selective vertical direct-touch configuration simplifies the integration of the dual-layer active structure with other display elements by providing robust electrode coupling without requiring complex multilayer interconnects.

[0137] In this case, the portion of the lower layer LL where hydrogen does not flow can become the first channel region CH1, and the portion of the upper layer UL where hydrogen does not flow can become the second channel region CH2.

[0138] In this embodiment, forming distinct channel regions (e.g., a first channel region CH1 and a second channel region CH2) in both the lower LL and upper UL layers enables dual-channel conduction behavior, which can be used to customize transistor characteristics, such as threshold voltage, transconductance, and drive current. By relying on undoped regions in both oxide semiconductor layers, the transistor TR exhibits an improved on / off current ratio and reduced variability across a large-area substrate. This layered channel structure also facilitates fine control over conduction characteristics and suppresses variability caused by process-induced defects in a single layer.

[0139] Therefore, a transistor TR can be formed that includes an active pattern ACT and a gate electrode GE on the active pattern ACT, wherein the active pattern ACT includes a lower layer LL and an upper layer UL. In other words, the gate electrode GE can form the transistor TR together with the active pattern ACT.

[0140] refer to Figure 12 After forming the transistor TR, the photoresist pattern PRP can be removed.

[0141] refer to Figure 13 A passivation layer PVX can be formed on the gate insulating layer GI, the gate electrode GE, the first connection electrode CNE1, and the second connection electrode CNE2. For example, the passivation layer PVX can be formed using a silicon compound.

[0142] Via insulating layers (VIA) can be formed on the passivation layer PVX. The via insulating layer VIA can be formed using organic materials. Through a chemical mechanical polishing process, the via insulating layer VIA can have a substantially flat upper surface.

[0143] Therefore, a transistor substrate TS can be manufactured, comprising a voltage line VL, a lower metal layer BML, a buffer layer BUF, a gate insulating layer GI, a transistor TR, a first connection electrode CNE1, a second connection electrode CNE2, a passivation layer PVX, and a via insulating layer VIA.

[0144] Figure 14 It shows along Figure 1 A cross-sectional view of an example section taken by line I-I'.

[0145] refer to Figure 14 According to embodiments of the present disclosure, the display device DD' may include a transistor substrate TS', a pixel defining layer PDL, a light-emitting element LED, and an encapsulation layer ENC sequentially disposed on a substrate SUB.

[0146] The transistor substrate TS' may include a first voltage line VL1, a second voltage line VL2, a first lower metal layer BML1, a second lower metal layer BML2, a buffer layer BUF, a gate insulating layer GI, a first transistor TR1, a second transistor TR2, a first connection electrode CNE1, a second connection electrode CNE2, a third connection electrode CNE3, a fourth connection electrode CNE4, a passivation layer PVX, and a via insulating layer VIA. The first transistor TR1 may include a first active pattern ACT1 and a first gate electrode GE1, and the second transistor TR2 may include a second active pattern ACT2 and a second gate electrode GE2. The light-emitting element LED may include a pixel electrode PE, a light-emitting layer EML, and a common electrode CE.

[0147] In addition to the first transistor TR1 and the second transistor TR2, reference Figure 14 The described display device DD' can be compared with the reference. Figure 3 and Figure 4 The described display devices DD are substantially the same or similar. Repeated descriptions will be omitted or simplified in the following text.

[0148] The first lower metal layer BML1 and the second lower metal layer BML2 can be disposed on the substrate SUB. For example, the first lower metal layer BML1 and the second lower metal layer BML2 can include metals, alloys, metal nitrides, conductive metal oxides, and transparent conductive materials. These materials can be used alone or in combination with each other.

[0149] The first lower metal layer BML1 and the second lower metal layer BML2 can respectively transmit signals and / or voltages to the first transistor TR1 and the second transistor TR2. For example, in an embodiment, the second lower metal layer BML2 can be electrically connected to the second gate electrode GE2 or a separate power supply line. In an embodiment, the second lower metal layer BML2 can be omitted.

[0150] First voltage line VL1 and second voltage line VL2 can be disposed on the substrate SUB. First voltage line VL1 and second voltage line VL2 can be disposed in the same layer as the first lower metal layer BML1 and second lower metal layer BML2. That is, first voltage line VL1 and second voltage line VL2 can comprise the same material as the first lower metal layer BML1 and second lower metal layer BML2, and can be formed by the same process. Various voltages (e.g., Figure 2 The driving voltage ELVDD or data voltage VDATA can be applied to the first voltage line VL1 and the second voltage line VL2, respectively.

[0151] A first active pattern ACT1 can be disposed on a buffer layer BUF. In an embodiment, the first active pattern ACT1 may include a lower layer LL and an upper layer UL disposed on the lower layer LL, wherein the lower layer LL comprises an amorphous oxide semiconductor and the upper layer UL comprises a crystalline oxide semiconductor. Therefore, a driving transistor (e.g., Figure 2 The driving range of the first transistor T1 can be expanded.

[0152] The lower layer LL may have a first channel region CH1, a first conductive region CD1, and a second conductive region CD2. The first channel region CH1 may be located between the first conductive region CD1 and the second conductive region CD2. The first conductive region CD1 and the second conductive region CD2 may be regions that are n+ type conductive. However, the embodiments of this disclosure are not necessarily limited thereto. The first channel region CH1 may be a non-conductive region.

[0153] The upper UL layer may have a second channel region CH2, a third conductive region CD3, and a fourth conductive region CD4. The second channel region CH2 may be located between the third conductive region CD3 and the fourth conductive region CD4. The second channel region CH2 may overlap with the first channel region CH1 in a plan view, and the third conductive region CD3 and the fourth conductive region CD4 may at least partially overlap with the first conductive region CD1 and the second conductive region CD2 in a plan view, respectively. The third conductive region CD3 and the fourth conductive region CD4 may be regions that are n+ type conductive. However, embodiments of this disclosure are not necessarily limited thereto. The second channel region CH2 may be a non-conductive region.

[0154] In this embodiment, the overlap between the first channel region CH1 and the second channel region CH2 allows the two layers of the first active pattern ACT1 to synergistically contribute to current modulation when a gate voltage is applied. The presence of the second channel region CH2 above the first channel region CH1 can improve electron mobility due to the crystallinity of the upper UL layer, while the amorphous lower LL layer can provide improved threshold voltage stability. Therefore, this vertically layered channel configuration enables the realization of a more robust drive transistor with improved electrical characteristics and reliability over long-term operation.

[0155] In this embodiment, the width of the lower LL can be greater than the width of the upper UL. Here, width refers to the length in the first direction DR1.

[0156] At least a portion of the upper surface of the exposed buffer layer BUF, including a first hole H1 and a second hole H2, can be defined in the lower layer LL. The first hole H1 can be surrounded by a first conductive region CD1, and the second hole H2 can be surrounded by a second conductive region CD2. That is, the first conductive region CD1 can have a planar shape surrounding the first hole H1, and the second conductive region CD2 can have a planar shape surrounding the second hole H2.

[0157] In an embodiment, a step may exist between the end of the upper UL facing the first connecting electrode CNE1 and the end of the first conductive region CD1 facing the first connecting electrode CNE1 and exposed by the first hole H1, and a step may also exist between the end of the upper UL facing the second connecting electrode CNE2 and the end of the second conductive region CD2 facing the second connecting electrode CNE2 and exposed by the second hole H2.

[0158] The thickness TH1 of the lower layer LL can be greater than approximately 50 angstroms. For example, the thickness TH1 of the lower layer LL can be in the range of greater than approximately 50 angstroms and less than approximately 300 angstroms. If the thickness TH1 of the lower layer LL is less than or equal to approximately 50 angstroms, etching the lower layer LL may not be easy, and it may be difficult to form the first active pattern ACT1 and the second active pattern ACT2. If the thickness TH1 of the lower layer LL is greater than or equal to approximately 300 angstroms, the process characteristics may deteriorate.

[0159] The thickness TH2 of the upper UL layer can be less than approximately 100 angstroms. For example, the thickness TH2 of the upper UL layer can be greater than approximately 20 angstroms and less than approximately 100 angstroms. If the thickness TH2 of the upper UL layer is less than or equal to approximately 20 angstroms, crystal growth may not proceed smoothly, and the current flowing through the upper UL layer may be disrupted. If the thickness TH2 of the upper UL layer is greater than approximately 100 angstroms, process characteristics may deteriorate.

[0160] In this embodiment, the selected thicknesses of the lower LL and upper UL layers can also be improved to control the vertical distribution of charge carriers and the electric field coupled to the gate electrode. A relatively thin upper UL layer allows the first gate electrode GE1 to effectively modulate both channel regions CH1 and CH2, while also maintaining reliable ohmic contact between the third conductive region CD3 and the fourth conductive region CD4 and the connection electrode. In contrast, a relatively thicker lower LL layer can serve as a basis for supporting stable channel formation and suppressing short-channel effects.

[0161] The second active pattern ACT2 can be disposed on the buffer layer BUF. The second active pattern ACT2 may include a metal-oxide-semiconductor. In an embodiment, the second active pattern ACT2 may include an amorphous oxide semiconductor.

[0162] In this embodiment, the second active pattern ACT2 can be disposed in the same layer as the lower layer LL of the first active pattern ACT1. That is, the second active pattern ACT2 can be formed by the same process as the lower layer LL of the first active pattern ACT1, and can include the same material as the lower layer LL of the first active pattern ACT1. The thickness of the second active pattern ACT2 can be the same as the thickness TH1 of the lower layer LL of the first active pattern ACT1.

[0163] In other words, the first active pattern ACT1 can have a two-layer structure in which amorphous oxide semiconductor and crystalline oxide semiconductor are stacked, and the second active pattern ACT2 can have a single-layer structure including amorphous oxide semiconductor.

[0164] In this configuration, in one embodiment, the second active pattern ACT2 provides a simpler single-layer structure for the second transistor TR2, which can be used for switching or control roles requiring enhanced drive strength without the need for a dual-layer configuration. By selectively employing a dual-layer structure for the driving transistor (i.e., the first transistor TR1) and a single-layer structure for the second transistor TR2, overall process complexity and material utilization can be improved without sacrificing performance in critical circuit regions.

[0165] The second active pattern ACT2 may include a third channel region CH3, a fifth conductive region CD5, and a sixth conductive region CD6. The third channel region CH3 may be located between the fifth conductive region CD5 and the sixth conductive region CD6. For example, the fifth conductive region CD5 and the sixth conductive region CD6 may be regions that are n+ type conductive. However, embodiments of this disclosure are not necessarily limited to this. The third channel region CH3 may be a non-conductive region.

[0166] At least a portion of the upper surface of the exposed buffer layer BUF, including the third hole H3 and the fourth hole H4, can be defined within the second active pattern ACT2. The third hole H3 can be surrounded by a fifth conductive region CD5, and the fourth hole H4 can be surrounded by a sixth conductive region CD6. That is, the fifth conductive region CD5 can have a planar shape surrounding the third hole H3, and the sixth conductive region CD6 can have a planar shape surrounding the fourth hole H4.

[0167] A gate insulating layer GI may be disposed on a buffer layer BUF, a first active pattern ACT1, and a second active pattern ACT2. The gate insulating layer GI may cover at least a portion of each of the first active pattern ACT1 and the second active pattern ACT2. A first opening OP1 connected to a first hole H1, a second opening OP2 connected to a second hole H2, a third opening OP3 connected to a third hole H3, and a fourth opening OP4 connected to a fourth hole H4 may be defined within the gate insulating layer GI.

[0168] For example, the first opening OP1 can expose the first hole H1, the first conductive region CD1, and the third conductive region CD3, and the second opening OP2 can expose the second hole H2, the second conductive region CD2, and the fourth conductive region CD4. In addition, the third opening OP3 can expose the third hole H3 and the fifth conductive region CD5, and the fourth opening OP4 can expose the fourth hole H4 and the sixth conductive region CD6.

[0169] The first gate electrode GE1 and the second gate electrode GE2 can be disposed on the gate insulating layer GI. The first gate electrode GE1 can overlap with the first channel region CH1 and the second channel region CH2 in the plan view, and the second gate electrode GE2 can overlap with the third channel region CH3 in the plan view.

[0170] In this embodiment, the first transistor TR1 may correspond to Figure 2 The first transistor T1, and the second transistor TR2 can correspond to Figure 2 The second transistor T2 or the third transistor T3.

[0171] The first connecting electrode CNE1, the second connecting electrode CNE2, the third connecting electrode CNE3, and the fourth connecting electrode CNE4 can be disposed on the gate insulating layer GI. The first connecting electrode CNE1 can be connected (or contacted) to the first lower metal layer BML1 through the first contact hole CNT1 penetrating the buffer layer BUF and the gate insulating layer GI. The second connecting electrode CNE2 can be connected (or contacted) to the first voltage line VL1 through the second contact hole CNT2 penetrating the buffer layer BUF and the gate insulating layer GI. And the fourth connecting electrode CNE4 can be connected (or contacted) to the second voltage line VL2 through the third contact hole CNT3 penetrating the buffer layer BUF and the gate insulating layer GI.

[0172] Furthermore, the first connecting electrode CNE1 can be connected (or contacted) with the first conductive region CD1 through the first opening OP1, the second connecting electrode CNE2 can be connected (or contacted) with the second conductive region CD2 through the second opening OP2, the third connecting electrode CNE3 can be connected (or contacted) with the fifth conductive region CD5 through the third opening OP3, and the fourth connecting electrode CNE4 can be connected (or contacted) with the sixth conductive region CD6 through the fourth opening OP4.

[0173] In other words, the first connecting electrode CNE1 can extend into the interior of the first opening OP1, but not into the interior of the first hole H1. The second connecting electrode CNE2 can extend into the interior of the second opening OP2, but not into the interior of the second hole H2. The third connecting electrode CNE3 can extend into the interior of the third opening OP3, but not into the interior of the third hole H3. The fourth connecting electrode CNE4 can extend into the interior of the fourth opening OP4, but not into the interior of the fourth hole H4.

[0174] Therefore, the first connecting electrode CNE1 can electrically connect the first lower metal layer BML1 and the first active pattern ACT1, and the second connecting electrode CNE2 can electrically connect the first voltage line VL1 and the first active pattern ACT1. Furthermore, the third connecting electrode CNE3 can be electrically connected to the second active pattern ACT2, and the fourth connecting electrode CNE4 can electrically connect the second voltage line VL2 and the second active pattern ACT2.

[0175] In this embodiment, the first connecting electrode CNE1, the second connecting electrode CNE2, the third connecting electrode CNE3, and the fourth connecting electrode CNE4 can be disposed in the same layer as the first gate electrode GE1 and the second gate electrode GE2. That is, the first connecting electrode CNE1, the second connecting electrode CNE2, the third connecting electrode CNE3, and the fourth connecting electrode CNE4 can comprise the same material as the first gate electrode GE1 and the second gate electrode GE2, and can be formed using the same process as the first gate electrode GE1 and the second gate electrode GE2.

[0176] The pixel electrode PE can be disposed on the via insulating layer VIA. The pixel electrode PE can be connected to the first connection electrode CNE1 through a contact hole penetrating the via insulating layer VIA.

[0177] Figures 15 to 29 It shows the manufacturing process. Figure 14 A cross-sectional view of the method for using a transistor substrate. In the following text, references will be omitted or simplified. Figure 14 The description of the transistor substrate TS' is repeated.

[0178] refer to Figure 15The first lower metal layer BML1 and the second lower metal layer BML2, as well as the first voltage line VL1 and the second voltage line VL2, can be formed simultaneously on the substrate SUB using the same process.

[0179] A buffer layer BUF covering a first lower metal layer BML1 and a second lower metal layer BML2, as well as a first voltage line VL1 and a second voltage line VL2, can be formed on the substrate SUB. A preliminary lower layer LL-P and a preliminary upper layer UL-P can be sequentially formed on the buffer layer BUF. In an embodiment, each of the preliminary lower layer LL-P and the preliminary upper layer UL-P can be formed using a metal-oxide-semiconductor.

[0180] refer to Figure 16 In one embodiment, a first photosensitive organic layer PR1 can be completely formed on the initial upper UL-P layer. For example, the first photosensitive organic layer PR1 may include a positive photoresist. In another embodiment, the first photosensitive organic layer PR1 may include a negative photoresist.

[0181] refer to Figure 17 , Figure 18 , Figure 19 and Figure 20 A mask MK can be disposed on the first photosensitive organic layer PR1. In an embodiment, the mask MK can be a halftone mask. For example, the mask MK may include a transmissive portion M1, a light-blocking portion M2, and a semi-transmissive portion M3. The transmissive portion M1 can fully transmit light, the light-blocking portion M2 can completely block light, and the semi-transmissive portion M3 can transmit some of the light.

[0182] The first photosensitive organic layer PR1 can be exposed and developed using a mask MK, allowing the portion of the first photosensitive organic layer PR1 corresponding to the transmissive portion M1 to be removed, while retaining the portion of the first photosensitive organic layer PR1 corresponding to the light-blocking portion M2 to form a first photoresist pattern PRP1. Furthermore, the portion of the first photosensitive organic layer PR1 corresponding to the semi-transmissive portion M3 can be partially removed to form a second photoresist pattern PRP2. Therefore, the first photoresist pattern PRP1 and the second photoresist pattern PRP2 can have different thicknesses.

[0183] A portion of the initial lower LL-P and a portion of the initial upper UL-P can be removed by a first etching process using a first photoresist pattern PRP1 and a second photoresist pattern PRP2 as masks. For example, the portion of the initial lower LL-P that does not overlap with the first photoresist pattern PRP1 and the second photoresist pattern PRP2, as well as the portion of the initial upper UL-P that does not overlap with the first photoresist pattern PRP1 and the second photoresist pattern PRP2, can be removed by the first etching process. Therefore, a first active pattern ACT1 comprising a lower LL overlapping with the first photoresist pattern PRP1 and an upper UL disposed on the lower LL can be formed, and simultaneously a second active pattern ACT2 overlapping with the second photoresist pattern PRP2 and a residual layer RL on the second active pattern ACT2 can be formed.

[0184] For example, the first etching process can be a wet etching process. However, the embodiments of this disclosure are not necessarily limited to this.

[0185] A portion of the first photoresist pattern PRP1 can be removed by an ashing process, and the entire second photoresist pattern PRP2 can be removed. For example, the first photoresist pattern PRP1 can be patterned by an ashing process to overlap with a portion (e.g., the central portion) of the first active pattern ACT1 in a planar view.

[0186] refer to Figure 21 A portion of the upper UL and the residual layer RL can be removed by a second etching process using the first photoresist pattern PRP1 as a mask. For example, the portion of the upper UL that does not overlap with the first photoresist pattern PRP1 and the entire residual layer RL can be removed by the second etching process. Therefore, the upper surface of the lower LL that does not overlap with the upper UL can be exposed, and the entire upper surface of the second active pattern ACT2 can be exposed.

[0187] For example, the second etching process can be a dry etching process. However, the embodiments of this disclosure are not necessarily limited thereto.

[0188] refer to Figure 22 The first photoresist pattern PRP1 can be removed. After removing the first photoresist pattern PRP1, a thermal processing process can be performed on the upper UL. Therefore, the upper UL can have a crystalline structure. That is, the upper UL can include a crystalline oxide semiconductor. In contrast, the lower LL and the second active pattern ACT2 can include an amorphous oxide semiconductor.

[0189] refer to Figure 23 A gate insulating layer GI can be formed on the buffer layer BUF, covering the first active pattern ACT1 and the second active pattern ACT2.

[0190] refer to Figure 24 A portion of each of the buffer layer BUF and the gate insulating layer GI can be removed by a third etching process. Therefore, a first contact hole CNT1 exposing at least a portion of the first lower metal layer BML1, a second contact hole CNT2 exposing at least a portion of the first voltage line VL1, and a third contact hole CNT3 exposing at least a portion of the second voltage line VL2 can be formed in the buffer layer BUF and the gate insulating layer GI. Essentially simultaneously, a first opening OP1 exposing at least a portion of the lower layer LL, a second opening OP2 exposing at least a portion of the lower layer LL, a third opening OP3 exposing at least a portion of the second active pattern ACT2, and a fourth opening OP4 exposing at least a portion of the second active pattern ACT2 can be formed in the gate insulating layer GI.

[0191] For example, the third etching process can be a dry etching process. However, the embodiments of this disclosure are not necessarily limited thereto.

[0192] During the process of removing the aforementioned portion of the gate insulating layer GI by the third etching process, hydrogen contained in the gate insulating layer GI can flow into the lower layer LL and the second active pattern ACT2. The portion of the lower layer LL from which hydrogen is introduced from the gate insulating layer GI can have a high carrier concentration due to the hydrogen, thereby becoming conductive, and thus can become the first conductive region CD1 and the second conductive region CD2. Essentially simultaneously, the portion of the second active pattern ACT2 from which hydrogen is introduced from the gate insulating layer GI can have a high carrier concentration due to the hydrogen, thereby becoming conductive, and thus can become the fifth conductive region CD5 and the sixth conductive region CD6.

[0193] The first conductive region CD1 and the second conductive region CD2 can be exposed by the first opening OP1 and the second opening OP2, respectively, and the fifth conductive region CD5 and the sixth conductive region CD6 can be exposed by the third opening OP3 and the fourth opening OP4, respectively.

[0194] refer to Figure 25 and Figure 26 A conductive layer CL can be completely formed on the gate insulating layer GI. The conductive layer CL can fill the first contact hole CNT1, the second contact hole CNT2 and the third contact hole CNT3, as well as the first opening OP1, the second opening OP2, the third opening OP3 and the fourth opening OP4.

[0195] A photosensitive organic layer can be formed on the conductive layer CL. Multiple third photoresist patterns PRP3 can be formed by exposing and developing the photosensitive organic layer. The multiple third photoresist patterns PRP3 can overlap with the regions where the first connection electrode CNE1, the first gate electrode GE1, the second connection electrode CNE2, the third connection electrode CNE3, the second gate electrode GE2, and the fourth connection electrode CNE4 will be formed, respectively.

[0196] For example, in one embodiment, the third photoresist pattern PRP3 may include a positive photoresist. In another embodiment, the third photoresist pattern PRP3 may include a negative photoresist.

[0197] A fourth etching process using the third photoresist pattern PRP3 as a mask can remove a portion of each of the first conductive region CD1, the second conductive region CD2, the fifth conductive region CD5, and the sixth conductive region CD6, as well as a portion of the conductive layer CL. For example, portions of each of the first conductive region CD1, the second conductive region CD2, the fifth conductive region CD5, and the sixth conductive region CD6 that do not overlap with the third photoresist pattern PRP3, as well as portions of the conductive layer CL that do not overlap with the third photoresist pattern PRP3, can be removed.

[0198] Therefore, a first connection electrode CNE1 filling the first contact hole CNT1 and connected to the first conductive region CD1, a first gate electrode GE1 overlapping the center portion of the first active pattern ACT1 in the plan view, a second connection electrode CNE2 filling the second contact hole CNT2 and connected to the second conductive region CD2, a third connection electrode CNE3 connected to the fifth conductive region CD5, a second gate electrode GE2 overlapping the center portion of the second active pattern ACT2 in the plan view, and a fourth connection electrode CNE4 filling the third contact hole CNT3 and connected to the sixth conductive region CD6 can be formed simultaneously. Essentially simultaneously, portions of the first conductive region CD1 that do not overlap with the third photoresist pattern PRP3, portions of the second conductive region CD2 that do not overlap with the third photoresist pattern PRP3, portions of the fifth conductive region CD5 that do not overlap with the third photoresist pattern PRP3, and portions of the sixth conductive region CD6 that do not overlap with the third photoresist pattern PRP3 can be removed respectively to form the first hole H1, the second hole H2, the third hole H3, and the fourth hole H4.

[0199] For example, the fourth etching process can be a wet etching process. However, the embodiments of this disclosure are not necessarily limited thereto.

[0200] refer to Figure 27 and Figure 28A portion of the gate insulating layer GI can be removed using a fifth etching process that uses the third photoresist pattern PRP3 as a mask. For example, the fifth etching process can remove the first and second portions of the gate insulating layer GI that do not overlap with the third photoresist pattern PRP3 but overlap with the first active pattern ACT1. Essentially simultaneously, the third and fourth portions of the gate insulating layer GI that do not overlap with the third photoresist pattern PRP3 but overlap with the second active pattern ACT2 can be removed. Therefore, the width of each of the first opening OP1, the second opening OP2, the third opening OP3, and the fourth opening OP4 can be increased.

[0201] For example, the fifth etching process can be a dry etching process. However, the embodiments of this disclosure are not necessarily limited thereto.

[0202] During the process of removing the aforementioned portion of the gate insulating layer GI by the fifth etching process, hydrogen contained in the gate insulating layer GI can flow into the first active pattern ACT1 and the second active pattern ACT2. The portion of the lower layer LL from which hydrogen is introduced from the gate insulating layer GI can have a high carrier concentration due to the introduced hydrogen, thus becoming conductive, and therefore can become the first conductive region CD1 and the second conductive region CD2. Similarly, the portion of the upper layer UL from which hydrogen is introduced from the gate insulating layer GI can have a high carrier concentration due to the introduced hydrogen, thus becoming conductive, and therefore can become the third conductive region CD3 and the fourth conductive region CD4. Essentially simultaneously, the portion of the second active pattern ACT2 from which hydrogen is introduced from the gate insulating layer GI can be conductive, and therefore can become the fifth conductive region CD5 and the sixth conductive region CD6.

[0203] In other words, after the fifth etching process is performed, the portions of the lower LL that overlap with the first and second portions of the gate insulating layer GI in the plan view can become the first conductive region CD1 and the second conductive region CD2, respectively, and the portions of the upper UL that overlap with the first and second portions of the gate insulating layer GI in the plan view can become the third conductive region CD3 and the fourth conductive region CD4, respectively.

[0204] Furthermore, after performing the fifth etching process, the portions of the second active pattern ACT2 that overlap with the third and fourth portions of the gate insulating layer GI in the planar view can respectively become the fifth conductive region CD5 and the sixth conductive region CD6.

[0205] Therefore, the first conductive region CD1 can be formed around the first hole H1, the second conductive region CD2 can be formed around the second hole H2, the fifth conductive region CD5 can be formed around the third hole H3, and the sixth conductive region CD6 can be formed around the fourth hole H4.

[0206] In this case, the portion of the lower LL layer that has not yet been introduced with hydrogen can become the first channel region CH1, the portion of the upper UL layer that has not yet been introduced with hydrogen can become the second channel region CH2, and the portion of the second active pattern ACT2 that has not yet been introduced with hydrogen can become the third channel region CH3.

[0207] Therefore, a first transistor TR1 comprising a first active pattern ACT1 and a first gate electrode GE1, and a second transistor TR2 comprising a second active pattern ACT2 and a second gate electrode GE2 can be formed. That is, the first gate electrode GE1 can form the first transistor TR1 together with the first active pattern ACT1, and the second gate electrode GE2 can form the second transistor TR2 together with the second active pattern ACT2.

[0208] After the first transistor TR1 and the second transistor TR2 are formed, the third photoresist pattern PRP3 can be removed.

[0209] refer to Figure 29 A passivation layer PVX and a via insulating layer VIA can be formed on the gate insulating layer GI, the first gate electrode GE1 and the second gate electrode GE2, and the first connection electrode CNE1, the second connection electrode CNE2, the third connection electrode CNE3 and the fourth connection electrode CNE4.

[0210] Therefore, a transistor substrate TS' can be manufactured including a first voltage line VL1 and a second voltage line VL2, a first lower metal layer BML1 and a second lower metal layer BML2, a buffer layer BUF, a gate insulating layer GI, a first transistor TR1 and a second transistor TR2, a first connection electrode CNE1, a second connection electrode CNE2, a third connection electrode CNE3 and a fourth connection electrode CNE4, a passivation layer PVX, and a via insulating layer VIA.

[0211] Figure 30 It shows along Figure 1 A cross-sectional view of an example section taken by line I-I'.

[0212] refer to Figure 30 The display device DD according to embodiments of the present disclosure may include a transistor substrate TS, a pixel defining layer PDL, a light-emitting element LED, and an encapsulation layer ENC sequentially disposed on a substrate SUB.

[0213] The transistor substrate "TS" may include a first voltage line VL1, a second voltage line VL2, a first lower metal layer BML1, a second lower metal layer BML2, a buffer layer BUF, a gate insulating layer GI, a first transistor TR1, a second transistor TR2, a first connection electrode CNE1, a second connection electrode CNE2, a third connection electrode CNE3, a fourth connection electrode CNE4, a passivation layer PVX, and a via insulating layer VIA. Here, the first transistor TR1 may include a first active pattern ACT1 and a first gate electrode GE1, and the second transistor TR2 may include a second active pattern ACT2 and a second gate electrode GE2. The light-emitting element LED may include a pixel electrode PE, a light-emitting layer EML, and a common electrode CE.

[0214] In addition to the first transistor TR1 and the gate insulating layer GI, reference Figure 30 The described display device "DD" can be compared with the reference. Figure 14 The described display device DD' is substantially the same or similar. In the following text, overlapping descriptions will be omitted or simplified.

[0215] The first active pattern ACT1 can be disposed on the buffer layer BUF. In an embodiment, the first active pattern ACT1 may include a lower layer LL and an upper layer UL, the lower layer LL comprising an amorphous oxide semiconductor, and the upper layer UL disposed on the lower layer LL and comprising a crystalline oxide semiconductor.

[0216] The lower layer LL may include a first channel region CH1, a first conductive region CD1, and a second conductive region CD2. The first channel region CH1 may be located between the first conductive region CD1 and the second conductive region CD2. For example, the first conductive region CD1 and the second conductive region CD2 may be regions that are n+ type conductive. However, the embodiments of this disclosure are not necessarily limited to this. The first channel region CH1 may be a non-conductive region.

[0217] The upper UL layer may not be fully conductive. The upper UL layer may at least partially overlap with the first channel region CH1 in the plan view, and may not overlap with the first conductive region CD1 and the second conductive region CD2.

[0218] In this embodiment, the width of the lower layer LL may be greater than the width of the upper layer UL. At least a portion of the first hole H1 and the second hole H2 of the exposed upper surface of the buffer layer BUF may be defined within the lower layer LL.

[0219] A gate insulating layer GI can be disposed on a buffer layer BUF, a first active pattern ACT1, and a second active pattern ACT2. The gate insulating layer GI can cover at least a portion of each of the first active pattern ACT1 and the second active pattern ACT2. In an embodiment, the gate insulating layer GI can completely cover the upper UL layer. That is, the gate insulating layer GI can completely cover the side surface of the upper UL layer.

[0220] The first gate electrode GE1 can be disposed on the gate insulating layer GI. In an embodiment, the first gate electrode GE1 can overlap with the entire upper UL layer in a plan view. That is, the entire upper UL layer can be covered by the first gate electrode GE1.

[0221] In a display device DD (display device DD' and DD'') according to an embodiment of the present disclosure, the transistor TR (first transistor TR1 and second transistor TR2) disposed on the transistor substrate TS (transistor substrate TS' and TS'') in the display area DA may include an active pattern ACT (first active pattern ACT1 and second active pattern ACT2), wherein the first active pattern ACT1 includes a lower layer LL comprising an amorphous oxide semiconductor and an upper layer UL comprising a crystalline oxide semiconductor. In this case, in the embodiment, both the driving transistor and the switching transistor of the transistor substrate TS may have the same structure as the transistor TR. In the embodiment, the first transistor TR1 disposed on the transistor substrate TS' and TS'' in the display area DA may include a first active pattern ACT1, which includes a lower layer LL comprising an amorphous oxide semiconductor and an upper layer UL comprising a crystalline oxide semiconductor, and the second transistor TR2 may include a second active pattern ACT2 having a single-layer structure comprising an amorphous oxide semiconductor. In this case, the driving transistor of the transistor substrate TS' and TS'' may have the same structure as the first transistor TR1, and the switching transistor may have the same structure as the second transistor TR2. Therefore, the driving range of the driving transistor can be expanded.

[0222] Figure 31 It shows including Figure 1 A block diagram of the electronic device for displaying the device. Figure 32 It is shown Figure 31 The electronic device is implemented as an example view of a television set. Figure 33 It is shown Figure 31 The electronic device is implemented as an example view of a smartphone.

[0223] refer to Figure 31 , Figure 32 and Figure 33In this embodiment, the electronic device 900 may include a processor 910, a memory device 920, a storage device 930, an input / output device (I / O device) 940, a power supply 950, and a display device 960. In this case, the display device 960 may correspond to a reference. Figures 1 to 4 The described display device DD, reference Figure 14 The described display device DD' or reference Figure 30 The described display device DD". The electronic device 900 may also include several ports capable of communicating with video cards, sound cards, memory cards and USB devices, etc.

[0224] In an embodiment, such as Figure 32 As shown, the electronic device 900 can be implemented as a television set. In an embodiment, as... Figure 33 As shown, electronic device 900 can be implemented as a smartphone. However, electronic device 900 is not limited to this, and for example, electronic device 900 can be implemented as a mobile phone, video phone, smart tablet, smartwatch, tablet computer, vehicle navigation device, computer monitor, laptop computer, and head-mounted display (HMD), etc.

[0225] Processor 910 can perform specific calculations or tasks. Processor 910 can control display device 960. In embodiments, processor 910 can be, for example, a microprocessor, a central processing unit (CPU), and / or an application processor (AP). Processor 910 can be connected to other components via, for example, an address bus, a control bus, and a data bus. Processor 910 can also be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0226] The memory device 920 can store data required for the operation of the electronic device 900. For example, the memory device 920 may include non-volatile memory devices such as erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, flash memory devices, phase-change random access memory (PRAM) devices, resistive random access memory (RRAM) devices, nanofloating GEe memory (NFGM) devices, polymer random access memory (PoRAM) devices, magnetic random access memory (MRAM) devices, ferroelectric random access memory (FRAM) devices, and / or volatile memory devices such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, and mobile DRAM devices.

[0227] Storage device 930 may include, for example, solid-state drives (SSDs), hard disk drives (HDDs), and CD-ROMs.

[0228] The input / output device 940 may include input devices such as a keyboard, keypad, touchpad, touch screen and mouse, and output devices such as a speaker and printer.

[0229] Power supply 950 can supply the power required for the operation of electronic device 900 to display device 960. Display device 960 can be connected to other components via a bus or other communication link. In an embodiment, display device 960 may be included in input / output device 940.

[0230] The embodiments of this disclosure can be applied to various electronic devices equipped with display devices. For example, the embodiments of this disclosure can be applied to high-resolution smartphones, mobile phones, smart tablets, smartwatches, tablet computers, vehicle navigation systems, televisions, computer monitors, and laptop computers.

[0231] While this disclosure has been specifically shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims.

Claims

1. A transistor substrate, wherein, The transistor substrate includes: Base; A first active pattern is disposed on the substrate and includes: The lower layer includes an amorphous oxide semiconductor and has a first conductive region, a second conductive region, and a first channel region positioned between the first conductive region and the second conductive region; and The upper layer is disposed on the lower layer and includes a crystalline oxide semiconductor; A first gate electrode is disposed on the first active pattern and overlaps with the first channel region in the planar view. Wherein, the first gate electrode and the first active pattern form the first transistor; A first connecting electrode contacts the first conductive region; and The second connecting electrode contacts the second conductive region.

2. The transistor substrate according to claim 1, wherein, The first-first hole surrounded by the first conductive region and the second-first hole surrounded by the second conductive region are defined in the lower layer. The first-second hole exposing the first-first-hole and the second-second hole exposing the second-first-hole are defined in the upper layer, and The width of the first hole is smaller than the width of the second hole, and the width of the second hole is smaller than the width of the second hole.

3. The transistor substrate according to claim 2, wherein, The first connecting electrode contacts the first conductive region through the first and second holes and does not overlap with the first and second holes in the plan view. The second connecting electrode contacts the second conductive area through the second-second hole and does not overlap with the second-first hole in the plan view.

4. The transistor substrate according to claim 2, wherein, The first connecting electrode faces the second connecting electrode in one direction, and The length of the lower layer in one direction is equal to the length of the upper layer in one direction.

5. The transistor substrate according to claim 2, wherein, The upper layer includes: a third conductive region that at least partially overlaps with the first conductive region in the plan view; a fourth conductive region that at least partially overlaps with the second conductive region in the plan view; and a second channel region that overlaps with the first channel region in the plan view.

6. The transistor substrate according to claim 5, wherein, The transistor substrate further includes: A gate insulating layer is disposed between the first active pattern and the first gate electrode. The first opening exposing the third conductive region, the first-first hole, and the first-second hole, and the second opening exposing the fourth conductive region, the second-first hole, and the second-second hole are defined in the gate insulating layer.

7. The transistor substrate according to any one of claims 1 to 6, wherein, The thickness of the upper layer is less than 100 angstroms, and the thickness of the lower layer is greater than 50 angstroms and less than 300 angstroms.

8. The transistor substrate according to claim 1, wherein, The transistor substrate further includes: A second active pattern is disposed on the substrate, the second active pattern comprising an amorphous oxide semiconductor and having a conductive region and a channel region; and A second gate electrode is disposed on the second active pattern and overlaps with the channel region in the planar view. The second gate electrode and the second active pattern form the second transistor.

9. The transistor substrate according to claim 8, wherein, The upper layer includes: a third conductive region that at least partially overlaps with the first conductive region in the plan view; a fourth conductive region that at least partially overlaps with the second conductive region in the plan view; and a second channel region that overlaps with the first channel region in the plan view.

10. The transistor substrate according to claim 8, wherein, The first hole surrounded by the first conductive region and the second hole surrounded by the second conductive region are defined in the lower layer, and The third hole, surrounded by the conductive region, is defined within the second active pattern.

11. The transistor substrate according to claim 10, wherein, There is a first step between the end of the upper layer facing the first connecting electrode and the end of the first conductive area exposed by the first hole and facing the first connecting electrode. There is a second step between the end of the upper layer facing the second connecting electrode and the end of the second conductive area exposed by the second hole and facing the second connecting electrode.

12. An electronic device, wherein, The electronic device includes: Display device; Power supply, providing power to the display device; and The processor controls the display device. The display device includes a transistor substrate according to any one of claims 1 to 11.

13. A method for manufacturing a transistor substrate, wherein, The method includes: A first active pattern is formed on a substrate. The first active pattern includes a lower layer and an upper layer on the lower layer. The lower layer includes an amorphous oxide semiconductor and has a first conductive region, a second conductive region, and a first channel region located between the first conductive region and the second conductive region. The upper layer includes a crystalline oxide semiconductor. A first gate electrode is formed on the first active pattern. Wherein, the first gate electrode overlaps with the first channel region in the planar view, and the first gate electrode and the first active pattern form a first transistor; and A first connecting electrode is formed that contacts the first conductive region and a second connecting electrode that contacts the second conductive region.

14. The method according to claim 13, wherein, The formation of the first active pattern includes: The lower layer is formed on the substrate and the upper layer is formed on the lower layer; A heat treatment process is performed on the upper layer; A gate insulating layer is formed covering the lower and upper layers; A portion of the gate insulating layer is removed to form a first-second via and a second-second via that exposes at least a portion of the lower layer to the upper layer; A conductive layer filling the first-second hole and the second-second hole is formed on the gate insulating layer; and A photoresist pattern is formed on the conductive layer. When the first-second hole and the second-second hole are formed, the portion of the lower layer exposed by the first-second hole becomes the first conductive region, and the portion of the lower layer exposed by the second-second hole becomes the second conductive region.

15. The method according to claim 14, wherein, After forming the conductive layer, the method further includes: The photoresist pattern is used as a mask to remove a portion of each of the conductive layer, the first conductive region, and the second conductive region to form a first-first hole exposed by the first-second hole and a second-first hole exposed by the second-second hole in the underlying layer; Using the photoresist pattern as a mask, the first and second portions of the gate insulating layer that overlap with the first active pattern in the planar view are removed; and Remove the photoresist pattern. When the first part and the second part are removed, the portions of the lower layer that overlap with the first part and the second part in the plan view become the first conductive region and the second conductive region, respectively, and the portions of the upper layer that overlap with the first part and the second part in the plan view become the third conductive region and the fourth conductive region, respectively.

16. The method according to claim 13, wherein, The method further includes: A second active pattern is formed on the substrate, the second active pattern comprising an amorphous oxide semiconductor and having a conductive region and a channel region; and A second gate electrode is formed on the second active pattern and overlaps with the channel region in the planar view. The second gate electrode and the second active pattern form the second transistor.

17. The method according to claim 16, wherein, The formation of the second active pattern includes: A preliminary lower layer is formed on the substrate; A preliminary upper layer is formed on the preliminary lower layer; A portion of the initial lower layer is removed to form the lower layer and the second active pattern, and a portion of the initial upper layer is simultaneously removed to form the upper layer and a residual layer on the second active pattern; Remove a portion of the upper layer and the entire residual layer; A heat treatment process is performed on the upper layer; A gate insulating layer is formed covering the lower layer, the upper layer, and the second active pattern; A portion of the gate insulating layer is removed to expose a portion of the underlying layer and a portion of the second active pattern; A conductive layer is formed on the gate insulating layer; and A third photoresist pattern is formed on the conductive layer. Specifically, when the portion of the lower layer and the portion of the second active pattern are exposed, the exposed portion of the lower layer becomes the first conductive region and the second conductive region, and the exposed portion of the second active pattern becomes the conductive region.

18. The method according to claim 17, wherein, The formation of the lower layer, the second active pattern, the upper layer, and the residual layer includes: A photosensitive organic layer is formed on the preliminary upper layer; The photosensitive organic layer is exposed and developed using a halftone mask to form a first photoresist pattern and a second photoresist pattern with different thicknesses. Using the first photoresist pattern and the second photoresist pattern as masks, a portion of each of the initial lower layer and the initial upper layer is removed to form the lower layer, the second active pattern, the upper layer, and the residual layer; and A portion of the first photoresist pattern and the entire second photoresist pattern are removed by an ashing process. The removal of the portion of the upper layer and the entire residual layer includes: Using the first photoresist pattern as a mask, remove the portion and the entire residual layer of the upper layer; and Remove the first photoresist pattern. The first photoresist pattern is formed in the region overlapping with the lower and upper layers in the plan view, and the second photoresist pattern is formed in the region overlapping with the second active pattern and the residual layer in the plan view.

19. The method of claim 17, wherein, After forming the conductive layer, the method further includes: The third photoresist pattern is used as a mask to remove a portion of each of the conductive layer, the first conductive region and the second conductive region to form a first and a second via in the underlying layer and a third via in the second active pattern. Using the third photoresist pattern as a mask, the first and second portions of the gate insulating layer overlapping with the first active pattern in the planar view, as well as the portion of the gate insulating layer overlapping with the second active pattern in the planar view, are removed; and Remove the third photoresist pattern. In the process of forming the first hole, the second hole, and the third hole, the first hole is formed by removing a portion of the first conductive region, the second hole is formed by removing a portion of the second conductive region, and the third hole is formed by removing a portion of the conductive region.

20. The method according to claim 19, wherein, During the process of removing the first part and the second part, The portions of the lower layer that overlap with the first portion and the second portion in the plan view become the first conductive region and the second conductive region, respectively, and the portion of the second active pattern that overlaps with the portion of the gate insulating layer in the plan view becomes the conductive region.

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