Thin-film transistors and display devices containing them

Abstract

This invention discloses a thin-film transistor and a display device comprising the same. The thin-film transistor includes a substrate, an active layer on the substrate, a gate insulating layer on the active layer, and a gate electrode on the gate insulating layer. The gate electrode includes an alloy layer, a first metal capping layer, and a second metal capping layer. The first metal capping layer is located on the top surface of the alloy layer, and the second metal capping layer is located on the top surface of the first metal capping layer and extends along both sides of the alloy layer to the gate insulating layer. This protects the alloy layer of the gate electrode from film rupture.

Description

Technical Field

[0001] This invention relates to a thin-film transistor and a display device, and more particularly to a thin-film transistor having a specific gate electrode structure and a display device comprising the same. Background Technology

[0002] Thin-film transistors (TFTs) are now widely used in display devices to control pixels. These devices can be, for example, liquid crystal displays (LCDs) or micro light-emitting diode (micro LED) displays. Specifically, when used in LCDs, TFTs act as electronic switches to control the liquid crystal pixels; when used in micro LED displays, they control the current to the light-emitting pixels, thereby controlling brightness.

[0003] High-end display devices (such as mobile phones or laptops) often use low-temperature polysilicon (LTPS) as the active layer material for their thin-film transistors. Because LTPS requires a high-temperature fabrication process, the gate electrode must be made of a high-temperature resistant metal. However, commonly used metal materials have excessively high resistance, which can easily lead to insufficient charging rates. Furthermore, the high-temperature fabrication process can easily cause hydrogen diffusion, potentially resulting in metal film rupture and consequently affecting the turn-on current (I0). on Insufficient display and abnormal screen display.

[0004] Therefore, there is an urgent need to provide a thin-film transistor to improve the above-mentioned problems. Summary of the Invention

[0005] One aspect of the present invention is to provide a thin-film transistor in which an alloy layer is covered by a second metal capping layer and extends along both sides of the alloy layer to protect the alloy layer from film rupture.

[0006] Another aspect of the present invention is to provide a display device comprising a thin-film transistor as described above.

[0007] According to one aspect of the present invention, a thin-film transistor is provided, comprising a substrate, an active layer on the substrate, a gate insulating layer on the active layer, and a gate electrode on the gate insulating layer. The gate electrode comprises an alloy layer, a first metal capping layer, and a second metal capping layer. The first metal capping layer is located on the top surface of the alloy layer, and the second metal capping layer is located on the top surface of the first metal capping layer and extends along both sides of the alloy layer to the gate insulating layer.

[0008] According to one embodiment of the present invention, the shortest distance between the end of the portion of the second metal capping layer located on the gate insulating layer and the alloy layer is not less than 0.05 μm.

[0009] According to one embodiment of the present invention, the active layer includes a lightly doped region and a heavily doped region, and a portion of the second metal capping layer is located on the lightly doped region.

[0010] According to one embodiment of the present invention, the second metal capping layer does not extend onto the heavily doped region.

[0011] According to one embodiment of the present invention, the first metal coating layer and the second metal coating layer are composed of a single metal.

[0012] According to one embodiment of the present invention, the first metal coating layer and the second metal coating layer are composed of molybdenum, tungsten or titanium, and the alloy layer is composed of aluminum alloy, tungsten alloy or molybdenum alloy.

[0013] According to one embodiment of the present invention, the thickness of the first metal cover layer is less than or equal to the thickness of the second metal cover layer.

[0014] According to one embodiment of the present invention, the first metal cover layer has a first thickness, the second metal cover layer has a second thickness, and the ratio of the second thickness to the sum of the first thickness and the second thickness is 1 / 2 to less than 1.

[0015] According to one embodiment of the present invention, the thickness of the second metal overlay is 500 Å to 1500 Å.

[0016] According to another aspect of the present invention, a display device is provided, which is the aforementioned thin-film transistor.

[0017] The thin-film transistor and display device incorporating the present invention protect the alloy layer of the gate electrode from rupture by providing a first metal capping layer and a second metal capping layer, thereby increasing and stabilizing the turn-on current and preventing abnormal display of the display device. Attached Figure Description

[0018] A better understanding of the present invention will be obtained by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, as is standard practice in the industry, many features are not drawn to scale. In fact, for clarity of discussion, the dimensions of many features may be arbitrarily scaled.

[0019] Figures 1A to 1C This is a cross-sectional view of an intermediate stage in the fabrication process of a thin-film transistor according to some embodiments of the present invention.

[0020] Figure 2This is a cross-sectional view of the gate electrode of a thin-film transistor according to some embodiments of the present invention.

[0021] Symbol Explanation

[0022] 101: Substrate

[0023] 110: Active (Proactive) Layer

[0024] 112: Channel (Ditch) Area

[0025] 114: Lightly doped region

[0026] 116: Heavily doped region

[0027] 120: Gate insulating layer

[0028] 130: Gate electrode

[0029] 132: Alloy layer

[0030] 132A: Top surface

[0031] 132B: Sidewall

[0032] 135: First metal overlay

[0033] 135A: Top surface

[0034] 138: Second metal overlay

[0035] 138P: Partial

[0036] T1, T2, T3: Thickness

[0037] Y: Length Detailed Implementation

[0038] The following disclosure provides numerous different embodiments or illustrations to implement various features of the invention. The specific examples of components and configurations described below are for the purpose of simplifying the invention. These are, of course, merely illustrative and are not intended to be limiting. For example, a description of a first feature being formed on or above a second feature includes embodiments where the first and second features are in direct contact, as well as embodiments where other features are formed between the first and second features such that the first and second features are not in direct contact. Furthermore, the invention repeats element symbols and / or letters in various specific examples. This repetition is for the purpose of simplifying and clarifying the description and does not imply a relationship between the various discussed embodiments and / or configurations.

[0039] Furthermore, spatially relative terms, such as "below," "below," "lower," "above," and "upper," are used to facilitate the description of the relationship between the parts or features depicted in the accompanying drawings and other parts or features. In addition to the directions depicted in the drawings, spatially relative terms also include different orientations of the elements during use or operation. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used in this invention can also be interpreted in this way.

[0040] The manufacture and use of embodiments of the present invention are discussed in detail below. However, it will be understood that the embodiments provide many applicable inventive concepts that can be implemented in a wide variety of specific contexts. The specific embodiments discussed are for illustrative purposes only and are not intended to limit the scope of the invention.

[0041] As used in this invention, "around," "about," "approximately," or "substantially" generally mean within 20 percent, 10 percent, or 5 percent of the stated value or range.

[0042] As described above, the present invention provides a thin-film transistor and a display device including the same, which protects the alloy layer of the gate electrode from rupture by setting a first metal capping layer and a second metal capping layer, thereby increasing and stabilizing the turn-on current and avoiding abnormal display of the display device.

[0043] Figures 1A to 1C This is a cross-sectional view illustrating an intermediate stage in the fabrication process of a thin-film transistor according to some embodiments of the present invention. The following utilizes... Figures 1A to 1C This section explains the main fabrication process of thin-film transistors. First, please refer to... Figure 1A , Figure 1A The structure includes a substrate 101, an active layer 110 on the substrate 101, a gate insulating layer 120 on the active layer 110, and an alloy layer 132 on the gate insulating layer 120. In some embodiments, the active layer 110 is formed of polysilicon. In some embodiments, the active layer 110 includes a channel region 112, two lightly doped regions 114, and two heavily doped regions 116, wherein the channel region 112 is undoped or very lightly doped. In this embodiment, the channel region 112 is located between the two lightly doped regions 114, while the two heavily doped regions 116 are located at opposite ends of the active layer 110. In other words, one of the lightly doped regions 114 is located between one of the heavily doped regions 116 and the channel region 112.

[0044] In some embodiments, the alloy layer 132 is disposed directly above the channel region 112. In some specific examples, the alloy layer 132 is formed of an aluminum alloy, a tungsten alloy, a molybdenum alloy, or other suitable metal alloy. The alloy layer 132 uses the aforementioned metal alloy to have high-temperature resistance properties, thus enabling it to withstand the high-temperature fabrication process of polycrystalline silicon.

[0045] Next, please refer to Figure 1B A first metal capping layer 135 is disposed on the top surface 132A of the alloy layer 132. In some embodiments, the first metal capping layer 135 completely covers the top surface 132A of the alloy layer 132. In some specific examples, the first metal capping layer 135 is formed of a single metal, such as molybdenum, tungsten, titanium, or other suitable metal. Using a pure metal as the first metal capping layer 135 can more effectively protect the alloy layer 132.

[0046] Specifically, the formation of the first metal cover layer 135 includes setting a photoresist layer and a photomask, performing development and etching steps to form the desired pattern, and then removing the excess portion.

[0047] Then, please see Figure 1C A second metal capping layer 138 is disposed on the top surface 135A of the first metal capping layer 135 and extends laterally along the sidewalls 132B of the alloy layer 132 to the gate insulating layer 120. In other words, the second metal capping layer 138 completely covers the alloy layer 132 and the first metal capping layer 135. Thus, the gate electrode 130, comprising the alloy layer 132, the first metal capping layer 135, and the second metal capping layer 138, is formed on the gate insulating layer 120. The arrangement of the first metal capping layer 135 and the alloy layer 132 is for switching the gate electrode 130. The first metal capping layer 135 and the second metal capping layer 138 protect the alloy layer 132 of the gate electrode 130 from film rupture, thereby increasing and stabilizing the turn-on current (I0). on ).

[0048] In some embodiments, the second metal capping layer 138 is formed of a single metal, such as molybdenum, tungsten, titanium, or other suitable metal. In some embodiments, the first metal capping layer 135 and the second metal capping layer 138 are formed of the same or different metals, preferably the same. The second metal capping layer 138, by completely covering the alloy layer 132 with pure metal, can more effectively protect the alloy layer 132 from the risk of film rupture and can improve the problem of insufficient charging rate.

[0049] Specifically, the second metal capping layer 138 is formed using the same fabrication process as the first metal capping layer 135, particularly using the same photomask, without requiring a different photomask. The difference between the second metal capping layer 138 and the first metal capping layer 135 can be achieved simply by adjusting the parameters of the etching step. Therefore, no additional adjustments to other step parameters or equipment are necessary.

[0050] Please continue reading. Figure 1C The portion 138P of the second metal capping layer 138 extending onto the gate insulating layer 120 has a length Y. It should be further noted that the length Y is defined as the shortest distance between the end of the portion 138P and the adjacent alloy layer 132. In some embodiments, the length Y is not less than about 0.05 μm. In some embodiments, the length Y of the portion 138P of the second metal capping layer 138 is from about 0.05 μm to about 1 μm. When the length Y of the portion 138P of the second metal capping layer 138 is within the aforementioned range, the underlying alloy layer 132 can be effectively protected. The length Y of the portion 138P of the second metal capping layer 138 is proportional to the thickness of the second metal capping layer 138 and is related to the parameters of its etching step. Therefore, the parameters of the etching step can be adjusted according to application requirements to obtain the desired length Y of the portion 138P of the second metal capping layer 138.

[0051] In some embodiments, a portion 138P of the second metal capping layer 138 is located on the lightly doped region 114. In some embodiments, the portion 138P of the second metal capping layer 138 extends to the end of the lightly doped region 114 but does not extend to the heavily doped region 116. In some specific examples, the width of the overlap between the portion 138P of the second metal capping layer 138 and the lightly doped region 114 is at least 1 / 10 of the width of the lightly doped region 114, preferably about 1 / 10 to about 1. When the second metal capping layer 138 is disposed on the lightly doped region 114, the electrical performance of the thin-film transistor can be improved, and the problem of insufficient charge rate can be mitigated.

[0052] Please see Figure 2 This is a cross-sectional view illustrating the gate electrode 130 of a thin-film transistor according to some embodiments of the present invention. In some embodiments, the thickness T1 of the alloy layer 132 is not less than 3000 Å, preferably about 3000 Å to about 8000 Å. Since the resistance is lower when the gate electrode 130 is thicker, the alloy layer 132 with a thickness T1 in the aforementioned range can have a more appropriate resistance, which helps to improve the problem of insufficient charging rate in thin-film transistor applications.

[0053] In some embodiments, the thickness T2 of the first metal capping layer 135 is not less than 500 Å, preferably from about 500 Å to about 1500 Å. In some embodiments, the thickness T3 of the second metal capping layer 138 is not less than 500 Å, preferably from about 500 Å to about 1500 Å. In some embodiments, the thickness T2 of the first metal capping layer 135 is less than or equal to the thickness T3 of the second metal capping layer 138. In some embodiments, the thickness T3 of the second metal capping layer 138 is the ratio of the thickness T2 of the first metal capping layer 135 to the thickness T3 of the second metal capping layer 138 (…). The thickness T2 of the first metal capping layer 135 and the thickness T3 of the second metal capping layer 138 also affect the resistance of the gate electrode 130, so it is preferred to have the aforementioned thickness range.

[0054] In some embodiments, the thin-film transistor described above can be an N-type metal oxide semiconductor (NMOS) field-effect transistor or a P-type metal oxide semiconductor (PMOS) field-effect transistor.

[0055] The display device provided by the present invention includes the thin-film transistor described above. In some embodiments, the display device may be a liquid crystal display (LCD) or a micro light-emitting diode (micro LED).

[0056] Based on the above, the thin-film transistor and display device containing the present invention, by providing a first metal capping layer and a second metal capping layer, protect the alloy layer of the gate electrode from film rupture, thereby increasing and stabilizing the turn-on current and preventing abnormal display of the display device.

[0057] Although the present invention has been disclosed above with several embodiments, it is not intended to limit the present invention. Any person skilled in the art to which this invention pertains may make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A thin-film transistor, comprising: Substrate; The active layer is located on the substrate; A gate insulating layer is located on the active layer; and A gate electrode is located on the gate insulating layer, wherein the gate electrode comprises: Alloy layer; A first metallic overlay is located on the top surface of the alloy layer; and A second metal capping layer is located on the top surface of the first metal capping layer and extends along both sides of the alloy layer to the gate insulating layer.

2. The thin-film transistor of claim 1, wherein the shortest distance between the end of the second metal capping layer located on a portion of the gate insulating layer and the alloy layer is not less than 0.05 μm.

3. The thin-film transistor of claim 1, wherein the active layer comprises a lightly doped region and a heavily doped region, and a portion of the second metal capping layer is located on the lightly doped region.

4. The thin-film transistor of claim 3, wherein the second metal capping layer does not extend onto the heavily doped region.

5. The thin-film transistor of claim 1, wherein the first metal capping layer and the second metal capping layer are composed of a single metal.

6. The thin-film transistor of claim 1, wherein the first metal capping layer and the second metal capping layer are composed of molybdenum, tungsten or titanium, and the alloy layer is composed of an aluminum alloy, a tungsten alloy or a molybdenum alloy.

7. The thin-film transistor of claim 1, wherein the thickness of the first metal capping layer is less than or equal to the thickness of the second metal capping layer.

8. The thin-film transistor of claim 1, wherein the first metal capping layer has a first thickness, the second metal capping layer has a second thickness, and the ratio of the second thickness to the sum of the first thickness and the second thickness is 1 / 2 to less than 1.

9. The thin-film transistor of claim 1, wherein the thickness of the second metal overlay is 500 Å to 1500 Å.

10. A display device comprising a thin-film transistor as claimed in any one of claims 1 to 9.

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