Superjunction structures and their fabrication methods, semiconductor devices, electronic devices

Abstract

This application provides a superjunction structure and its fabrication method, semiconductor device, and electronic device. The method includes forming multiple first grooves within a first epitaxial layer of a first conductivity type, selecting one of the first grooves as a position alignment mark, forming a first superjunction region within the first epitaxial layer, and then epitaxially forming a second epitaxial layer of the first conductivity type on the first epitaxial layer. During the epitaxial formation and filling of the first grooves in the second epitaxial layer, at least one second groove naturally forms on the side of the second epitaxial layer facing away from the substrate at a position corresponding to the first groove. This allows the second superjunction region to be directly aligned and connected with the first superjunction region in the vertical direction by using one of the corresponding second grooves in the second epitaxial layer as a position alignment mark during the subsequent formation of the second superjunction region within the second epitaxial layer. This eliminates the need for additional marking or etching processes, thereby reducing the complexity of the existing superjunction structure fabrication process.

Description

Technical Field

[0001] This application relates to the field of semiconductor device manufacturing technology, and more specifically, to a superjunction structure and its preparation method, a semiconductor device, and an electronic device. Background Technology

[0002] Silicon carbide, as a wide bandgap semiconductor material, possesses excellent physical properties such as wide bandgap, high breakdown electric field, and high thermal conductivity. As a result, superjunction structure devices based on silicon carbide materials are widely used in new energy vehicles, photovoltaic energy storage, smart grids and other fields due to their characteristics of high temperature resistance, high voltage resistance, high frequency and high power, and have extremely high industrial value.

[0003] Currently, the fabrication process of superjunction devices generally requires two or more epitaxial processes, and each epitaxial growth overwrites the photolithographic marks prepared in the previous stage. To ensure the accuracy of subsequent processes, related technologies perform photolithography again after each epitaxial growth to form new alignment marks. However, multiple photolithographic alignment operations not only increase the complexity of the fabrication process and reduce production efficiency, but also severely restrict the large-scale, high-quality fabrication of silicon carbide superjunction devices. Summary of the Invention

[0004] To address the aforementioned problems, the first aspect of this application provides a method for preparing a superjunction structure, comprising: A substrate is provided, and a first epitaxial layer of a first conductivity type is formed on the substrate; Multiple first grooves with different opening sizes are formed on the side of the first epitaxial layer opposite to the substrate; Among the plurality of first grooves, the first groove with a first opening size is selected as a position alignment mark to form a first superjunction region in the first epitaxial layer. The first superjunction region includes a plurality of first pillars, the plurality of first pillars having a second conductivity type, each first pillar extending along a first direction perpendicular to the substrate surface and spaced apart from each other and arranged in an array in a second direction parallel to the substrate surface. At least one second epitaxial layer of a first conductivity type is formed on the first epitaxial layer, and at least one second groove is naturally formed on the side of each second epitaxial layer facing away from the substrate at a position corresponding to the plurality of first grooves; In each of the second epitaxial layers, at least one of the second grooves is selected as a position alignment mark, and a second superjunction region is formed in the corresponding second epitaxial layer. The second superjunction region includes a plurality of second pillars, each of which has the second conductivity type. The plurality of second pillars correspond one-to-one with the plurality of first pillars, and each second pillar is aligned with the corresponding first pillar in the first direction.

[0005] The aforementioned superjunction structure fabrication method involves forming multiple first grooves with different opening sizes within a first epitaxial layer of a first conductivity type. Then, a first groove with a first opening size is selected from these grooves as a position alignment mark. A first superjunction region is formed within a predetermined area of ​​the first epitaxial layer. Next, a second epitaxial layer of the first conductivity type is epitaxially formed on the first epitaxial layer. During the epitaxial formation and filling of the first grooves in the second epitaxial layer, multiple second grooves naturally form on the side of the second epitaxial layer facing away from the substrate at positions corresponding to the first grooves. Therefore, during the subsequent formation of the second superjunction region at a predetermined position in the second epitaxial layer, the second grooves with second opening sizes formed in the second epitaxial layer can be directly used as position alignment marks. This allows each second pillar of the second conductivity type in the second superjunction region to be vertically aligned and connected to each first pillar of the second conductivity type in the first superjunction region, eliminating the need for additional marking or etching processes. This reduces the complexity of existing superjunction structure fabrication processes and further improves the production efficiency of superjunction structures and related semiconductor devices.

[0006] A second aspect of this application provides a superjunction structure, comprising: Substrate; A first epitaxial layer of a first conductivity type is provided in the first epitaxial layer, which has a plurality of first grooves with different opening sizes and a plurality of first pillars of a second conductivity type. Each first pillar extends along a first direction perpendicular to the surface of the substrate and is spaced apart from each other and arranged in an array in a second direction parallel to the surface of the substrate. At least one second epitaxial layer of a first conductivity type is provided, the second epitaxial layer being located on the first epitaxial layer; each second epitaxial layer has at least one second groove on the side facing away from the substrate corresponding to the position of the first groove, and the position of each second groove corresponds to one of the first grooves; furthermore, each second epitaxial layer also has a plurality of second pillars of a second conductivity type, and the plurality of second pillars of each second epitaxial layer correspond one-to-one with the plurality of first pillars of the first epitaxial layer, and each second pillar and the corresponding first pillar are aligned with each other in the first direction.

[0007] In the aforementioned superjunction structure, by controlling the formation position of the first groove and the formation thickness of the second epitaxial layer within the first groove, and by corresponding the position of each second groove to the position of a first groove, the formation position and opening size of the second groove can be selectively controlled. This allows the second groove with a preset opening size to be selected as a position alignment mark within the corresponding second epitaxial layer during the alignment process of forming the second superjunction region, without the need for additional mark forming or etching processes. This reduces the need for repeated preparation of position alignment marks, simplifies the process flow, and lowers the manufacturing cost, thereby reducing the complexity of the existing superjunction structure manufacturing process and further improving the production efficiency of superjunction structures and related semiconductor devices.

[0008] A third aspect of this application provides a semiconductor device including the superjunction structure provided in the second aspect above.

[0009] The fourth aspect of this application provides an electronic device, including the semiconductor device provided in the third aspect above.

[0010] The semiconductor device provided in the third aspect and the electronic device provided in the fourth aspect both possess the semiconductor device provided in the second aspect, and therefore possess all the beneficial effects of the semiconductor device provided in the second aspect, which will not be elaborated here. Attached Figure Description

[0011] Figure 1 This is a top view schematic diagram of a superstructure according to an embodiment of this application.

[0012] Figures 2-10 for Figure 1 A schematic diagram of the cross-sectional structure along line AA during the formation process of the superstructure.

[0013] Figure 11 This is a structural block diagram of an electronic device according to an embodiment of this application.

[0014] Explanation of key component symbols: 110 Substrate; 120 First epitaxial layer; 121 First trench; 122 Trench; 130 Buffer layer; 140 First superjunction region; 141 First pillar; 150 Second epitaxial layer; 151 Second trench; 1501 Pretreatment layer; 160 Second superjunction region; 161 Second pillar; 200 Semiconductor device; 210 Circuit board; S Position alignment mark.

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings of the embodiments of this application will be described below in conjunction with specific implementation methods. Obviously, the drawings and embodiments described below only involve some embodiments of this application and are not intended to limit this disclosure. Detailed Implementation

[0016] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the embodiments of this application, and should not be construed as limiting this application.

[0017] In the description of the embodiments of this application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the implementation methods of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0018] In the description of the embodiments of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features.

[0019] In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0020] In the description of the embodiments of this application, unless otherwise stated, the terms "installation", "connection" and "linking" should be interpreted broadly. For example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections, electrical connections, or connections that can communicate with each other; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two components or interactive relationships between two components.

[0021] Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0022] As described in the background art, currently, the fabrication process of superjunction structure devices generally requires two or more epitaxial processes. Each epitaxial growth will cover the photolithographic marks prepared in the previous stage, so that subsequent epitaxial processes need to be photolithographically re-performed and new position alignment marks need to be formed in order to maintain the fabrication accuracy of the superjunction structure. The multiple photolithographic alignment processes will increase the complexity of the fabrication process and reduce production efficiency.

[0023] Based on the above problems, this application provides a method for fabricating a superjunction structure. First, multiple first grooves with different opening sizes are formed in a first epitaxial layer of a first conductivity type. Then, a first groove with a first opening size is selected from the multiple first grooves as a position alignment mark. Multiple first pillars of a second conductivity type are formed in a predetermined area in the first epitaxial layer, arranged sequentially and spaced apart in the horizontal direction. Next, at least one second epitaxial layer of the first conductivity type is epitaxially formed on the first epitaxial layer. During the epitaxial formation and filling of the first grooves, multiple second grooves are naturally formed on the side of the second epitaxial layer facing away from the substrate at positions corresponding to the first grooves. Therefore, during the subsequent formation of multiple second pillars of the second conductivity type arranged sequentially and spaced apart in the horizontal direction at predetermined positions of each second epitaxial layer, the second grooves with a second opening size formed in the same second epitaxial layer can be directly used as position alignment marks. This allows each second pillar to be aligned and connected with each first pillar in the vertical direction without the need for additional marking or etching processes. This reduces the complexity of the existing superjunction structure fabrication process and further improves the production efficiency of superjunction structures and related semiconductor devices.

[0024] To make the above-mentioned objectives, features and beneficial effects of this application more apparent and understandable, the specific embodiments of the invention of this application will be described in detail below with reference to the accompanying drawings.

[0025] Figure 1 This is a top view schematic diagram of the superstructure in one embodiment of this application. Figures 2 to 10 for Figure 1 A schematic diagram of the cross-sectional structure along line AA during the formation of the superstructure.

[0026] According to a first aspect of this application, a method for preparing a superjunction structure is provided.

[0027] An embodiment of this application illustrates a method for preparing a superjunction structure, which includes the following steps: Step S100: Provide a substrate 110 and form a first epitaxial layer 120 of a first conductivity type on the substrate 110.

[0028] like Figure 2 and Figure 3 As shown, substrate 110 refers to a single-crystal semiconductor substrate, including but not limited to one of Si substrate, Ge substrate, GeSi substrate, GaAs substrate or SiC substrate.

[0029] The first epitaxial layer 120 is a SiC epitaxial layer, including but not limited to one of a 4H-SiC epitaxial layer or a 6H-SiC epitaxial layer. Furthermore, the first epitaxial layer 120 can be grown on the substrate 110 using conventional epitaxial processes, including but not limited to vapor phase epitaxy and molecular beam epitaxy. For example, the first epitaxial layer 120 can be formed on the substrate 110 using vapor phase epitaxy, resulting in a uniform overall thickness that is easy to control, which is beneficial for improving the performance of the corresponding semiconductor device.

[0030] The first conductivity type refers to the doping type of impurity ions that is opposite to the subsequent second conductivity type. This includes N-type or P-type impurity ion doping, and the specific type can be determined based on the device type corresponding to the superjunction structure. For example, when the first conductivity type is N-type doping, the second conductivity type is P-type doping, or vice versa.

[0031] Among them, P-type impurity ions include impurity ions such as aluminum ions, boron ions, or indium ions, while N-type impurity ions include impurity ions such as nitrogen ions, phosphorus ions, or arsenic ions.

[0032] As an example, when the first epitaxial layer 120 is a SiC epitaxial layer, such as Figure 2 As shown, the substrate 110 can be an intrinsic SiC substrate of the same material as the first epitaxial layer 120, or it can be a SiC substrate of the same conductivity type as the first epitaxial layer 120. In this case, the first epitaxial layer 120 can be directly epitaxially formed on the substrate 110.

[0033] When the first epitaxial layer 120 is SiC, such as Figure 3 As shown, the substrate 110 can also be made of a different material than the first epitaxial layer 120, such as a single crystal silicon substrate. In this case, in order to further improve the epitaxial formation quality of the first epitaxial layer 120 on the substrate 110 and reduce the defect density of the first epitaxial layer 120, a buffer layer 130 can be formed on the substrate 110 first, and then the first epitaxial layer 120 can be epitaxially formed on the buffer layer 130.

[0034] The buffer layer 130 can be a gradient-doped SiC buffer layer, wherein the gradient doping is configured such that the doping concentration is gradually adjusted from the side near the substrate 110 to the side near the first epitaxial layer 120 to match the doping concentration of the first epitaxial layer 120. Alternatively, the buffer layer 130 can also be a lattice-matched transition buffer layer, including AlN, GaN, or a composite layer of SiC and AlN with a lattice constant between Si and SiC.

[0035] It should be noted that the material composition of the heterogeneous substrate 110 and the buffer layer 130 is only used as an example for illustration. The specific type of combination of substrate 110 and buffer layer 130 is not specifically limited here.

[0036] In step S200, a plurality of first grooves 121 with different opening sizes are formed on the side of the first epitaxial layer 120 away from the substrate 110.

[0037] like Figure 4 As shown, the first groove 121 refers to a plurality of patterned grooves formed on the surface of the first epitaxial layer 120, which can be formed by etching from the surface of the first epitaxial layer 120 along the thickness direction using dry or wet etching methods.

[0038] In some embodiments, the step of forming a plurality of first grooves 121 with different opening sizes within the first epitaxial layer 120 includes: A first mask layer (not shown) is formed on the first epitaxial layer 120. The first mask layer includes a plurality of first window regions that expose a portion of the surface of the first epitaxial layer 120, and the plurality of first window regions have different opening sizes. Using the first mask layer as an etching mask, the first epitaxial layer 120 is etched through multiple first window areas to form a patterned first groove 121 on the surface of the first epitaxial layer 120. Remove the first mask layer on the first epitaxial layer 120.

[0039] The patterned first groove 121 can be one or more of circular, square, or other polygonal grooves. Furthermore, multiple first grooves 121 with different opening sizes are formed together on the surface of the first epitaxial layer 120 opposite to the substrate 110, forming a groove array.

[0040] For example, the first groove 121 is a plurality of square grooves etched into the first epitaxial layer 120. Furthermore, the etching depth of the first groove 121 ranges from 1μm to 100μm, which is less than the actual thickness of the first epitaxial layer 120.

[0041] In addition, the first mask can be removed by chemical mechanical polishing (CMP) to achieve global planarization of the first mask layer, while ensuring that the surface of the underlying first epitaxial layer 120 is flat and undamaged, providing a clean and flat process interface for the subsequent fabrication of the superjunction structure.

[0042] In step S300, a first groove 121 with a first opening size is selected from the plurality of first grooves 121 as a position alignment mark, and a first superjunction region 130 is formed in the first epitaxial layer 120. The first superjunction region 130 includes a plurality of first pillars 141, the plurality of first pillars 141 having a second conductivity type, each first pillar 141 extending along a first direction perpendicular to the surface of the substrate 110, and spaced apart from each other and arranged in an array in a second direction parallel to the surface of the substrate 110.

[0043] like Figure 5 and Figure 6 As shown, the first direction refers to the direction perpendicular to the surface of the substrate 110, or the direction of the thickness of the first epitaxial layer 120, which is also the X direction in the figure. The second direction refers to the direction parallel to the surface of the substrate 110, which is the horizontal direction, and is also the Y direction in the figure.

[0044] The first opening size refers to the size of any first groove 121 among multiple first grooves 121 with different opening sizes that can meet the requirements of the lithography machine for accurate identification. For example, the first opening size is the smallest opening size among multiple first grooves 121 with different opening sizes, and the opening sizes of subsequent first grooves 121 are opening sizes that increase linearly with respect to the first opening size.

[0045] For example, the opening size of the first groove 121 with the smallest opening size is set to X0, and the opening sizes of the other first grooves 121 sequentially satisfy: Xn = X 0 +D 1 +D 2 +……D n-1 .

[0046] in, n The number of first grooves 121 formed in the first epitaxial layer 120, and n D is a natural number greater than 1. D is the difference in opening size between any two adjacent first grooves 121, and the difference can be the same.

[0047] Since the first pillar 141 extends in the first epitaxial layer 120 along the first direction and connects with the portion of the first epitaxial layer 120 along the adjacent first conductivity type in the second direction to form a first superjunction region 140, a charge-complementary local superjunction structure is formed, thereby optimizing the device's withstand voltage and on-resistance.

[0048] In some embodiments, such as Figure 6 As shown, the step of forming a first superjunction region 140 within the first epitaxial layer 120 includes: Among a plurality of first grooves 121, a first groove 121 with a first opening size is selected as a position alignment mark S, and a second mask layer (not shown) is formed on the first epitaxial layer 120. The second mask layer includes an ion implantation window that exposes a portion of the surface of the first epitaxial layer 120.

[0049] An ion implantation process is used to implant impurity ions of a second conductivity type into a preset region of the first epitaxial layer 120 to form a first pillar 141 of multiple second conductivity types.

[0050] Remove the second mask layer on the first epitaxial layer 120.

[0051] The preset region of the first epitaxial layer 120 refers to the region corresponding to the ion implantation window of the second mask layer, and the preset region does not overlap with the region corresponding to the first groove 121.

[0052] Furthermore, the formation position of the first pillar 141 corresponds to the ion implantation position of the impurity ions of the second conductivity type in the first epitaxial layer 120, and extends to a predetermined depth along the first direction, and is connected with the portion of the first epitaxial layer 120 along the adjacent first conductivity type in the second direction to form a first superjunction region 140.

[0053] In other embodiments, such as Figure 5 and Figure 6 As shown, the step of forming a first superjunction region 140 in a predetermined region within the first epitaxial layer 120 includes: Among a plurality of first grooves 121, a first groove 121 with a first opening size is selected as a position alignment mark S, and a second mask layer (not shown) is formed on the first epitaxial layer 120. The second mask layer includes an ion implantation window that exposes a portion of the surface of the first epitaxial layer 120.

[0054] A dry or wet etching process is used to etch a preset area of ​​the first epitaxial layer 120 to form multiple trenches 122 that extend along the first direction and are spaced apart from each other in the second direction. A material of a second conductivity type is epitaxially grown inside and outside the trench 122 using an epitaxial process, and the trench 122 is fully filled to form a plurality of first pillars 141 of the second conductivity type. The second mask layer on the first epitaxial layer 120 and the second conductive material layer outside the trench 122 are removed, and the first groove 121 is exposed, thereby planarizing the surface of the first epitaxial layer 120.

[0055] The preset region of the first epitaxial layer 120 refers to the region corresponding to the second etching window of the second mask layer, and the preset region does not overlap with the region corresponding to the first mark 121.

[0056] For example, the material of the second mask layer may be the same as or different from that of the first mask layer, including but not limited to hard mask layers composed of one or more materials such as silicon oxide and silicon nitride. Its ion implantation window or second etching window can be precisely controlled according to the process requirements of subsequent ion implantation or etching to form the first pillar 141 of the second conductivity type. At the same time, the second mask layer is also used to mask and protect the non-target areas of the first epitaxial layer 120, preventing impurity ions or etching liquids and etching gases from eroding them. This allows the first pillar 141 in the first superjunction region 140 to connect with the portion of the first epitaxial layer 120 along the adjacent first conductivity type, forming a charge-complementary local superjunction structure, thereby ensuring the optimization of the device's withstand voltage and on-resistance.

[0057] The second mask layer can also be removed by chemical mechanical polishing (CMP) to achieve global planarization of the second mask layer and / or the material layer of the second conductivity type, while ensuring that the surface of the underlying first epitaxial layer 120 is flat and undamaged, providing a clean and flat process interface for the subsequent fabrication of the superjunction structure.

[0058] In step S400, at least one second epitaxial layer 150 of the first conductivity type is formed on the first epitaxial layer 120. Each second epitaxial layer 150 has at least one second groove 121 naturally formed on the side facing away from the substrate 110 at a position corresponding to the plurality of first grooves 121.

[0059] like Figure 7 As shown, the second groove 151 refers to the patterned groove that is naturally formed during the formation of the second epitaxial layer 150. Since the formation of the second groove 151 does not require additional marking or etching processes, and there is a known and stable relative positional relationship between each second groove 151 and the corresponding first groove 121, the second groove 151 can be directly used as a position alignment mark S, reducing the complexity of the existing superjunction structure fabrication process and further improving the production efficiency of superjunction structures and related semiconductor devices.

[0060] Since the first groove 121 is a patterned groove etched in the first epitaxial layer 120, during the formation of the second epitaxial layer 150 on the first epitaxial layer 120, the constituent material of the second epitaxial layer 150 will nucleate from the surface of the first epitaxial layer 120 away from the substrate 110, the sidewall of the first groove 121, and the bottom of the first groove 121, and gradually deposit, filling the interior of the first groove 121. As a result, the second groove 151 will naturally form on the side of the second epitaxial layer 150 away from the substrate 110 at the position corresponding to the multiple first grooves 121.

[0061] Furthermore, since each second groove 151 is formed at a position corresponding to a first groove 121, and the second epitaxial layer 150 will also be deposited directly on the sidewall of the first groove 121 during the process of partially filling the first groove 121, the opening size of the corresponding second groove 151 formed in the second epitaxial layer 150 is smaller than that of the corresponding first groove 121.

[0062] Therefore, by controlling the deposition thickness (thickness along the second direction) of the sidewall of the second epitaxial layer 150 in the first groove 121, the opening size of each second groove 151 naturally formed within the second epitaxial layer 150 can be controlled. Simultaneously, based on the relative positional spacing between each first groove 121 (which can be controlled during the etching process of the first groove 121 to maintain a relatively fixed positional relationship between each first groove 121), the position and size of the second groove 151, serving as the subsequent positional alignment mark S, are controlled. This provides a precise alignment reference for the subsequent formation of the second superjunction region 160 within the second epitaxial layer 150, and for the second superjunction region 160 and the first superjunction region 140 to electrically connect and form a superjunction structure.

[0063] For example, such as Figure 8 As shown, prior to the step of forming at least one second epitaxial layer 150 on the first epitaxial layer 120, the method further includes: HCl is used as an additional reactant to control and increase the Cl / Si ratio of the reactant gas during the epitaxial deposition of the second epitaxial layer 150, so as to perform surface pretreatment on the inner walls of the multiple first grooves 121 and form a pretreatment layer 1501 at the bottom of the first grooves 121.

[0064] Here, the reaction gas for forming the second epitaxial layer 150 typically includes a silicon-containing precursor gas and a carbon-containing precursor gas. The silicon-containing precursor gas may include, but is not limited to, at least one of silane (SiH4), trichlorosilane (SiHCl3), or silicon tetrachloride (SiCl4), and the carbon-containing precursor gas may include, but is not limited to, at least one of propane (C3H8), ethylene (C2H4), or methane (CH4).

[0065] Since the first groove 121 is formed on the surface of the first epitaxial layer 120 by etching, the inner wall (including the bottom and sidewalls) of the first groove 121 inevitably retains lattice damage, surface dangling bonds, amorphous surface layer and micro-roughness defects generated during the etching process. At the same time, the surface may adsorb etching residues. If silicon- or carbon-containing precursor gases are directly introduced to grow the second epitaxial layer 150, not only will these defects be inherited by the subsequent epitaxial layers, inducing problems such as dislocation multiplication and deep-level defects, but also, due to the non-selectivity of epitaxial growth, uneven steps, depressions and other morphological distortions will appear on the surface of the second epitaxial layer 150, affecting the integrity of the device structure and the consistency of electrical performance.

[0066] Therefore, by introducing hydrogen chloride (HCl) as an additional reactant, the chloride-to-silicon ratio (Cl / Si) of the reaction gas can be precisely increased. The chlorine free radicals generated by the dissociation of HCl exert a strong etching effect, performing comprehensive surface pretreatment on the inner wall of the first groove 121. A pretreatment layer 1501 is formed at the bottom of the first groove 121, allowing for in-situ etching to remove the amorphous layer, damaged lattice, and dangling bonds from the inner wall, repairing lattice distortion and purifying the growth interface, reducing the adverse effects of defects on subsequent epitaxial growth. Simultaneously, under the etching-dominant atmosphere of a high Cl / Si ratio, SiC can only achieve stable nucleation at the bottom of the first groove 121, where the deposition rate is greater than the etching rate, thus forming a dense, low-defect pretreatment layer 1501. However, due to the dominant etching rate, the sidewalls of the first groove 121 and the flat surface of the first epitaxial layer 120 cannot form effective deposition. This lays a good foundation for the uniform growth of the second epitaxial layer 150 under the subsequent low Cl / Si ratio conditions, ensuring that the surface of the second epitaxial layer 150 is flat and the structure is uniform, while improving the interfacial bonding strength between the second epitaxial layer 150 and the first groove 121.

[0067] In step S500, a second groove 151 with a second opening size is selected from at least one second groove 151 in each second epitaxial layer 150 as a position alignment mark, and a second superjunction region 160 is formed in the corresponding second epitaxial layer 150. The second superjunction region 160 includes a plurality of second pillars 161, each second pillar 161 having a second conductivity type. The plurality of second pillars 161 correspond one-to-one with a plurality of first pillars 131, and each second pillar 161 is aligned with the corresponding first pillar 131 in a first direction.

[0068] like Figure 7 and 9 As shown, the second opening size refers to the size of any second groove 151 among multiple second grooves 151 with different opening sizes that can meet the requirements of the lithography machine for precise identification. Since the second groove 151 is naturally formed after partially filling the first groove 121 during the deposition of the second epitaxial layer 150, the opening size of the second groove 151 is directly related to the opening size of the first groove 121 and the thickness of the corresponding second epitaxial layer 150. By controlling the thickness of the second epitaxial layer 150, especially the thickness of the second epitaxial layer 150 formed along the second direction on the sidewall of the first groove 121, the opening size of the second groove 151 can be controlled, so that the second opening size of the second groove 151, which serves as a position alignment mark S in the second epitaxial layer 150, matches the first opening size of the first groove 121, which serves as a position alignment mark S in the first epitaxial layer 120.

[0069] Here, matching the first opening size and the second opening size means that the two sizes are basically the same, similar, or have a specific quantitative relationship within the range of process error.

[0070] For example, the second opening size of the second groove 151 in the second epitaxial layer 150, which serves as a position alignment mark S, is substantially the same as the first opening size of the first groove 121 in the first epitaxial layer 120, which serves as a position alignment mark S.

[0071] Among them, such as Figure 10 As shown, the step of selecting a second groove 151 with a second opening size as a position alignment mark S from at least one second groove 151 and forming a second superjunction region 160 in the second epitaxial layer 150 is the same as the step of selecting a first groove 121 with a first opening size as a position alignment mark S from a plurality of first grooves 121 and forming a first superjunction region 140 in the first epitaxial layer 120. The specific formation process can refer to the above-described step of forming a first superjunction region 140 in the first epitaxial layer 120, which will not be described in detail here.

[0072] Since the second pillars 161 of the second conductivity type formed in the second superjunction region 160 are all aligned with the second grooves 151 with the second opening size as the position alignment mark S, and the second grooves 151 are formed on the first grooves 121 and are aligned with the formation position of a first groove 121 in the first direction, the formation position of the second pillars 161 in the second superjunction region 160 can be aligned and connected with the formation position of the first pillars 141 in the first superjunction region 140 with high precision, forming a continuous conductive path through the first epitaxial layer 120 and the second epitaxial layer 150, and connecting with the adjacent first conductivity type of part of the first epitaxial layer 120 or the second epitaxial layer 150 to construct a complete and vertically penetrating superjunction structure, thereby ensuring uniform charge compensation of the superjunction structure and improving the stability of the device's withstand voltage and electrical performance.

[0073] Meanwhile, by directly selecting the second groove 151 with the second opening size from at least one naturally formed second groove 151 as the position alignment mark S, the formation process of the position alignment mark in the subsequent epitaxy and alignment process can be reduced, which greatly simplifies the preparation process of the superjunction structure and reduces the process complexity and preparation cost.

[0074] In some embodiments, such as Figure 10 As shown, the step of forming at least one second epitaxial layer 150 of a first conductivity type on the first epitaxial layer 120 includes: A plurality of second epitaxial layers 150 (e.g., 150-1, 150-2) are formed on the first epitaxial layer 120, and each second epitaxial layer 150 has at least one second groove 151 naturally formed on the side away from the substrate 110 at a position corresponding to the plurality of first grooves 121, and the opening size of each second groove 151 decreases sequentially along the direction away from the substrate 110. In at least one second groove 151, a second groove 151 with a second opening size is selected as a position alignment mark S, and a second superjunction region 160 is formed in the corresponding second epitaxial layer 150.

[0075] Since the number of second epitaxial layers 150 formed on the first epitaxial layer 120 includes multiple layers, and each of the different second epitaxial layers 150 has a second superjunction region 160, and in the process of forming multiple second pillars 161 of the second conductivity type, the second superjunction regions 160 of the different second epitaxial layers 150 use a second groove 151 with a second opening size formed in at least one second groove 151 in the corresponding second epitaxial layer as a position alignment mark S, so that the second pillars 161 formed in the different second epitaxial layers 150 can be aligned and connected to each other in the first direction.

[0076] Furthermore, by setting the number of layers of the second epitaxial layer 150 formed on the first epitaxial layer 120 to multiple layers, and having the second pillar 161 in the multiple layers of the second epitaxial layer 150 correspond to and connect with the first pillar 141 in the first epitaxial layer 120, the reverse breakdown voltage of the device can be further improved, while ensuring that the superjunction structure has better structural integrity and electrical uniformity, thereby enabling it to meet the requirements of power devices with higher withstand voltage levels.

[0077] It should be noted that the specific number of layers of the second epitaxial layer 150 can be flexibly configured according to the design voltage withstand capability of the device, and this application does not impose specific restrictions on this.

[0078] Furthermore, the doping concentration range of impurity ions of the first conductivity type in the first epitaxial layer 120 and the different second epitaxial layers 150 is the same. The doping concentration range of impurity ions in the first pillar 141 formed in the first epitaxial layer 120 and the multiple second pillars 161 of the second conductivity type in the different second epitaxial layers 150 is the same. This can ensure that the doping characteristics and charge compensation capabilities between the first pillar 141 and the second pillar 161, and between the second pillars 161, are consistent. This avoids problems such as electric field concentration and charge imbalance caused by interlayer doping differences, thereby ensuring the overall charge balance of the superjunction structure and improving the stability and reliability of the device's electrical performance.

[0079] Furthermore, this application sets the doping concentration of impurity ions of the first conductivity type in the first epitaxial layer 120 (or the second epitaxial layer 150) to be the same as the doping concentration range of impurity ions of the second conductivity type in the first pillar 141 (or the second pillar 161). This allows for precise charge compensation in the first superjunction region 140 (or the second superjunction region 160), thereby effectively balancing the space charge region of the device under reverse bias, suppressing electric field concentration, improving the breakdown voltage and withstand voltage stability of the device, and achieving a good balance between high withstand voltage and low on-resistance.

[0080] For example, both the first epitaxial layer 120 and the different second epitaxial layers 150 are doped with nitrogen impurity ions, and the impurity ion doping concentration is 1×10⁻⁶. 14 cm -3 ~1×10 18 cm -3 For example, 1×10 14 cm -3 ~5×10 14 cm -3 5×10 14 cm -3 ~1×10 15 cm -3 1×10 15 cm -3 ~5×10 15 cm -3 5×10 15 cm -3 ~1×10 16 cm -3 1×10 16 cm -3 ~5×10 16 cm -3 5×10 16 cm -3 ~1×10 17 cm -3 1×10 17 cm -3 ~5×10 17 cm -3 5×10 17 cm -3 ~1×10 18 cm -3 The first pillar 141 (or the second pillar 161) within the first epitaxial layer 120 (or the second epitaxial layer 150) is doped with aluminum impurity ions, and the doping concentration of the impurity ions is 1×10⁻⁶. 14 cm -3 ~1×10 18 cm -3 For example, 1×10 14 cm -3~5×10 14 cm -3 5×10 14 cm -3 ~1×10 15 cm -3 1×10 15 cm -3 ~5×10 15 cm -3 5×10 15 cm -3 ~1×10 16 cm -3 1×10 16 cm -3 ~5×10 16 cm -3 5×10 16 cm -3 ~1×10 17 cm -3 1×10 17 cm -3 ~5×10 17 cm -3 5×10 17 cm -3 ~1×10 18 cm -3 .

[0081] According to a second aspect of this application, a superjunction structure is also provided.

[0082] like Figure 1 , Figure 9 and Figure 10 As shown, an embodiment of this application illustrates a superjunction structure prepared using the superjunction structure preparation method described in any embodiment of the first aspect above, comprising: a substrate 110, a first epitaxial layer 120 of a first conductivity type located on the substrate 110, and at least one second epitaxial layer 150 located on the first epitaxial layer 120. The first epitaxial layer 120 has a plurality of first grooves 121 with different opening sizes and a plurality of first pillars 141 of a second conductivity type. The plurality of first pillars 141 extend along a first direction perpendicular to the surface of the substrate 110 and are spaced apart from each other and arranged in an array in a second direction parallel to the surface of the substrate 110. The second epitaxial layer 150 has at least one second groove 151 on the side away from the substrate 110 corresponding to the position of the first groove 121. The position of each second groove 151 corresponds to one of the first grooves 121. Furthermore, each second epitaxial layer 150 also has a plurality of second pillars 161 of a second conductivity type, and each second pillar 161 of each second epitaxial layer 150 is aligned and connected to each first pillar 141 of the first epitaxial layer 120 in the first direction.

[0083] Since the position of each second groove 151 corresponds to the position of a first groove 121, this application can selectively control the formation position and opening size of the second groove 151 by controlling the formation position of the first groove 121 and the formation thickness of the second epitaxial layer 150 in the first groove 121. Thus, during the alignment process of forming the second superjunction region 160 in the second epitaxial layer 150, the second groove 151 with a preset opening size can be selected as the position alignment mark in the corresponding second epitaxial layer 150 without the need for additional mark forming or etching processes. This reduces the process steps of repeatedly preparing the position alignment mark S, simplifies the process flow, reduces the preparation cost, thereby reducing the complexity of the existing superjunction structure preparation process and further improving the production efficiency of superjunction structures and related semiconductor devices.

[0084] It should be noted that for the details of the superjunction structure provided in the second aspect embodiment that are not shown, the same applies to the superjunction structure preparation method provided in the first aspect embodiment above, which will not be described in detail here.

[0085] According to a third aspect of this application, a semiconductor device is also provided.

[0086] like Figure 9 and Figure 10 As shown, a semiconductor device 100 illustrated in one embodiment of this application includes a superjunction structure, which includes the superjunction structure provided in the second aspect embodiment above, or is formed using the superjunction structure preparation method provided in the first aspect embodiment above.

[0087] In some embodiments, the semiconductor device 100 provided in this application is a silicon carbide device. This silicon carbide device includes, but is not limited to, one of the following: a super-junction metal-oxide-semiconductor field-effect transistor (SJ-MOSFET), a super-junction insulated gate bipolar transistor (SJ-IGBT), a super-junction field-effect transistor (SJ-JFET), and a super-junction diode (SJ-SBD). This application does not specifically limit the specific type of silicon carbide device.

[0088] For example, the silicon carbide device is a metal-oxide-semiconductor field-effect transistor, which includes a gate structure, a source structure, and a drain structure, as well as the superjunction structure described in any of the above embodiments. The gate structure is disposed on the front side of the device and includes a gate insulating dielectric layer and a gate electrode located above it; the source structure includes a source contact layer forming an ohmic contact with the source region and a source electrode, the source region being disposed within the base region, which is located above the superjunction structure; the drain structure is disposed on the back side of the device, opposite to the gate and source structures on the front side of the device.

[0089] For example, the silicon carbide device described above also includes semiconductor structures such as an interlayer dielectric layer, a passivation layer, and a metal interconnect layer. The aforementioned method for fabricating the superjunction structure, combined with the aforementioned semiconductor device structure, is beneficial for improving the voltage withstand characteristics, conduction characteristics, and yield of the silicon carbide device.

[0090] According to a fourth aspect of this application, an electronic device is also provided.

[0091] like Figure 11 As shown in the figure, an electronic device 200 according to an embodiment of this application includes a circuit board 210 and a semiconductor device 100 provided in the third aspect of this application. The semiconductor device 100 is disposed on the circuit board 210.

[0092] In some embodiments, the electronic device may include, but is not limited to, power conversion devices, such as power adapters, energy storage devices, switching power supplies, DC / DC converters, photovoltaic power generation devices, and electric drive systems. In other embodiments, the electronic device may also be other devices with power conversion devices, such as consumer electronics, home electronics, automotive electronics, and financial terminal products. Consumer electronics include, for example, mobile phones, tablets, laptops, e-readers, personal digital assistants, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality terminal devices, augmented reality terminal devices, and drones. Home electronics include, for example, smart door locks, televisions, remote controls, refrigerators, and rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners). Automotive electronics include, for example, in-vehicle navigation systems. Financial terminal products include, for example, self-service terminals.

[0093] The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the above preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application should not depart from the spirit and scope of the technical solutions of this application.

Claims

1. A method for preparing a superjunction structure, characterized in that, include: A substrate is provided, and a first epitaxial layer of a first conductivity type is formed on the substrate; Multiple first grooves with different opening sizes are formed on the side of the first epitaxial layer opposite to the substrate; Among the plurality of first grooves, the first groove with a first opening size is selected as a position alignment mark to form a first superjunction region in the first epitaxial layer. The first superjunction region includes a plurality of first pillars, the plurality of first pillars having a second conductivity type, each first pillar extending along a first direction perpendicular to the substrate surface and spaced apart from each other and arranged in an array in a second direction parallel to the substrate surface. At least one second epitaxial layer of a first conductivity type is formed on the first epitaxial layer, and at least one second groove is naturally formed on the side of each second epitaxial layer facing away from the substrate at a position corresponding to the plurality of first grooves; In each of the second epitaxial layers, at least one of the second grooves is selected as a position alignment mark, and a second superjunction region is formed in the corresponding second epitaxial layer. The second superjunction region includes a plurality of second pillars, each of which has the second conductivity type. The plurality of second pillars correspond one-to-one with the plurality of first pillars, and each second pillar is aligned with the corresponding first pillar in the first direction.

2. The method for preparing a superjunction structure as described in claim 1, characterized in that, The number of the first grooves is not less than the total number of the first epitaxial layer and the second epitaxial layer, and each second groove in the second epitaxial layer that serves as a position alignment mark corresponds to one of the first grooves.

3. The method for preparing a superjunction structure as described in claim 2, characterized in that, The second preset opening size in the second epitaxial layer, which serves as a position alignment mark, is matched with the first preset opening size in the first epitaxial layer, which also serves as a position alignment mark.

4. The method for preparing a superjunction structure according to any one of claims 1 to 3, characterized in that, The first superjunction region and / or the second superjunction region are formed in the first epitaxial layer or the second epitaxial layer by ion implantation, or by a combination of etching and epitaxial filling.

5. The method for preparing a superjunction structure as described in claim 4, characterized in that, The step of forming a first superjunction region within the first epitaxial layer includes: Among the plurality of first grooves, the first groove with a first opening size is selected as the position alignment mark. The first epitaxial layer is implanted with impurity ions of the second conductivity type using the ion implantation method to form a plurality of first pillars of the second conductivity type. The plurality of first pillars of the second conductivity type are connected with the first epitaxial layer of the first conductivity type adjacent along the second direction to form the first superjunction region.

6. The method for preparing a superjunction structure as described in claim 4, characterized in that, The step of forming a first superjunction region within the first epitaxial layer includes: Among the multiple first grooves, the first groove with the first opening size is selected as the position alignment mark, and the preset area of ​​the first epitaxial layer is etched by an etching method to form multiple grooves that extend along the first direction and are spaced apart from each other in the second direction. A material of a second conductivity type is epitaxially grown inside and outside the trench to fully fill the trench and form a plurality of first pillars of the second conductivity type. The plurality of first pillars of the second conductivity type are connected to a portion of the first epitaxial layer of the first conductivity type adjacent along the second direction to form the first superjunction region.

7. The method for preparing a superjunction structure as described in claim 6, characterized in that, After the step of forming the first superjunction region within the first epitaxial layer, the method further includes: Remove the second conductive material layer formed outside the trench to planarize the surface of the first epitaxial layer.

8. The method for preparing a superjunction structure as described in claim 1, characterized in that, The step of epitaxially forming at least one second epitaxial layer of a first conductivity type on the first epitaxial layer includes: Multiple layers of the second epitaxial layer of the first conductivity type are epitaxially formed on the first epitaxial layer, and the doping concentration range of the multiple layers of the second epitaxial layer of the first conductivity type is the same as that of the first epitaxial layer.

9. The method for preparing a superjunction structure as described in claim 8, characterized in that, The second pillar formed within the second epitaxial layer of multiple layers has the same doping concentration range of impurity ions of the second conductivity type as the first pillar formed within the first epitaxial layer.

10. The method for preparing a superjunction structure as described in claim 8 or 9, characterized in that, The doping concentration of impurity ions of the second conductivity type formed in the first pillar within the first epitaxial layer is in the same range as the doping concentration of impurity ions of the first conductivity type within the first epitaxial layer.

11. The method for preparing a superjunction structure as described in claim 1, characterized in that, Before the step of forming the second epitaxial layer on the first epitaxial layer, the method further includes: Hydrogen chloride is used as an additional reactant to control and increase the chloro-silicon ratio of the reactant gas during the epitaxial deposition process of the second epitaxial layer, so as to pre-treat the inner walls of the multiple first grooves and form a pre-treated layer at the bottom of the first grooves.

12. A superjunction structure, characterized in that, include: Substrate; A first epitaxial layer of a first conductivity type is provided in the first epitaxial layer, which has a plurality of first grooves with different opening sizes and a plurality of first pillars of a second conductivity type. Each first pillar extends along a first direction perpendicular to the surface of the substrate and is spaced apart from each other and arranged in an array in a second direction parallel to the surface of the substrate. At least one second epitaxial layer of a first conductivity type is provided, the second epitaxial layer being located on the first epitaxial layer; each second epitaxial layer has at least one second groove on the side facing away from the substrate corresponding to the position of the first groove, and the position of each second groove corresponds to one of the first grooves; furthermore, each second epitaxial layer also has a plurality of second pillars of a second conductivity type, and the plurality of second pillars of each second epitaxial layer correspond one-to-one with the plurality of first pillars of the first epitaxial layer, and each second pillar and the corresponding first pillar are aligned with each other in the first direction.

13. The superjunction structure as described in claim 12, characterized in that, The first epitaxial layer has multiple layers of the second epitaxial layer, and the doping concentration range of the multiple layers of the second epitaxial layer is the same as that of the first epitaxial layer for the first conductivity type of impurity ions.

14. The superjunction structure as described in claim 13, characterized in that, The second pillar in the second epitaxial layer of the multilayer has the same doping concentration range of the second conductivity type of the impurity ions as the first pillar in the first epitaxial layer.

15. The superjunction structure as described in claim 14, characterized in that, The doping concentration of impurity ions of the second conductivity type in the first pillar within the first epitaxial layer is within the same range as the doping concentration of impurity ions of the first conductivity type in the first epitaxial layer.

16. The superjunction structure as described in claim 12, characterized in that, The first epitaxial layer and the second epitaxial layer are composed of either 4H-SiC or 6H-SiC.

17. A semiconductor device, characterized in that, The semiconductor device includes the superjunction structure as described in any one of claims 12 to 16.

18. An electronic device, characterized in that, The electronic device includes: Circuit boards; and, Semiconductor devices; The semiconductor device includes the semiconductor device as described in claim 17.

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