Semiconductor devices

Abstract

This invention discloses a semiconductor device comprising a substrate, a first well region, a second well region, a third well region, a source contact region, a drain contact region, a gate, and a buried layer; the first well region has a first conductivity type and is disposed within the substrate; the second well region has a first conductivity type and is disposed within the substrate and surrounds the first well region; the third well region has a second conductivity type and is disposed within the substrate, located between the first and second well regions, and surrounds the first well region; the source contact region is disposed within the second well region, the drain contact region is disposed within the first well region, and the gate is disposed directly above the third well region; the buried layer has a second conductivity type and is disposed within the substrate, extending laterally from directly below the third well region to directly below the second well region.

Description

Technical Field

[0001] This invention relates to semiconductor devices suitable for switching circuits, and more particularly to semiconductor devices incorporating double-diffused metal-oxide-semiconductor (DMOS) transistors around the level shifter region. Background Technology

[0002] Switching circuits (or bridge circuits) typically include high-side (or upper bridge) components, low-side (or lower bridge) components, a boost converter, a level shift circuit, a high-side drive circuit, a low-side drive circuit, and control logic. The high-side and low-side components are connected in series and alternately turned on and off. In the boost converter of a switching circuit, a bootstrap diode is required between the high-side and low-side voltages. When the high-side circuit is on, the bootstrap diode operates under reverse bias to prevent damage to the low-side circuit from high-voltage signals; when the high-side circuit is off, the bootstrap diode operates under forward bias to charge the capacitor in the boost converter using the low-side voltage, thereby maintaining the high-side voltage at a certain level. However, current bootstrap diode architectures in switching circuits cannot meet the various requirements of integrated circuits. Summary of the Invention

[0003] In view of this, the present invention proposes a semiconductor device suitable for switching circuits, which integrates a double-diffused metal-oxide-semiconductor (DMOS) transistor around the level shifter region to replace the bootstrap diode architecture in the boost device, and provides a buried layer below the channel region and source well region of the DMOS transistor to reduce the parasitic NPN bipolar transistor effect, thereby avoiding or reducing substrate leakage current, without affecting the various electrical performance characteristics of the semiconductor device.

[0004] According to an embodiment of the present invention, a semiconductor device is provided, comprising: a substrate; a first well region having a first conductivity type and disposed within the substrate; a second well region having the first conductivity type and disposed within the substrate and surrounding the first well region; a third well region having a second conductivity type and disposed within the substrate, located between the first well region and the second well region, and surrounding the first well region; a source contact region disposed within the second well region; a drain contact region disposed within the first well region; a gate electrode disposed directly above the third well region; and a buried layer having the second conductivity type and disposed within the substrate, extending laterally from directly below the third well region to directly below the second well region.

[0005] The beneficial effects of the technical solution of the present invention are mainly reflected in the following: the DMOS transistor incorporated in the periphery of the level shifting element region in the semiconductor device of the present invention includes a buried layer, and the buried layer of the second conductivity type extends at least laterally from directly below the third well region of the second conductivity type in the channel region to directly below the second well region of the first conductivity type in the source region. By means of the buried layer, the parasitic NPN bipolar transistor effect generated by the first well region, the third well region and the second well region of the first conductivity type can be reduced, thereby reducing the β current gain value, and thus avoiding or reducing the substrate leakage current of the semiconductor device; and, the various electrical performances of the semiconductor device are not affected, which can improve the utilization of the semiconductor device in integrated circuits. Attached Figure Description

[0006] To facilitate understanding of the following text, reference should be made to the accompanying drawings and their detailed description while reading this invention. Specific embodiments of the invention are explained in detail through reference to the corresponding drawings, which illustrate the working principles of these embodiments. Furthermore, for clarity, features in the drawings may not be drawn to scale, and therefore the dimensions of some features in certain drawings may be intentionally enlarged or reduced.

[0007] Figure 1 This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention, showing a planar arrangement of a buried layer and some components.

[0008] Figure 2 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention, which is along... Figure 1 The tangent line AA of the section is drawn.

[0009] Figure 3 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention, which is along... Figure 1 Draw the section tangent line B-B'.

[0010] Figure 4 This is a top view schematic diagram of a semiconductor device according to another embodiment of the present invention, showing a planar arrangement of a buried layer with a racetrack-shaped pattern and some components.

[0011] Figure 5 This is a schematic cross-sectional view of a semiconductor device illustrated according to another embodiment of the present invention, which is along... Figure 4 The tangent line of the section is drawn using CC.

[0012] Figure 6 This is a schematic cross-sectional view of a semiconductor device according to yet another embodiment of the present invention.

[0013] Figure 7This is a top view schematic diagram of a semiconductor device according to yet another embodiment of the present invention, showing a planar arrangement of a buried layer with a finger-shaped pattern and some components.

[0014] Explanation of reference numerals in the attached figures:

[0015] 100… Semiconductor Devices

[0016] 101…base

[0017] 101-1…P-type substrate

[0018] 101-2…P-type epitaxial layer

[0019] 103…First High-Pressure Well Area

[0020] 104…Second High-Pressure Well Area

[0021] 105…Fifth Well Area

[0022] 106…Sixth Well Area

[0023] 107… transistors

[0024] 108… Level shifting element area

[0025] 109…High-side components

[0026] 110…P-type buried layer

[0027] 111…First Well Area

[0028] 112…Second Well Area

[0029] 112S, 114S... outer surface

[0030] 113…Third Well Area

[0031] 114…Fourth Well Area

[0032] 116…P-type well area

[0033] 117…P-type doped top layer

[0034] 120… Buried layer

[0035] 120S1…Inner side

[0036] 120S2…Outer side

[0037] 121…Pump Contact Area

[0038] 122…Source Contact Region

[0039] 123…P-type heavily doped region

[0040] 124…Base contact area

[0041] 130…Isolation Zone

[0042] 131…gate dielectric layer

[0043] 133…gate

[0044] 135…field board

[0045] 139…through hole

[0046] 140…metal layer

[0047] 140B…substrate electrode

[0048] 140S…Source Electrode

[0049] 140G…gate electrode

[0050] 140D…Drain electrode

[0051] 151…Pump Contact Area

[0052] 152…Source Contact Region

[0053] 153, 163… gate

[0054] 154…Base contact area

[0055] 155…field board

[0056] 162…N-type heavily doped region

[0057] 164…P-type heavily doped region

[0058] AA, B-B', CC... Tangents in the cross section

[0059] Lch…channel area length Detailed Implementation

[0060] This invention provides several different embodiments for implementing various features of the invention. For the sake of simplicity, examples of specific components and arrangements are also described. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, the following statement regarding "a first feature forming on or above a second feature" may mean "the first feature and the second feature are in direct contact," or it may mean "there are other features between the first feature and the second feature," such that the first feature and the second feature are not in direct contact. Furthermore, various embodiments of this invention may use repeated reference numerals and / or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and not to indicate any correlation between different embodiments and / or configurations.

[0061] Furthermore, for the purposes of this invention, spatially related terms such as "below," "low," "down," "above," "above," "up," "top," "bottom," and similar terms are used to describe the relative relationship between one element or feature and another (or more) elements or features in the accompanying drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of the semiconductor device during use and operation. The spatially related descriptions used to describe the orientation of the semiconductor device should be interpreted in a similar manner, depending on the orientation of the semiconductor device (rotation of 90 degrees or other orientations).

[0062] Although the present invention uses terms such as first, second, third, etc., to describe various elements, components, regions, layers, and / or sections, it should be understood that such elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or section discussed below may also be referred to as the second element, component, region, layer, or section, etc.

[0063] The terms "about" or "substantially" as used in this invention generally mean within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, meaning that the meaning of "about" or "substantially" may be implied even without specific specification.

[0064] The terms "coupled," "coupled," and "electrically connected" as used in this invention include any direct or indirect means of electrical connection. For example, if the text describes a first component coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other means of connection.

[0065] Although the invention is described below with reference to specific embodiments, the inventive principles of the invention can also be applied to other embodiments. Furthermore, to avoid obscuring the spirit of the invention, certain details have been omitted; these omitted details are within the scope of knowledge of those skilled in the art.

[0066] This invention relates to a semiconductor device incorporating a double-diffused metal-oxide-semiconductor (DMOS) transistor around a level shifter region. Suitable for switching circuits, the DMOS transistor can replace the bootstrap diode architecture in a boost converter. A buried layer is disposed beneath the channel region and source well region of the DMOS transistor. This buried layer reduces parasitic NPN bipolar transistor effects, thereby avoiding or reducing substrate leakage current without affecting the various electrical performance characteristics of the semiconductor device, thus improving its usability in integrated circuits. Furthermore, the fabrication of the DMOS transistor with the buried layer can be integrated with the level shifter region fabrication process, eliminating the need for additional photomasks and process steps, thereby saving on semiconductor device manufacturing costs.

[0067] Figure 1 This is a top view schematic diagram of a semiconductor device 100 according to an embodiment of the present invention, showing a planar arrangement of a buried layer 120 and some components. The buried layer 120 has a rectangular pattern. For the sake of simplicity and clarity, Figure 1 The image shows the substrate 101, the level shifting element region 108, and the first well region 111, the third well region 113, the buried layer 120, the drain contact region 121, the source contact region 122, and the base contact region 124 of the DMOS transistor, which are incorporated around the level shifting element region 108. Other components of the semiconductor device 100 (not shown) will be depicted later. Figure 2 and Figure 3 The illustration is shown in the middle.

[0068] like Figure 1 A first well region 111 is disposed in the substrate 101, and a drain contact region 121 is disposed on the first well region 111. A level shifting element region 108 is disposed in the substrate 101. Viewed from a top angle, a buried layer 120 surrounds the level shifting element region 108 and the first well region 111. Furthermore, a third well region 113 is disposed on the buried layer 120, and a source contact region 122 is located above the buried layer 120. The third well region 113 serves as the channel region of the DMOS transistor, located between the drain contact region 121 and the source contact region 122. In this embodiment, a base contact region 124 is also located above the buried layer 120, surrounding the source contact region 122, and the vertical projection area of ​​the buried layer 120 extends beyond the base contact region 124. In one embodiment, the outer surface 120S2 of the buried layer 120 may be vertically aligned with the outer surface 114S of the fourth well region (not shown) where the base contact region 124 is located. Additionally, the level shifting element region 108 may include a transistor 107 located on one side, and the buried layer 120 may continuously or discontinuously surround the level shifting element region 108, but not surrounding the transistor 107. In one embodiment, as... Figure 1As shown, the buried layer 120 may be a C-shaped annular region continuously surrounding the level shifting element region 108. In another embodiment, the buried layer 120 may be composed of multiple blocks that are separate from each other, thereby discontinuously surrounding the level shifting element region 108. To clearly illustrate some features of the semiconductor device 100, Figure 1 The dimensions of some components outside the mid-position quasi-shifting element area 108 are shown in magnified form; in reality, the dimensions of each component can be adjusted according to layout requirements.

[0069] Figure 2 This is a schematic cross-sectional view of a semiconductor device 100 according to an embodiment of the present invention, which is along... Figure 1 The cross-sectional tangent AA shows the DMOS transistor merged around the level shifting element region 108. (Reference) Figure 2 The semiconductor device 100 includes a substrate 101. In one embodiment, the substrate 101 is formed, for example, by stacking a P-type epitaxial layer 101-2 on a P-type substrate 101-1. Furthermore, the semiconductor device 100 includes a first well region 111 disposed within the substrate 101. The first well region 111 has a first conductivity type, for example, formed by stacking a high-voltage N-type well region (HVNW) on a high-voltage N-type deep well region (DHVNW). A drain contact region 121 is disposed within the first well region 111. The drain contact region 121 has a first conductivity type, for example, an N-type heavily doped region (N... + A second well region 112 is disposed within the substrate 101 and surrounds the first well region 111. The second well region 112 has a first conductivity type, such as an N-type well region (NW), and the bottom surface of the second well region 112 is higher than the bottom surface of the first well region 111. A source contact region 122 is disposed within the second well region 112 and has a first conductivity type, such as an N-type heavily doped region (NW). + ).

[0070] The third well region 113 is disposed within the substrate 101, located between the first well region 111 and the second well region 112, and surrounds the first well region 111. The third well region 113 is laterally separated from both the first well region 111 and the second well region 112. The third well region 113 has a second conductivity type, such as a P-type well region (PW) or a P-type heavily doped region (P... + A third well region 113 is disposed on the third well region 113. A fourth well region 114 is disposed within the substrate 101, surrounding and adjacent to the second well region 112. The bottom surface of the fourth well region 114 and the bottom surface of the second well region 112 may be at the same horizontal level. The fourth well region 114 has a second conductivity type, such as a P-type well region (PW). A bulk contact region 124 is disposed within the fourth well region 114, and the bulk contact region 124 has a second conductivity type, such as a P-type heavily doped region (PW). + ).

[0071] Multiple isolation regions 130, such as field oxide (FOX) or shallow trench isolation (STI) structures, are disposed on the substrate 101 and located between the base contact region 124, the source contact region 122, the P-type heavily doped region 123, and the drain contact region 121. A gate 133 is disposed directly above the third well region 113, and the gate 133 is, for example, composed of polysilicon. The third well region 113 serves as the channel region of the DMOS transistor, and the channel region length Lch is the length of the third well region 113 in the direction (X-axis direction) from the first well region 111 to the second well region 122. A gate dielectric layer 131 is disposed below the gate 133 and is located between the gate 133 and the P-type heavily doped region (P... + Between 123. Additionally, a P-type doped top layer (PTOP) 117 can be disposed in the first well region 111, directly below the isolation region 130 between the gate 133 and the drain contact region 121. The P-type doped top layer 117 can reduce the surface electric field. A field plate 135 is disposed on the isolation region 130 directly above the P-type doped top layer 117 and adjacent to the drain contact region 121. The field plate 135 can disperse the electric field. The field plate 135 is composed, for example, of polysilicon and can be formed simultaneously with the gate 133 via deposition and patterning processes. Furthermore, a portion of the gate 133 can also extend laterally onto the isolation region 130 to serve as another field plate. A metal layer 140 is disposed on the substrate 101. The metal layer 140 may include a base electrode 140B, a source electrode 140S, a gate electrode 140G, and a drain electrode 140D, which are electrically connected to the base contact region 124, the source contact region 122, the gate electrode 133, the field plate 135, and the drain contact region 121, respectively, vias 139. The vias 139, the gate electrode 133, and the field plate 135 may be located within an interlayer dielectric layer (not shown), and the metal layer 140 may be formed on the interlayer dielectric layer.

[0072] According to some embodiments of the present invention, the semiconductor device 100 further includes a buried layer 120 disposed within the substrate 101, extending at least laterally from directly beneath the third well region 113 along the XY plane direction to directly beneath the second well region 112, and the inner side surface 120S1 of the buried layer 120 contacts the side surface of the first well region 111. The buried layer 120 has a second conductivity type, such as a P-type buried layer (PBL), and the doping concentration of the buried layer 120 is higher than the doping concentration of the substrate 101 and lower than the doping concentration of the third well region 113. In some embodiments, the doping concentration of the buried layer 120 is, for example, about 1E17 cm⁻¹. -3 Approximately 1E18 cm -3In this embodiment, the buried layer 120 further extends laterally from directly below the second well area 112 to directly below the fourth well area 114. Viewed from a top angle, the outer surface 120S2 of the buried layer 120 may be vertically aligned with the outer surface 114S of the fourth well area 114, and the vertical projected area of ​​the buried layer 120 may be greater than the sum of the vertical projected areas of the second well area 112, the third well area 113, and the fourth well area 114. In one embodiment, the top surface of the buried layer 120 may contact the bottom surface of the second well area 112, the bottom surface of the third well area 113, and the bottom surface of the fourth well area 114. In another embodiment, the top surface of the buried layer 120 may contact the bottom surface of the third well area 113 and is slightly lower than the bottom surfaces of the second well area 112 and the fourth well area 114. Furthermore, the bottom surface of the buried layer 120 is higher than the bottom surface of the first well area 111.

[0073] In the semiconductor device 100, the first well region 111 (NW), the third well region 113 (PW), and the second well region 112 (NW) generate parasitic NPN bipolar transistors. When the concentration of the P-type dopant at the bottom of the parasitic NPN bipolar transistor is higher, and / or the width of the bottom P-type doped region in the XY plane is larger, the beta gain of the parasitic NPN bipolar transistor can be reduced. A lower beta gain results in a smaller current amplification factor through the substrate 101, thereby avoiding or reducing substrate leakage current. According to some embodiments of the present invention, since the doping concentration of the buried layer 120 is higher than that of the substrate 101, that is, the doping concentration of the buried layer 120 is higher than that of the P-type epitaxial layer 101-2 and also higher than that of the P-type substrate 101-1, and the buried layer 120 extends at least laterally from directly below the third well region 113 to directly below the second well region 112. Compared to the comparative example where the third well region 113, the second well region 112, and the fourth well region 114 do not have a buried layer 120 directly below them, resulting in a low-doped P-type epitaxial layer 101-2 at the bottom of the parasitic NPN bipolar transistor, the embodiments of the present invention can effectively reduce the parasitic NPN bipolar transistor effect generated by the first well region 111 (NW), the third well region 113 (PW), and the second well region 112 (NW), thereby reducing the β current gain value. Even under operating conditions with increased current, the substrate leakage current can still be effectively avoided or reduced. Furthermore, the buried layer 120 does not affect the various electrical performance characteristics of the semiconductor device 100, such as the electrical performance in terms of threshold voltage (Vt), drive current (Ion), saturation current (Isat), off-state breakdown voltage (BVoff), and N-type well junction breakdown voltage (NWjunction BV).

[0074] Figure 3This is a schematic cross-sectional view of a semiconductor device 100 according to an embodiment of the present invention, which is along... Figure 1 The cross-sectional tangent B-B' illustrates the level shifting element region 108, which includes a transistor 107 and a high-side element 109. In one embodiment, the transistor 107 includes a first high-voltage well region 103, a fifth well region 105, and a P-type buried layer (PBL) 110 disposed within the substrate 101. The first high-voltage well region 103 may be formed, for example, by stacking a high-voltage N-type well region (HVNW) on a high-voltage N-type deep well region (DHVNW). The fifth well region 105 may be, for example, a P-type well region (PW). The P-type buried layer 110 is located directly below the fifth well region 105, and both the fifth well region 105 and the P-type buried layer 110 are laterally separated from the first high-voltage well region 103. The drain contact region 151 is located within the first high-pressure well region 103, and the source contact region 152 and the base contact region 154 are located within the fifth well region 105. The drain contact region 151 and the source contact region 152 are, for example, both N-type heavily doped regions (N... + The base contact region 154 is, for example, a heavily p-type doped region (P... + A gate 153 is disposed on a substrate 101, and a gate dielectric layer 131 is disposed between the gate 153 and the substrate 101. An isolation region 130 is disposed between the gate 153 and the drain contact region 151, and a P-type doped top layer 117 is disposed directly below this isolation region 130 to reduce the surface electric field.

[0075] Still referencing Figure 3 The high-side element 109 includes a second high-voltage well region 104, a sixth well region 106, and a P-type buried layer 110 disposed within the substrate 101. The second high-voltage well region 104 may be formed, for example, by stacking high-voltage N-type well regions (HVNW) on high-voltage N-type deep well regions (DHVNW). The sixth well region 106 is, for example, a P-type well region (PW). The P-type buried layer 110 is located directly below the sixth well region 106, and both the sixth well region 106 and the P-type buried layer 110 are laterally separated from the second high-voltage well region 104. Furthermore, a P-type well region 116 is disposed between the first high-voltage well region 103 of the transistor 107 and the second high-voltage well region 104 of the high-side element 109 as an isolation ring to isolate the transistor 107 and the high-side element 109. A field plate 155 is disposed on an isolation region 130 above the P-type well region 116. The N-type heavily doped region (N... + )162 is located within the second high-pressure well region 104, in the P-type heavily doped region (P + Gate 164 is disposed within the sixth well region 106, gate 163 is disposed on substrate 101, and gate dielectric layer 131 is disposed between gate 163 and substrate 101. Isolation region 130 is disposed in the N-type heavily doped region (N... +Between the gate 162 and the gate 163, another P-type doped top layer 117 is disposed directly below this isolation region 130 to reduce the surface electric field. A metal layer 140 is disposed on the substrate 101. The metal layer 140 includes a plurality of laterally separated electrode portions, which are electrically connected via a plurality of vias 139 to the base contact region 154, source contact region 152, gate 153, drain contact region 151 and field plate 155 of the transistor 107, and to the heavily doped N-type region 162, gate 163 and heavily doped P-type region 164 of the high-side element 109, respectively.

[0076] The fabrication of the DMOS transistor surrounding the level shifting element region 108 can be integrated with the fabrication process of the level shifting element region 108. The first well region 111 of the DMOS transistor and the first high-voltage well region 103 and the second high-voltage well region 104 of the level shifting element region 108 can be formed simultaneously via the same ion implantation process. The fourth well region 114 of the DMOS transistor and the fifth well region 105 and the sixth well region 106 of the level shifting element region 108 can be formed via the same ion implantation process. The buried layer 120 of the DMOS transistor and the P-type buried layer 110 of the level shifting element region 108 can also be formed via the same ion implantation process. The buried layer 120 and the P-type buried layer 110 have the same conductivity type and doping concentration, and the bottom surfaces of the buried layer 120 and the P-type buried layer 110 can be approximately at the same horizontal level. Furthermore, the ion implantation process for forming the buried layer 120 and the P-type buried layer 110 is performed only after the second well region 112, the third well region 113, and the fourth well region 114 are formed, thereby avoiding any impact on the various electrical performance characteristics of the semiconductor device 100. Other similar components of the DMOS transistor and the level shifting element region 108, such as heavily doped regions, P-type doped top layers, isolation regions, gates, and field plates with the same conductivity type, can also be formed together via the same process steps. Therefore, according to some embodiments of the present invention, the fabrication of a DMOS transistor including the buried layer 120 and incorporated around the level shifting element region 108 does not require additional photomasks and process steps, thereby saving on the manufacturing cost of the semiconductor device.

[0077] Figure 4 This is a top view schematic diagram of a semiconductor device 100 according to another embodiment of the present invention, wherein the buried layer 120 of the DMOS transistor incorporated around the level shifting element region 108 has a racetrack-shaped pattern. For the sake of simplicity and clarity, Figure 4 The image shows the substrate 101, the level shifting element region 108, and the third well region 113, buried layer 120, drain contact region 121, source contact region 122, and base contact region 124 of the semiconductor device 100. Other components of the semiconductor device 100 will be shown later. Figure 5 The illustration is shown in the middle. (For example...) Figure 4As shown, in one embodiment, the DMOS transistor surrounding the level shifting element region 108 may have a racetrack-shaped pattern, wherein the drain contact region 121, source contact region 122, base contact region 124, third well region 113, and buried layer 120 surround the level shifting element region 108 and have a racetrack-shaped planar configuration. To clearly illustrate some features of the semiconductor device 100, Figure 4 The dimensions of some components other than the mid-level shift element region 108 are shown enlarged; in reality, the size ratio of the mid-level shift element region 108 can be larger. In this embodiment, viewed from a top angle, the outer surface 120S2 of the buried layer 120 is within the base contact region 124, and the third well region 113 corresponds to the racetrack-shaped pattern of the buried layer 120 and is located directly above the buried layer 120.

[0078] Figure 5 This is a cross-sectional schematic diagram of a semiconductor device 100 according to another embodiment of the present invention, which is along... Figure 4 The cross-sectional tangent CC is used to draw the DMOS transistors merged around the level shift element region 108. In this embodiment, the buried layer 120 extends laterally from directly below the third well region 113 to directly below the second well region 112. The outer surface 120S2 of the buried layer 120 can be vertically aligned with the outer surface 112S of the second well region 112, and the buried layer 120 does not extend directly below the fourth well region 114. The vertical projected area of ​​the buried layer 120 can be greater than the sum of the vertical projected areas of the second well region 112 and the third well region 113. Figure 5 Details of other components of the semiconductor device 100 can be found in the foregoing. Figure 2 The relevant description of the semiconductor device 100 will not be repeated here.

[0079] Furthermore, when the adjacent components of the semiconductor device 100 do not primarily use N-type well regions, for example, when the adjacent components are not PMOS transistors, such as... Figure 5 As shown, the P-type buried layer 120 does not need to extend directly below the fourth well region 114. When adjacent components of the semiconductor device 100 primarily use N-type well regions, for example, when adjacent components are PMOS transistors, such as... Figure 2 As shown, the P-type buried layer 120 needs to extend directly below the fourth well region 114 to reduce the parasitic NPN bipolar transistor effect between the second well region 112 (NW), the fourth well region 114 (PW) of the semiconductor device 100 and the N-type well region of the adjacent element.

[0080] Figure 6This is a cross-sectional schematic diagram of a semiconductor device 100 according to another embodiment of the present invention, illustrating a DMOS transistor incorporated around a level shifting element region. In this embodiment, the buried layer 120 extends laterally from directly below the third well region 113 to directly below the second well region 112, and also laterally extends to a portion directly below the fourth well region 114, for example, the buried layer 120 may extend directly below the base contact region 124. Viewed from a top angle, the outer surface 120S2 of the buried layer 120 is located between the outer surface 112S of the second well region 112 and the outer surface 114S of the fourth well region 114. Figure 6 The buried layer 120 in the embodiment can also reduce the parasitic NPN bipolar transistor effect generated by the first well region 111 (NW), the third well region 113 (PW), and the second well region 112 (NW), thereby reducing the β current gain value to avoid or reduce the substrate leakage current. Figure 6 Details of other components of the semiconductor device 100 can be found in the foregoing. Figure 2 The relevant description of the semiconductor device 100 will not be repeated here.

[0081] Figure 7 This is a top view schematic diagram of a semiconductor device 100 according to another embodiment of the present invention, wherein the buried layer 120 of the DMOS transistor incorporated around the level shifting element region 108 has a finger-shaped pattern. For the sake of simplicity and clarity, Figure 7 The diagram shows the substrate 101, the level shifting element region 108, and the third well region 113, buried layer 120, drain contact region 121, source contact region 122, and base contact region 124 of the semiconductor device 100. Other components of the semiconductor device 100 (not shown) can be found in the foregoing. Figure 2 Related explanations. For example... Figure 7 As shown, in one embodiment, the DMOS transistor surrounding the level shifting element region 108 may have a finger-shaped pattern, wherein the drain contact region 121, source contact region 122, base contact region 124, third well region 113, and buried layer 120 all surround the level shifting element region 108 and all have a finger-shaped planar configuration. Viewed from a top angle, the third well region 113 corresponds to the finger-shaped pattern of the buried layer 120 and is disposed directly above the buried layer 120. To clearly show some features of the semiconductor device 100, Figure 7 The dimensions of some components outside the level shifting element region 108 are shown enlarged. The relative size ratio of the level shifting element region 108 and its surrounding DMOS transistors can be adjusted according to actual needs. Figure 7 In the embodiments, reference may also be made to Figure 6 The outer surface 120S2 of the buried layer 120 can be roughly vertically aligned with the base contact area 124.

[0082] According to an embodiment of the present invention, the DMOS transistor of the semiconductor device, which is incorporated around the level shifting element region, includes a buried layer. The buried layer (PBL) of the second conductivity type extends laterally from directly below the third well region (PW) of the second conductivity type in the channel region to directly below the second well region (NW) of the first conductivity type in the source region. The buried layer (PBL) reduces the parasitic NPN bipolar transistor effect generated by the first well region 111 (NW), the third well region 113 (PW), and the second well region 112 (NW) of the first conductivity type, thereby reducing the β current gain value and thus avoiding or reducing the substrate leakage current of the semiconductor device. Simultaneously, the various electrical performance characteristics of the semiconductor device are not affected, improving the utilization of the semiconductor device in integrated circuits.

[0083] Furthermore, according to some embodiments of the present invention, the fabrication of DMOS transistors containing buried layers can be integrated with the fabrication process of level shifting element regions, thus eliminating the need for additional photomasks and process steps, thereby saving on the manufacturing cost of semiconductor devices.

[0084] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, several equivalent substitutions or obvious modifications can be made without departing from the concept of the present invention, and all such modifications, achieving the same performance or purpose, should be considered within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that, include: One base; A first well zone, having a first conductivity type, is disposed within the substrate; A second well region, having the first conductivity type, is disposed within the substrate and surrounds the first well region; A third well region, having a second conductivity type, is disposed within the substrate, located between the first well region and the second well region, and surrounding the first well region; A source electrode contact region is located within the second well region; A first-stage contact zone is provided within the first well area; A gate is positioned directly above the third well area; as well as A buried layer having the second conductivity type is disposed within the substrate and extends laterally from directly below the third well zone to directly below the second well zone.

2. The semiconductor device as claimed in claim 1, characterized in that, The vertical projected area of ​​the buried layer is greater than the sum of the vertical projected areas of the second well area and the third well area.

3. The semiconductor device as claimed in claim 1, characterized in that, The top surface of the buried layer contacts the bottom surface of the second well area and the bottom surface of the third well area.

4. The semiconductor device as claimed in claim 1, characterized in that, One outer side of the buried layer is vertically aligned with one outer side of the second well area.

5. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A fourth well region, having the second conductivity type, is disposed within the substrate, surrounding and adjacent to the second well region; as well as A base contact region is provided within the fourth well region; The buried layer extends laterally from directly below the second well area to directly below the fourth well area.

6. The semiconductor device as claimed in claim 5, characterized in that, One outer side of the buried layer is vertically aligned with one outer side of the fourth well area.

7. The semiconductor device as claimed in claim 5, characterized in that, Viewed from above, one outer side of the buried layer is located between one outer side of the second well area and one outer side of the fourth well area.

8. The semiconductor device as claimed in claim 5, characterized in that, The vertical projected area of ​​the buried layer is greater than the sum of the vertical projected areas of the second well area, the third well area, and the fourth well area.

9. The semiconductor device as claimed in claim 5, characterized in that, The top surface of the buried layer contacts the bottom surface of the second well zone, the bottom surface of the third well zone, and the bottom surface of the fourth well zone.

10. The semiconductor device as claimed in claim 1, characterized in that, One inner side of the buried layer contacts one side of the first well area.

11. The semiconductor device as claimed in claim 1, characterized in that, The bottom surface of the buried layer is higher than the bottom surface of the first well area.

12. The semiconductor device as claimed in claim 1, characterized in that, The third well region is laterally separated from both the first and second well regions.

13. The semiconductor device as claimed in claim 1, characterized in that, The substrate has the second conductivity type, and the doping concentration of the buried layer is higher than that of the substrate.

14. The semiconductor device as claimed in claim 1, characterized in that, The doping concentration of the buried layer is lower than that of the third well zone.

15. The semiconductor device as claimed in claim 1, characterized in that, It also includes a quasi-displacement element region disposed in the substrate, viewed from a top angle, with the buried layer surrounding the quasi-displacement element region.

16. The semiconductor device as claimed in claim 15, characterized in that, Viewed from above, the buried layer includes a racetrack-shaped pattern or a finger-shaped pattern.

17. The semiconductor device as claimed in claim 16, characterized in that, Viewed from above, the third well area corresponds to the runway-shaped pattern or the finger-shaped pattern and is located directly above the buried layer.

18. The semiconductor device as claimed in claim 15, characterized in that, Viewed from above, the buried layer continuously surrounds the positioning displacement element region.

19. The semiconductor device as claimed in claim 15, characterized in that, Viewed from above, the buried layer discontinuously surrounds the level shifting element region.

20. The semiconductor device as claimed in claim 15, characterized in that, The level shifting element region includes another buried layer having the second conductivity type, disposed within the substrate, wherein the buried layer and the other buried layer have the same doping concentration, and the bottom surfaces of the buried layer and the other buried layer are at the same horizontal height.

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