Semiconductor devices and methods for manufacturing semiconductor devices

Abstract

This application relates to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a semiconductor substrate having an active region comprising a first impurity implantation region, a second impurity implantation region, and a channel region located between the first and second impurity implantation regions. Each of the first and second impurity implantation regions includes: a nitrogen region adjacent to an upper surface of the semiconductor substrate; and a source / drain region separated from the upper surface of the semiconductor substrate by the nitrogen region and including conductive impurities.

Description

Technical Field

[0001] Various embodiments of this disclosure generally relate to semiconductor devices and methods of manufacturing semiconductor devices, and more specifically, to semiconductor devices having transistors and methods of manufacturing semiconductor devices. Background Technology

[0002] Semiconductor devices are used in a wide variety of electronic systems, such as small electronic devices, automobiles, healthcare devices, and data centers, and these devices are highly integrated and have high capacity according to user needs. Semiconductor devices include transistors. During the manufacture of semiconductor devices, the electrical characteristics of transistors can degrade due to various reasons. Summary of the Invention

[0003] According to embodiments of this disclosure, a semiconductor device may include: a semiconductor substrate including an active region comprising a first impurity implantation region, a second impurity implantation region, and a channel region located between the first and second impurity implantation regions; a gate insulating layer and a gate electrode, the gate insulating layer and the gate electrode being stacked over the channel region; and a multiple insulating structure covering the surfaces of the first impurity implantation region, the second impurity implantation region, the gate insulating layer, and the gate electrode. Each of the first and second impurity implantation regions may include: a nitrogen region adjacent to an upper surface of the semiconductor substrate; and a source / drain region spaced apart from the upper surface of the semiconductor substrate by the nitrogen region, the source / drain region including conductive impurities.

[0004] According to embodiments of this disclosure, a method for manufacturing a semiconductor device may include the following steps: forming a stacked structure including a gate insulating layer and a gate electrode over an active region of a semiconductor substrate; forming a nitrogen region in each of a first region and a second region of the active region disposed on opposite sides of the gate electrode; forming a buffer layer to cover the nitrogen region of each of the first region and the second region, the sidewalls of the stacked structure, and the upper surface of the stacked structure; and forming a source / drain region by implanting conductive impurities into portions of each of the first region and the second region, the portions being separated from the upper surface of the semiconductor substrate by the nitrogen region. Attached Figure Description

[0005] Figure 1 This is a block diagram illustrating an electronic system including a semiconductor device according to an embodiment of the present disclosure;

[0006] Figure 2 This is a block diagram illustrating a semiconductor device according to an embodiment of the present disclosure;

[0007] Figure 3 This is a perspective view showing the memory cell array structure and peripheral circuit structure of a semiconductor device according to an embodiment of the present disclosure;

[0008] Figure 4A and Figure 4B This is a cross-sectional view showing a transistor of a semiconductor device according to an embodiment of the present disclosure;

[0009] Figure 5A and Figure 5B This is a cross-sectional view illustrating a semiconductor device including a transistor according to some embodiments of the present disclosure; and

[0010] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E and Figure 6F This is a cross-sectional view showing various configurations formed by using methods of manufacturing transistors according to some embodiments of the present disclosure. Detailed Implementation

[0011] The specific structural or functional descriptions disclosed herein are illustrative only, intended to describe embodiments of the concepts presented herein. Embodiments of the concepts presented herein can be implemented in various forms and should not be construed as limited to the specific embodiments set forth herein.

[0012] Terms such as “first” and “second” are used to distinguish various elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one example, a first element may be named a second element, and in another example, a second element may be named a first element. Terms such as “vertical,” “above,” “lower,” “upper,” and other terms that imply relative spatial relationships or orientations are used only for the purpose of description or reference to the accompanying drawings and are not intended to limit in any other way. It should be understood that when an element or layer is referred to as being “on,” “connected,” or “linked” to another element or layer, that element or layer may be directly on, directly connected to, or directly linked to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being “directly” on, “directly connected to,” or “directly linked” to another element or layer, there are no intermediate elements or layers. Crosshairs running through the drawings indicate corresponding or similar areas between the drawings and do not indicate material associated with these areas.

[0013] Some embodiments of this disclosure may relate to a semiconductor device and a method of manufacturing the semiconductor device, the semiconductor device being able to improve the electrical characteristics of the transistors included in the semiconductor device.

[0014] Figure 1 This is a block diagram illustrating an electronic system 1000 including a semiconductor device according to an embodiment of the present disclosure.

[0015] Reference Figure 1 The electronic system 1000 can be a computing system, medical device, communication device, wearable device, memory system, etc. The electronic system 1000 may include a host 1100 and a storage device 1200.

[0016] The host 1100 can store data in the storage device 1200 or read data stored in the storage device 1200 based on an interface. The interface may include one or more of the following: Double Data Rate (DDR) interface, Universal Serial Bus (USB) interface, Multimedia Card (MC) interface, Embedded MMC (eMMC) interface, Peripheral Component Interconnect (PCI) interface, High-Speed ​​PCI (PCI-E) interface, Advanced Technology Accessory (ATA) interface, Serial ATA interface, Parallel ATA interface, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE) interface, FireWire interface, Universal Flash Storage (UFS) interface, and Non-Volatile High Speed ​​Memory (NVMe) interface.

[0017] Storage device 1200 may include memory controller 1210 and semiconductor device 1220. In some embodiments, storage device 1200 may be a storage medium such as a solid-state drive (SSD), a universal serial bus (USB) memory, etc.

[0018] The memory controller 1210 can store data in the semiconductor device 1220 or read data stored in the semiconductor device 1220 under the control of the host 1100.

[0019] Semiconductor device 1220 may include a single memory chip or multiple memory chips. Semiconductor device 1220 may store data or output stored data under the control of memory controller 1210.

[0020] Semiconductor device 1220 may be a non-volatile memory device. Semiconductor device 1220 may include a memory cell array and peripheral circuitry for controlling the operation of the memory cell array. The memory cell array may include multiple memory cells. Each memory cell may be a non-volatile memory cell. In embodiments, each memory cell may be configured as a NAND flash memory cell, a ferroelectric memory cell, a variable resistance memory cell, etc.

[0021] Figure 2 This is a block diagram illustrating a semiconductor device 1220 according to an embodiment of the present disclosure.

[0022] Reference Figure 2 The semiconductor device 1220 may include peripheral circuitry 40 and a memory cell array 10. In some embodiments, the semiconductor device 1220 may include the memory cell array 10 and the peripheral circuitry 40 of the NAND flash memory device. Hereinafter, embodiments of the present disclosure will be described based on the peripheral circuitry 40 of the NAND flash memory device and the memory cell array 10, but the embodiments of the present disclosure are not limited thereto.

[0023] The peripheral circuitry 40 is configured to perform programming operations for storing data in the memory cell array 10, reading operations for outputting data stored in the memory cell array 10, and erasing operations for erasing data stored in the memory cell array 10. In an embodiment, the peripheral circuitry 40 may include an input / output circuitry 21, a control circuitry 23, a voltage generation circuitry 31, a row decoder 33, a column decoder 35, a page buffer 37, and a source driver 39.

[0024] The peripheral circuit 40 can be connected to the memory cell array 10 through multiple common source structures CS, multiple bit lines BL, multiple drain select lines DSL, multiple word lines WL, and multiple source select lines SSL.

[0025] Input / output circuit 21 can input from external devices (e.g., semiconductor device 1220) Figure 1 The memory controller 1210 shown receives the command CMD and address ADD, which are then transmitted to the control circuit 23. The input / output circuit 21 can exchange data DATA with external devices and the column decoder 35.

[0026] Control circuit 23 can output operation signal OP_S, row address RADD, common source control signal CS_S, page buffer control signal PB_S and column address CADD in response to command CMD and address ADD.

[0027] The voltage generation circuit 31 can generate various operating voltages Vop for programming, reading and erasing operations in response to the operation signal OP_S.

[0028] The line decoder 33 can transmit the operating voltage Vop to multiple drain select lines DSL, multiple word lines WL, and multiple source select lines SSL in response to the line address RADD.

[0029] The column decoder 35 can transfer data DATA input from the input / output circuit 21 to the page buffer 37, or transfer data DATA stored in the page buffer 37 to the input / output circuit 21, in response to the column address CADD. The column decoder 35 can exchange data DATA with the input / output circuit 21 via the column line CL. The column decoder 35 can exchange data DATA with the page buffer 37 via the data line DL.

[0030] Page buffer 37 can control bit lines BL in response to page buffer control signal PB_S. During programming operations, page buffer 37 can store data DATA received from column decoder 35 in response to page buffer control signal PB_S, and can apply voltages to multiple bit lines BL based on the stored data DATA. During read operations, page buffer 37 can sense the voltage or current of bit lines BL in response to page buffer control signal PB_S, and can store the sensing results.

[0031] The source driver 39 can control the voltage or bias applied to each of the plurality of common source structures CS in response to the common source control signal CS_S received from the control circuit 23, or it can ground each of the plurality of common source structures CS.

[0032] The memory cell array 10 includes multiple memory blocks BLK1 to BLKn, where n is a natural number greater than or equal to 2. The multiple memory blocks BLK1 to BLKn are connected to the page buffer 37 via multiple bit lines BL. Erasure operations can be controlled either on a common source structure CS or on a memory block basis. At least one source layer can be connected to the common source structure CS.

[0033] Figure 3 This is a perspective view showing the memory cell array structure 10S and peripheral circuit structure 40S of the semiconductor device 1220 according to an embodiment of the present disclosure.

[0034] Figure 3 The first direction DR1, the second direction DR2, and the third direction DR3 shown are the directions facing each other of the intersecting axes. In the embodiment, the first direction DR1, the second direction DR2, and the third direction DR3 can correspond to the directions facing the X-axis, Y-axis, and Z-axis, respectively.

[0035] Reference Figure 3The memory cell array structure 10S includes multiple memory blocks BLK1 to BLKn, where n is a natural number greater than or equal to 2. In an embodiment, each of the multiple memory blocks BLK1 to BLKn in the NAND flash memory device may include multiple memory cell strings MS. The multiple memory cell strings MS can be arranged in multiple rows and columns. Memory cell strings MS arranged in a row along a first direction DR1 form each row, and memory cell strings MS arranged in a row along a second direction DR2 form each column.

[0036] Each of the memory cell string MS can be connected to a first conductive layer L1, a second conductive layer L2, at least one first select line SEL1, multiple word lines WL, and at least one second select line SEL2. One of the first conductive layer L1 and the second conductive layer L2 forms a source layer, and the other forms a bit line. The first conductive layer L1 and the second conductive layer L2 can be spaced apart from each other along a third direction DR3 and can be electrically connected to both ends of the memory cell string MS. One of the first select line SEL1 and the second select line SEL2 serves as a source select line, and the other serves as a drain select line. At least one first select line SEL1, multiple word lines WL, and at least one second select line SEL2 can be disposed between the first conductive layer L1 and the second conductive layer L2, and they can be spaced apart from each other along a third direction DR3. At least one first select line SEL1 is disposed between the first conductive layer L1 and the multiple word lines WL. In an embodiment, two first select lines SEL1 can be disposed between the first conductive layer L1 and the multiple word lines WL. At least one second selection line SEL2 is disposed between the second conductive layer L2 and multiple word lines WL. In an embodiment, two second selection lines SEL2 may be disposed between the second conductive layer L2 and multiple word lines WL. The memory cell string MS includes a first selection transistor ST1 connected to the first selection line SEL1, multiple memory cells MC connected to the multiple word lines WL, and a second selection transistor ST2 connected to the second selection line SEL2. One of the first selection transistor ST1 and the second selection transistor ST2 serves as a source selection transistor, and the other serves as a drain selection transistor. The first selection transistor ST1, the multiple memory cells MC, and the second selection transistor ST2 can be connected in series via electrical connections to the channel pillars of the first conductive layer L1 and the second conductive layer L2.

[0037] The peripheral circuit structure 40S includes the formation of a reference. Figure 2The described peripheral circuit 40 includes a plurality of transistors. Each of the plurality of transistors may include a gate insulating layer of thickness designed to match the drive voltage used to drive each transistor. In one embodiment, the plurality of transistors may include a first transistor having a first voltage applied as a maximum gate voltage, a second transistor having a second voltage applied as a maximum gate voltage, and a third transistor having a third voltage applied as a maximum gate voltage. The first transistor includes a first gate insulating layer of a first thickness, the second transistor includes a second gate insulating layer of a second thickness, and the third transistor includes a third gate insulating layer of a third thickness. The first voltage is greater than the second voltage, and the second voltage is greater than the third voltage. In this case, the first thickness is greater than the second thickness, and the second thickness is greater than the third thickness, thereby ensuring the breakdown voltage characteristics of the first to third transistors.

[0038] The memory cell array structure 10S and the peripheral circuit structure 40S overlap each other along the third direction DR3. After forming the memory cell array structure 10S and the peripheral circuit structure 40S, a hydrogen annealing process for defect elimination can be performed. Each of the plurality of transistors in the peripheral circuit structure 40S may include a nitrogen region capable of reducing or blocking the movement path of hydrogen ions generated in the hydrogen annealing process, etc.

[0039] Figure 4A and Figure 4B This is a cross-sectional view showing the transistor TR of a semiconductor device according to an embodiment of the present disclosure.

[0040] Reference Figure 4A The transistor TR may include a channel region 101CH, a first impurity implantation region 101I1 and a second impurity implantation region 101I2 formed in the semiconductor substrate 101, and may include a gate insulating layer 111 and a gate electrode 113 stacked above the channel region 101CH of the semiconductor substrate 101.

[0041] The semiconductor substrate 101 includes a semiconductor material. In this embodiment, the semiconductor material may include one or more of group IV semiconductors, group III-V compound semiconductors, and group II-VI compound semiconductors. Group IV semiconductors may include single-crystal silicon (Si), polycrystalline silicon, germanium (Ge), or silicon-germanium (SiGe). Group III-V compound semiconductors may include GaAs, GaN, GaP, GaAsP, GaInAsP, AlAs, AlGa, InP, InSb, or InGaAs. Group II-VI compound semiconductors may include ZnS, ZnO, or CdS.

[0042] The semiconductor substrate 101 may further include a dielectric layer. In an embodiment, the semiconductor substrate 101 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. The semiconductor substrate 101 may also include organic materials. In an embodiment, the semiconductor substrate 101 may include graphene.

[0043] The semiconductor substrate 101 may be a bulk wafer or an epitaxial layer grown by a selective epitaxial growth (SEG) method. Alternatively, the semiconductor substrate 101 may be a layer formed by a metal-induced lateral crystallization (MILC) method and may partially include metal.

[0044] The semiconductor substrate 101 may be in a single-crystal, polycrystalline, or amorphous state. The semiconductor substrate 101 may include impurities of Group II, III, IV, V, or VI elements. In some embodiments, the semiconductor substrate 101 may include an n-well region doped with n-type impurities, a p-well region doped with p-type impurities, or both an n-well region and a p-well region.

[0045] The semiconductor substrate 101 includes an active region 101ACT separated by an isolation layer 103. The channel region 101CH, the first impurity implantation region 101I1, and the second impurity implantation region 101I2 of the transistor TR are formed in the active region 101ACT.

[0046] The channel region 101CH is formed between the first impurity implantation region 101I1 and the second impurity implantation region 101I2. The channel region 101CH may include conductive impurities such as n-type and p-type impurities designed with consideration of the threshold voltage of the transistor TR.

[0047] Each of the first impurity implantation region 101I1 and the second impurity implantation region 101I2 includes a nitrogen region 101N and a source / drain region 101SD. The nitrogen region 101N is disposed adjacent to the upper surface 101TS of the semiconductor substrate 101. The nitrogen region 101N may include nitrogen ions written in an exponential manner at a dose ranging from 1E13 ions / cm² to 1E14 ions / cm². The nitrogen region 101N may be formed to have a thickness of 120 Å to 140 Å from the upper surface 101TS of the semiconductor substrate 101 to the interior of the semiconductor substrate 101. Depending on the electrical characteristics of the transistor TR, the majority carriers of the source / drain region 101SD may include n-type impurities or p-type impurities. In this embodiment, the transistor TR is a P-channel metal-oxide-semiconductor (PMOS) transistor, and the source / drain region 101SD includes p-type impurities as majority carriers. In another embodiment, the transistor TR is an N-channel metal-oxide-semiconductor (NMOS) transistor, and the source / drain region 101SD includes N-type impurities as majority carriers. The source / drain region 101SD is spaced apart from the upper surface 101TS of the semiconductor substrate 101 by a nitrogen region 101N. According to embodiments of the present disclosure, the diffusion of hydrogen ions around the source / drain region 101SD can be prevented or reduced by the nitrogen region 101N. According to embodiments of the present disclosure, the diffusion of hydrogen ions around the source / drain region 101SD can be prevented or reduced by combining nitrogen ions inside the nitrogen region 101N with diffused hydrogen ions.

[0048] Each of the first impurity implantation region 101I1 and the second impurity implantation region 101I2 may further include a doped region 101LDD. The doped region 101LDD includes impurities of the same conductivity type as the source / drain region 101SD as majority carriers. The doped region 101LDD is disposed between the source / drain region 101SD and the channel region 101CH, and has a lower concentration of the conductivity type impurities comprising majority carriers in the doped region 101LDD compared to the source / drain region 101SD. The leakage current between the source / drain regions 101SD of the first impurity implantation region 101I1 and the source / drain regions 101SD of the second impurity implantation region 101I2 can be reduced by including the doped region 101LDD with a relatively low concentration of conductivity type impurities.

[0049] A gate insulating layer 111 is disposed between the gate electrode 113 and the channel region 101CH of the semiconductor substrate 101, and may comprise a single-layer or multi-layer structure of various insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. In an embodiment, the gate insulating layer 111 may be formed as a double-layer structure comprising a silicon oxide layer and a silicon nitride layer.

[0050] The gate electrode 113 may comprise a single-layer or multi-layer structure of various conductive materials, such as doped semiconductor materials, conductive metal nitrides, metals, and metal-semiconductor compounds. In an embodiment, the gate electrode 113 may comprise doped silicon 113A, a stack comprising titanium, tungsten nitride, and tungsten nitride silicon 113B, and tungsten 113C.

[0051] The gate electrode 113 may be disposed between the gate cover pattern 115 and the gate insulating layer 111. The gate cover pattern 115 may include a single-layer or multi-layer structure of various insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. In an embodiment, the gate cover pattern 115 may include a tetraethylsilicic acid (TEOS) oxide layer.

[0052] The surface of the transistor TR can be covered with multiple insulating structures 120. The multiple insulating structures 120 can cover the surfaces of the first impurity implantation region 101I1, the second impurity implantation region 101I2, the gate insulating layer 111, the gate electrode 113, and the gate cover pattern 115, and can extend to cover the isolation layer 103.

[0053] The multiple insulating structure 120 may include a buffer layer 125 and a diffusion barrier layer 127. Each of the buffer layer 125 and the diffusion barrier layer 127 may extend to cover the upper surface of the first impurity implantation region 101I1, the upper surface of the second impurity implantation region 101I2, the sidewall of the gate electrode 113, and the upper surface of the gate electrode 113. The diffusion barrier layer 127 may reduce further diffusion of dopants or diffusion of hydrogen ions into the transistor TR. The diffusion barrier layer 127 may include silicon nitride. The buffer layer 125 may be disposed between each of the first impurity implantation region 101I1 and the second impurity implantation region 101I2 and the diffusion barrier layer 127 to reduce the stress applied to the semiconductor substrate 101 during the formation of the diffusion barrier layer 127. The buffer layer 125 may include silicon oxide and may extend between each of the gate electrode 113 and the gate overlay pattern 115 and the diffusion barrier layer 127. During the formation of the oxide layer of the buffer layer 125, the density of trap sites caused by the oxidation of the semiconductor substrate 101 can be reduced because the nitrogen region 101N can reduce or prevent the oxidation of the semiconductor substrate 101.

[0054] The multiple insulating structure 120 may further include a spacer oxide layer 123 and a cover nitride layer 121. The spacer oxide layer 123 is disposed between the buffer layer 125 and the sidewall of the gate electrode 113. The cover nitride layer 121 is disposed between each of the first impurity implantation region 101I1 and the second impurity implantation region 101I2 located on one side and the buffer layer 125 located on the other side. The cover nitride layer 121 extends between the gate electrode 113 and the spacer oxide layer 123. The thickness of the cover nitride layer 121 between each of the first impurity implantation region 101I1 and the second impurity implantation region 101I2 and the buffer layer 125 is thinner than the thickness between the gate electrode 113 and the spacer oxide layer 123. The cover nitride layer 121 may extend between the buffer layer 125 and the gate cover pattern 115.

[0055] Figure 4B yes Figure 4A An enlarged view of the nitrogen region 101N of the semiconductor substrate 101 and the covering nitride layer 121 located above the nitrogen region 101N.

[0056] Reference Figure 4A and Figure 4B Silicon-deuterium bonding (Si-D) can be formed along the surface of the nitrogen region 101N. The number of trap sites at the upper surface 101TS of the semiconductor substrate 101 can be reduced by silicon-deuterium bonding (Si-D).

[0057] Reference Figure 4A and Figure 4B The described transistor TR can be applied to various semiconductor devices, and in implementations, it can be applied to transistors forming the peripheral circuitry of NAND flash memory devices.

[0058] Figure 5A and Figure 5B This is a cross-sectional view illustrating a semiconductor device including a transistor according to some embodiments of the present disclosure. In the embodiments, Figure 5A and Figure 5B It shows a reference. Figure 3 A cross-sectional view of the described semiconductor device.

[0059] Reference Figure 5A and Figure 5B The peripheral circuit structure of a semiconductor device may include a semiconductor substrate 101 in which an isolation layer 103 is formed, and a reference... Figure 4A The described transistor TR, reference Figure 4AThe description includes a multi-layer insulating structure 120, a peripheral circuit-side insulating structure 140 formed over a semiconductor substrate 101 to cover the multi-layer insulating structure 120, and interconnects 130 connected to a transistor TR. The peripheral circuit-side insulating structure 140 may include multiple insulating layers. Each of the interconnects 130 may include conductive patterns 131, 132, 133, 134, 135, and 136 disposed in the peripheral circuit-side insulating structure 140. The interconnects 130 may be connected to the gate electrode 113 and the source / drain region 101SD of the transistor TR. The lowest conductive pattern 131 of the interconnect 130 connected to the source / drain region 101SD may penetrate the nitrogen region 101N.

[0060] The memory cell array structure of a semiconductor device may include a doped semiconductor structure 150 or 180, a gate stack structure 160, a bit line BL, a channel pillar CHP, and a memory layer 161A or 161. The gate stack structure 160 is disposed between the doped semiconductor structure 150 or 180 and the bit line BL, and the channel pillar CHP passes through the gate stack structure 160 and is connected to the doped semiconductor structure 150 or 180.

[0061] The gate stack structure 160 may include a plurality of conductive layers SSL, WL, and DSL formed in a planar shape extending along a first direction DR1 and a second direction DR2, as well as a plurality of interlayer insulating layers IL. The plurality of conductive layers SSL, WL, and DSL and the plurality of interlayer insulating layers IL may be alternately arranged along a third direction DR3.

[0062] The plurality of conductive layers SSL, WL, and DSL include at least one source select line SSL, at least one drain select line DSL, and multiple word lines WL disposed between the source select line SSL and the drain select line DSL. The source select line SSL is connected to the gate electrode of the source select transistor, the drain select line DSL is connected to the gate electrode of the drain select transistor, and the multiple word lines WL are respectively connected to multiple gates of multiple memory cells. Each of the plurality of conductive layers SSL, WL, and DSL may include various conductive materials such as doped semiconductor layers and metal layers. The doped semiconductor layer may include a doped silicon layer. The metal layer may include tungsten, copper, molybdenum, etc. Each of the plurality of conductive layers SSL, WL, and DSL may also include a metal barrier layer. The metal barrier layer may include a metal nitride layer, and the metal nitride layer may include titanium nitride, tantalum nitride, molybdenum nitride, etc. In an embodiment, the metal barrier layer may include a double layer of titanium and titanium nitride. Each of the plurality of interlayer insulating layers IL may include an insulating material such as a silicon oxide layer or a silicon oxynitride layer.

[0063] The channel pillar CHP extends along the third direction DR3 to penetrate the gate stack structure 160. The channel pillar CHP includes a channel layer 163A. The channel layer 163A may include a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof, which can be used as a channel region of a memory cell string. The channel layer 163A may have a tubular shape. The channel pillar CHP including the tubular channel layer 163A may also include a core insulating layer 165 and a cover pattern 163B disposed in the tubular central region formed by the channel layer 163A. The cover pattern 163B may include a semiconductor layer doped with conductive impurities. The conductive impurities may include n-type impurities or may include both n-type and p-type impurities. In an embodiment, the cover pattern 163B may include n-type doped silicon containing n-type impurities as majority carriers.

[0064] Memory layers 161A or 161 may surround the sidewalls of the channel pillar CHP. Memory layers 161A or 161 may include a tunnel insulating layer, a data storage layer, and a barrier insulating layer. Although not shown in the figures, the tunnel insulating layer is disposed between the channel pillar CHP and the gate stack 160, the data storage layer is disposed between the tunnel layer and the gate stack 160, and the barrier insulating layer is disposed between the data storage layer and the gate stack 160. The tunnel insulating layer may include an oxide such as silicon dioxide (SiO2). The data storage layer may include a material layer capable of storing data altered by using Fowler-Nordheim tunneling. In embodiments, the data storage layer may include a charge trapping layer or may include an insulating layer comprising conductive nanodots. The charge trapping layer may include a silicon nitride layer. The barrier insulating layer may include an oxide such as silicon dioxide (SiO2), a high-dielectric insulator with a dielectric constant higher than silicon dioxide, etc. The high-dielectric insulating material may include an aluminum oxide layer, a hafnium oxide layer, etc.

[0065] The source-select transistor can be formed at the intersection of the source-select line SSL and the channel layer 163A, and the drain-select transistor can be formed at the intersection of the drain-select line DSL and the channel layer 163A. Multiple memory cells can be formed at the intersections of multiple word lines WL and the channel layer 163A. The source-select transistor, multiple memory cells, and the drain-select transistor can be connected in series through the channel pillar CHP to form... Figure 3 The memory cell string MS is shown.

[0066] The channel pillar CHP can be connected to the doped semiconductor structure 150 or 180 and the bit line BL.

[0067] The doped semiconductor structure 150 or 180 may include at least one doped semiconductor layer. The doped semiconductor layer of the doped semiconductor structure 150 or 180 may include either an n-type impurity or a p-type impurity. In an embodiment, the doped semiconductor structure 150 or 180 may include at least one of a first conductive doped semiconductor layer containing an n-type impurity as a majority carrier and a second conductive doped semiconductor layer containing a p-type impurity as a majority carrier. The first conductive doped semiconductor layer may serve as a source layer, and the second conductive doped semiconductor layer may serve as a well region. The source layer of the doped semiconductor structure 150 or 180 may be in direct contact with the sidewall or bottom surface of the channel pillar CHP.

[0068] Reference Figure 5A In one embodiment, a portion of the sidewall of the channel layer 163A may form a contact surface with the doped semiconductor structure 150. In another embodiment, the doped semiconductor structure 150 may include a first source layer 151, a second source layer 155, and a contact source layer 153 located between the first source layer 151 and the second source layer 155. Each of the first source layer 151, the second source layer 155, and the contact source layer 153 may include a doped semiconductor layer. The channel layer 163A may extend into each of the first source layer 151, the second source layer 155, and the contact source layer 153. A memory layer 161A may extend between the second source layer 155 and the channel layer 163A. A dummy memory layer 161B may be disposed between the first source layer 151 and the channel layer 163A. The dummy memory layer 161B may include the same material as the memory layer 161A. The contact source layer 153 can be disposed between the memory layer 161A and the dummy memory layer 161B, and it can contact the channel layer 163A.

[0069] Reference Figure 5B The end of the channel layer 163A can extend into the doped semiconductor structure 180 and can form a contact surface with the doped semiconductor structure 180.

[0070] Reference Figure 5A and Figure 5B The overlay pattern 163B of the channel pillar CHP can be electrically connected to the bit line BL via the bit line connection structure 173. The bit line connection structure 173 and the bit line BL can be disposed in an insulating structure 171. The insulating structure 171 may include multiple insulating layers covering the gate stack structure 160. The bit line connection structure 173 may include one or more conductive patterns. In an embodiment, the bit line connection structure 173 may include a first conductive pattern 173A and a second conductive pattern 173B that overlap each other along a third direction DR3.

[0071] One of the doped semiconductor structure 150 or 180 and the bit line BL can be disposed adjacent to the peripheral circuit-side insulating structure 140. (Refer to...) Figure 5A In one embodiment, the doped semiconductor structure 150 may be configured to be closer to the peripheral circuit-side insulating structure 140 than the bit line BL. (See also...) Figure 5B In an implementation, the bit line BL can be positioned closer to the peripheral circuit-side insulating structure 140 than the doped semiconductor structure 180.

[0072] Reference Figure 5A and Figure 5B The memory cell array structure, including doped semiconductor structures 150 or 180, can be formed on the peripheral circuit side insulating structure 140, or can be connected to the peripheral circuit structure through a bonding process.

[0073] Reference Figure 5A In one embodiment, a process for forming a memory cell array structure, such as a doped semiconductor structure 150, can be performed over the peripheral circuit-side insulating structure 140.

[0074] Reference Figure 5B In one embodiment, the peripheral circuit structure may further include a peripheral circuit-side intercalation insulating layer 141 located above the peripheral circuit-side insulating structure 140, a peripheral circuit-side bonding pad PBP located inside the peripheral circuit-side intercalation insulating layer 141, and a peripheral circuit-side bonding contact PBC extending from the peripheral circuit-side bonding pad PBP to connect to the uppermost conductive pattern 136 of the interconnect 130. In another embodiment, the memory cell array structure may further include a cell-side intercalation insulating layer 175 covering the insulating structure 171, a cell-side bonding pad CBP located inside the cell-side intercalation insulating layer 175, and a cell-side bonding contact CBC extending from the cell-side bonding pad CBP to connect to wiring such as a bit line BL. The gate stack structure 160, memory layer 161, channel pillar CHP, bit line connection structure 173, bit line BL, insulating structure 171, cell-side intercalation insulating layer 175, cell-side bonding contact CBC, and cell-side bonding pad CBP of the memory cell array structure may be formed on a sacrificial substrate separate from the peripheral circuit structure. Subsequently, the cell-side bonding pad CBP is bonded to the peripheral circuit-side bonding pad PBP, and after removing the sacrificial substrate, the end of the channel layer 163A facing in the opposite direction (DR3 direction) to the direction toward the bit line BL can be exposed. After exposing the end of the channel layer 163A, a doped semiconductor structure 180 can be formed, and the doped semiconductor structure 180 can contact the exposed end of the channel layer 163A.

[0075] Figure 6A , Figure 6B , Figure 6C , Figure 6D, Figure 6E and Figure 6F This is a cross-sectional view showing various configurations formed by using methods of manufacturing transistors according to some embodiments of the present disclosure.

[0076] Reference Figure 6A An isolation layer 203 is formed in the semiconductor substrate 201. The active region 201ACT of the semiconductor substrate 201 is separated by the isolation layer 203.

[0077] Semiconductor substrate 201 may include, for example, reference Figure 4A Various semiconductor materials are described for the semiconductor substrate 101.

[0078] In one embodiment, forming the isolation layer 203 may include forming a trench in the semiconductor substrate 201 and filling the trench with an insulator.

[0079] Subsequently, a gate insulating layer 211L, a gate electrode layer 213L, and a gate capping layer 215L can be stacked over the upper surface 201TS of the semiconductor substrate 201. The gate insulating layer 211L can be formed by various methods such as vapor deposition and oxidation. The gate electrode layer 213L can include various conductive materials. In one embodiment, the gate electrode layer 213L can include doped silicon 213A, a stack 213B comprising titanium, tungsten nitride, and tungsten nitride silicon, and tungsten 213C. The gate capping layer 215L can include various insulating materials.

[0080] Reference Figure 6B Etching using photolithography and etching processes Figure 6A The gate capping layer 215L and gate electrode layer 213L are shown. As a result, a gate capping pattern 215 and a gate electrode 213 are formed. In an embodiment, the gate capping layer 215 and gate electrode 213 can be removed. Figure 6A The portion of the gate insulating layer 211L shown exposes the first region 201A1 and the second region 201A2 of the active region 201ACT to the opposite sides of the gate electrode 213. Embodiments of this disclosure are not limited thereto, and... Figure 6A The portion of the gate insulating layer 211L shown above the first region 201A1 and the second region 201A2 can cover the first region 201A1 and the second region 201A2 with a thickness reduced by an etching process. Hereinafter, the reference numeral "211" is used to denote the etched gate insulating layer.

[0081] After forming a stacked structure 210 including a gate insulating layer 211, a gate electrode 213, and a gate cover pattern 215 using the above process, a cover nitride layer 221 can be formed. The cover nitride layer 221 extends along the surfaces of the first region 201A1 and the second region 201A2 of the semiconductor substrate 101 and the surface of the stacked structure 210.

[0082] Subsequently, conductive impurities 310, including n-type or p-type impurities of a first concentration, can be implanted into the first region 201A1 and the second region 201A2 of the semiconductor substrate 101, which are covered by a nitride layer 221. The conductive impurities 310 can be implanted from the upper surface 201TS of the semiconductor substrate 201 at a first depth. An annealing process can then be performed to activate the implanted conductive impurities. Subsequently, a doped region 201LDD is formed in each of the first region 201A1 and the second region 201A2 of the semiconductor substrate 101, and a channel region 201CH with a doping distribution different from that of the doped region 201LDD is formed between the first region 201A1 and the second region 201A2.

[0083] The nitride layer 221 can protect the semiconductor substrate 201 during the impurity implantation process to form the doped region 201LDD.

[0084] Reference Figure 6C A spacer oxide layer 223 can be formed on the sidewall of the nitride layer 221, so that the end of the doped region 201LDD adjacent to the gate electrode 213 is covered by the spacer oxide layer 223.

[0085] In one embodiment, forming the spacer oxide layer 223 may include forming an oxide layer over the surface of the covering nitride layer 221, and etching the oxide layer using an etching process such as etch-back, taking advantage of the difference in etch selectivity between the oxide layer and the nitride layer. Etching of the oxide layer may be performed to expose portions of the covering nitride layer 221 located above the first region 201A1 and the second region 201A2 of the semiconductor substrate 101, and another portion of the covering nitride layer 221 located above the upper surface of the stacked structure 210. During the etching of the oxide layer, the thickness of the exposed areas of the covering nitride layer 221 may be reduced.

[0086] Reference Figure 6D Nitrogen ions 320 are injected into each of the first region 201A1 and the second region 201A2 of the semiconductor substrate 101 to form a nitrogen region 201N. In an embodiment, the nitrogen region 201N can be formed by injecting nitrogen ions 320 with an energy of 5 keV to 10 keV at an injection angle θ of 1° to 5° relative to an axis AX orthogonal to the upper surface 201TS of the semiconductor substrate 201.

[0087] The nitrogen region 201N can be formed thinner than the doped region 201LDD. In an embodiment, the nitrogen region 201N can be distributed with a thickness of 120 Å to 140 Å from the upper surface 201TS of the semiconductor substrate 201 toward the interior of the semiconductor substrate. The nitrogen region 201N can be separated from the channel region 201CH by the doped region 201LDD.

[0088] Reference Figure 6E A buffer layer 225 is formed above the spacer oxide layer 223 and the covering nitride layer 221. The buffer layer 225 can cover... Figure 6D The nitrogen region 201N of each of the first region 201A1 and the second region 201A2 shown is wherein a covering nitride layer 221 is inserted between a buffer layer 225 and the nitrogen region 201N. The buffer layer 225 may cover the sidewalls of the laminated structure 210, wherein a spacer oxide layer 223 and a covering nitride layer 221 are inserted between the buffer layer 225 and the laminated structure 210. The buffer layer 225 may cover the upper surface of the laminated structure 210, wherein the covering nitride layer 221 is inserted between the buffer layer 225 and the laminated structure 210.

[0089] The buffer layer 225 may include a high-temperature oxide (HTO) layer formed at a temperature of 800 degrees Celsius (°C) or higher. In one embodiment, the buffer layer 225 may include silicon oxide. Oxidation of the semiconductor substrate 201 during the formation of the buffer layer 225 can be reduced or prevented by the nitrogen region 201N.

[0090] Subsequently, deuterium ions 330 can be provided to the surface of the nitrogen region 201N through a deuterium annealing process. The deuterium ions 330 can bind to trap sites on the surface of the semiconductor substrate 201 to reduce surface defects in the semiconductor substrate 201. The deuterium annealing process can be performed at a temperature of 750°C to 850°C and a pressure of 15 atm to 20 atm for 30 to 90 minutes. After performing the deuterium annealing process, one or both of a nitrogen annealing process and an oxygen annealing process can be further performed in situ.

[0091] Reference Figure 6F A diffusion barrier layer 227 is formed above the buffer layer 225. The diffusion barrier layer 227 may cover the nitrogen region 201N of each of the first region 201A1 and the second region 201A2, wherein the buffer layer 225 is interposed between the diffusion barrier layer 227 and the nitrogen region 201N. The diffusion barrier layer 227 can improve the diffusion of unwanted dopants and hydrogen ions into the semiconductor substrate 201. The diffusion barrier layer 227 may include silicon nitride. Covering the nitride layer 221, the spacer oxide layer 223, the buffer layer 225 and the diffusion barrier layer 227 can form a multilayer insulating structure 220.

[0092] Subsequently, conductive impurities 340, including n-type or p-type impurities of a second concentration, can be implanted into the first region 201A1 and the second region 201A2 of the semiconductor substrate 101. The conductive impurities 340 can be implanted from the upper surface 201TS of the semiconductor substrate 201 at a second depth. An annealing process can then be performed to activate the implanted conductive impurities. Subsequently, source / drain regions 201SD can be formed in each of the first region 201A1 and the second region 201A2 of the semiconductor substrate 101.

[0093] The conductive impurity 340 has the same conductivity type as the conductive impurity forming the majority carriers of the doped region 201LDD, and can be either an n-type or p-type impurity. The second concentration can be greater than the above reference. Figure 6B The first concentration is described, and the second depth can be controlled to be greater than the reference above. Figure 6B The first description is more in-depth.

[0094] Source / drain regions 201SD are formed in each of the first region 201A1 and the second region 201A2 of the semiconductor substrate 201, and are formed at a location spaced apart from the upper surface 201TS of the semiconductor substrate 201 by the nitrogen region 201N. A portion of the doped region 201LDD that maintains conductive impurities at a lower concentration than that of the source / drain regions 201SD may be disposed between the source / drain regions 201SD and the channel region 201CH.

[0095] The aforementioned source / drain region 201SD, doped region 201LDD, and nitrogen region 201N can form the impurity implantation region 201I.

[0096] In this embodiment, after forming the multiple insulating structure 220 and the impurity implantation region 201I, the formation of... Figure 5A The following processes are described: subsequent processes for the interconnect 130, doped semiconductor structure 150, gate stack structure 160, channel pillar CHP, bit line BL, etc., as well as hydrogen annealing. In another embodiment, after forming the multiple insulating structure 220 and the impurity implantation region 201I, a process for forming... Figure 5B The subsequent processes for the interconnect 130, peripheral circuit side bonding contacts PBC, peripheral circuit side bonding pads PBP, etc., shown, include bonding the cell side bonding pads CBP to... Figure 5B The following are the subsequent processes and hydrogen annealing processes for the peripheral circuit side bonding pad PBP shown.

[0097] Hydrogen ions generated during the hydrogen annealing process can be blocked by the nitrogen region 201N or combine with nitrogen ions in the nitrogen region 201N. A transistor having a nitrogen region 201N can be formed by performing a nitrogen ion implantation process as described in the embodiments of this disclosure, and the diffusion of hydrogen ions to the interface between the gate insulating layer 211 and the semiconductor substrate 201 can be reduced compared to a transistor formed without performing a nitrogen ion implantation process. Therefore, according to the embodiments of this disclosure, the trap site density at the interface between the gate insulating layer 211 and the semiconductor substrate 201 can be increased.

[0098] In addition to reference Figure 6E In addition to the deuterium annealing process described, one or both of the nitrogen annealing and oxygen annealing processes may be additionally performed to improve leakage current in the transistor's off-state.

[0099] According to some embodiments of this disclosure, the source / drain regions of the transistor are separated from the upper surface of the semiconductor substrate by a nitrogen region formed inside the semiconductor substrate. Because the nitrogen region can reduce oxidation of the semiconductor substrate, the density of trap sites caused by semiconductor substrate oxidation can be reduced around the source / drain regions. Furthermore, because the nitrogen region can reduce or prevent the diffusion of hydrogen ions into the transistor, the electrical characteristics of the transistor can be improved.

[0100] Cross-references to related applications

[0101] This application claims priority to Korean Patent Application No. 10-2025-0018799, filed on February 13, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A semiconductor substrate, the semiconductor substrate including an active region, the active region including a first impurity implantation region, a second impurity implantation region and a channel region located between the first impurity implantation region and the second impurity implantation region; A gate insulating layer and a gate electrode, wherein the gate insulating layer and the gate electrode are stacked over the channel region; as well as A multiple insulating structure is provided, which covers the surface of the first impurity implantation region, the surface of the second impurity implantation region, the surface of the gate insulating layer, and the surface of the gate electrode. Each of the first impurity injection region and the second impurity injection region includes: A nitrogen region, said nitrogen region being adjacent to the upper surface of said semiconductor substrate; and The source / drain region is separated from the upper surface of the semiconductor substrate by the nitrogen region, and the source / drain region includes conductive impurities.

2. The semiconductor device of claim 1, further comprising silicon-deuterium bonds formed along the surface of the nitrogen region.

3. The semiconductor device according to claim 1, wherein, Each of the first impurity implantation region and the second impurity implantation region further includes a doped region comprising a lower concentration of conductive impurities than those in the source / drain region, the doped region being disposed between the source / drain region and the channel region.

4. The semiconductor device according to claim 1, wherein, The multiple insulation structure includes: A diffusion barrier layer covering the upper surface of the first impurity implantation region, the upper surface of the second impurity implantation region, the sidewall of the gate electrode, and the upper surface of the gate electrode; and A buffer layer is disposed between the diffusion barrier layer and each of the first impurity injection region and the second impurity injection region, the buffer layer extending between the gate electrode and the diffusion barrier layer.

5. The semiconductor device according to claim 4, wherein, The buffer layer comprises silicon oxide, and the diffusion barrier layer comprises silicon nitride.

6. The semiconductor device according to claim 4, wherein, The multiple insulation structure also includes: A spacer oxide layer, the spacer oxide layer being disposed between the buffer layer and the sidewall of the gate electrode; and A nitride layer is provided between the first impurity implantation region and the buffer layer, and between the second impurity implantation region and the buffer layer, and the nitride layer extends between the gate electrode and the spacer oxide layer.

7. The semiconductor device of claim 1, further comprising a peripheral circuit-side insulating structure formed above the semiconductor substrate to cover the multiple insulating structures; Interconnectors are respectively connected to the gate electrode and the source / drain regions, and the interconnectors are embedded in the peripheral circuit-side insulation structure; as well as A memory cell array structure is disposed above the insulating structure on the peripheral circuit side.

8. A method for manufacturing a semiconductor device, the method comprising the following steps: A stacked structure including a gate insulating layer and a gate electrode is formed above the active region of a semiconductor substrate; A nitrogen region is formed in each of the first and second regions located on opposite sides of the gate electrode in the active region; A buffer layer is formed to cover the nitrogen region of each of the first region and the second region, the sidewalls of the laminated structure, and the upper surface of the laminated structure; as well as Source / drain regions are formed by implanting conductive impurities into a portion of each of the first and second regions, the portions being separated from the upper surface of the semiconductor substrate by the nitrogen region.

9. The method according to claim 8, further comprising the following step: Before the formation of the nitrogen region, A covering nitride layer is formed extending along the surface of the first region, the surface of the second region, and the surface of the stacked structure; With the first region and the second region covered by the nitride layer, a doped region is formed inside each of the first region and the second region; as well as A spacer oxide layer is formed on the sidewall of the nitride layer, such that the end of the doped region adjacent to the gate electrode is covered. The doped region includes conductive impurities with a lower concentration than those in the source / drain regions.

10. The method according to claim 8, wherein, The step of forming the nitrogen region includes: implanting a dose of 1E13 ions / cm at an energy of 5 keV to 10 keV and an implantation angle of 1° to 5° relative to an axis orthogonal to the upper surface of the semiconductor substrate. 2 Up to 1E14 ions / cm 2 Nitrogen ions.

11. The method according to claim 8, further comprising the step of: After the buffer layer is formed and before the source / drain regions are formed, a deuterium annealing process is performed at a temperature of 750°C to 850°C and a pressure of 15 atm to 20 atm for 30 to 90 minutes.

12. The method according to claim 11, further comprising the following step: After performing the deuterium annealing process, at least one of the nitrogen annealing process and the oxygen annealing process is performed.

13. The method according to claim 8, further comprising the following step: Before the source / drain regions are formed, a diffusion barrier layer is formed above the buffer layer.

14. The method according to claim 13, wherein, The buffer layer comprises silicon oxide, and the diffusion barrier layer comprises silicon nitride.

Images