Semiconductor devices

Abstract

A semiconductor device may include: a substrate; a channel isolation pattern on the substrate, the channel isolation pattern including a first region and a second region, wherein the second region is located in a first direction relative to the first region; a channel pattern located on the channel isolation pattern in a second direction intersecting the first direction, the channel pattern overlapping the first region of the channel isolation pattern in the second direction; a gate electrode located on the first region and the second region of the channel isolation pattern in the second direction, the gate electrode extending in the first direction; and a source / drain pattern located on at least one side of the gate electrode and connected to the channel pattern, wherein the thickness of the channel isolation pattern in the first region is different from the thickness of the channel isolation pattern in the second region.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0018749, filed on February 13, 2025, with the Korean Intellectual Property Office. Technical Field

[0002] Some embodiments of this disclosure relate to a semiconductor device and a method of manufacturing a semiconductor device. Background Technology

[0003] As one of the scaling techniques to increase the density of semiconductor devices, multi-gate transistors have been proposed that form finned silicon bodies on a substrate and form gates on the surface of the silicon bodies.

[0004] Because this multi-gate transistor uses a three-dimensional channel, it is easy to scale. Furthermore, current control capability can be improved without increasing the gate length of the multi-gate transistor. Additionally, the short-channel effect (SCE), where the channel region potential is affected by the drain voltage, can be effectively suppressed.

[0005] Recently, a technique has been used to increase the carrier mobility in the channel region of a semiconductor device by forming a layer of stress material in a finned silicon body. Summary of the Invention

[0006] According to some embodiments of this disclosure, a semiconductor device with improved operational performance and reliability can be provided.

[0007] According to some embodiments of this disclosure, a method for manufacturing a semiconductor device with improved operational performance and reliability can be provided.

[0008] According to some embodiments of this disclosure, a semiconductor device may include: a substrate; a channel isolation pattern on the substrate, the channel isolation pattern including a first region and a second region, wherein the second region is located in a first direction relative to the first region; a channel pattern located on the channel isolation pattern in a second direction intersecting the first direction, the channel pattern overlapping the first region of the channel isolation pattern in the second direction; a gate electrode located on the first region and the second region of the channel isolation pattern in the second direction, the gate electrode extending in the first direction; and a source / drain pattern located on at least one side of the gate electrode and connected to the channel pattern, wherein the thickness of the channel isolation pattern in the first region of the channel isolation pattern is different from the thickness of the channel isolation pattern in the second region of the channel isolation pattern.

[0009] According to some embodiments of the present disclosure, a semiconductor device may include: a substrate; a channel isolation pattern on the substrate, wherein the channel isolation pattern includes a plate portion, a first protrusion portion, and a second protrusion portion, wherein each of the first protrusion portion and the second protrusion portion protrudes from the plate portion of the channel isolation pattern in a first direction, wherein the first protrusion portion and the second protrusion portion are spaced apart from each other in a second direction intersecting the first direction; a first channel pattern located on the channel isolation pattern in the first direction and overlapping the first protrusion portion in the first direction; a second channel pattern located on the channel isolation pattern in the first direction and overlapping the second protrusion portion in the first direction; a gate electrode located on the channel isolation pattern, the first channel pattern, and the second channel pattern, and extending in the second direction; and a source / drain pattern located on at least one side of the gate electrode and connected to the first channel pattern.

[0010] According to some embodiments of the present disclosure, a semiconductor device may include: a substrate; a channel isolation pattern on the substrate, the channel isolation pattern including a first region and a second region, wherein the second region is located in a first direction relative to the first region; a channel pattern located on the channel isolation pattern in a second direction intersecting the first direction, the channel pattern overlapping the first region in the second direction, wherein the channel pattern includes a plurality of sheet patterns spaced apart from each other in the second direction; a gate electrode located on the first region and the second region of the channel isolation pattern, the gate electrode extending in the first direction; and a source / drain pattern on at least one side of the gate electrode and connected to the plurality of sheet patterns, wherein the thickness of the channel isolation pattern in the first region of the channel isolation pattern is greater than the thickness of the channel isolation pattern in the second region of the channel isolation pattern, and wherein, in a cross-sectional view of the semiconductor device, the gate electrode at least partially surrounds the plurality of sheet patterns.

[0011] The technical aspects of the embodiments of this disclosure are not limited to those described above, and those skilled in the art can clearly understand other unmentioned technical aspects of the embodiments of this disclosure from the following description.

[0012] Specific details of other embodiments of this disclosure are included in the detailed description and the accompanying drawings.

[0013] The effects of the embodiments of this disclosure are not limited to those described above, and other effects of the embodiments of this disclosure will become clear from the following description. Attached Figure Description

[0014] The above and other aspects and features of this disclosure will become clearer from the detailed description of embodiments thereof with reference to the accompanying drawings, in which: Figure 1 This is an example plan view used to illustrate a semiconductor device according to some embodiments.

[0015] Figure 2 It is along Figure 1 The cross-sectional view taken from line AA.

[0016] Figure 3 It is along Figure 1 The cross-sectional view of line BB.

[0017] Figure 4 It is along Figure 1 The cross-sectional view taken from line CC.

[0018] Figure 5 It is along Figure 1 The cross-sectional view of line DD.

[0019] Figure 6 It is used to show Figures 2 to 5 A perspective view of the shape of the channel isolation pattern.

[0020] Figure 7 It is shown Figure 3 A diagram illustrating the trench isolation pattern.

[0021] Figure 8 and Figure 9 They are Figure 7 A magnified view of part P.

[0022] Figures 10 to 13 This is a diagram used to illustrate a semiconductor device according to some embodiments.

[0023] Figures 14 to 16 These are diagrams illustrating semiconductor devices according to some embodiments.

[0024] Figures 17 to 19 These are diagrams illustrating semiconductor devices according to some embodiments.

[0025] Figure 20 and Figure 21 This is a diagram used to illustrate a semiconductor device according to some embodiments.

[0026] Figure 22 and Figure 23 This is a diagram used to illustrate a semiconductor device according to some embodiments.

[0027] Figure 24 and Figure 25 This is a diagram used to illustrate a semiconductor device according to some embodiments.

[0028] Figure 26 and Figure 27 This is a diagram used to illustrate a semiconductor device according to some embodiments.

[0029] Figure 28 This is a diagram used to illustrate a semiconductor device according to some embodiments.

[0030] Figures 29 to 47 This is a diagram illustrating an intermediate structure corresponding to an intermediate step in a method for manufacturing a semiconductor device according to some embodiments. Detailed Implementation

[0031] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or blocks, these elements, components, regions, layers, and / or blocks should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or block from another. Therefore, the first element, component, region, layer, or block described below may be referred to as the second element, component, region, layer, or block without departing from the spirit and scope of this disclosure.

[0032] It should be understood that when a component or layer is referred to as being "on," "connected to," or "bonded to" another component or layer, it may be located directly on, directly connected to, or directly bonded to that other component or layer, or there may be intermediate components or layers. Conversely, when a component or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another component or layer, there are no intermediate components or layers.

[0033] Semiconductor devices according to some embodiments may include tunneling transistors (e.g., tunneling field-effect transistors (FETs)), three-dimensional (3D) transistors, or FETs based on two-dimensional (2D) materials, and heterostructures thereof. Furthermore, semiconductor devices according to some embodiments may include bipolar junction transistors, laterally diffused metal-oxide-semiconductor (LDMOS) transistors, etc.

[0034] Reference Figures 1 to 9 A semiconductor device is described according to some embodiments.

[0035] Figure 1 This is an example plan view used to illustrate a semiconductor device according to some embodiments. Figures 2 to 5 They are along Figure 1 The cross-sectional view of lines AA, BB, CC and DD. Figure 6 It is used to show Figures 2 to 5 A perspective view of the shape of the channel isolation pattern. Figure 7 It is shown Figure 3 A diagram illustrating the trench isolation pattern. Figure 8 and Figure 9 They are Figure 7 A magnified view of part P.

[0036] For reference only. Figure 1 The semiconductor device is schematically shown in addition to the gate insulating film 130, the source / drain etch stop film 185, the first interlayer insulating film 190, the second interlayer insulating film 191, the front wiring structure 195, etc.

[0037] Reference Figures 1 to 9 According to some embodiments, a semiconductor device may include a channel isolation pattern 110, a first channel pattern CH1, a second channel pattern CH2, a gate electrode 120, a first source / drain pattern 150, and a second source / drain pattern 250.

[0038] A first substrate 100 may be provided, and the first substrate 100 may be made of bulk silicon or silicon-on-insulator (SOI). Alternatively, the first substrate 100 may be a silicon substrate, or may include materials other than silicon, such as silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. However, embodiments of this disclosure are not limited thereto.

[0039] A channel isolation pattern 110 may be disposed on a first substrate 100. The channel isolation pattern 110 may include a plate portion 110PL and a plurality of protrusions 110PR.

[0040] Each protrusion 110PR of the channel isolation pattern 110 may protrude from the plate portion 110PL of the channel isolation pattern 110 on a third-direction DR3. Each protrusion 110PR of the channel isolation pattern 110 may protrude in a direction away from the first substrate 100. The plate portion 110PL of the channel isolation pattern 110 may contact (e.g., in direct contact) the protrusion 110PR of the channel isolation pattern 110.

[0041] Each protrusion 110PR of the channel isolation pattern 110 may extend in a first direction DR1. The protrusions 110PR of the channel isolation pattern 110 may be spaced apart from each other in a second direction DR2. For example, the plurality of protrusions 110PR of the channel isolation pattern 110 may include a first protrusion 110PR_1 and a second protrusion 110PR_2. Each of the first protrusion 110PR_1 and the second protrusion 110PR_2 of the channel isolation pattern 110 may extend in the first direction DR1. The first protrusion 110PR_1 of the channel isolation pattern 110 may be spaced apart from the second protrusion 110PR_2 of the channel isolation pattern 110 in the second direction DR2.

[0042] For example, the first direction DR1 and the second direction DR2 may intersect with the third direction DR3 (e.g., may be perpendicular to the third direction DR3). The first direction DR1 may intersect with the second direction DR2 (e.g., may be perpendicular to the second direction DR2).

[0043] exist Figure 7 In the trench isolation pattern 110, the protruding portion 110PR may include an upper surface 110PR_US and a bottom surface 110PR_BS opposite to each other on the third direction DR3. The protruding portion 110PR of the trench isolation pattern 110 may include sidewalls 110PR_SW opposite to each other on the second direction DR2.

[0044] The bottom surface 110PR_BS of the protrusion 110PR of the channel isolation pattern 110 may face the first substrate 100. The bottom surface 110PR_BS of the protrusion 110PR of the channel isolation pattern 110 may contact (e.g., directly contact) the plate portion 110PL of the channel isolation pattern 110. For example, the bottom surface 110PR_BS of the protrusion 110PR of the channel isolation pattern 110 may be the surface of the protrusion 110PR of the channel isolation pattern 110 that contacts (e.g., directly contacts) the plate portion 110PL of the channel isolation pattern 110. The sidewall 110PR_SW of the protrusion 110PR of the channel isolation pattern 110 connects the upper surface 110PR_US of the protrusion 110PR of the channel isolation pattern 110 to the bottom surface 110PR_BS of the protrusion 110PR of the channel isolation pattern 110.

[0045] The trench isolation pattern 110 includes insulating material. The trench isolation pattern 110 may include a sacrificial field insulating film 105_SC (see below) relative to the sacrificial field insulating film 105_SC described below. Figure 32 The material has etching selectivity. When the sacrificial field insulating film 105_SC comprises silicon oxide, the channel isolation pattern 110 may comprise, for example, silicon nitride, silicon oxynitride, silicon carbonitride, silicon boron nitride, silicon boron oxynitride, silicon carbonitride, or combinations thereof. However, embodiments of this disclosure are not limited thereto. When the material included in the sacrificial field insulating film 105_SC is different from the materials described above, the insulating material included in the channel isolation pattern 110 may be changed.

[0046] Each of the plate portion 110PL and the protruding portion 110PR of the channel isolation pattern 110 may include (but is not limited to) silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon boron nitride, silicon boron oxynitride, or silicon oxycarbide.

[0047] In one example, the plate portion 110PL and the protruding portion 110PR of the trench isolation pattern 110 may comprise insulating materials different from each other. (See reference...) Figure 8 and Figure 9 The boundary between the plate portion 110PL of the channel isolation pattern 110 and the protruding portion 110PR of the channel isolation pattern 110 can be the bottom surface 110PR_BS of the protruding portion 110PR of the channel isolation pattern 110. Figure 8 In the cross-sectional view, the boundary between the plate portion 110PL and the protruding portion 110PR of the channel isolation pattern 110 can be flat. Figure 9 In the cross-sectional view, the boundary between the plate portion 110PL of the channel isolation pattern 110 and the protruding portion 110PR of the channel isolation pattern 110 may include a curved surface.

[0048] Unlike the example shown, a portion of the protrusion 110PR of the channel isolation pattern 110 may protrude into the plate portion 110PL of the channel isolation pattern 110. In this case, the boundary between the plate portion 110PL and the protrusion 110PR of the channel isolation pattern 110 may have a "U" shape or a similar "U" shape in the cross-sectional view.

[0049] In another example, the plate portion 110PL and the protruding portion 110PR of the trench isolation pattern 110 may comprise the same insulating material. In this case, the boundary between the plate portion 110PL and the protruding portion 110PR of the trench isolation pattern 110 may be as follows: Figures 7 to 9 As shown in the diagram. When the boundary between the plate portion 110PL of the channel isolation pattern 110 and the protruding portion 110PR of the channel isolation pattern 110 is not defined, the bottom surface 110PR_BS of the protruding portion 110PR of the channel isolation pattern 110 can be a portion that protrudes from a two-dimensional plate in the third direction DR3.

[0050] In a semiconductor device according to some embodiments, the width W21 of the upper surface 110PR_US of the protrusion 110PR of the channel isolation pattern 110 in the second direction DR2 may be equal to the width W22 of the bottom surface 110PR_BS of the protrusion 110PR of the channel isolation pattern 110 in the second direction DR2.

[0051] The trench isolation pattern 110 may include at least one first region 110_R1 and at least one second region 110_R2. The first region 110_R1 and the second region 110_R2 of the trench isolation pattern 110 may be arranged alternately on the second direction DR2.

[0052] The thickness t11 of the channel isolation pattern 110 in the first region 110_R1 of the channel isolation pattern 110 on the third direction DR3 may be different from the thickness t12 of the channel isolation pattern 110 in the second region 110_R2 of the channel isolation pattern 110 on the third direction DR3. For example, the thickness t11 of the channel isolation pattern 110 in the first region 110_R1 of the channel isolation pattern 110 may be greater than the thickness t12 of the channel isolation pattern 110 in the second region 110_R2 of the channel isolation pattern 110.

[0053] The first region 110_R1 of the channel isolation pattern 110 may include a portion of the plate portion 110PL of the channel isolation pattern 110 and the protruding portion 110PR of the channel isolation pattern 110. The second region 110_R2 of the channel isolation pattern 110 may include a portion of the plate portion 110PL of the channel isolation pattern 110 and may not include the protruding portion 110PR of the channel isolation pattern 110.

[0054] Each of the first channel pattern CH1 and the second channel pattern CH2 may be disposed on the channel isolation pattern 110. The channel isolation pattern 110 may be disposed between the first channel pattern CH1 and the first substrate 100 and between the second channel pattern CH2 and the first substrate 100.

[0055] Each of the first channel pattern CH1 and the second channel pattern CH2 may be disposed on the first region 110_R1 of the channel isolation pattern 110. Each of the first channel pattern CH1 and the second channel pattern CH2 may overlap with the first region 110_R1 of the channel isolation pattern 110 on the third direction DR3.

[0056] Each of the first channel pattern CH1 and the second channel pattern CH2 may be disposed on the protruding portion 110PR of the channel isolation pattern 110. For example, the first channel pattern CH1 may be disposed on the first protruding portion 110PR_1 of the channel isolation pattern 110. The second channel pattern CH2 may be disposed on the second protruding portion 110PR_2 of the channel isolation pattern 110.

[0057] The first channel pattern CH1 may overlap with the first protrusion 110PR_1 of the channel isolation pattern 110 in the third direction DR3. The center line of the width of the first channel pattern CH1 in the second direction DR2 may extend through the first protrusion 110PR_1 of the channel isolation pattern 110. The first channel patterns CH1 may be spaced apart from each other in the first direction DR1, and each of the first channel patterns CH1 may be disposed on the protrusion 110PR of the channel isolation pattern 110.

[0058] The second channel pattern CH2 may overlap with the second protrusion 110PR_2 of the channel isolation pattern 110 in the third direction DR3. The center line of the width of the second channel pattern CH2 in the second direction DR2 may extend through the second protrusion 110PR_2 of the channel isolation pattern 110. The second channel patterns CH2 may be spaced apart from each other in the first direction DR1, and each of the second channel patterns CH2 may be disposed on the protrusion 110PR of the channel isolation pattern 110. The first channel pattern CH1 and the second channel pattern CH2 may be spaced apart from each other in the second direction DR2.

[0059] Each of the first channel pattern CH1 and the second channel pattern CH2 may include a plurality of sheet patterns spaced apart from each other on the third-direction DR3. Although each of the first channel pattern CH1 and the second channel pattern CH2 is shown to include three sheet patterns, this is only for illustrative purposes and embodiments of the present disclosure are not limited thereto.

[0060] The first channel pattern CH1 may include a plurality of first sheet patterns NS1. The plurality of first sheet patterns NS1 may be arranged on the third-direction DR3 and may be disposed on the channel isolation pattern 110. The first sheet patterns NS1 may be spaced apart from each other on the third-direction DR3.

[0061] The second channel pattern CH2 may include a plurality of second sheet patterns NS2. The plurality of second sheet patterns NS2 may be arranged on the third-direction DR3 and may be disposed on the channel isolation pattern 110. The second sheet patterns NS2 may be spaced apart from each other on the third-direction DR3.

[0062] In a semiconductor device according to some embodiments, each of the first channel pattern CH1 and the second channel pattern CH2 may not be in direct contact with the channel isolation pattern 110. For example, each of the first channel pattern CH1 and the second channel pattern CH2 may not be in direct contact with the protrusion 110PR of the channel isolation pattern 110. Each of the first sheet patterns NS1 included in the first channel pattern CH1 may be spaced apart from the channel isolation pattern 110 on a third-direction DR3. Each of the second sheet patterns NS2 included in the second channel pattern CH2 may be spaced apart from the channel isolation pattern 110 on a third-direction DR3.

[0063] For example, a first channel pattern CH1 may include an upper surface CH1_US and a bottom surface CH1_BS opposite to each other on a third-direction DR3. The bottom surface CH1_BS of the first channel pattern CH1 may not be in direct contact with the first protrusion 110PR_1 of the channel isolation pattern 110. The bottom surface CH1_BS of the first channel pattern CH1 may overlap with the first protrusion 110PR_1 of the channel isolation pattern 110 on the third-direction DR3. Each of the first sheet patterns NS1 may include an upper surface and a bottom surface opposite to each other on a third-direction DR3. For example, the bottom surface of each first sheet pattern NS1 may face the channel isolation pattern 110. For example, the uppermost upper surface of the first sheet pattern NS1 may be the upper surface CH1_US of the first channel pattern CH1. The bottom surface of the lowermost first sheet pattern NS1 may be the bottom surface CH1_BS of the first channel pattern CH1.

[0064] The description of the first channel pattern CH1 can also be applied to the second channel pattern CH2.

[0065] In a semiconductor device according to some embodiments, the width W11 of the upper surface CH1_US of the first channel pattern CH1 in the second direction DR2 may be equal to the width W12 of the bottom surface CH1_BS of the first channel pattern CH1 in the second direction DR2.

[0066] Each of the first channel pattern CH1 and the second channel pattern CH2 may include silicon or germanium as an elemental semiconductor material. Additionally, each of the first channel pattern CH1 and the second channel pattern CH2 may include a compound semiconductor, and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0067] Group IV-IV compound semiconductors may include, for example, binary compounds comprising two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), ternary compounds comprising three of them, or compounds obtained by doping them with group IV elements.

[0068] For example, III-V compound semiconductors may include binary compounds obtained by combining one of the group III elements aluminum (Al), gallium (Ga), and indium (In) with one of the group V elements phosphorus (P), arsenic (As), and antimony (Sb); ternary compounds obtained by combining two of the group III elements aluminum (Al), gallium (Ga), and indium (In) with one of the group V elements phosphorus (P), arsenic (As), and antimony (Sb); or quaternary compounds obtained by combining three of the group III elements aluminum (Al), gallium (Ga), and indium (In) with one of the group V elements phosphorus (P), arsenic (As), and antimony (Sb).

[0069] In one example, the first channel pattern CH1 and the second channel pattern CH2 may be disposed in the p-channel metal-oxide-semiconductor (PMOS) formation region. In another example, the first channel pattern CH1 and the second channel pattern CH2 may be disposed in the n-channel metal-oxide-semiconductor (NMOS) formation region. In yet another example, one of the first channel pattern CH1 and the second channel pattern CH2 may be disposed in the PMOS formation region, and the other may be disposed in the NMOS formation region.

[0070] Multiple gate structures GS may be disposed on the first substrate 100. For example, multiple gate structures GS may be disposed on the channel isolation pattern 110. Gate structures GS may be disposed on the first channel pattern CH1 and the second channel pattern CH2.

[0071] Each gate structure GS may extend in the second direction DR2. The gate structures GS may be spaced apart from each other in the first direction DR1. The gate structures GS may be adjacent to each other in the first direction DR1.

[0072] For example, a gate structure GS may be disposed on each of the opposite sides of the first source / drain pattern 150 in the first direction DR1. According to some embodiments, the gate structure GS may be disposed on each of the opposite sides of the second source / drain pattern 250 in the first direction DR1.

[0073] For example, the gate structure GS may include a gate electrode 120, a gate insulating film 130, a gate spacer 140, and a gate cap pattern 145.

[0074] Reference Figure 2 The gate structure GS may include an inner gate structure GS_INT disposed between the channel isolation pattern 110 and the lowermost first sheet pattern NS1, and between the first sheet patterns NS1 adjacent to each other on the third-direction DR3. According to some embodiments, the inner gate structure GS_INT may be disposed between the channel isolation pattern 110 and the lowermost second sheet pattern NS2, and between the second sheet patterns NS2 adjacent to each other on the third-direction DR3. The inner gate structure GS_INT may include a gate electrode 120 and a gate insulating film 130.

[0075] The gate structure GS is shown disposed above a first channel pattern CH1 and a second channel pattern CH2 that are adjacent to each other. However, embodiments of this disclosure are not limited thereto. For example, a portion of the gate structure GS may be divided into two parts that may be disposed on the channel isolation pattern 110. That is, the first gate structure on the first channel pattern CH1 may be isolated from the second gate structure on the second channel pattern CH2 in the second direction DR2. In this case, the first gate electrode and the first gate insulating film included in the first gate structure may be isolated from the second gate electrode and the second gate insulating film included in the second gate structure.

[0076] Gate electrode 120 may be disposed on channel isolation pattern 110. Gate electrode 120 may be disposed on a first region 110_R1 and a second region 110_R2 of channel isolation pattern 110. Gate electrode 120 may extend in a second direction DR2. Gate electrode 120 may be disposed on a first channel pattern CH1 and a second channel pattern CH2. For example, gate electrode 120 may surround each of the first channel pattern CH1 and the second channel pattern CH2. In a semiconductor device according to some embodiments, gate electrode 120 may surround each of a first sheet pattern NS1 and each of a second sheet pattern NS2.

[0077] The gate electrode 120 may include at least one of a metal, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal nitride.

[0078] For example, the gate electrode 120 may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium tantalum nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), and tantalum carbonitride (TaCN). Tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof. However, embodiments of this disclosure are not limited thereto. Conductive metal oxides and conductive metal nitrides may include oxidation products of the above-described materials. However, embodiments of this disclosure are not limited thereto.

[0079] Gate electrodes 120 may be disposed on each of the opposite sides of the first source / drain pattern 150, which will be described later. For example, each of the gate electrodes 120 disposed on the opposite sides of the first source / drain pattern 150 may be a normal gate electrode used as the gate of a transistor. In another example, a gate electrode 120 disposed on one side of the first source / drain pattern 150 may be used as the gate of a transistor, while a gate electrode 120 disposed on the other side of the first source / drain pattern 150 may be a dummy gate electrode.

[0080] The gate insulating film 130 may be disposed on the channel isolation pattern 110. The gate electrode 120 may be disposed on the gate insulating film 130.

[0081] The gate insulating film 130 may be disposed between the gate electrode 120 and the channel isolation pattern 110, between the gate electrode 120 and the first channel pattern CH1, and between the gate electrode 120 and the second channel pattern CH2. The gate insulating film 130 may extend along the contour of each of the plate portion 110PL and the protruding portion 110PR of the channel isolation pattern 110.

[0082] The gate insulating film 130 may include silicon oxide, silicon-germanium oxide, germanium oxide, silicon oxynitride, silicon nitride, or a high-k material with a dielectric constant higher than that of silicon oxide. For example, high-k materials may include at least one of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0083] Although the gate insulating film 130 is shown as being implemented by a single film, this is for illustrative purposes only, and embodiments of this disclosure are not limited thereto. The gate insulating film 130 may include multiple films. The gate insulating film 130 may include an interface film (disposed between the gate electrode 120 and the first channel pattern CH1 and between the gate electrode 120 and the second channel pattern CH2) and a high-k insulating film.

[0084] The semiconductor device according to some embodiments may include a negative capacitance (NC) FET utilizing a negative capacitor. For example, the gate insulating film 130 may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0085] Ferroelectric films can have negative capacitance, and paraelectric films can have positive capacitance. For example, when two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance is less than the capacitance of each individual capacitor. Conversely, when at least one of the capacitances of two or more capacitors connected in series has a negative capacitance, the total capacitance can be positive and greater than the absolute value of each individual capacitor.

[0086] When a ferroelectric film with negative capacitance and a paraelectric film with positive capacitance are connected in series, the total capacitance of the two films connected in series can be increased. By utilizing the increase in total capacitance, a transistor including a ferroelectric film can have a subthreshold swing (SS) of less than about 60 mV / decade at room temperature.

[0087] Ferroelectric material films may possess ferroelectric properties. For example, ferroelectric material films may include at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. In this embodiment, in one example, hafnium zirconium oxide may refer to a material obtained by doping hafnium oxide with zirconium (Zr). In another example, hafnium zirconium oxide may refer to a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0088] Ferroelectric material films may also contain dopants. For example, dopants may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant contained in the ferroelectric material film may vary depending on the type of ferroelectric material included in the ferroelectric material film.

[0089] When the ferroelectric material film includes hafnium oxide, the dopant contained in the ferroelectric material film may include at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al) and yttrium (Y).

[0090] When the dopant is aluminum (Al), the ferroelectric material film may contain approximately 3 at% (atomic%) to approximately 8 at% aluminum. In this embodiment, the dopant content may be based on the aluminum content of the sum of hafnium and aluminum.

[0091] When the dopant is silicon (Si), the ferroelectric film may contain about 2 at% to about 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric film may contain about 2 at% to about 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric film may contain about 1 at% to about 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric film may contain about 50 at% to about 80 at% zirconium.

[0092] The paraelectric material film may possess paraelectric properties. For example, the paraelectric material film may include at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include at least one of, for example, hafnium oxide, zirconium oxide, and aluminum oxide. However, the embodiments disclosed herein are not limited thereto.

[0093] Ferroelectric and paraelectric material films may contain the same materials. Ferroelectric material films may have ferroelectric properties, but paraelectric material films may not. For example, when each of the ferroelectric and paraelectric material films includes hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric material film may be different from the crystal structure of the hafnium oxide contained in the paraelectric material film.

[0094] Ferroelectric material films can have a thickness capable of exhibiting ferroelectric properties. While the thickness of ferroelectric material films can range, for example, from about 0.5 nm to about 10 nm, the embodiments of this disclosure are not limited thereto. Because the critical thickness for exhibiting ferroelectric properties can vary based on the type of ferroelectric material, the thickness of the ferroelectric material film can vary depending on the type of ferroelectric material.

[0095] In one example, the gate insulating film 130 may include a ferroelectric material film. In another example, the gate insulating film 130 may include a plurality of ferroelectric material films spaced apart from each other. The gate insulating film 130 may have a multilayer structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked on top of each other.

[0096] A gate spacer 140 may be disposed on the sidewall of the gate electrode 120. The entire gate spacer 140 may be disposed on the channel isolation pattern 110. The gate spacer 140 may be disposed on a first region 110_R1 and a second region 110_R2 of the channel isolation pattern 110. The gate spacer 140 may be in contact with the channel isolation pattern 110 (e.g., in direct contact).

[0097] For example, the gate spacer 140 may comprise silicon nitride, silicon oxynitride, silicon oxide, silicon carbonitride, boron silicon nitride, boron silicon oxynitride, silicon carbonitride, or combinations thereof. Although the gate spacer 140 is shown as being implemented by a single film, this is intended for illustrative purposes only, and embodiments of this disclosure are not limited thereto.

[0098] A gate capping pattern 145 may be disposed on the gate electrode 120 and the gate spacer 140. The gate capping pattern 145 may be disposed on the upper surface of the gate electrode 120. The upper surface of the gate capping pattern 145 may be coplanar with the upper surface of the first interlayer insulating film 190. However, embodiments of this disclosure are not limited thereto. Unlike the illustrated example, the gate capping pattern 145 may be disposed between the gate spacers 140.

[0099] For example, the gate cap pattern 145 may include silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, or combinations thereof. The gate cap pattern 145 may include a material that has etch selectivity relative to the first interlayer insulating film 190.

[0100] Unlike the example shown, the gate capping pattern 145 may not be provided on the gate electrode 120. That is, the gate structure GS may not include the gate capping pattern 145.

[0101] Each of the first source / drain pattern 150 and the second source / drain pattern 250 may be disposed on the channel isolation pattern 110. Each of the first source / drain pattern 150 and the second source / drain pattern 250 may be disposed on the first region 110_R1 of the channel isolation pattern 110.

[0102] The first source / drain pattern 150 may be disposed on the protrusion 110PR of the channel isolation pattern 110. For example, the first source / drain pattern 150 may be disposed on the first protrusion 110PR_1 of the channel isolation pattern 110. The first source / drain pattern 150 may overlap with the protrusion 110PR of the channel isolation pattern 110 on the third-direction DR3.

[0103] A first source / drain pattern 150 may be connected to a first channel pattern CH1. The first source / drain pattern 150 may contact (e.g., directly contact) a channel isolation pattern 110. In a semiconductor device according to some embodiments, the channel isolation pattern 110 may be disposed between the first source / drain pattern 150 and a first substrate 100. A first region 110_R1 of the channel isolation pattern 110 may be disposed between the first source / drain pattern 150 and the first substrate 100.

[0104] The first source / drain pattern 150 may be disposed on at least one side of the gate electrode 120. The first source / drain pattern 150 may be disposed between adjacent gate electrodes 120 along the first direction DR1. For example, the first source / drain pattern 150 may be disposed on each of the opposite sides of the gate electrodes 120. Unlike the example shown, the first source / drain pattern 150 may be disposed on one side of the gate electrode 120 but may not be disposed on the other side of the gate electrode 120.

[0105] The second source / drain pattern 250 may be disposed on the protrusion 110PR of the channel isolation pattern 110. For example, the second source / drain pattern 250 may be disposed on the second protrusion 110PR_2 of the channel isolation pattern 110. The second source / drain pattern 250 may overlap with the protrusion 110PR of the channel isolation pattern 110 on the third-direction DR3.

[0106] The second source / drain pattern 250 may contact (e.g., in direct contact) the channel isolation pattern 110. According to some embodiments, the second source / drain pattern 250 may be connected to the second channel pattern CH2.

[0107] The first source / drain pattern 150 and the second source / drain pattern 250 may be included in the source / drain of a transistor that includes a first channel pattern CH1 and a second channel pattern CH2 as channel regions.

[0108] Each of the first source / drain pattern 150 and the second source / drain pattern 250 may include an epitaxial pattern. Each of the first source / drain pattern 150 and the second source / drain pattern 250 includes a semiconductor material. Although each of the first source / drain pattern 150 and the second source / drain pattern 250 is shown to have a pentagonal or hexagonal cross-section, this is only for illustrative purposes, and embodiments of this disclosure are not limited thereto. Unlike the illustrated example, each of the first source / drain pattern 150 and the second source / drain pattern 250 may have a quadrilateral cross-section.

[0109] For example, each of the first source / drain pattern 150 and the second source / drain pattern 250 may include silicon or germanium as an elemental semiconductor material. Alternatively, for example, each of the first source / drain pattern 150 and the second source / drain pattern 250 may include a binary compound having two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), a ternary compound including three of these, or a compound obtained by doping it with a group IV element. In one example, when the first source / drain pattern 150 or the second source / drain pattern 250 is included in the source / drain region of a p-type transistor, the first source / drain pattern 150 or the second source / drain pattern 250 may include a silicon-germanium film. In another example, when the first source / drain pattern 150 or the second source / drain pattern 250 is included in the source / drain region of an n-type transistor, the first source / drain pattern 150 or the second source / drain pattern 250 may include a silicon film. However, the embodiments of this disclosure are not limited thereto.

[0110] Each of the first source / drain pattern 150 and the second source / drain pattern 250 may contain impurities doped into the semiconductor material. For example, when the first source / drain pattern 150 or the second source / drain pattern 250 is included in the source / drain region of a p-type transistor, the first source / drain pattern 150 or the second source / drain pattern 250 may contain p-type impurities. For example, p-type impurities may include at least one of boron (B) and gallium (Ga). In another example, when the first source / drain pattern 150 or the second source / drain pattern 250 is included in the source / drain region of an n-type transistor, the first source / drain pattern 150 or the second source / drain pattern 250 may contain n-type impurities. For example, n-type impurities may include at least one of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi).

[0111] Although each of the first source / drain pattern 150 and the second source / drain pattern 250 is shown to be implemented by a single film, this is only for illustrative purposes and the embodiments of this disclosure are not limited thereto.

[0112] A source / drain etch stop film 185 may be disposed on the sidewall of the gate spacer 140 and on the upper surface of each of the first source / drain pattern 150 and the second source / drain pattern 250. The source / drain etch stop film 185 may be disposed on the channel isolation pattern 110. For example, the source / drain etch stop film 185 may extend along the upper surface of the plate portion 110PL of the channel isolation pattern 110.

[0113] The source / drain etch stop film 185 may include a material that has etch selectivity relative to the first interlayer insulating film 190, which will be described later. For example, the source / drain etch stop film 185 may include silicon nitride, silicon oxynitride, silicon carbonitride, boron silicon nitride, boron silicon oxynitride, silicon carbonitride, or combinations thereof.

[0114] The first interlayer insulating film 190 may be disposed on the source / drain etch stop film 185. The first interlayer insulating film 190 may be disposed on the first source / drain pattern 150 and the second source / drain pattern 250. The first interlayer insulating film 190 may not cover the upper surface of the gate cap pattern 145.

[0115] The channel isolation pattern 110 may be disposed between the first substrate 100 and the first interlayer insulating film 190. For example, the channel isolation pattern 110 may be disposed between the source / drain etch stop film 185 and the first substrate 100.

[0116] For example, the first interlayer insulating film 190 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. For example, the low-k material may include fluorinated tetraethyl orthosilicate (FTEOS), silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylchlorotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), TOSZ (Tonen SilaZen), FSG (fluorosilicate glass), polyimide nanofoams such as polypropylene oxide, CDO (carbon-doped silicon oxide), OSG (SiLK), amorphous fluorinated carbon, silica aerogel, silica degel, mesoporous silica, or combinations thereof. However, embodiments of this disclosure are not limited thereto.

[0117] The channel isolation pattern 110 prevents leakage current between adjacent first source / drain patterns 150 on the first direction DR1. Furthermore, due to the channel isolation pattern 110, the vertical and horizontal alignment of the bottom surfaces of the first source / drain patterns 150 arranged on the first direction DR1 can be uniform. Therefore, the performance and reliability of the semiconductor device according to some embodiments can be improved.

[0118] A first front source / drain contact 180 may be disposed on a first source / drain pattern 150. The first front source / drain contact 180 may be connected to the first source / drain pattern 150. The first front source / drain contact 180 may extend through a first interlayer insulating film 190 and a source / drain etch stop film 185 to connect to the first source / drain pattern 150.

[0119] A second front source / drain contact 280 may be disposed on the second source / drain pattern 250. The second front source / drain contact 280 may be connected to the second source / drain pattern 250. The second front source / drain contact 280 may extend through the first interlayer insulating film 190 and the source / drain etch stop film 185 to connect to the second source / drain pattern 250.

[0120] Although each of the first source / drain contact 180 and the second source / drain contact 280 is shown as being implemented by a single film, this is merely for illustrative purposes and embodiments of the present disclosure are not limited thereto. Each of the first source / drain contact 180 and the second source / drain contact 280 may include, for example, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, a two-dimensional (2D) material, or a combination thereof. In a semiconductor device according to some embodiments, the two-dimensional material may be a metallic material and / or a semiconductor material. Two-dimensional materials (2D materials) may include two-dimensional allotropes or two-dimensional composites, and may include, for example, at least one of graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten distelluride (WSe2), and tungsten disulfide (WS2). However, embodiments of the present disclosure are not limited thereto. That is, since the two-dimensional materials described above are listed by way of example only, the two-dimensional materials that may be included in the semiconductor devices of the present disclosure are not limited to the materials described above.

[0121] A first front-contact silicide film 155 may be disposed between the first front-contact source / drain contact 180 and the first source / drain pattern 150. A second front-contact silicide film 255 may be disposed between the second front-contact source / drain contact 280 and the second source / drain pattern 250. Each of the first front-contact silicide film 155 and the second front-contact silicide film 255 may include a metal silicide.

[0122] The second interlayer insulating film 191 may be disposed on the first interlayer insulating film 190. For example, the second interlayer insulating film 191 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0123] A front wiring structure 195 may be disposed in the second interlayer insulating film 191. The front wiring structure 195 may be connected to the first front source / drain contact 180. According to some embodiments, the front wiring structure 195 may be connected to the second front source / drain contact 280.

[0124] The front wiring structure 195 may include a front wiring 197 and a front wiring pass-through 196. The front wiring 197 can be connected to the first front source / drain contact 180 via the front wiring pass-through 196. The gate electrode 120 may be disposed between the channel isolation pattern 110 and the front wiring 197.

[0125] Although front wiring 197 and front wiring pass-through 196 are shown as distinct from each other, this is merely for illustrative purposes, and embodiments of this disclosure are not limited thereto. That is, for example, front wiring 197 may be formed after front wiring pass-through 196 has been formed. In another example, front wiring pass-through 196 and front wiring 197 may be formed simultaneously.

[0126] Although each of the front wiring 197 and the front wiring pass-through 196 is shown as being implemented by a single film, this is merely for illustrative purposes and embodiments of this disclosure are not limited thereto. Each of the front wiring 197 and the front wiring pass-through 196 may include at least one of, for example, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material.

[0127] Figures 10 to 13 This is a diagram illustrating a semiconductor device according to some embodiments. For ease of description, the main description will be consistent with the above references. Figures 1 to 9 The differences in the described embodiments.

[0128] For example, Figure 10 It is along Figure 1 The cross-sectional view of line BB. Figures 11 to 13 They are shown respectively Figure 10 A diagram illustrating the trench isolation pattern.

[0129] Reference Figures 10 to 13 In a semiconductor device according to some embodiments, the width W21 of the upper surface 110PR_US of the protrusion 110PR of the channel isolation pattern 110 in the second direction DR2 may be greater than the width W22 of the bottom surface 110PR_BS of the protrusion 110PR of the channel isolation pattern 110 in the second direction DR2.

[0130] The width of the protruding portion 110PR of the channel isolation pattern 110 may increase as the protruding portion 110PR extends away from the plate portion 110PL of the channel isolation pattern 110.

[0131] exist Figure 11 In the cross-sectional view, the sidewall 110PR_SW of the protruding portion 110PR of the channel isolation pattern 110 can be flat. For example, the sidewall 110PR_SW of the protruding portion 110PR of the channel isolation pattern 110 can be an inclined surface.

[0132] exist Figure 12 and Figure 13 In the trench isolation pattern 110, at least a portion of the sidewall 110PR_SW of the protruding portion 110PR can be a curved surface. Figure 12 In the cross-sectional view, the sidewall 110PR_SW of the protruding portion 110PR of the channel isolation pattern 110 can be a combination of flat and curved surfaces. Figure 13 In the cross-sectional view, the sidewall 110PR_SW of the protruding portion 110PR of the channel isolation pattern 110 can be a curved surface.

[0133] Figures 14 to 16These are diagrams illustrating semiconductor devices according to some embodiments. For ease of description, the main description will be consistent with the above references. Figures 1 to 9 The differences in the described embodiments.

[0134] Reference Figure 14 In a semiconductor device according to some embodiments, the plate portion 110PL of the channel isolation pattern may include a second channel isolation insulating film 110PL2 and a first channel isolation insulating film 110PL1 sequentially stacked on a first substrate 100.

[0135] The first channel isolation insulating film 110PL1 may be disposed between the second channel isolation insulating film 110PL2 and the protrusion 110PR of the channel isolation pattern 110. The second channel isolation insulating film 110PL2 may be in contact (e.g., in direct contact) with the first substrate 100 and the first channel isolation insulating film 110PL1.

[0136] The first trench isolation insulating film 110PL1 may include, relative to the sacrificial field insulating film (105_SC) described below (see below) Figure 32 The material is etch-selective. The first channel insulating film 110PL1 may include (but is not limited to) silicon nitride, silicon oxynitride, silicon carbonitride, boron silicon nitride, boron silicon oxynitride, silicon carbonitride, or combinations thereof.

[0137] The second channel insulating film 110PL2 may include one of silicon oxide and silicon carbonitride. However, the embodiments disclosed herein are not limited thereto.

[0138] Reference Figure 15 and Figure 16 In a semiconductor device according to some embodiments, the width W11 of the upper surface CH1_US of the first channel pattern CH1 in the second direction DR2 may be different from the width W12 of the bottom surface CH1_BS of the first channel pattern CH1 in the second direction DR2.

[0139] Reference Figure 15 The width W11 of the upper surface CH1_US of the first channel pattern CH1 in the second direction DR2 can be greater than the width W12 of the bottom surface CH1_BS of the first channel pattern CH1 in the second direction DR2.

[0140] Reference Figure 16 The width W11 of the upper surface CH1_US of the first channel pattern CH1 in the second direction DR2 may be smaller than the width W12 of the bottom surface CH1_BS of the first channel pattern CH1 in the second direction DR2.

[0141] Figures 17 to 19These are diagrams illustrating semiconductor devices according to some embodiments. For ease of description, the main description will be consistent with the above references. Figures 1 to 9 The differences in the described embodiments.

[0142] Reference Figure 17 In a semiconductor device according to some embodiments, a portion of the first source / drain pattern 150 may protrude into the channel isolation pattern 110.

[0143] A portion of the first source / drain pattern 150 may protrude into the first region 110_R1 of the channel isolation pattern 110.

[0144] According to some embodiments, the second source / drain pattern 250 (see...) Figure 4 A portion of the ) may be highlighted into the first region 110_R1 of the channel isolation pattern.

[0145] Reference Figure 18 In a semiconductor device according to some embodiments, a first source / drain pattern 150 may extend through a channel isolation pattern 110.

[0146] The first source / drain pattern 150 may extend through a first region 110_R1 of the channel isolation pattern 110 to contact (e.g., directly contact) the first substrate 100.

[0147] According to some embodiments, the second source / drain pattern 250 (see...) Figure 4 () can extend through the trench isolation pattern 110.

[0148] Reference Figure 19 According to some embodiments, a semiconductor device may include an inner spacer 140IN.

[0149] The inner spacer 140IN may be disposed between the first sheet patterns NS1 adjacent to each other on the third-direction DR3 and between the channel isolation pattern 110 and the lowermost first sheet pattern NS1. The inner spacer 140IN may contact (e.g., in direct contact) a portion of the gate insulating film 130 included in the inner gate structure GS_INT.

[0150] The inner spacer 140IN may include insulating material.

[0151] Figure 20 and Figure 21 This is a diagram illustrating a semiconductor device according to some embodiments. For ease of description, the main description will be consistent with the above references. Figures 1 to 9 The differences in the described embodiments.

[0152] Reference Figure 20 and Figure 21In a semiconductor device according to some embodiments, one of a plurality of first sheet patterns NS1 may contact (e.g., directly contact) a channel isolation pattern 110.

[0153] One of the plurality of second sheet patterns NS2 may contact (e.g., in direct contact) the channel isolation pattern 110. The lowermost first sheet pattern NS1 of the plurality of first sheet patterns NS1 may contact (e.g., in direct contact) the channel isolation pattern 110. The lowermost second sheet pattern NS2 of the plurality of second sheet patterns NS2 may contact (e.g., in direct contact) the channel isolation pattern 110.

[0154] Each of the first channel pattern CH1 and the second channel pattern CH2 may contact (e.g., directly contact) the protrusion 110PR of the channel isolation pattern 110. The bottom surface CH1_BS of the first channel pattern CH1 and the bottom surface of the second channel pattern CH2 may contact (e.g., directly contact) the channel isolation pattern 110.

[0155] Figure 22 and Figure 23 This is a diagram used to illustrate a semiconductor device according to some embodiments. Figure 24 and Figure 25 This is a diagram illustrating a semiconductor device according to some embodiments. For ease of description, the main description will be consistent with the above references. Figures 1 to 9 The differences in the described embodiments.

[0156] Reference Figures 22 to 25 In a semiconductor device according to some embodiments, each of the first channel pattern CH1 and the second channel pattern CH2 may not include a plurality of sheet patterns spaced apart from each other on a third-direction DR3.

[0157] Reference Figure 22 and Figure 23 Each of the first channel pattern CH1 and the second channel pattern CH2 may not be in direct contact with the channel isolation pattern 110. The gate electrode 120 and the gate insulating film 130 may be disposed between the first channel pattern CH1 and the channel isolation pattern 110, and between the second channel pattern CH2 and the channel isolation pattern 110. As an example, the first channel pattern CH1 is described. The gate electrode 120 and the gate insulating film 130 may surround the upper surface CH1_US, the bottom surface CH1_BS, and the sidewalls of the first channel pattern CH1.

[0158] Reference Figure 24 and Figure 25Each of the first channel pattern CH1 and the second channel pattern CH2 may contact (e.g., in direct contact) the channel isolation pattern 110. Each of the bottom surfaces CH1_BS of the first channel pattern CH1 and the second channel pattern CH2 may contact (e.g., in direct contact) the protrusion 110PR of the channel isolation pattern 110. For example, the gate electrode 120 and the gate insulating film 130 may be disposed on the upper surface CH1_US of the first channel pattern and the sidewall of the first channel pattern CH1. The gate electrode 120 and the gate insulating film 130 may not be disposed on the bottom surface CH1_BS of the first channel pattern CH1.

[0159] Figure 26 and Figure 27 This is a diagram illustrating a semiconductor device according to some embodiments. For ease of description, the main description will be consistent with the above references. Figures 1 to 9 The differences in the described embodiments.

[0160] Reference Figure 26 and Figure 27 A semiconductor device according to some embodiments may include a first back wiring 50, a second back wiring 60, a back source / drain contact 175, a channel isolation pattern 110, a first channel pattern CH1, a second channel pattern CH2, a gate electrode 120, and a first source / drain pattern 150.

[0161] Since the channel isolation pattern 110, the first channel pattern CH1, the second channel pattern CH2, the gate electrode 120, and the first source / drain pattern 150 are comparable to those referenced... Figures 1 to 9 Since they are described the same, the following description will focus on the differences between them.

[0162] A second substrate 200 may be provided, which may include an insulating material. The second substrate 200 may include (but is not limited to) at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0163] A first rear wiring 50 and a second rear wiring 60 may be disposed in a second substrate 200. Each of the first rear wiring 50 and the second rear wiring 60 may extend in a first direction DR1. The first rear wiring 50 may be spaced apart from the second rear wiring 60 in a second direction DR2.

[0164] For example, the first rear wiring 50 and the second rear wiring 60 can be power lines that supply power to a semiconductor device. In another example, the first rear wiring 50 and the second rear wiring 60 can be signal lines that provide operating signals to a semiconductor device. In yet another example, one of the first rear wiring 50 and the second rear wiring 60 can be a power line and the other can be a signal line.

[0165] The first post-wiring 50 may include a first surface 50_S1 and a second surface 50_S2 opposite to each other on the third-direction DR3. The second post-wiring 60 may include a first surface and a second surface opposite to each other on the third-direction DR3. The first surface 50_S1 of the first post-wiring 50 and the first surface of the second post-wiring 60 may face the first source / drain pattern 150, the channel isolation pattern 110, and the gate electrode 120.

[0166] Each of the first rear wiring 50 and the second rear wiring 60 is shown to have a trapezoidal cross-section. However, embodiments of this disclosure are not limited thereto. Unlike the example shown, each of the first rear wiring 50 and the second rear wiring 60 may have a rectangular cross-section. The width of the first surface 50_S1 of the first rear wiring 50 in the second direction DR2 may be smaller than the width of the second surface 50_S2 of the first rear wiring 50 in the second direction DR2.

[0167] For example, each of the first back wiring 50 and the second back wiring 60 can be formed using an damascene process. After forming a trench extending in the first direction DR1 in the second substrate 200, each of the trenches can be filled with a conductive material, thereby forming each of the first back wiring 50 and the second back wiring 60.

[0168] Although each of the first post-wiring 50 and the second post-wiring 60 is shown to have a single conductive film structure, this is merely for illustrative purposes, and embodiments of this disclosure are not limited thereto. For example, each of the first post-wiring 50 and the second post-wiring 60 may include at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material.

[0169] Unlike the example shown, each of the first rear wiring 50 and the second rear wiring 60 may extend in the second direction DR2. The first rear wiring 50 may be spaced apart from the second rear wiring 60 in the first direction DR1. In this case, along Figure 1 The shape of each section taken from line AA and line BB can vary.

[0170] Unlike the example shown, each of the first rear wiring 50 and the second rear wiring 60 may include a line portion and a through portion. For example, the line portion of the first rear wiring 50 may extend elongatedly in a first direction DR1. The through portion of the first rear wiring 50 may protrude from the line portion of the first rear wiring 50 in a third direction DR3. The through portion of the first rear wiring 50 may protrude toward the rear source / drain contact 175.

[0171] The channel isolation pattern 110 may be disposed on the second substrate 200. The channel isolation pattern 110 may be disposed on the first surface 50_S1 of the first rear wiring 50. The channel isolation pattern 110 may be disposed between the first rear wiring 50 and the gate electrode 120 and between the second rear wiring 60 and the gate electrode 120.

[0172] The first rear wiring 50 and the second rear wiring 60 can be respectively disposed on the bottom surface CH1_BS of the first channel pattern CH1 and the bottom surface of the second channel pattern CH2. The front wiring 197 can be disposed on the upper surface CH1_US of the first channel pattern CH1 and the upper surface of the second channel pattern CH2. The channel isolation pattern 110 and the gate electrode 120 can be disposed between the first rear wiring 50 and the front wiring 197 and between the second rear wiring 60 and the front wiring 197.

[0173] The channel isolation pattern 110 may contact (e.g., in direct contact) the second substrate 200. Unlike the example shown, a plate-shaped semiconductor substrate portion may be disposed between the channel isolation pattern 110 and the second substrate 200. The plate-shaped semiconductor substrate portion may be a portion remaining after a portion of the first substrate 100 has been removed during the process of forming the first post-wiring 50 and the second post-wiring 60.

[0174] The first source / drain pattern 150 may include a first front source / drain pattern 150_1 and a first rear source / drain pattern 150_2. The first front source / drain pattern 150_1 and the first rear source / drain pattern 150_2 may be disposed on the first surface 50_S1 of the first rear wiring 50.

[0175] The first front source / drain pattern 150_1 and the first rear source / drain pattern 150_2 may be spaced apart from each other in the first direction DR1, while the first channel pattern CH1 is located between them.

[0176] The first front source / drain contact 180 may be connected (e.g., electrically connected) to the first front source / drain pattern 150_1. A first front contact silicide film 155 may be disposed between the first front source / drain contact 180 and the first front source / drain pattern 150_1. For example, the first front source / drain pattern 150_1 may not be connected (e.g., may not be electrically connected) to the first rear wiring 50 and the second rear wiring 60.

[0177] The post-source / drain contact 175 can be connected to the first post-source / drain pattern 150_2. For example, the post-source / drain contact 175 can be electrically connected to the first post-source / drain pattern 150_2.

[0178] The rear source / drain contact 175 may be disposed between the first rear source / drain pattern 150_2 and the first rear wiring 50. The rear source / drain contact 175 may overlap with the first rear wiring 50 and the first rear source / drain pattern 150_2 on the third-direction DR3.

[0179] The rear source / drain contact 175 can connect (e.g., electrically connect) the first rear source / drain pattern 150_2 and the first rear wiring 50 to each other. The rear source / drain contact 175 can be connected (e.g., electrically connect) to the first rear wiring 50. The rear source / drain contact 175 can be connected (e.g., electrically connect) to the first surface 50_S1 of the first rear wiring 50.

[0180] A rear source / drain contact 175 may be disposed in the second substrate 200. The rear source / drain contact 175 may extend from a first surface 50_S1 of the first rear wiring 50 to a first rear source / drain pattern 150_2. In a semiconductor device according to some embodiments, the rear source / drain contact 175 may extend through a channel isolation pattern 110 and connect to the first rear source / drain pattern 150_2.

[0181] According to some embodiments, when the plate-shaped semiconductor substrate portion is disposed between the channel isolation pattern 110 and the second substrate 200, a rear contact insulating pad may also be disposed between the rear source / drain contact 175 and the plate-shaped semiconductor substrate portion. The rear contact insulating pad may include an insulating material.

[0182] Although the post-source / drain contact 175 is shown as being implemented by a single film, this is merely for illustrative purposes and embodiments of this disclosure are not limited thereto. For example, the post-source / drain contact 175 may include a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, a two-dimensional (2D) material, or a combination thereof.

[0183] The rear contact silicide film 156 may also be disposed between the rear source / drain contact 175 and the first rear source / drain pattern 150_2. The rear contact silicide film 156 may include a metal silicide.

[0184] Figure 28 This is a diagram illustrating a semiconductor device according to some embodiments. For ease of description, the main description will be consistent with the above references. Figure 26 and Figure 27 The differences in the described embodiments.

[0185] Reference Figure 28 In a semiconductor device according to some embodiments, the rear source / drain contact 175 may not extend through the channel isolation pattern 110.

[0186] The first post-source / drain pattern 150_2 may extend through the channel isolation pattern 110. The post-source / drain contact 175 may be connected to the first post-source / drain pattern 150_2 that extends through the channel isolation pattern 110.

[0187] Figures 29 to 47 This is a diagram illustrating an intermediate structure corresponding to an intermediate step in a method for manufacturing a semiconductor device according to some embodiments.

[0188] Reference Figures 29 to 31 A first fin pattern F1 and a second fin pattern F2 can be formed on the sacrificial substrate 100_SC.

[0189] The sacrificial substrate 100_SC may be a silicon substrate, or may include materials other than silicon, such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. However, embodiments of this disclosure are not limited thereto.

[0190] Each of the first fin pattern F1 and the second fin pattern F2 may extend in the first direction DR1. Each of the first fin pattern F1 and the second fin pattern F2 may protrude from the sacrificial substrate 100_SC in the third direction DR3.

[0191] The first fin pattern F1 and the second fin pattern F2 may be spaced apart from each other in the second direction DR2. The first fin pattern F1 and the second fin pattern F2 may be isolated from each other via fin grooves F_T extending in the first direction DR1.

[0192] Each of the first fin pattern F1 and the second fin pattern F2 may include a plurality of sacrificial patterns SC_P and a plurality of active patterns ACT_P alternately stacked on top of each other. For example, the active pattern ACT_P may include a silicon film. The sacrificial pattern SC_P may include a silicon-germanium film.

[0193] A fin hard mask pattern F_HM may be disposed on each of the first fin pattern F1 and the second fin pattern F2. The fin hard mask pattern F_HM may be used as a mask for forming the first fin pattern F1 and the second fin pattern F2. The fin hard mask pattern F_HM may include (but is not limited to) silicon nitride, silicon oxynitride, silicon carbonitride, silicon boron nitride, silicon boron oxynitride, or silicon carbonitride.

[0194] Reference Figure 32 A sacrificial field insulating film 105_SC can be formed on the sacrificial substrate 100_SC.

[0195] The sacrificial field insulating film 105_SC may fill the fin trench F_T. The sacrificial field insulating film 105_SC may not cover the fin hard mask pattern F_HM, thus exposing the fin hard mask pattern F_HM. The sacrificial field insulating film 105_SC may include, for example, silicon oxide. However, embodiments of this disclosure are not limited thereto.

[0196] While forming the sacrificial field insulating film 105_SC, a portion of the fin hard mask pattern F_HM can be removed to reduce the thickness of the fin hard mask pattern F_HM. However, the embodiments of this disclosure are not limited thereto.

[0197] Reference Figure 32 and Figure 33 The channel isolation plate film 110PL can be formed on the fin hard mask pattern F_HM and the sacrificial field insulating film 105_SC.

[0198] The channel isolation membrane 110PL can contact the fin hard mask pattern F_HM. Therefore, a channel isolation pattern 110 including the channel isolation membrane 110PL and the fin hard mask pattern F_HM can be formed. The channel isolation membrane 110PL can be... Figure 3 The plate portion 110PL of the channel isolation pattern 110. The fin hard mask pattern F_HM can be the protruding portion 110PR of the channel isolation pattern 110.

[0199] Reference Figures 33 to 35 The sacrificial substrate 100_SC, on which the channel isolation pattern 110 has been formed, can be bonded to the first substrate 100.

[0200] The first substrate 100 and the sacrificial substrate 100_SC can be bonded to each other, so that the channel isolation pattern 110 can be disposed between the first substrate 100 and the sacrificial substrate 100_SC.

[0201] Unlike the example shown, the first substrate 100 and the sacrificial substrate 100_SC can be bonded to each other using a bonding insulating film. In this case, the bonding insulating film can be a second channel isolation insulating film 110PL2 (see...). Figure 14 ).

[0202] Reference Figures 34 to 37 After the sacrificial substrate 100_SC has been bonded to the first substrate 100, the sacrificial substrate 100_SC can be removed.

[0203] The sacrificial substrate 100_SC can be removed to expose the first fin pattern F1, the second fin pattern F2, and the sacrificial field insulating film 105_SC. The sacrificial pattern SC_P that is furthest from the channel isolation pattern 110 among the sacrificial patterns SC_P included in each of the first fin pattern F1 and the second fin pattern F2 can be exposed.

[0204] Reference Figures 36 to 39It can remove the sacrificial pattern SC_P that is furthest from the channel isolation pattern 110 in each of the first fin pattern F1 and the second fin pattern F2.

[0205] After removing the sacrificial pattern SC_P, which is furthest from the channel isolation pattern 110, the sacrificial field insulating film 105_SC can be removed. As a result, the channel isolation pattern 110 can be exposed.

[0206] Reference Figures 38 to 41 A dummy gate electrode 120P can be formed on the channel isolation pattern 110.

[0207] A dummy gate electrode 120P can be formed on the first fin pattern F1 and the second fin pattern F2. The dummy gate electrode 120P can intersect with the first fin pattern F1 and the second fin pattern F2. The dummy gate electrode 120P can extend in the second direction DR2.

[0208] A dummy gate insulating film 130P can be formed between the dummy gate electrode 120P and the first fin pattern F1, between the dummy gate electrode 120P and the second fin pattern F2, and between the dummy gate electrode 120P and the channel isolation pattern 110. A dummy gate capping film 120_HM can be formed along the upper surface of the dummy gate electrode 120P.

[0209] The dummy gate insulating film 130P may include, for example, silicon oxide. However, embodiments of this disclosure are not limited thereto. The dummy gate electrode 120P may include, for example, polysilicon. However, embodiments of this disclosure are not limited thereto. The dummy gate capping film 120_HM may include, for example, silicon nitride. However, embodiments of this disclosure are not limited thereto.

[0210] Reference Figures 40 to 42 A gate spacer 140 can be formed on the sidewall of the dummy gate electrode 120P.

[0211] While forming the gate spacer 140, the source / drain recess can be formed in the first fin pattern F1 by using the gate spacer 140 and the dummy gate electrode 120P as a mask.

[0212] Reference Figure 42 and Figure 43 A first source / drain pattern 150 can be formed on the channel isolation pattern 110.

[0213] The first source / drain pattern 150 can fill the source / drain recesses.

[0214] A source / drain etch stop film 185 and a first interlayer insulating film 190 can be formed on the first source / drain pattern 150.

[0215] Next, a portion of the first interlayer insulating film 190, a portion of the source / drain etch stop film 185, and the dummy gate capping film 120_HM can be removed to expose the upper surface of the dummy gate electrode 120P. While exposing the upper surface of the dummy gate electrode 120P, a portion of the gate spacer 140 can be removed.

[0216] Reference Figures 43 to 45 The dummy gate insulating film 130P and the dummy gate electrode 120P can be removed to expose the first fin pattern F1.

[0217] Next, the sacrificial pattern SC_P included in the first fin pattern F1 can be removed to form the first channel pattern CH1. The active pattern ACT_P included in the first fin pattern F1 can be the first sheet pattern NS1 included in the first channel pattern CH1.

[0218] Therefore, a gate trench of 120t can be formed.

[0219] Reference Figures 44 to 47 A gate insulating film 130 and a gate electrode 120 can be formed in the gate trench 120t.

[0220] Additionally, a gate capping pattern 145 may be formed on the gate electrode 120.

[0221] Refer to the above Figures 42 to 47 In the described manufacturing process, the dummy gate electrode 120P can be replaced by the gate electrode 120.

[0222] According to some embodiments of this disclosure, a method of manufacturing a semiconductor device may include: forming a channel isolation pattern on a substrate, the channel isolation pattern including a first region and a second region, wherein the second region is located in a first direction relative to the first region; forming a channel pattern on the channel isolation pattern along a second direction intersecting the first direction, the channel pattern overlapping the first region of the channel isolation pattern in the second direction; forming a gate electrode along the second direction on the first region and the second region of the channel isolation pattern, the gate electrode extending in the first direction; and forming a source / drain pattern connected to the channel pattern, wherein the source / drain pattern is located on at least one side of the gate electrode, and wherein the thickness of the channel isolation pattern in the first region of the channel isolation pattern is different from the thickness of the channel isolation pattern in the second region of the channel isolation pattern.

[0223] According to some embodiments of this disclosure, the thickness of the channel isolation pattern in the first region of the channel isolation pattern is greater than the thickness of the channel isolation pattern in the second region of the channel isolation pattern.

[0224] According to some embodiments of this disclosure, the channel pattern does not directly contact the channel isolation pattern.

[0225] According to some embodiments of the present disclosure, the channel pattern includes a plurality of sheet patterns spaced apart from each other in a second direction.

[0226] While non-limiting exemplary embodiments of this disclosure have been described with reference to the accompanying drawings, this disclosure is not limited to the above exemplary embodiments, and embodiments of this disclosure can be implemented in many different forms. Those skilled in the art should understand that embodiments of this disclosure can be practiced in other specific forms without departing from the spirit and scope of this disclosure. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive.

Claims

1. A semiconductor device, comprising: Substrate; A trench isolation pattern on the substrate, the trench isolation pattern comprising a first region and a second region, wherein the first region and the second region are arranged alternately with each other in a first direction; A channel pattern is located on the channel isolation pattern in a second direction intersecting the first direction, and the channel pattern overlaps with the first region of the channel isolation pattern in the second direction; A gate electrode, located in the second direction on the first region and the second region of the channel isolation pattern, the gate electrode extending in the first direction; and A source / drain pattern, which is located on at least one side of the gate electrode and connected to the channel pattern. The thickness of the channel isolation pattern in the first region of the channel isolation pattern is different from the thickness of the channel isolation pattern in the second region of the channel isolation pattern.

2. The semiconductor device according to claim 1, wherein, The thickness of the channel isolation pattern in the first region of the channel isolation pattern is greater than the thickness of the channel isolation pattern in the second region of the channel isolation pattern.

3. The semiconductor device according to claim 1, wherein, The channel pattern does not directly contact the channel isolation pattern.

4. The semiconductor device according to claim 3, wherein, The channel pattern includes a plurality of sheet-like patterns, which are spaced apart from each other in the second direction.

5. The semiconductor device according to claim 1, wherein, The channel pattern is in direct contact with the channel isolation pattern.

6. The semiconductor device according to claim 1, wherein, The channel isolation pattern includes a plate portion and a protruding portion. The protruding portion protrudes from the plate portion in the second direction. The first region of the channel isolation pattern includes the protruding portion and the first part of the plate portion. The second region of the channel isolation pattern includes the second portion of the plate portion and does not include the protruding portion.

7. The semiconductor device according to claim 6, wherein, The plate portion of the trench isolation pattern includes a first insulating film and a second insulating film located on the first insulating film in the second direction.

8. The semiconductor device according to claim 1, wherein, The source / drain pattern extends through the channel isolation pattern.

9. The semiconductor device according to claim 1, wherein, The source / drain pattern is in direct contact with the channel isolation pattern. The first region of the channel isolation pattern is located between the source / drain pattern and the substrate.

10. The semiconductor device of claim 1, further comprising: Source / drain contacts connected to the source / drain pattern; as well as Wiring, which connects to the source / drain contacts, The gate electrode is located between the wiring and the channel isolation pattern.

11. The semiconductor device according to claim 1, further comprising: Source / drain contacts connected to the source / drain pattern; as well as Wiring, which connects to the source / drain contacts, The channel isolation pattern is located between the gate electrode and the wiring. The source / drain contacts are located in the substrate.

12. A semiconductor device, comprising: Substrate; A channel isolation pattern on the substrate, wherein the channel isolation pattern includes a plate portion, a first protrusion portion and a second protrusion portion, wherein each of the first protrusion portion and the second protrusion portion protrudes from the plate portion of the channel isolation pattern in a first direction, wherein the first protrusion portion and the second protrusion portion are spaced apart from each other in a second direction intersecting the first direction; A first channel pattern is located on the channel isolation pattern in the first direction and overlaps with the first protrusion in the first direction; A second channel pattern is located on the channel isolation pattern in the first direction and overlaps with the second protrusion in the first direction; A gate electrode, which is located on the channel isolation pattern, the first channel pattern, and the second channel pattern, and the gate electrode extends in the second direction; and A source / drain pattern located on at least one side of the gate electrode and connected to the first channel pattern.

13. The semiconductor device according to claim 12, wherein, The first protruding portion includes an upper surface and a bottom surface opposite to the upper surface in the first direction. The bottom surface of the first protruding portion is in direct contact with the plate portion. Wherein, the width of the upper surface of the first protruding portion in the second direction is greater than the width of the bottom surface of the first protruding portion in the second direction.

14. The semiconductor device according to claim 13, wherein, The first protruding portion of the channel isolation pattern includes sidewalls that are opposite each other in the second direction. Each of the sidewalls of the first protrusion has at least a curved surface.

15. The semiconductor device according to claim 12, wherein, The first protruding portion of the channel isolation pattern includes an upper surface and a bottom surface opposite to the upper surface in the first direction. The bottom surface of the first protruding portion is in contact with the plate portion. Wherein, the width of the upper surface of the first protruding portion in the second direction is equal to the width of the bottom surface of the first protruding portion in the second direction.

16. The semiconductor device according to claim 12, wherein, The first channel pattern includes a plurality of sheet-like patterns, which are spaced apart from each other in the first direction.

17. The semiconductor device according to claim 16, wherein, Each of the plurality of sheet patterns is spaced apart from the channel isolation pattern in the first direction.

18. The semiconductor device according to claim 16, wherein, One of the plurality of sheet-like patterns is in direct contact with the channel isolation pattern.

19. A semiconductor device, comprising: Substrate; A trench isolation pattern on the substrate, the trench isolation pattern comprising a first region and a second region, wherein the first region and the second region are arranged alternately with each other in a first direction; A channel pattern located on the channel isolation pattern in a second direction intersecting the first direction, the channel pattern overlapping the first region in the second direction, wherein the channel pattern comprises a plurality of sheet-like patterns spaced apart from each other in the second direction; A gate electrode, located on the first region and the second region of the channel isolation pattern, extending in the first direction; and Source / drain patterns are located on at least one side of the gate electrode and are connected to the plurality of sheet patterns. Wherein, the thickness of the channel isolation pattern in the first region of the channel isolation pattern is greater than the thickness of the channel isolation pattern in the second region of the channel isolation pattern, and In a cross-sectional view of the semiconductor device, the gate electrode at least partially surrounds the plurality of sheet-like patterns.

20. The semiconductor device of claim 19, further comprising: Source / drain contacts are located in the substrate and are connected to the source / drain pattern; as well as Wiring that connects to the source / drain contacts.

Images