Semiconductor device fabrication methods and field-effect transistors

Abstract

This application relates to the field of semiconductor device technology, and discloses a method for fabricating a semiconductor device and a field-effect transistor. The method for fabricating the semiconductor device includes: providing a substrate; forming a first epitaxial layer on the substrate, and etching a portion of the first epitaxial layer to form a trench; forming a shielding gate within the trench; and fabricating a second epitaxial layer on the first epitaxial layer. This fabrication method, by sequentially forming the first epitaxial layer, etching trenches, and fabricating a shielding gate on the substrate, combined with a segmented process layout for fabricating the second epitaxial layer on the first epitaxial layer, can significantly optimize the structural stability and electrical performance of the semiconductor device, while improving process yield and production compatibility.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and more particularly to a method for fabricating a semiconductor device and a field-effect transistor. Background Technology

[0002] Shielded Gate Trench (SGT) MOSFETs are widely used in electronic devices due to their excellent conduction performance and low conduction losses, and are one of the core types of power semiconductor devices. Their fabrication process requires a stable substrate, precise structural processing, and reliable insulation to ensure the device's electrical performance and long-term stability.

[0003] Currently, traditional SGT device fabrication processes have many shortcomings: epitaxial layers often adopt a monolithic thick-layer growth mode, which can easily lead to problems such as tilted trench sidewalls, uneven bottoms, uneven layer deposition, and polysilicon filling voids during subsequent etching processes, affecting subsequent structure building. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This part of the invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art or related art.

[0006] Therefore, a first aspect of the present invention provides a method for fabricating a semiconductor device.

[0007] A second aspect of the present invention provides a field-effect transistor.

[0008] In view of the above, a method for fabricating a semiconductor device is provided according to a first aspect of the embodiments of this application, comprising: Provide substrate; A first epitaxial layer is formed on the substrate, and a portion of the first epitaxial layer is etched to form trenches; A shielding grid is formed within the trench, and a first isolation oxide layer is prepared on the shielding grid; A second epitaxial layer is prepared on the first epitaxial layer.

[0009] A further improvement of the present invention is that the step of forming a shielding grid in the trench includes: A second insulating oxide layer is formed within the trench; The shielding gate is formed by filling polycrystalline silicon material onto the second isolation oxide layer. The first isolation oxide layer is located within the trench.

[0010] A further improvement of the present invention is that the step of forming the first isolation oxide layer on the shielding gate includes: An oxide deposition layer is formed on the shielding grid by chemical vapor deposition; The first isolating oxide layer is prepared by processing the oxide deposit layer with chemical mechanical polishing.

[0011] A further improvement of the present invention is that the step of forming the first isolation oxide layer on the shielding gate further includes: Prior to the step of forming an oxide deposition layer on the shielding grid by chemical vapor deposition, the sidewalls of the trench are etched to widen the opening, thereby forming an oxide deposition layer on the second isolation oxide layer and the shielding grid.

[0012] A further improvement of the present invention is that the step of forming a first epitaxial layer on the substrate and etching a portion of the first epitaxial layer to form trenches includes: The first epitaxial layer is epitaxially grown on the substrate; A buffer oxide layer and a mask layer are formed sequentially from bottom to top on the first epitaxial layer; An etching region is defined on the mask layer using a photoresist layer; The trench is formed by etching the first epitaxial layer based on the etched area; The mask layer includes a silicon nitride layer and a silicon oxide layer.

[0013] A further improvement of the present invention is that the step of forming the first isolation oxide layer on the shielding gate further includes: Etching removes the buffer oxide layer and the mask layer; The first isolation oxide layer and the first epitaxial layer were smoothed using a chemical mechanical polishing process.

[0014] A further improvement of this invention is that the method for fabricating the semiconductor device further includes: A dielectric layer is formed on the second epitaxial layer; A control gate is formed above the first isolation oxide layer.

[0015] A further improvement of this invention is that the method for fabricating the semiconductor device further includes: The second epitaxial layer is doped to form P-type well regions and N-type well regions, which are located below the dielectric layer.

[0016] A further improvement of this invention is that the method for fabricating the semiconductor device further includes: A plurality of contact holes are formed in the dielectric layer, and the contact holes are connected to at least one of the control gate, the P-type well region, or the N-type well region; The contact hole is filled with conductive material; A metal layer is formed on the dielectric layer, and the metal layer is conductive to the contact hole.

[0017] A field-effect transistor is provided according to a second aspect of the embodiments of this application. The field-effect transistor is fabricated based on the semiconductor device fabrication method described in any of the above technical solutions.

[0018] A further improvement of the present invention is that the field-effect transistor includes: Substrate; A first epitaxial layer is disposed on the substrate, and a trench is formed on the first epitaxial layer; A second insulating oxide layer is disposed on the wall and bottom surfaces of the trench; A shielding grid, wherein the shielding grid is disposed on the second isolation oxide layer; A first isolation oxide layer is disposed on the shielding grid; The second epitaxial layer is disposed above the first epitaxial layer; The second isolation oxide layer, the shielding gate, and the first isolation oxide layer are all located within the trench.

[0019] A further improvement of the present invention is that the field-effect transistor further includes: A well region, wherein the well region is formed by doping the second epitaxial layer; A control gate, wherein the control gate is disposed on the first isolation oxide layer; A dielectric layer is disposed above the well region; A metal layer disposed on the dielectric layer, the metal layer being connected to the well region and / or the control gate via a contact hole.

[0020] Compared with the prior art, the present invention has the following unexpected technical effects: The semiconductor device fabrication method provided in this application significantly optimizes the structural stability and electrical performance of the semiconductor device by sequentially forming a first epitaxial layer, etching trenches, and fabricating a shielding gate on a substrate, combined with a segmented process layout for fabricating a second epitaxial layer on the first epitaxial layer. This also improves process yield and production compatibility. By forming the first epitaxial layer first and then etching the trenches, the depth, width, and sidewall morphology of the trenches can be precisely controlled, avoiding morphological distortion and sharp bottom corners caused by directly processing high aspect ratios in thick epitaxial structures. This provides a regular structural foundation for the subsequent formation of the shielding gate. Fabricating the shielding gate within the trenches before growing the second epitaxial layer effectively reduces the overall aspect ratio of the trenches, mitigating defects such as uneven deposition and polysilicon voids caused by excessively deep or narrow trenches in traditional processes. This ensures a dense and defect-free interface between the shielding gate and the surrounding dielectric and epitaxial layers, improving the device's insulation reliability and withstand voltage capability.

[0021] The unexpected technical effects of this application are as follows: The fabrication method provided in this application allows for independent control of parameters such as doping concentration and thickness of the first and second epitaxial layers through segmented epitaxy, adapting to different withstand voltage levels and on-resistance requirements, thus enhancing device design flexibility. Simultaneously, this process sequence simplifies the processing difficulty of complex trench structures, reduces the superposition error of photolithography and etching processes, and lowers the over-reliance on equipment precision, which is beneficial for large-scale mass production. Fabricating the shielding gate within the trench and then growing the second epitaxial layer effectively reduces the overall aspect ratio of the trench, alleviating defects such as uneven layer deposition and polysilicon filling voids caused by excessively deep or narrow trenches in traditional processes. This ensures a dense and defect-free interface between the shielding gate and the surrounding dielectric and epitaxial layers, improving the device's insulation reliability and withstand voltage capability.

[0022] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0023] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 A schematic flowchart illustrating the steps of a semiconductor device fabrication method according to an embodiment of this application; Figure 2 A schematic structural diagram of the first step of a semiconductor device fabrication method according to an embodiment of this application; Figure 3 A schematic structural diagram of the second step of a semiconductor device fabrication method according to an embodiment of this application; Figure 4 A schematic structural diagram of the third step of a semiconductor device fabrication method according to an embodiment of this application; Figure 5 A schematic structural diagram of the fourth step of a semiconductor device fabrication method according to an embodiment of this application; Figure 6 A schematic structural diagram of the fifth step of a semiconductor device fabrication method according to an embodiment of this application; Figure 7 A schematic structural diagram of the sixth step of a semiconductor device fabrication method according to an embodiment of this application; Figure 8 A schematic structural diagram of the seventh step of a semiconductor device fabrication method according to an embodiment of this application; Figure 9 A schematic structural diagram of the eighth step of a semiconductor device fabrication method according to an embodiment of this application; Figure 10 A schematic structural diagram of the ninth step of a semiconductor device fabrication method according to an embodiment of this application; Figure 11 A schematic structural diagram of the tenth step of a semiconductor device fabrication method according to an embodiment of this application; Figure 12 A schematic structural diagram of the eleventh step of a semiconductor device fabrication method according to an embodiment of this application; Figure 13 A schematic structural diagram of a field-effect transistor fabricated by a semiconductor device fabrication method according to an embodiment of this application.

[0024] in, Figures 2 to 13 The correspondence between the reference numerals and component names in the attached drawings is as follows: 110, Substrate; 120, First epitaxial layer; 130, Shielding gate; 140, Second epitaxial layer; 150, Second isolation oxide layer; 160, First isolation oxide layer; 170, Buffer oxide layer; 180, Mask layer; 190, Dielectric layer; 1100, Control gate; 1110, P-type well region; 1120, N-type well region; 1130, Contact hole; 1140, Metal layer; 1150, Photoresist layer; 121. Trench; 161. Oxidized deposit layer; 210. Trap region; 181. Silicon nitride layer; 182. Silicon oxide layer. Detailed Implementation

[0025] The following description provides numerous specific details to offer a more thorough understanding of the technical solutions provided by this invention. However, it will be apparent to those skilled in the art that the technical solutions provided by this invention can be implemented without one or more of these details.

[0026] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0027] Exemplary embodiments according to the present invention will now be described in more detail with reference to the accompanying drawings. However, these exemplary embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of the invention is thorough and complete, and that the concept of these exemplary embodiments is fully conveyed to those skilled in the art.

[0028] like Figure 1 As shown, a method for fabricating a semiconductor device is provided according to a first aspect of the embodiments of this application, comprising: Step 101: Provide a substrate.

[0029] It is understandable that a substrate refers to the basic support substrate required for the fabrication of semiconductor devices. The substrate is used to provide a stable support platform for subsequent structures such as the first epitaxial layer, trenches, and shielding gates. The specific selection of the substrate can include, but is not limited to, single-crystal silicon substrates or epitaxial substrates.

[0030] Step 102: Form a first epitaxial layer on the substrate, and etch a portion of the first epitaxial layer to form trenches.

[0031] Understandably, the first epitaxial layer can be formed on the substrate through chemical vapor deposition, providing a basic conductive carrier for the device. Dry etching processes can be used to form trenches, commonly plasma etching, which uses high-energy plasma to bombard a designated area of ​​the first epitaxial layer; alternatively, reactive ion etching can be used to precisely control the trench dimensions, ensuring smooth trench walls, providing a foundation for the subsequent fabrication of the shielding gate, and guaranteeing stable electrical performance of the device.

[0032] Step 103: Form a shielding grid in the trench and prepare a first isolation oxide layer on the shielding grid.

[0033] Understandably, the shielding gate serves to isolate and protect the device while controlling the electric field. The material can be highly conductive polycrystalline silicon, doped with phosphorus to enhance conductivity. It can shield against electric field interference within the trench, preventing leakage risks, while simultaneously fixing the internal potential of the device, optimizing the current conduction path, and providing a stable foundation for subsequent control gates and dielectric layers, thus ensuring the overall insulation and operational stability of the semiconductor device.

[0034] Step 104: Prepare a second epitaxial layer on the first epitaxial layer.

[0035] It is understandable that the materials of the first epitaxial layer and the second epitaxial layer can be the same (e.g., both are single crystal silicon), and the doping concentration can be adjusted according to the conductivity requirements. Both are prepared by epitaxial growth process to ensure tight interlayer bonding, provide a stable substrate for subsequent preparation of control gate and contact holes, ensure that the switching performance and withstand voltage of the device meet the standards, and can be adapted to the design requirements of SGT structure (Shielded Gate Trench).

[0036] like Figures 1 to 12 As shown, the semiconductor device fabrication method provided in this application, by sequentially forming a first epitaxial layer 120, etching trenches 121, and fabricating a shielding gate 130 on a substrate 110, combined with a segmented process layout of fabricating a second epitaxial layer 140 on the first epitaxial layer 120, can significantly optimize the structural stability and electrical performance of the semiconductor device, while improving process yield and production compatibility. By forming the first epitaxial layer 120 first and then etching the trenches 121, the depth, width, and sidewall morphology of the trenches 121 can be precisely controlled, avoiding morphological distortion and sharp bottom corners caused by directly processing high aspect ratios in a thick epitaxial structure, thus providing a regular structural basis for the subsequent formation of the shielding gate 130. After fabricating the shielding gate 130 in the trench 121, the second epitaxial layer 140 is grown. This can effectively reduce the overall depth-to-width ratio of the trench 121, alleviate the defects such as uneven layer deposition and polysilicon filling voids caused by the trench 121 being too deep or too narrow in the traditional process, ensure that the interface between the shielding gate 130 and the surrounding dielectric layer 190 and epitaxial layer is dense and defect-free, and improve the insulation reliability and withstand voltage of the device.

[0037] The fabrication method provided in this application allows for independent control of parameters such as doping concentration and thickness of the first epitaxial layer 120 and the second epitaxial layer 140 through segmented epitaxy, adapting to different voltage ratings and on-resistance requirements and enhancing device design flexibility. Simultaneously, this process sequence simplifies the fabrication difficulty of the complex trench 121 structure, reduces the superposition error of photolithography and etching processes, and lowers the over-reliance on equipment precision, facilitating large-scale mass production. The shielding gate 130 is confined within the trench 121, forming a layered structure with the second epitaxial layer 140. This effectively optimizes the internal electric field distribution of the device, suppresses the drain-induced barrier reduction effect, reduces leakage current, and improves the device's switching performance and operational stability. Ultimately, this significantly improves the overall performance, process controllability, and mass production feasibility of the semiconductor device.

[0038] The fabrication method provided in this application uses a segmented first epitaxial layer 120 and a second epitaxial layer 140 to prepare a first isolation oxide layer 160 via chemical vapor deposition. The first isolation oxide layer 160 serves as the isolation layer for the shielding gate 130. The grown first isolation oxide layer 160 can be used as a stop layer through the first epitaxial layer 120. After CMP planarization, the thickness of the first isolation oxide layer 160 becomes very flat, which can optimize the electric field distribution of the MOSFET-SGT device. In conventional SGT products, the oxide layer is formed by wet etching (WET), resulting in an uneven first isolation oxide layer 160. During electric field distribution, the electric field at the isolation oxide layer is relatively concentrated, which cannot effectively deplete the device drift region laterally, forming a dense electric field that leads to premature device breakdown, insufficient device breakdown voltage (insufficient BVDSS), and leakage current (increased IDSS). The application, through the flat first isolation oxide layer 160, can be expected to improve the performance of key parameters such as drain-source breakdown voltage (BVDSS) and drain-source saturation current (IDSS) by 10% to 15%, with an overall average improvement of about 5%.

[0039] like Figure 2 and Figure 3 As shown, in one feasible embodiment, the steps of forming a first epitaxial layer 120 on a substrate 110 and etching a portion of the first epitaxial layer 120 to form a trench 121 include: forming a buffer oxide layer 170 and a mask layer 180 sequentially from bottom to top on the first epitaxial layer 120; defining an etchable region on the mask layer 180 through a photoresist layer 1150; and etching the first epitaxial layer 120 to form the trench 121 based on the etchable region; wherein the mask layer 180 includes a silicon nitride layer 181 and a silicon oxide layer 182.

[0040] In this technical solution, the buffer oxide layer 170 and the mask layer 180 effectively isolate the first epitaxial layer 120 from subsequent etching processes, preventing impurity contamination and providing stable support for etching positioning. By defining the etching area with photoresist, the position, size, and depth of the trench 121 can be precisely controlled, ensuring that the trench 121 has a regular shape, free of burrs and damage.

[0041] In this technical solution, the mask layer 180, composed of silicon nitride layer 181 and silicon oxide layer 182, possesses excellent insulation and etching resistance, preventing damage to the first epitaxial layer 120 during etching and avoiding structural defects caused by over-etching. The layered etching and forming process can precisely control the trench 121 dimensions, reduce etching deviations, improve device structural consistency, thereby optimizing the electric field distribution, reducing leakage risk, and ensuring the normal fabrication of the subsequent shielding gate 130 and control gate 1100. This provides structural support for the stable operation of semiconductor devices and meets the long-term reliable operation requirements of power devices.

[0042] like Figures 3 to 8 As shown, in one feasible embodiment, the step of forming a shielding gate 130 in the trench 121 includes: forming a second isolation oxide layer 150 in the trench 121; filling the second isolation oxide layer 150 with polysilicon material to form the shielding gate 130; and then forming a first isolation oxide layer 160 on the shielding gate 130; wherein the first isolation oxide layer 160 is located in the trench 121.

[0043] In this technical solution, the stepwise fabrication method of forming a second isolation oxide layer 150 on the wall of the trench 121, filling the second isolation oxide layer 150 with polycrystalline silicon material to form a shielding gate 130, and forming a first isolation oxide layer 160 on the shielding gate 130 can significantly improve the integrity of the shielding gate 130 structure and the electrical reliability of the device. The second isolation oxide layer 150, as the insulating dielectric layer 190 of the inner wall of the trench 121, can achieve effective electrical isolation between the shielding gate 130 and the first epitaxial layer 120, avoiding problems such as leakage and short circuit caused by direct contact between the shielding gate 130 and the silicon substrate, while protecting the sidewall of the trench 121 from damage in subsequent processes and maintaining a regular interface morphology.

[0044] It is understood that the specific steps for forming the second isolation oxide layer 150 in the trench 121 may include first depositing an oxide layer (OX) on the entire surface, and then removing the OX on the SI surface by means of a CMP process, while retaining the OX in the trench 121, thereby forming the second isolation oxide layer 150.

[0045] like Figure 4As shown, in this technical solution, the shielding gate 130 is formed by filling with polycrystalline silicon material, which ensures that the shielding gate 130 structure has stable conductivity and structural strength, adapts to the high aspect ratio filling requirements of the trench 121, reduces defects such as filling voids and loose interfaces, and provides a stable conductive carrier for electric field shielding and potential control. The first isolation oxide layer 160 formed above the shielding gate 130 can further realize the insulation isolation between the shielding gate 130 and the subsequent control gate 1100, avoid signal interference and electrical breakdown between the two gate structures, and improve the operating stability of the device.

[0046] In this technical solution, the first isolation oxide layer 160 is located inside the trench 121, which can maintain a good morphological match with the surface of the first epitaxial layer 120, providing a smooth and dense transition interface for the subsequent growth of the second epitaxial layer 140, reducing interlayer stress and interface defects. The overall fabrication process not only ensures the structural forming accuracy of the shielding gate 130, but also optimizes the internal electric field distribution of the device through a multilayer insulation structure, suppresses electric field concentration, and improves the device's withstand voltage and long-term operational reliability, providing a structural foundation for the subsequent fabrication of the control gate 1100, the well region 210, and the metal interconnect structure.

[0047] It is understood that forming a second isolation oxide layer 150 in the trench 121 can mean forming a second isolation oxide layer 150 on the inner wall surface and bottom of the trench 121.

[0048] like Figures 5 to 8 As shown, in one feasible embodiment, the step of forming a first isolation oxide layer 160 on the shielding gate 130 includes: forming an oxide deposition layer 161 on the shielding gate 130 based on plasma silicon oxide material by high-density plasma chemical vapor deposition (HDP-CVD); and smoothing the oxide deposition layer 161 based on chemical mechanical polishing (CMP) to prepare and obtain the first isolation oxide layer 160.

[0049] In this technical solution, a plasma chemical vapor deposition process is used to form an oxide deposition layer 161 on the shielding gate 130. This enables the deposition of a high-quality silicon oxide dielectric layer 190 with high step coverage inside the trench 121, effectively avoiding defects such as gaps, voids, and uneven filling that are prone to occur in traditional deposition methods. This ensures that the first isolation oxide layer 160 has a dense, uniform structure and is free of interface defects, providing stable and reliable electrical isolation between the shielding gate 130 and the subsequent control gate 1100. This deposition method produces high-quality films with controllable stress, is adaptable to the environment of high aspect ratio trenches 121, and significantly improves the insulation performance and withstand voltage stability of the device.

[0050] In this technical solution, the oxide deposition layer 161 is smoothed using a chemical mechanical polishing (CMP) process, which precisely removes redundant surface material, ensuring a highly flat surface between the first isolating oxide layer 160 and the first epitaxial layer 120. This eliminates morphological issues such as local protrusions and thickness deviations, providing a smooth and clean interface for the subsequent growth of the second epitaxial layer 140, and reducing interlayer bonding defects and interface stress. Simultaneously, CMP allows for precise control of the thickness of the first isolating oxide layer 160, improving process consistency and repeatability, which is beneficial for large-scale production.

[0051] In this technical solution, the deposition-then-grinding method ensures the complete formation of the first isolation oxide layer 160 within the trench 121 and achieves global surface planarization, effectively optimizing the internal electric field distribution of the device, suppressing electric field concentration, reducing leakage current and breakdown risk, and improving the long-term operational reliability of the device. This process is simple, controllable, and highly compatible, significantly improving the overall structural stability and electrical performance of the semiconductor device, and providing a structural foundation for subsequent processes such as the control gate 1100, well region 210, and metal interconnects.

[0052] Understandably, the oxide deposition layer 161 is smoothed using chemical mechanical polishing (CMP) to prepare the first isolation oxide layer 160. A flat shielding gate 130 isolation oxide layer can be formed. Subsequently, a second epitaxial layer 140 can be grown on the first epitaxial layer 120 using atmospheric pressure chemical vapor deposition (APCVD) with silane and hydrogen gas. Since the surface of this semiconductor device is mainly composed of the first epitaxial layer 120 and the first isolation oxide layer 160, the epitaxial layer grown by APCVD is selective. Due to lattice differences, SiO2 only nucleates on the first epitaxial layer 120 to form the second epitaxial layer 140. SiO2 cannot be formed on the surface of the first isolation oxide layer 160. Therefore, a first isolation oxide layer 160 can be grown on the first epitaxial layer 120 by APCVD to form the trench 121 structure. This configuration ensures that silicon nucleates only in the first epitaxial layer 120 to form the second epitaxial layer 140, avoiding the silicon dioxide surface. This precise construction of the trench 121 structure optimizes the device's electric field distribution, reduces leakage risk, and improves device stability and process controllability. It effectively optimizes the peak electric field distribution in the drift region. The flat first isolation oxide layer 160 prevents the electric field from concentrating at surface protrusions. The second epitaxial layer 140, formed by the APCVD process, has a lattice match with the first epitaxial layer 120, creating a uniform drift region structure, weakening local peak electric field intensity, and reducing electric field distortion. This reduces the risk of drift region breakdown, improves device withstand voltage performance, reduces electric field interference during current transmission, lowers leakage losses, and ensures stable device operation under high voltage conditions. This meets the core requirement of power semiconductor devices for uniform electric field distribution in the drift region, guaranteeing long-term reliable device operation.

[0053] like Figure 5 As shown, in one feasible embodiment, the step of forming the first isolation oxide layer 160 on the shielding gate 130 further includes: etching the sidewalls of the trench 121 to widen the opening before forming the oxide deposition layer 161 on the shielding gate 130 by chemical vapor deposition based on plasma silicon oxide material, so as to form the oxide deposition layer 161 on the second isolation oxide layer 150 and the shielding gate 130.

[0054] In this technical solution, by etching and widening the sidewalls of the trench 121 before depositing the oxide deposition layer 161, the internal space of the trench 121 can be effectively increased. On the one hand, this ensures that the subsequent plasma silicon oxide material uniformly covers the surface of the shielding gate 130 and the sidewalls of the trench 121, avoiding problems such as insufficient deposition and gaps caused by the trench 121 being too narrow. This significantly improves the bonding tightness between the oxide deposition layer 161 and the shielding gate 130 and the sidewalls of the trench 121, reduces interface defects, and enhances insulation performance. On the other hand, after the widening process, the coverage of the oxide deposition layer 161 is more comprehensive, which can better isolate the shielding gate 130 from the subsequent control gate 1100, avoiding signal interference. At the same time, it provides a smoother foundation for the subsequent chemical mechanical polishing of the oxide deposition layer 161, improving process consistency.

[0055] In this technical solution, the plasma-enhanced silicon oxide material possesses excellent insulation properties. The formed oxide deposition layer 161 effectively blocks the current conduction between the shielding gate 130 and the control gate 1100, preventing leakage. Simultaneously, it optimizes the internal electric field distribution of the device, reduces electric field concentration, and improves the device's withstand voltage performance. The overall process not only solves the problem of uneven oxide layer deposition within narrow trenches but also enhances the structural insulation reliability, providing a strong guarantee for the subsequent fabrication of the control gate 1100 and the overall stable performance of the device, thus meeting the long-term stable operation requirements of power devices.

[0056] It is understandable that wet etching can be used to etch and enlarge the sidewalls of the trench 121.

[0057] like Figure 6 , Figure 7 and Figure 8 As shown, in one feasible embodiment, the step of forming the first isolation oxide layer 160 on the shielding gate 130 further includes: etching away the buffer oxide layer 170 and the mask layer 180; and grinding the first isolation oxide layer 160 and the first epitaxial layer 120 using a chemical mechanical polishing process.

[0058] In this technical solution, etching to remove the buffer oxide layer 170 and the mask layer 180 can completely eliminate interference factors in subsequent processes, avoid insulation failure and signal interference caused by the residue of the buffer oxide layer 170 and the mask layer 180, ensure that the connection between the subsequent first isolation oxide layer 160 and the control gate 1100 and the well region 210 is not obstructed, and at the same time avoid impurity residues affecting the electrical performance of the device.

[0059] In this technical solution, chemical mechanical polishing is used to smooth the first isolation oxide layer 160 and the first epitaxial layer 120. This can precisely control the thickness uniformity of the first isolation oxide layer 160, avoid problems such as uneven electric field distribution and leakage caused by uneven surface, and ensure that the connection between the first isolation oxide layer 160 and the control gate 1100 and the well region 210 is tight and stable.

[0060] In this technical solution, the process not only solves the problems of uneven surface and loose interlayer bonding after traditional etching, but also ensures that the insulation performance of the first isolation oxide layer 160 meets the standards. At the same time, it provides a flat structure for the subsequent preparation of contact holes 1130 and the laying of metal layers 1140, improves the repeatability and stability of the overall process, and thus ensures that the switching performance and withstand voltage performance of semiconductor devices meet the design requirements, and is suitable for the long-term stable operation of SGT structures.

[0061] In this technical solution, the buffer oxide layer 170 can be the substrate oxide layer. Since the buffer oxide layer 170 and the silicon nitride layer 181 serve as a hard mask, the position of the first isolation oxide layer 160 has been defined. After removing the buffer oxide layer 170 and the silicon nitride layer 181, when only the first isolation oxide layer 160 and the first epitaxial layer 120 remain as the top material, the second epitaxial layer 140 grown by APCVD is selective. Due to lattice differences, SI only nucleates on the first epitaxial layer 120 to form the second epitaxial layer 140. SI cannot be formed on the SiO2 surface, thus achieving the formation of the corresponding structure without a new photomask. Saving one photomask can reduce cost expenditure. Generally, SGT requires seven photomasks. By using the fabrication method provided in this application embodiment to fabricate semiconductor devices, the cost can be saved by about 15%.

[0062] In this technical solution, the optimization of the aspect ratio of trench 121, when removing the buffer oxide layer 170 and mask layer 180 by wet etching, will expose excess oxide (OX) in the first isolation oxide layer 160. A flat shielding gate 130 isolation oxide layer can be formed by OXCMP process, which can optimize the voltage percentage of the first isolation oxide layer 160 of the entire wafer device, especially improve the uniformity of the thickness of the first isolation oxide layer 160. The formed first isolation oxide layer 160 is flatter, and the thickness difference of the first isolation oxide layer 160 of the semiconductor device is smaller. In this way, the breakdown voltage of the overall device is at a uniform level, making the device easier to uniformly control. The first isolation oxide layer 160 of each device will also be flatter. In particular, it can optimize the electric field distribution of the MOSFET-SGT device.

[0063] like Figure 9 and Figure 10 As shown, in one feasible embodiment, the method for fabricating a semiconductor device further includes: forming a dielectric layer 190 on the second epitaxial layer 140; and forming a control gate 1100 over the first isolation oxide layer 160.

[0064] In this technical solution, the dielectric layer 190 provides electrical isolation between the control gate 1100 and other structures, preventing short circuits between the control gate 1100 and other conductive structures of the semiconductor device. It also prevents external impurities and moisture from entering, protecting the control gate 1100 and the underlying first isolation oxide layer 160 and shielding gate 130 structure. This improves the device's insulation reliability, avoids leakage current, breakdown, and other faults, and provides a smooth and clean interface for the subsequent fabrication of the contact hole 1130 and metal layer 1140. As the core control structure of the device, the control gate 1100 can precisely regulate current conduction and cutoff. Combined with the previously formed shielding gate 130 structure, it optimizes the internal electric field distribution of the device, effectively reducing electric field concentration, lowering leakage current, improving the device's switching performance and operational stability, and ensuring that the device can accurately respond to control signals, meeting the operational requirements of power devices.

[0065] like Figure 11 As shown, in one feasible embodiment, the method for fabricating a semiconductor device further includes: doping the second epitaxial layer 140 to form a P-type well region 1110 and an N-type well region 1120, wherein the P-type well region 1110 and the N-type well region 1120 are located below the dielectric layer 190.

[0066] In this technical solution, by doping the second epitaxial layer 140 to form P-type well regions 1110 and N-type well regions 1120, the conductivity characteristics of the semiconductor device can be precisely controlled, providing a stable current-carrying region for current conduction. The P-type well regions 1110 and N-type well regions 1120 respectively undertake different conductivity functions, forming a reasonable electric field distribution in conjunction with the gate oxide layer, effectively avoiding leakage current and signal interference, ensuring stable switching performance of the device, and providing a structural basis for the subsequent fabrication of contact holes 1130 and metal layers 1140, ensuring that the electrical performance of the semiconductor device meets the standards, its operation is reliable, and it meets the design and usage requirements of power devices.

[0067] In some examples, the fabrication process involves first forming a P-type well region 1110 on the entire surface, then using photolithography to define and form an N-type well region 1120, implanting N-type impurities to form a PN junction, and then drilling contact holes 1130 and inserting conductive material ContactIMP into the holes.

[0068] like Figure 12 and Figure 13 As shown, in one feasible embodiment, the method for fabricating a semiconductor device further includes: forming a plurality of contact holes 1130 in a dielectric layer 190, wherein the contact holes 1130 are connected to at least one of a control gate 1100, a P-type well region 1110, or an N-type well region 1120; filling the contact holes 1130 with a conductive material; and forming a metal layer 1140 on the dielectric layer 190, wherein the metal layer 1140 is connected to the contact holes 1130.

[0069] In this technical solution, by creating contact holes 1130 in the dielectric layer 190, filling them with conductive material, and forming a metal layer 1140, a conductive path is constructed between the inside and outside of the device, enabling effective conduction of electrical signals. The contact holes 1130 precisely connect to the control gate 1100, the P-type well region 1110, or the N-type well region 1120, ensuring stable transmission of electrical signals in each functional area and avoiding problems such as poor contact and signal loss. The conductive material filling the contact holes 1130 ensures conductivity, reduces contact resistance, and improves signal transmission efficiency. The metal layer 1140 precisely mates with the contact holes 1130, leading out the internal electrical signals of the device and achieving effective connection with external circuits, providing a foundation for subsequent device power-on operation and signal control.

[0070] It is understood that the fact that the contact hole 1130 is connected to at least one of the control gate 1100, the P-type well region 1110, or the N-type well region 1120 can mean that a portion of the contact hole 1130 is connected to the control gate 1100, another portion of the contact hole 1130 is used to connect to the P-type well region 1110, and yet another portion of the contact hole 1130 is used to connect to the N-type well region 1120.

[0071] like Figure 13As shown, a field-effect transistor is provided according to a second aspect of the embodiments of this application. The field-effect transistor is fabricated based on the semiconductor device fabrication method of any of the above technical solutions.

[0072] The field-effect transistor provided in this application embodiment is fabricated based on the semiconductor device fabrication method of any of the above technical solutions. Therefore, the field-effect transistor has all the beneficial effects of the semiconductor device fabrication method of the above technical solutions, which will not be repeated here.

[0073] like Figure 13 As shown, in one feasible embodiment, the field-effect transistor includes: a substrate 110; a first epitaxial layer 120 disposed on the substrate 110, on which a trench 121 is formed; a second isolation oxide layer 150 disposed on the wall and bottom surface of the trench 121; a shielding gate 130 disposed on the second isolation oxide layer 150; a first isolation oxide layer 160 disposed on the shielding gate 130; and a second epitaxial layer 140 disposed above the first epitaxial layer 120; wherein the second isolation oxide layer 150, the shielding gate 130, and the first isolation oxide layer 160 are all located within the trench 121.

[0074] In this technical solution, the structural design of the field-effect transistor effectively optimizes the electrical performance and structural stability of the device. The substrate 110 provides stable support for the entire device. The first epitaxial layer 120 serves as the basic conductive region. The trench 121 structure, combined with the second isolation oxide layer 150, effectively isolates the shielding gate 130 from the semiconductor substrate, avoiding leakage risks. The shielding gate 130 optimizes the electric field distribution, suppresses potential concentration, and improves the device's withstand voltage performance. The first isolation oxide layer 160 further strengthens insulation protection, preventing signal interference and short circuits. The second epitaxial layer 140 works in conjunction with the first epitaxial layer 120 to achieve layered control of the device, improving structural stability. Each layer is located within the trench 121, resulting in a compact and reasonable layout. This reduces the space occupied by the device, ensures the coordinated operation of all components, reduces signal loss, improves the switching performance and operational reliability of the device, meets the requirements of power devices, and complies with semiconductor device design specifications and mass production requirements.

[0075] like Figure 13 As shown, in one feasible embodiment, the field-effect transistor further includes: a well region 210, which is formed by doping a second epitaxial layer 140; a control gate 1100 disposed on a first isolation oxide layer 160; a dielectric layer 190 disposed above the well region 210; and a metal layer 1140 disposed on the dielectric layer 190, which is connected to the well region 210 and / or the control gate 1100 through a contact hole 1130.

[0076] In this technical solution, the well region 210 is doped with the second epitaxial layer 140, which can precisely control the conductivity of the device, adapt to different current conduction requirements, and provide a stable current-carrying channel for the device. Simultaneously, it works synergistically with the control gate 1100 to optimize the electric field distribution and suppress leakage risks. The control gate 1100 is disposed on the first isolation oxide layer 160, which can precisely control the switching state of the device and achieve effective current on / off control. The dielectric layer 190 serves as insulation, preventing short circuits between the metal layer 1140 and the well region 210 and the control gate 1100, ensuring independent and stable operation of each structure. The metal layer 1140 is connected to the well region 210 and the control gate 1100 through contact holes 1130, constructing a complete conductive path to ensure efficient signal transmission and reduce signal loss.

[0077] It is understood that the well region 210 may include a P-type well region 1110 and an N-type well region 1120, and the contact hole 1130 may be filled with conductive material to ensure conductivity efficiency.

[0078] In this invention, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term "multiple" refers to two or more unless otherwise explicitly defined. The terms "install," "connect," "link," and "fix" should be interpreted broadly. For example, "connect" can be a fixed connection, a detachable connection, or an integral connection; "link" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0079] In the description of this invention, it should be understood that the terms "upper," "lower," "left," "right," "front," "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0080] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0081] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A first epitaxial layer is formed on the substrate, and a portion of the first epitaxial layer is etched to form trenches; A shielding grid is formed within the trench, and a first isolation oxide layer is prepared on the shielding grid; A second epitaxial layer is prepared on the first epitaxial layer.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of forming a shielding grid in the trench includes: A second insulating oxide layer is formed within the trench; The shielding gate is formed by filling polycrystalline silicon material onto the second isolation oxide layer. The first isolation oxide layer is located within the trench.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The step of forming the first isolation oxide layer on the shielding gate includes: An oxide deposition layer is formed on the shielding grid by chemical vapor deposition; The first isolating oxide layer is prepared by processing the oxide deposit layer with chemical mechanical polishing.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The step of forming the first isolation oxide layer on the shielding gate further includes: Prior to the step of forming an oxide deposition layer on the shielding grid by chemical vapor deposition, the sidewalls of the trench are etched to widen the opening, thereby forming the oxide deposition layer on the second isolation oxide layer and the shielding grid.

5. The method for fabricating a semiconductor device according to claim 3, characterized in that, The step of forming a first epitaxial layer on the substrate and etching a portion of the first epitaxial layer to form trenches includes: The first epitaxial layer is epitaxially grown on the substrate; A buffer oxide layer and a mask layer are formed sequentially from bottom to top on the first epitaxial layer; An etching region is defined on the mask layer using a photoresist layer; The trench is formed by etching the first epitaxial layer based on the etched area; The mask layer includes a silicon nitride layer and a silicon oxide layer.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The step of forming the first isolation oxide layer on the shielding gate further includes: Etching removes the buffer oxide layer and the mask layer; The first isolation oxide layer and the first epitaxial layer are ground smooth using a chemical mechanical polishing process.

7. The method for fabricating a semiconductor device according to any one of claims 1 to 6, characterized in that, Also includes: A dielectric layer is formed on the second epitaxial layer; A control gate is formed above the first isolation oxide layer; The second epitaxial layer is doped to form a P-type well region and an N-type well region, which are located below the dielectric layer; A plurality of contact holes are formed in the dielectric layer, and the contact holes are connected to at least one of the control gate, the P-type well region, or the N-type well region; The contact hole is filled with a conductive material; A metal layer is formed on the dielectric layer, and the metal layer is conductive to the contact hole.

8. A field-effect transistor, characterized in that, The field-effect transistor is fabricated based on the method for fabricating a semiconductor device as described in any one of claims 1 to 7.

9. The field-effect transistor according to claim 8, characterized in that, include: Substrate; A first epitaxial layer is disposed on the substrate, and a trench is formed on the first epitaxial layer; A second insulating oxide layer is disposed on the wall and bottom surfaces of the trench; A shielding grid, wherein the shielding grid is disposed on the second isolation oxide layer; A first isolation oxide layer is disposed on the shielding grid; The second epitaxial layer is disposed above the first epitaxial layer; The second isolation oxide layer, the shielding gate, and the first isolation oxide layer are all located within the trench.

10. The field-effect transistor according to claim 9, characterized in that, Also includes: A well region, wherein the well region is formed by doping the second epitaxial layer; A control gate, wherein the control gate is disposed on the first isolation oxide layer; A dielectric layer is disposed above the well region; A metal layer disposed on the dielectric layer, the metal layer being connected to the well region and / or the control gate via a contact hole.

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