semiconductor devices

Abstract

A semiconductor device includes: a substrate having a first surface and a second surface opposite to each other; an epitaxial layer located on the first surface of the substrate, including a gate trench and having a first conductivity type; a channel layer located on the inner sidewall of the gate trench and having a first conductivity type; a gate electrode located on the inner side surface of the channel layer; a gate insulating layer located on the bottom surface of the gate trench and between the channel layer and the gate electrode; a source electrode located on the epitaxial layer; and a drain electrode located on the second surface of the substrate.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2025-0018309, filed with the Korean Intellectual Property Office on February 12, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor devices. Background Technology

[0004] Semiconductor devices are typically closely intertwined with our daily lives. Power semiconductor devices, in particular, are becoming increasingly important in various sectors, such as transportation (e.g., electric vehicles, trains, and trams), renewable energy systems (e.g., solar and wind power), and mobile devices. A power semiconductor device is a semiconductor device capable of handling high voltage or high current and performs functions such as power conversion and control in large power systems and high-power electronic devices. Power semiconductor devices possess the ability and robustness to handle high power, enabling them to handle large currents and withstand high voltages. For example, power semiconductor devices can handle voltages from hundreds to thousands of volts and currents from tens to thousands of amperes. Power semiconductor devices can improve energy efficiency by reducing power losses. Furthermore, power semiconductor devices can be stably driven in environments such as high temperatures. Summary of the Invention

[0005] Power semiconductor devices can be classified according to their materials, such as silicon carbide (SiC) power semiconductor devices and gallium nitride (GaN) power semiconductor devices. SiC or GaN can be used instead of silicon (Si) wafers to fabricate power semiconductor devices, thereby compensating for the instability of silicon at high temperatures. SiC power semiconductor devices are heat-resistant and have low power loss, making them suitable for electric vehicles, renewable energy systems, etc. GaN power semiconductor devices are more expensive but faster, making them suitable for fast charging of mobile devices, etc. The disclosed embodiments provide a semiconductor device with stable electrical characteristics and improved reliability.

[0006] According to some embodiments, a semiconductor device includes: a substrate including a first surface and a second surface opposite to the first surface; an epitaxial layer on the first surface of the substrate, the epitaxial layer including a gate trench, wherein the epitaxial layer has a first conductivity type; a channel layer on the inner sidewall of the gate trench, wherein the channel layer has a first conductivity type and has a defect rate lower than that of the epitaxial layer; a gate electrode in the gate trench; a gate insulating layer on the bottom surface of the gate trench and between the channel layer and the gate electrode; a source electrode on the epitaxial layer; and a drain electrode on the second surface of the substrate.

[0007] According to some embodiments, a semiconductor device includes: a substrate including a first surface and a second surface opposite to the first surface; an epitaxial layer on the first surface of the substrate, the epitaxial layer including a gate trench, wherein the epitaxial layer has a first conductivity type; a well region on the epitaxial layer and having a second conductivity type different from the first conductivity type; a channel layer having a first conductivity type on the inner sidewall of the gate trench, wherein the channel layer has a lower defect rate than the epitaxial layer; a gate electrode in the gate trench, wherein the gate electrode extends in a first direction; a gate insulating layer between the channel layer and the gate electrode; a source electrode on the well region; and a drain electrode on the second surface of the substrate, wherein the channel layer extends in the first direction and protrudes from the lower surface of the well region toward the first surface of the substrate.

[0008] According to some embodiments, a semiconductor device includes: a substrate including a first surface and a second surface opposite to the first surface; an epitaxial layer on the first surface of the substrate including a gate trench and comprising 4H-SiC; a channel layer comprising 3C-SiC, wherein the channel layer is on the inner sidewall of the gate trench, and wherein the channel layer has a lower defect rate than the epitaxial layer; a gate electrode in the trench; a gate insulating layer between the channel layer and the gate electrode; a source electrode on the epitaxial layer; and a drain electrode on the second surface of the substrate.

[0009] According to some embodiments, a method for manufacturing a semiconductor device includes the following steps: forming an epitaxial layer having a first conductivity type on a first surface of a substrate; forming a gate trench in the epitaxial layer; forming a channel material layer having a first conductivity type in the gate trench; patterning the channel material layer to form a channel layer exposing the bottom surface of the gate trench; forming a gate insulating layer on the inner surface of the channel layer and the bottom surface of the gate trench; forming a gate electrode on the gate insulating layer; and forming a source electrode on the epitaxial layer and a drain electrode on a second surface of the substrate opposite to the first surface.

[0010] The channel layer may include the same material as the epitaxial layer.

[0011] The channel layer can have a different crystal structure than the epitaxial layer.

[0012] The channel layer may include a first material and a second material different from the first material, wherein the first material may include Si and the second material may include C.

[0013] The lower surface of the gate insulating layer can contact the epitaxial layer.

[0014] The distance between the lower surface of the gate insulating layer and the first surface of the substrate can be equal to the distance between the lower surface of the channel layer and the first surface of the substrate.

[0015] The thickness of the channel layer can be 1 / 10 to 1 / 3 of the width of the gate trench. The channel layer may include a portion whose thickness increases with the distance from the bottom surface of the gate trench.

[0016] The steps of forming the trench layer may include removing at least a portion of the trench material layer by dry etching.

[0017] The step of forming the epitaxial layer may also include the step of forming a well region within the epitaxial layer having a second conductivity type different from the first conductivity type.

[0018] The channel layer can protrude from the lower surface of the well region toward the first surface of the substrate.

[0019] The channel layer can overlap with the trap region and the epitaxial layer.

[0020] According to the implementation method, the reliability of semiconductor devices can be improved. Attached Figure Description

[0021] Figure 1 This is a cross-sectional view of a semiconductor device according to some embodiments.

[0022] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 This is a cross-sectional view of a semiconductor device according to some embodiments.

[0023] Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 and Figure 21 This is an intermediate process cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments. Detailed Implementation

[0024] In the following, various embodiments will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily implement the techniques discussed herein. This disclosure discusses many different forms of implementation, but is not limited to the embodiments described herein.

[0025] In this disclosure, parts unrelated to the description have been omitted, and throughout this specification, the same reference numerals are used for the same or similar components.

[0026] Furthermore, for ease of illustration, the dimensions and thicknesses of each component shown in the accompanying drawings are arbitrarily illustrated, and therefore this disclosure is not necessarily limited to what is shown. To clearly illustrate the various layers and regions in the drawings, their thicknesses are enlarged and shown. And in the drawings, for ease of illustration, the thicknesses of some layers and regions are exaggerated.

[0027] Furthermore, when referring to a component (such as a layer, membrane, region, or plate) as being "above" or "on top of" another component, this includes not only the case where it is "directly above" the other component, but also the case where there are other components in between. Conversely, when referring to a component as being "directly above" another component, it means that there are no other components in between. Additionally, "above" or "on top of" a reference component means being located above or below the reference component, and does not necessarily mean being "above" or "on top of" in the opposite direction of gravity.

[0028] Additionally, throughout this specification, whenever a component is referred to as "including" an assembly, it does not mean that it excludes other components, but rather that it may include other components, unless otherwise expressly stated.

[0029] Additionally, throughout this specification, when "in a plan view" is mentioned, it means when the target portion is viewed from above; when "in a cross-sectional view" is mentioned, it means when the target portion is viewed from the side of a vertically cut cross-section.

[0030] Figure 1 This is a cross-sectional view of a semiconductor device according to some embodiments.

[0031] refer to Figure 1 A semiconductor device according to some embodiments includes: a substrate 110 including a first surface 110a and a second surface 110b opposite to each other (e.g., the second surface 110b is on the side of the substrate 110 opposite to the first surface 110a); an epitaxial layer 131 located on the first surface 110a of the substrate 110 and including a gate trench 160 and having a first conductivity type; a channel layer 300 located on the inner sidewall 160_S of the gate trench 160 and having a first conductivity type; a gate electrode 150 located on the inner surface of the channel layer 300; a gate insulating layer 140 located between the channel layer 300 and the gate electrode 150 and on the bottom surface 160_B of the gate trench 160; a source electrode 173 located on the epitaxial layer 131; and a drain electrode 175 located on the second surface 110b of the substrate 110.

[0032] Substrate 110 may be a semiconductor substrate including SiC. For example, substrate 110 may be made of a 4H-SiC substrate. In some cases, substrate 110 may be made of a 3C-SiC substrate, a 6H-SiC substrate, etc. Substrate 110 may have a first conductivity type. Substrate 110 may be doped with impurities of the first conductivity type. Substrate 110 may be heavily doped with impurities of the first conductivity type. Here, the first conductivity type may be n-type, but the example embodiment is not limited thereto. The resistivity of substrate 110 may be between about 0.005 Ωcm and about 0.035 Ωcm. The thickness of substrate 110 may be from about 10 μm to about 700 μm. The material, doping type, doping concentration, resistivity, thickness, etc. of substrate 110 are not limited thereto and can be varied. Substrate 110 may include a first surface 110a and a second surface 110b opposite to each other. The first surface 110a of substrate 110 may be the upper surface, and the second surface 110b of substrate 110 may be the lower surface.

[0033] The epitaxial layer 131 may be located on the first surface 110a of the substrate 110, i.e., the upper surface. The lower surface of the epitaxial layer 131 may be in contact with the first surface 110a of the substrate 110. However, the exemplary embodiment is not limited thereto, and other layers may be additionally disposed between the substrate 110 and the epitaxial layer 131. The epitaxial layer 131 may be an epitaxial layer formed from the substrate 110 using an epitaxial growth method.

[0034] Epitaxial layer 131 may include a semiconductor material. For example, epitaxial layer 131 may include a first material and a second material different from the first material. The first material may include silicon (Si), and the second material may include carbon (C). Epitaxial layer 131 may include SiC. As an example, epitaxial layer 131 may include 4H-SiC. Epitaxial layer 131 may include SiC having a 4H hexagonal crystal structure.

[0035] Epitaxial layer 131 may have a first conductivity type. Epitaxial layer 131 may be doped with impurities of the first conductivity type. Epitaxial layer 131 may be lightly doped with impurities of the first conductivity type. Here, the first conductivity type may be n-type, but the example embodiment is not limited to this. The doping concentration of epitaxial layer 131 may be lower than the doping concentration of substrate 110. The doping concentration of epitaxial layer 131 may be approximately 1*10. 15 cm -3 Approximately 1*10 17 cm -3 The thickness of the epitaxial layer 131 can be from about 1 μm to about 13 μm. The material, doping type, doping concentration, thickness, etc. of the epitaxial layer 131 are not limited to these and can be varied.

[0036] The epitaxial layer 131 may include a gate trench 160. The gate trench 160 may be formed to have a predetermined depth. The cross-section of the gate trench 160 may be generally U-shaped. The gate trench 160 may include a bottom surface 160_B and an inner sidewall 160_S extending from the bottom surface 160_B. The inner sidewall 160_S of the gate trench 160 may be defined by the epitaxial layer 131, the well region 133 described later, and a first conductivity type doped layer 137. The bottom surface 160_B of the gate trench 160 may be defined by the epitaxial layer 131. Figure 1 In the example, the angle of the inner sidewall 160_S of the gate trench 160 relative to the bottom surface 160_B is depicted as vertical, but the example implementation is not limited to this.

[0037] The gate trench 160 may extend in a second direction (Y direction). According to some embodiments, the semiconductor device may include a plurality of gate trenches 160 extending in the second direction (Y direction). A plurality of gate trenches 160 may be provided, and the plurality of gate trenches 160 may be arranged to be spaced apart from each other in a first direction (X direction). Each of the plurality of gate trenches 160 may extend in the second direction (Y direction). Here, the second direction (Y direction) may refer to a direction intersecting the first direction (X direction). For example, the second direction (Y direction) may be orthogonal to the first direction (X direction).

[0038] The channel layer 300 may be located within the gate trench 160. The channel layer 300 may be located on the inner sidewall 160_S of the gate trench 160. For example, the channel layer 300 may be completely located on the inner sidewall 160_S of the gate trench 160. The channel layer 300 may be located on the side surface of the epitaxial layer 131 defining the inner sidewall 160_S of the gate trench 160 and on the side surface of the well region 133, which will be described later. The channel layer 300 may overlap with the epitaxial layer 131 and the well region 133, which will be described later, in a first direction (X direction), and may not overlap with the source electrode 173, which will be described later, in the first direction (X direction). The channel layer 300 may be in contact with the epitaxial layer 131 and the well region 133, which will be described later. Additionally, the channel layer 300 may be located on the side surface of the first conductivity type doped layer 137, which will be described later. The channel layer 300 may overlap with the first conductivity type doped layer 137 in a first direction (X direction), as will be described later. The channel layer 300 may contact the first conductivity type doped layer 137, as will be described later. The length of the channel layer 300 in a third direction (Z direction) may be less than or equal to the depth of the gate trench 160 in the third direction (Z direction), but the example implementation is not limited thereto. The channel layer 300 may extend in the third direction (Z direction) to the inner sidewall 160_S of the gate trench 160. The channel layer 300 may extend in a second direction (Y direction). The channel layer 300 can be used as a channel for a transistor.

[0039] The channel layer 300 may be located on the inner sidewall 160_S of the gate trench 160 and has a substantially uniform thickness TH1. Here, the thickness TH1 of the channel layer 300 may represent the thickness of the channel layer 300 in the first direction (X direction). The thickness TH1 of the channel layer 300 in the first direction (X direction) may remain constant as it moves away from the bottom surface 160_B of the gate trench 160, but the example embodiment is not limited thereto. For example, the thickness TH1 of the channel layer 300 in the first direction (X direction) may be about 1 / 10 to about 1 / 3 of the gate trench 160, but the example embodiment is not limited thereto. For example, the thickness TH1 of the channel layer 300 in the first direction (X direction) may be about 100 nm or greater, but the example embodiment is not limited thereto.

[0040] The lower surface 300_B of the channel layer 300 may be aligned with the bottom surface 160_B of the gate trench 160 and have the same boundary. The lower surface 300_B of the channel layer 300 is the surface of the channel layer 300 facing the first surface 110a of the substrate 110. That is, the lower surface 300_B of the channel layer 300 and the bottom surface 160_B of the gate trench 160 may be located at substantially the same height. The lower surface 300_B of the channel layer 300 and the bottom surface 160_B of the gate trench 160 may be located at substantially the same distance from the first surface 110a of the substrate 110. Accordingly, the lower surface 300_B of the channel layer 300 and the lower surface of the gate insulating layer 140 (described later, wherein the lower surface of the gate insulating layer 140 is the surface of the gate insulating layer 140 facing the first surface 110a of the substrate 100) may be located at substantially the same height, but the example embodiment is not limited thereto. The lower surface 300_B of the channel layer 300 and the lower surface of the gate insulating layer 140, described later, can be located at substantially the same distance from the first surface 110a of the substrate 110. The distance between the lower surface of the gate insulating layer and the first surface of the substrate can be equal to the distance between the lower surface of the channel layer and the first surface of the substrate. However, the exemplary embodiment is not limited to this, and the channel layer 300 may be located only on a portion of the inner sidewall 160_S of the gate trench 160. In this case, the lower surface 300_B of the channel layer 300 may be located at a height higher than the bottom surface 160_B of the gate trench 160. Reference will be made later. Figure 4 This will be described.

[0041] The channel layer 300 may protrude from the lower surface of the well region 133, which will be described later, toward the first surface 110a of the substrate 110. The lower surface 300_B of the channel layer 300 may be located at a lower height than the lower surface of the well region 133. The lower surface 300_B of the channel layer 300 may be located closer to the first surface 110a of the substrate 110 than the lower surface of the well region 133.

[0042] The upper surface of the channel layer 300 may be located at substantially the same height as the upper surface of the first conductivity type doped layer 137, which will be described later. The upper surface of the channel layer 300 and the upper surface of the first conductivity type doped layer 137, which will be described later, may be located at substantially the same distance from the first surface 110a of the substrate 110. The upper surface of the channel layer 300 may be located at substantially the same height as the upper surface of the second conductivity type doped layer 139, which will be described later. The upper surface of the channel layer 300 and the upper surface of the gate electrode 150, which will be described later, may be located at substantially the same distance from the first surface 110a of the substrate 110. The upper surface of the channel layer 300 and the upper surface of the gate insulating layer 140, which will be described later, may be located at substantially the same distance from the first surface 110a of the substrate 110.

[0043] The channel layer 300 may not be located on at least a portion of the bottom surface 160_B of the gate trench 160. For example, the channel layer 300 extends in a third direction (Z direction) such that the lower surface 300_B can contact the bottom surface 160_B of the gate trench 160. In this case, the channel layer 300 may not overlap with the gate electrode 150 in the third direction (Z direction), as described later. However, the exemplary embodiment is not limited thereto; as another example, the channel layer 300 may be located entirely on the bottom surface 160_B of the gate trench 160. Reference will be made later. Figure 11 This will be described.

[0044] The channel layer 300 may be an epitaxial layer formed from the epitaxial layer 131 using an epitaxial growth method. For example, the channel layer 300 may be an epitaxial layer grown from a portion of the epitaxial layer 131 exposed by the inner sidewall 160_S of the gate trench 160. The channel layer 300 may include a semiconductor material. The channel layer 300 may include the same material as the epitaxial layer 131. For example, the channel layer 300 may include a first material and a second material different from the first material. The first material may include silicon (Si), and the second material may include carbon (C). For example, the channel layer 300 may include SiC.

[0045] The channel layer 300 may have a different crystal structure than the epitaxial layer 131. For example, the channel layer 300 may include 3C-SiC. The channel layer 300 may include SiC having a 3C cubic crystal structure. Conversely, the epitaxial layer 131 may include 4H-SiC. The epitaxial layer 131 may include SiC having a 4H hexagonal crystal structure. The channel layer 300 may include a material with a different band gap than the epitaxial layer 131. For example, the band gap of the material constituting the channel layer 300 may be smaller than the band gap of the material constituting the epitaxial layer 131.

[0046] The content (atomic percentage) of the first material in the channel layer 300 can be substantially the same as the content (atomic percentage) of the first material in the epitaxial layer 131, but the example embodiment is not limited thereto. The first material may include silicon (Si), and the second material may include carbon (C). The channel layer 300 may have the same conductivity type as the epitaxial layer 131. The channel layer 300 may have a first conductivity type. The channel layer 300 may be doped with impurities of the first conductivity type. The channel layer 300 may be lightly doped with impurities of the first conductivity type. Here, the first conductivity type may be n-type, but the example embodiment is not limited thereto. The doping concentration of the channel layer 300 may be lower than the doping concentration of the substrate 110. The doping concentration of the channel layer 300 may be approximately 1*102 15 cm -3 Or higher, and approximately 1*10 17 cm -3 Or even lower. The material, doping type, doping concentration, etc. of the channel layer 300 are not limited to this, and can be changed in various ways.

[0047] In some embodiments, during the process of forming the gate trench 160 by etching at least a portion of the epitaxial layer 131, defects may occur in portions of the epitaxial layer 131 defining the inner sidewall 160_S of the gate trench 160 and in portions of the epitaxial layer 131 defining the bottom surface 160_B of the gate trench 160. According to some embodiments, the semiconductor device may include a channel layer 300 comprising the same material as the epitaxial layer 131 and having a different crystal structure on the inner sidewall 160_S of the gate trench 160. The channel layer 300 may include a material with a lower defect rate than the epitaxial layer 131. For example, the channel layer 300 may include 3C-SiC, which has a lower defect rate than the epitaxial layer 131, while the epitaxial layer 131 may include 4H-SiC in some embodiments. Accordingly, even if defects occur in at least a portion of the epitaxial layer 131 during the process of forming the gate trench 160, the reliability of the semiconductor device can be improved according to some embodiments because the channel layer 300 has a relatively low defect rate.

[0048] Meanwhile, in semiconductor devices according to some embodiments, when a channel layer 300 is formed on the surface of the epitaxial layer 131, defects may occur in a portion of the channel layer 300 depending on the crystal plane of the grown channel layer 300. For example, when a channel material layer is formed within the gate trench 160 (see... Figure 16 In the case of 300P, it may be at the point where the bottom surface 160_B of the gate trench 160 intersects with the inner sidewall 160_S (see Figure 16 The channel material layer formed by a1) (see a1) Figure 16A portion of the 300P), at the point where the inner sidewall 160_S of the gate trench 160 intersects with the upper surface of the first conductivity type doped layer 137 (see [reference]). Figure 16 The channel material layer formed by a2) (see a2) Figure 16 A portion of the 300P) and a channel material layer formed on the bottom surface 160_B of the gate trench 160 (see [reference]). Figure 16 A defect appears in a portion of the 300P. According to some embodiments, this is achieved by forming a channel material layer (see...). Figure 16 After etching the channel material layer (see 300P), the channel material layer is then etched (see 300P). Figure 16 At least a portion of the 300P semiconductor device can form a channel layer 300. In this process, defects appearing in the channel layer 300 can be removed, thereby improving the reliability of the semiconductor device.

[0049] Gate electrode 150 may be located within gate trench 160. Gate electrode 150 may extend in a second direction (Y direction). Gate electrode 150 may be spaced apart from epitaxial layer 131. Gate electrode 150 may be spaced apart from epitaxial layer 131 at a substantially constant pitch. However, the exemplary embodiment is not limited thereto, and the distance between gate electrode 150 and epitaxial layer 131 may vary depending on the position. The cross-sectional shape of gate electrode 150 may be similar to, but is not limited to, gate trench 160. See description therein. Figure 3 exist Figure 2 As given in the document, as described below.

[0050] The gate electrode 150 may be spaced apart from the channel layer 300 in a first direction (X direction). The gate electrode 150 may be spaced apart from the channel layer 300 at a substantially constant distance. However, the exemplary embodiments are not limited thereto, and the distance between the gate electrode 150 and the channel layer 300 may vary depending on the position.

[0051] The gate electrode 150 may include a lower surface and a side surface extending from the lower surface. The gate electrode 150 may also include an upper surface opposite the lower surface, and the side surface may be connected between the lower and upper surfaces. The lower surface of the gate electrode 150 may face the bottom surface 160_B of the gate trench 160. The side surface of the gate electrode 150 may face the inner surface of the channel layer 300. The lower surface of the gate electrode 150 may be located at a height higher than the lower surface 300_B of the channel layer 300. The lower surface of the gate electrode 150 may be located further away from the first surface 110a of the substrate 110 than the lower surface 300_B of the channel layer 300.

[0052] The gate electrode 150 may include a conductive material. For example, the gate electrode 150 may include polycrystalline silicon doped with impurities. As another example, the gate electrode 150 may include a metal, a metal alloy, a metal silicide, a doped semiconductor material, a conductive metal oxide, a conductive metal nitride, or a combination thereof. The gate electrode 150 may be formed of a single layer or multiple layers.

[0053] A gate insulating layer 140 may be located between the channel layer 300 and the gate electrode 150. The gate insulating layer 140 may be located on the inner surface of the channel layer 300. The gate insulating layer 140 may cover the side surface of the gate electrode 150. The gate insulating layer 140 may contact the channel layer 300. Additionally, the gate insulating layer 140 may be located on the bottom surface 160_B of the gate trench 160. The gate insulating layer 140 may be located between the epitaxial layer 131 and the gate electrode 150. The gate insulating layer 140 may be located below the gate electrode 150 and may cover the lower surface of the gate electrode 150. The lower surface of the gate insulating layer 140 may contact the epitaxial layer 131. The gate electrode 150 may be insulated from the epitaxial layer 131 and the channel layer 300 by the gate insulating layer 140. The gate electrode 150 may be surrounded by the gate insulating layer 140. The gate insulating layer 140 may be located on the bottom surface 160_B of the gate trench 160 and the inner surface of the channel layer 300 with a substantially uniform thickness, but the example implementation is not limited thereto.

[0054] The lower surface of the gate insulating layer 140 may be located at substantially the same height as the lower surface 300_B of the channel layer 300. The lower surface of the gate insulating layer 140 and the lower surface 300_B of the channel layer 300 may be located at substantially the same distance from the first surface 110a of the substrate 110. The distance between the lower surface of the gate insulating layer and the first surface of the substrate may be equal to the distance between the lower surface of the channel layer and the first surface of the substrate. The lower surface of the gate insulating layer 140 may be located at a lower height than the lower surface of the gate electrode 150. The lower surface of the gate insulating layer 140 may be located closer to the first surface 110a of the substrate 110 than the lower surface of the gate electrode 150.

[0055] According to some embodiments, the gate insulating layer 140 of the semiconductor device may include a first portion 140_P1 located on the inner surface of the channel layer 300 and a second portion 140_P2 located on the bottom surface 160_B of the gate trench 160.

[0056] The first portion 140_P1 may extend in the third direction (Z direction). The first portion 140_P1 may extend parallel to the channel layer 300. The first portion 140_P1 may be located between the channel layer 300 and the gate electrode 150. The first portion 140_P1 may contact the inner surface of the channel layer 300 and the side surface of the gate electrode 150. The first portion 140_P1 may refer to the portion of the gate insulating layer 140 located between the channel layer 300 and the gate electrode 150 and extending in the third direction (Z direction).

[0057] The upper surface of the first portion 140_P1 may be located at substantially the same height as the upper surface of the channel layer 300. The upper surface of the first portion 140_P1 and the upper surface of the channel layer 300 may be located at substantially the same distance from the first surface 110a of the substrate 110. Additionally, the upper surface of the first portion 140_P1 may be located at substantially the same height as the upper surface of the first conductivity type doped layer 137, which will be described later. The upper surface of the first portion 140_P1 and the upper surface of the first conductivity type doped layer 137, which will be described later, may be located at substantially the same distance from the first surface 110a of the substrate 110.

[0058] The second portion 140_P2 may be located on the bottom surface 160_B of the gate trench 160. The second portion 140_P2 may be conformally located on the bottom surface 160_B of the gate trench 160. The second portion 140_P2 may extend in a first direction (X direction). The second portion 140_P2 may be connected to the first portion 140_P1. The second portion 140_P2 may refer to the portion of the gate insulating layer 140 located on the bottom surface 160_B of the gate trench 160. The thickness of the second portion 140_P2 along the third direction (Z direction) may be substantially the same as the thickness of the first portion 140_P1 along the first direction (X direction), but the exemplary embodiment is not limited thereto. For example, the thickness of the second portion 140_P2 along the third direction (Z direction) may be greater than the thickness of the first portion 140_P1 along the first direction (X direction). Reference will be made later. Figure 8 This will be described.

[0059] The gate insulating layer 140 may include an insulating material. For example, the gate insulating layer 140 may include silicon oxide (SiO2). However, the example embodiments are not limited to this, and the material of the gate insulating layer 140 may be varied in various ways. As another example, the gate insulating layer 140 may include SiN, SiON, SiC, SiCN, or combinations thereof. In some embodiments, the gate insulating layer 140 may also include certain elements. For example, the gate insulating layer 140 may include carbon (C), nitrogen (N), or combinations thereof. For example, the gate insulating layer 140 may be composed of silicon oxide (SiO2) containing carbon (C) and nitrogen (N). The gate insulating layer 140 may be formed as a single layer or multiple layers.

[0060] According to some embodiments, the semiconductor device may also include a capping layer 142 located on the gate electrode 150.

[0061] Capping layer 142 may cover the upper surface of gate electrode 150. Additionally, capping layer 142 may cover at least a portion of channel layer 300, gate insulating layer 140 adjacent to gate electrode 150, and first conductivity type doped layer 137, described later. Capping layer 142 may be located between source electrodes 173, described later. The thickness of capping layer 142 along the third direction (Z direction) may be almost constant. However, the example embodiment is not limited to this, and the thickness of capping layer 142 in the third direction (Z direction) may gradually decrease from the center of capping layer 142 towards the opposite edge. The thickness of capping layer 142 may differ from the thickness of gate insulating layer 140. For example, the thickness of capping layer 142 may be greater than the thickness of gate insulating layer 140. In some cases, the thickness of capping layer 142 may be similar to the thickness of gate insulating layer 140.

[0062] Capping layer 142 may include an insulating material. For example, capping layer 142 may include SiO2, SiOP, SiN, SiON, or combinations thereof. However, the exemplary embodiments are not limited thereto, and the material of capping layer 142 may be varied in various ways. Capping layer 142 may be formed as a single layer or multiple layers. Capping layer 142 may include the same material as gate insulating layer 140, or it may include a different material. When capping layer 142 is made of the same material as gate insulating layer 140, the boundary between capping layer 142 and gate insulating layer 140 may not be clearly distinguishable at the contact points.

[0063] The source electrode 173 may be located on the epitaxial layer 131. The source electrode 173 may be located on the upper surface of the first conductivity type doped layer 137 and the upper surface of the second conductivity type doped layer 139, which will be described later.

[0064] The source electrode 173 may be spaced apart from the gate trench 160. For example, the source electrode 173 may be spaced apart from the gate trench 160 in a first direction (X direction). The source electrode 173 may be spaced apart from the channel layer 300 in the first direction (X direction). The source electrode 173 may not overlap with the gate trench 160 and the gate electrode 150 in a third direction (Z direction). The source electrode 173 may not overlap with the channel layer 300 in a third direction (Z direction).

[0065] The source electrode 173 may include a conductive material. For example, the source electrode 173 may include a metal, a metal alloy, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal nitride. For example, the source electrode 173 may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (WN), etc. The source electrode 173 may be formed of aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof, but the exemplary embodiments are not limited thereto. The source electrode 173 may be formed of a single layer or multiple layers.

[0066] According to some embodiments, the semiconductor device may also include a well region 133 located on the epitaxial layer 131.

[0067] Well region 133 may be located on epitaxial layer 131. Well region 133 may be located between epitaxial layer 131 and source electrode 173. Well region 133 may be located on the portion of epitaxial layer 131 adjacent to gate trench 160. Well region 133 may face gate insulating layer 140, with channel layer 300 between well region and gate insulating layer. Well region 133 may be spaced apart from gate insulating layer 140 in a first direction (X direction). Well region 133 may contact channel layer 300, but the exemplary embodiment is not limited thereto.

[0068] Well region 133 may be conformally located on epitaxial layer 131. Well region 133 may be an epitaxial layer formed from epitaxial layer 131 using an epitaxial growth method. Alternatively, well region 133 may be a doped region formed within epitaxial layer 131 using an ion implantation process.

[0069] Well region 133 may include a semiconductor material. For example, well region 133 may include a first material and a second material different from the first material. The first material may include silicon (Si), and the second material may include carbon (C). Well region 133 may include SiC. As an example, well region 133 may include 4H-SiC. Well region 133 may have a second conductivity type different from the first conductivity type. Well region 133 may be doped with impurities of the second conductivity type. Well region 133 may be lightly doped with impurities of the second conductivity type. Here, the second conductivity type may be p-type, but the example embodiment is not limited to this. The doping concentration in well region 133 may be approximately 1*10⁻⁶. 17 cm -3 Approximately 1*10 19 cm -3 The thickness of well region 133 can be about 0.3 μm or greater, and about 1.1 μm or less, but the example implementation is not limited thereto. The material, doping type, doping concentration, thickness, etc. of well region 133 are not limited thereto, and can be varied in various ways.

[0070] According to some embodiments, the semiconductor device may further include a first conductivity type doped layer 137 and a second conductivity type doped layer 139 located on the well region 133.

[0071] The first conductivity type doped layer 137 may be located on the epitaxial layer 131. The first conductivity type doped layer 137 may be located on the well region 133. The first conductivity type doped layer 137 may be located between the well region 133 and the source electrode 173.

[0072] The first conductivity type doped layer 137 may be located on opposite sides of the gate trench 160 along the first direction (X direction). The gate trench 160 may be located between the first conductivity type doped layers 137 spaced apart from each other along the first direction (X direction). The first conductivity type doped layer 137 may not overlap with the gate trench 160 in the third direction (Z direction). The first conductivity type doped layer 137 may not overlap with the channel layer 300 in the third direction (Z direction). The side surface of the first conductivity type doped layer 137 may contact the channel layer 300, but the exemplary embodiment is not limited thereto. The first conductivity type doped layer 137 may not cover the gate trench 160.

[0073] The first conductivity type doped layer 137 may face the gate insulating layer 140, and the channel layer 300 is located between the first conductivity type doped layer and the gate insulating layer. The side surface of the first conductivity type doped layer 137 facing the gate insulating layer 140 may be located on the same boundary as the sidewall of the gate trench 160. The lower surface of the first conductivity type doped layer 137 may contact the well region 133, while the upper surface of the first conductivity type doped layer 137 may contact the metal silicide layer 191 (or the source electrode 173). The source electrode 173 and the metal silicide layer 191 may have ohmic contact with the first conductivity type doped layer 137.

[0074] The region within the first conductivity type doped layer 137 that contacts the metal silicide layer 191 can be doped at a relatively higher concentration than other regions. However, the exemplary embodiment is not limited to this, and another layer may be disposed between the first conductivity type doped layer 137 and the source electrode 173. At least a portion of the upper surface of the first conductivity type doped layer 137 may be covered by the capping layer 142, but the exemplary embodiment is not limited to this.

[0075] The first conductivity type doped layer 137 may be a doped region formed within the well region 133 using an ion implantation process. The first conductivity type doped layer 137 may include a semiconductor material. For example, the first conductivity type doped layer 137 may include a first material and a second material different from the first material. The first material may include silicon (Si), and the second material may include carbon (C). The first conductivity type doped layer 137 may include SiC. As an example, the first conductivity type doped layer 137 may include 4H-SiC. The first conductivity type doped layer 137 may have a first conductivity type. The first conductivity type doped layer 137 may be doped with a first conductivity type impurity. The first conductivity type doped layer 137 may be heavily doped with a first conductivity type impurity. Here, the first conductivity type may be n-type, but the example embodiment is not limited to this. The doping concentration of the first conductivity type doped layer 137 may be greater than the doping concentration of the epitaxial layer 131. The doping concentration of the first conductivity type doped layer 137 may be approximately 1*102 18 cm -3 Or higher, and approximately 5*10 20 cm -3 Or even lower. The thickness of the first conductivity type doped layer 137 can be about 0.1 μm or more, and about 0.5 μm or less. The material, doping type, doping concentration, etc. of the first conductivity type doped layer 137 are not limited thereto, and can be changed in various ways.

[0076] The second conductivity type doped layer 139 may be located on the well region 133. The second conductivity type doped layer 139 may be located between the well region 133 and the source electrode 173.

[0077] In some embodiments, the second conductivity type doped layer 139 may be located on one side of the first conductivity type doped layer 137. For example, the second conductivity type doped layer 139 may be located on one side of the first conductivity type doped layer 137 along a first direction (X direction). That is, the first conductivity type doped layer 137 may be located between the second conductivity type doped layer 139 and the channel layer 300. The second conductivity type doped layer 139 may be spaced apart from the gate trench 160 in the first direction (X direction). The second conductivity type doped layer 139 may be spaced apart from the channel layer 300 in the first direction (X direction).

[0078] The second conductivity type doped layer 139 may be located in the same layer as the first conductivity type doped layer 137. The upper surface of the second conductivity type doped layer 139 may be at substantially the same height as the upper surface of the first conductivity type doped layer 137. The upper surfaces of the second conductivity type doped layer 139 and the first conductivity type doped layer 137 may be located at substantially the same distance from the first surface 110a of the substrate 110. The lower surface of the second conductivity type doped layer 139 may be located at a lower height than the lower surface of the first conductivity type doped layer 137, but the example embodiment is not limited thereto. The lower surface of the second conductivity type doped layer 139 may be closer to the first surface 110a of the substrate 110 than the lower surface of the first conductivity type doped layer 137, but the example embodiment is not limited thereto.

[0079] The second conductivity type doped layer 139 may be a doped region formed within the epitaxial layer 131 using an ion implantation process. The second conductivity type doped layer 139 may include a semiconductor material. For example, the second conductivity type doped layer 139 may include a first material and a second material different from the first material. The first material may include silicon (Si), and the second material may include carbon (C). The second conductivity type doped layer 139 may include SiC. As an example, the second conductivity type doped layer 139 may include 4H-SiC. The second conductivity type doped layer 139 may have a second conductivity type. The second conductivity type doped layer 139 may be doped with a second conductivity type impurity. The second conductivity type doped layer 139 may be heavily doped with a second conductivity type impurity. Here, the second conductivity type may be p-type, but the example embodiment is not limited to this. The doping concentration of the second conductivity type doped layer 139 may be greater than the doping concentration of the well region 133. The doping concentration of the second conductivity type doped layer 139 may be approximately 1*10⁻⁶. 18 cm -3 Or higher, and approximately 5*10 20 cm -3 Or even lower. The material, doping type, doping concentration, etc. of the second conductivity type doped layer 139 are not limited to this, and can be changed in various ways.

[0080] According to some embodiments, the semiconductor device may further include a metal silicide layer 191 located between the source electrode 173 and the well region 133. For example, the metal silicide layer 191 may be located between the first conductivity type doped layer 137 and the source electrode 173, and between the second conductivity type doped layer 139 and the source electrode 173. The first conductivity type doped layer 137 and the source electrode 173, as well as the second conductivity type doped layer 139 and the source electrode 173, can be smoothly electrically connected through the metal silicide layer 191. The metal silicide layer 191 may contact the first conductivity type doped layer 137, the second conductivity type doped layer 139, and the source electrode 173, but the example embodiments are not limited thereto.

[0081] Drain electrode 175 may be located on the second surface 110b (i.e., the lower surface) of substrate 110. The upper surface of drain electrode 175 may contact the second surface 110b of substrate 110. Drain electrode 175 may have an ohmic contact with substrate 110. The region within substrate 110 in contact with drain electrode 175 may be doped at a relatively higher concentration than other regions. However, the exemplary embodiment is not limited to this, and additional layers may be additionally formed between drain electrode 175 and substrate 110. For example, an additional silicide layer may be formed between drain electrode 175 and substrate 110. Drain electrode 175 and substrate 110 may be smoothly electrically connected via the silicide layer.

[0082] The drain electrode 175 may include a conductive material. For example, the drain electrode 175 may include a metal, a metal alloy, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal nitride. The drain electrode 175 may be made of the same material as the source electrode 173, or it may be made of a different material. The drain electrode 175 may be formed as a single layer or multiple layers.

[0083] According to some embodiments, the semiconductor device may be an n-type field-effect transistor (n-FET). However, the example embodiments are not limited thereto, and according to some embodiments, the semiconductor device may be a p-type field-effect transistor (p-FET). In this case, the substrate 110, the epitaxial layer 131, and the first conductivity type doped layer 137 may be doped with p-type, while the well region 133 may be doped with n-type.

[0084] According to some embodiments, a semiconductor device is described having a structure in which a gate electrode 150 is located within a gate trench 160 and a source electrode 173 is located in a layer above the gate electrode 150, but the example embodiments are not limited thereto. For example, according to some embodiments, the semiconductor device may include a gate electrode 150 located within a gate trench 160 and a source trench located adjacent to one side of the gate trench 160 (see [link to relevant documentation]). Figure 12 Source electrode 173 within (400). See below for further details. Figure 12This will be described in more detail. As another example, according to some embodiments, the semiconductor device may have a gate electrode 150 located on the upper surface of the epitaxial layer 131, and a source electrode 173 located between the gate electrode 150 and the epitaxial layer 131. As another example, according to some embodiments, the semiconductor device may include a Si IGBT (Insulated Gate Bipolar Transistor) structure. As another example, according to some embodiments, the semiconductor device may include a superjunction structure in which the p-type and n-type regions are completely depleted, thereby forming a two-dimensional uniform electric field distribution.

[0085] In the following text, reference will be made to Figures 2 to 12 Describes a semiconductor device according to some implementation methods.

[0086] Figures 2 to 12 This is a cross-sectional view of a semiconductor device according to some embodiments.

[0087] Figures 2 to 12 It shows Figure 1 Various modifications of semiconductor devices according to some implementation methods are shown. Figures 2 to 12 The implementation methods shown are the same as Figure 1 The embodiments shown are essentially the same, therefore their descriptions will be omitted, and the differences will be mainly explained. Additionally, the same reference numerals are used for components that are the same as in the previous embodiments.

[0088] refer to Figures 2 to 4 According to some embodiments, the channel layer 300 of the semiconductor device can have various shapes. The inner surface of the channel layer 300 can have a shape that slopes from the inner sidewall 160_S of the gate trench 160. For example, as Figure 2 and Figure 3 As shown, the channel layer 300 may include a portion whose thickness increases with distance from the bottom surface 160_B of the gate trench 160. The thickness of the channel layer 300 in the first direction (X direction) may increase with distance from the bottom surface 160_B of the gate trench 160. As another example, the channel layer 300 may include a portion whose thickness decreases with distance from the bottom surface 160_B of the gate trench 160. As another example, the channel layer 300 may include a recess toward the well region 133. This can be achieved by forming a channel material layer within the gate trench 160 (see [link to documentation]). Figure 16 After removing the channel material layer (see 300P in the middle) Figure 16 The structure is formed during the process of forming at least a portion of the channel layer 300 (300P). As another example, such as Figure 4As shown, the thickness of the channel layer 300 in the first direction (X direction) can decrease as it moves away from the bottom surface 160_B of the gate trench 160. The length of the channel layer 300 in the third direction (Z direction) can be less than the depth of the gate trench 160 in the third direction (Z direction), but the example embodiment is not limited thereto. The lower surface 300_B of the channel layer 300 and the bottom surface 160_B of the gate trench 160 can be located at substantially the same distance from the first surface 110a of the substrate 110. However, the example embodiment is not limited thereto; in some embodiments, the length of the channel layer 300 of the semiconductor device in the third direction (Z direction) can be less than the depth of the gate trench 160 in the third direction (Z direction).

[0089] In some embodiments, the side surface of the gate electrode 150 may have a shape that slopes from the inner sidewall 160_S of the gate trench 160. For example, as Figure 4 As shown, the thickness of the channel layer 300 in the first direction (X direction) can increase as it moves away from the bottom surface 160_B of the gate trench 160. This is likely due to the process characteristics of filling the channel layer 300 and forming the gate insulating layer 140 and the gate electrode 150 in the remaining portion of the gate trench 160.

[0090] However, the example implementation is not limited to this, such as Figure 2 As shown, the side surface of the gate electrode 150 may not extend in a direction parallel to the inner sidewall 160_S of the gate trench 160. This is because the gate insulating layer 140 is not uniformly formed within a space having an inverted conical shape, as the channel layer 300 includes a portion whose thickness increases with distance from the bottom surface 160_B of the gate trench 160.

[0091] refer to Figure 5 According to some embodiments, the epitaxial layer 131 of the semiconductor device may also include a groove 165 recessed from the bottom surface 160_B of the gate trench 160.

[0092] The recess 165 can be configured to have a predetermined depth from the bottom surface 160_B of the gate trench 160. The recess 165 can be recessed from the bottom surface 160_B of the gate trench 160 toward the first surface 110a of the substrate 110. The recess 165 can be located between the channel layers 300 on the inner sidewalls 160_S of the gate trench 160. The recess 165 can be formed to have a generally U-shaped cross-section. The bottom surface 165_B of the recess 165 can be defined by the epitaxial layer 131. The bottom surface 165_B of the recess 165 can be located at a height lower than the bottom surface 160_B of the gate trench 160. The bottom surface 165_B of the recess 165 can be located closer to the first surface 110a of the substrate 110 than the bottom surface 160_B of the gate trench 160. The bottom surface 165_B of the recess 165 can be located at a height lower than the lower surface 300_B of the channel layer 300. The bottom surface 165_B of the recess 165 can be located closer to the first surface 110a of the substrate 110 than the lower surface 300_B of the channel layer 300. The recess 165 may not overlap with the channel layer 300 in the third direction (Z direction). The recess 165 can be formed during the process of forming the channel layer 300 by removing the channel material layer within the gate trench 160 (see...). Figure 16 The space formed by removing at least a portion of the epitaxial layer 131 that constitutes the bottom surface 160_B of the gate trench 160 (300P).

[0093] In some embodiments, the gate insulating layer 140 may be located within a recess 165. The gate insulating layer 140 and / or the gate electrode 150 may fill the recess 165. The gate insulating layer 140 may protrude from the lower surface 300_B of the channel layer 300 toward the first surface 110a of the substrate 110. The lower surface of the gate insulating layer 140 may be located at a height lower than the lower surface 300_B of the channel layer 300. The lower surface of the gate insulating layer 140 may be located closer to the first surface 110a of the substrate 110 than the lower surface 300_B of the channel layer 300.

[0094] like Figure 6 And refer to Figure 7 According to some embodiments, the gate trench 160 of the semiconductor device may have a trapezoidal cross-section. The width of the gate trench 160 in the first direction (X direction) may increase as it moves away from the first surface 110a of the substrate 110. The angle between the inner sidewall 160_S of the gate trench 160 and the bottom surface 160_B may be an obtuse angle, but the example embodiments are not limited thereto.

[0095] In some embodiments, the channel layer 300 may be located on the inner sidewall 160_S of the gate trench 160. For example, as Figure 6As shown, the channel layer 300 can be located on the inner sidewall 160_S of the gate trench 160 with a substantially uniform thickness. The thickness of the channel layer 300 in the first direction (X direction) can be constant. The angle between the inner surface of the channel layer 300 and the bottom surface 160_B of the gate trench 160 can be an obtuse angle. As another example, as Figure 7 As shown, the thickness of the channel layer 300 in the first direction (X direction) can decrease as it moves away from the bottom surface 160_B of the gate trench 160. The angle between the inner surface of the channel layer 300 and the bottom surface 160_B of the gate trench 160 can be vertical, but the example embodiment is not limited to this. The lower surface 300_B of the channel layer 300 and the bottom surface 160_B of the gate trench 160 can be located at substantially the same distance from the first surface 110a of the substrate 110.

[0096] refer to Figure 8 According to some embodiments, the gate insulating layer 140 of the semiconductor device may include portions with different thicknesses. For example, the thickness TH3 of the second portion 140_P2 of the gate insulating layer 140 along the third direction (Z direction) may be greater than the thickness TH2 of the first portion 140_P1 along the first direction (X direction). The distance between the epitaxial layer 131 and the gate electrode 150 in the third direction (Z direction) may be greater than the distance between the channel layer 300 and the gate electrode 150 in the first direction (X direction). Accordingly, the electric field formed by the drain electrode 175 and / or the epitaxial layer 131 can be prevented from concentrating on the gate electrode 150, and the breakdown voltage of the semiconductor device according to this embodiment can be improved.

[0097] like Figure 9 And refer to Figure 10 According to some embodiments, the semiconductor device may also include a shielding pattern 350 located between the epitaxial layer 131 and the gate insulating layer 140.

[0098] The shielding pattern 350 may be located on the epitaxial layer 131. The shielding pattern 350 may be located below the gate trench 160. The shielding pattern 350 may be located between the epitaxial layer 131 and the gate insulating layer 140. The shielding pattern 350 may be located between the epitaxial layer 131 and the channel layer 300. For example, the shielding pattern 350 may be located between the outer surface of the channel layer 300 and the epitaxial layer 131, and between the lower surface of the channel layer 300 and the epitaxial layer 131. The shielding pattern 350 may surround at least a portion of the channel layer 300. The shielding pattern 350 may intersect with the channel layer 300, but the exemplary embodiments are not limited thereto. The shielding pattern 350 may be located below the gate trench 160. For example, as... Figure 9As shown, the shielding pattern 350 can be completely located below the gate trench 160. In this case, the bottom surface 160_B of the gate trench 160 can be defined by the shielding pattern 350. As another example, as Figure 10 As shown, the shielding pattern 350 may be located below at least a portion of the gate trench 160. In this case, the bottom surface 160_B of the gate trench 160 may be defined by the shielding pattern 350 and the epitaxial layer 131.

[0099] The shielding pattern 350 may include a semiconductor material. For example, the shielding pattern 350 may include a first material and a second material different from the first material. The first material may include silicon (Si), and the second material may include carbon (C). The shielding pattern 350 may include SiC. As an example, the shielding pattern 350 may include 4H-SiC. The shielding pattern 350 may have a second conductivity type different from the first conductivity type. The shielding pattern 350 may be doped with impurities of the second conductivity type. Here, the second conductivity type may be p-type, but the example embodiment is not limited thereto. The material, doping type, doping concentration, thickness, etc., of the shielding pattern 350 are not limited thereto and can be changed in various ways. The shielding pattern 350 can prevent the breakdown voltage of the transistor from decreasing due to the electric field generated by the voltage applied to the gate electrode 150. Accordingly, according to this embodiment, the reliability of the semiconductor device can be improved.

[0100] refer to Figure 11 According to some embodiments, the channel layer 300 of the semiconductor device may be located on the inner sidewall 160_S and the bottom surface 160_B of the gate trench 160. For example, the channel layer 300 may include a vertical portion 300_V extending along the inner sidewall 160_S of the gate trench 160 and a horizontal portion 300_H extending along the bottom surface 160_B of the gate trench 160.

[0101] The vertical portion 300_V may extend in the third direction (Z direction). The vertical portion 300_V may be located between the gate insulating layer 140 and the first conductivity type doped layer 137, between the gate insulating layer 140 and the well region 133, and between the gate insulating layer 140 and the epitaxial layer 131. The vertical portion 300_V may overlap with the first conductivity type doped layer 137, the well region 133, and the epitaxial layer 131 in the first direction (X direction). The vertical portion 300_V may contact the first conductivity type doped layer 137, the well region 133, and the epitaxial layer 131, but the example embodiment is not limited thereto.

[0102] The horizontal portion 300_H may extend in a first direction (X direction). The horizontal portion 300_H may be located on a portion of the epitaxial layer 131 constituting the bottom surface 160_B of the gate trench 160. The horizontal portion 300_H may be connected to the vertical portion 300_V. The horizontal portion 300_H may be located between the gate insulating layer 140 and the epitaxial layer 131. The horizontal portion 300_H may overlap with the gate electrode 150 in a third direction (Z direction). The thickness of the vertical portion 300_V in the third direction (Z direction) may be greater than or equal to the thickness of the horizontal portion 300_H in the first direction (X direction), but the example implementation is not limited thereto. As another example, the thickness of the horizontal portion 300_H along the third direction (Z direction) may be less than the thickness of the vertical portion 300_V along the first direction (X direction). The horizontal portion 300_H may be a channel material layer located on the bottom surface 160_B of the gate trench 160 (see [link to documentation]). Figure 16 Part of the 300P), this horizontal portion is formed by etching the channel material layer within the gate trench 160 (see [reference]). Figure 16 At least a portion of the channel material layer (see 300P) is used to form the channel layer 300 during the process of forming the channel layer 300 (see 300P). Figure 16 It was formed when the 300P in the middle was not sufficiently etched.

[0103] refer to Figure 12 The epitaxial layer 131 may further include a source trench 400. The source trench 400 may be located on the upper surface of the epitaxial layer 131 and has a predetermined depth. The source trench 400 may be spaced apart from the gate trench 160. For example, the source trench 400 may be spaced apart from the gate trench 160 in a first direction (X direction). The source trench 400 may be located on opposite sides of the gate trench 160 in the first direction (X direction). The source trenches 400 located on opposite sides of the gate trench 160 may be connected to each other or may not be connected to each other. The cross-section of the source trench 400 may be formed in a generally U-shape, and only a portion of the U-shaped source trench 400 is shown in the figures. The source trench 400 may include a bottom surface and sidewalls extending from the bottom surface. The angle of the sidewalls of the source trench 400 relative to the bottom may be vertical, but the example embodiment is not limited thereto. The bottom surface of the source trench 400 can be located at a lower height than the lower surface of the channel layer 300. The bottom surface of the source trench 400 can be located closer to the first surface 110a of the substrate 110 than the lower surface of the channel layer 300.

[0104] In some embodiments, the well region 133 may be located within the source trench 400, and the second conductivity type doped layer 139 may be located on a portion of the well region 133 within the source trench 400. Accordingly, the lower surface of the well region 133 may be located at a lower height than the lower surface of the channel layer 300. The lower surface of the well region 133 may be located closer to the first surface 110a of the substrate 110 than the lower surface of the channel layer 300.

[0105] In the following text, reference will be made to Figures 13 to 21 This describes a method for manufacturing a semiconductor device according to some implementation methods.

[0106] Figures 13 to 21 This is an intermediate process cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments.

[0107] refer to Figure 13 An epitaxial layer 131 can be formed on the first surface 110a of the substrate 110.

[0108] Substrate 110 may be a semiconductor substrate including SiC. For example, substrate 110 may be made of 4H SiC substrate. In some cases, substrate 110 may be made of 3C SiC substrate, 6H SiC substrate, etc. Substrate 110 may have a first conductivity type. Substrate 110 may be heavily doped to the first conductivity type. The first conductivity type may be n-type, but the example embodiments are not limited thereto. The resistivity of substrate 110 may be between about 0.005 Ωcm and about 0.035 Ωcm. The thickness of substrate 110 may be from about 10 μm to about 700 μm. The material, doping type, doping concentration, resistivity, thickness, etc. of substrate 110 are not limited thereto and may be varied. Substrate 110 may include a first surface 110a and a second surface 110b opposite to each other. The first surface 110a of substrate 110 may be the upper surface, and the second surface 110b of substrate 110 may be the lower surface.

[0109] Epitaxial layer 131 may be formed on the first surface 110a of substrate 110. The lower surface of epitaxial layer 131 may contact the first surface 110a of substrate 110. However, the exemplary embodiment is not limited thereto, and other layers may be disposed between substrate 110 and epitaxial layer 131. Epitaxial layer 131 may be an epitaxial layer formed from substrate 110 using an epitaxial growth method.

[0110] Epitaxial layer 131 may include a semiconductor material. For example, epitaxial layer 131 may include a first material and a second material different from the first material. The first material may include silicon (Si), and the second material may include carbon (C). Epitaxial layer 131 may include SiC. As an example, epitaxial layer 131 may include 4H-SiC. Epitaxial layer 131 may include SiC having a 4H hexagonal crystal structure. Epitaxial layer 131 may have a first conductivity type. Epitaxial layer 131 may be doped with impurities of the first conductivity type. Epitaxial layer 131 may be lightly doped with impurities of the first conductivity type. Here, the first conductivity type may be n-type, but the example embodiment is not limited to this.

[0111] refer to Figure 14 Well region 133, first conductivity type doped layer 137 and second conductivity type doped layer 139 can be formed in epitaxial layer 131.

[0112] First, an ion implantation process can be performed to form a well region 133 on the upper side of the epitaxial layer 131. The well region 133 may have a predetermined depth along a third direction (Z direction). The well region 133 may include a semiconductor material. For example, the well region 133 may include a first material and a second material different from the first material. The first material may include silicon (Si), and the second material may include carbon (C). The well region 133 may include SiC. As an example, the well region 133 may include 4H-SiC. The well region 133 may have a second conductivity type different from the first conductivity type. The well region 133 may be doped with impurities of the second conductivity type. The well region 133 may be lightly doped with impurities of the second conductivity type. Here, the second conductivity type may be p-type, but the example embodiment is not limited to this.

[0113] Next, a first conductivity type doped layer 137 and a second conductivity type doped layer 139 can be formed within the well region 133. An ion implantation process can be performed to form the first conductivity type doped layer 137 and the second conductivity type doped layer 139 on the upper side of the well region 133.

[0114] The first conductivity type doped layer 137 and the second conductivity type doped layer 139 may have a predetermined depth along a third direction (Z direction). The first conductivity type doped layer 137 may include a semiconductor material. For example, the first conductivity type doped layer 137 may include a first material and a second material different from the first material. The first material may include silicon (Si), and the second material may include carbon (C). The first conductivity type doped layer 137 may include SiC. As an example, the first conductivity type doped layer 137 may include 4H-SiC. The first conductivity type doped layer 137 may have a first conductivity type. The first conductivity type doped layer 137 may be doped with a first conductivity type impurity. The first conductivity type doped layer 137 may be heavily doped with a first conductivity type impurity. Here, the first conductivity type may be n-type, but the example embodiment is not limited to this.

[0115] The second conductivity type doped layer 139 may include a semiconductor material. For example, the second conductivity type doped layer 139 may include a first material and a second material different from the first material. The first material may include silicon (Si), and the second material may include carbon (C). The second conductivity type doped layer 139 may include SiC. As an example, the second conductivity type doped layer 139 may include 4H-SiC. The second conductivity type doped layer 139 may have a second conductivity type. The second conductivity type doped layer 139 may be doped with a second conductivity type impurity. The second conductivity type doped layer 139 may be heavily doped with a second conductivity type impurity. Here, the second conductivity type may be p-type, but the example embodiment is not limited to this.

[0116] refer to Figure 15 The first conductivity type doped layer 137, well region 133 and epitaxial layer 131 can be patterned to form a gate trench 160 in the first conductivity type doped layer 137, well region 133 and epitaxial layer 131.

[0117] For example, a first mask pattern MK1 with a first opening OP1 can be formed on the first conductivity type doped layer 137 and the second conductivity type doped layer 139. The first opening OP1 can expose at least a portion of the first conductivity type doped layer 137. The first mask pattern MK1 can be used as a mask to pattern the first conductivity type doped layer 137, the well region 133, and the epitaxial layer 131 to form the gate trench 160.

[0118] A gate trench 160 can be formed to a predetermined depth. The cross-section of the gate trench 160 can be formed as generally U-shaped. The gate trench 160 may include a bottom surface 160_B and an inner sidewall 160_S extending from the bottom surface 160_B. The inner sidewall 160_S of the gate trench 160 may be defined by an epitaxial layer 131, a well region 133, and a first conductivity type doped layer 137. The bottom surface 160_B of the gate trench 160 may be defined by the epitaxial layer 131. The angle of the inner sidewall 160_S of the gate trench 160 relative to the bottom surface 160_B may be vertical, but the example embodiment is not limited thereto. As another example, such as Figure 6 and Figure 7 As shown in the embodiment, the width of the gate trench 160 in the first direction (X direction) can increase as it moves away from the first surface 110a of the substrate 110. The gate trench 160 can expose the epitaxial layer 131. The gate trench 160 can expose the side surface of the well region 133 and the side surface of the first conductivity type doped layer 137.

[0119] The depth of the gate trench 160 in the third direction (Z direction) can be greater than the thickness of the well region 133 in the third direction (Z direction). The bottom surface 160_B of the gate trench 160 can be located at a lower height than the lower surface of the well region 133. The bottom surface 160_B of the gate trench 160 can be located closer to the first surface 110a of the substrate 110 than the lower surface of the well region 133.

[0120] refer to Figure 16 After removing the first mask pattern MK1, a channel material layer 300P can be formed within the gate trench 160.

[0121] A channel material layer 300P can be formed on the bottom surface 160_B and the inner sidewall 160_S of the gate trench 160. In this case, the channel material layer 300P can be formed simultaneously on the upper surface of the first conductivity type doped layer 137 and the upper surface of the second conductivity type doped layer 139. The channel material layer 300P can fill the gate trench 160. The channel material layer 300P can contact the epitaxial layer 131, the well region 133, and the first conductivity type doped layer 137.

[0122] The channel material layer 300P may include a semiconductor material. The channel material layer 300P may include the same material as the epitaxial layer 131. For example, the channel material layer 300P may include a first material and a second material different from the first material. The first material may include silicon (Si), and the second material may include carbon (C). As an example, the channel material layer 300P may include SiC.

[0123] The channel material layer 300P may have a different crystal structure than the epitaxial layer 131. For example, the channel material layer 300P may include 3C-SiC. The channel material layer 300P may include SiC with a 3C cubic crystal structure. Conversely, the epitaxial layer 131 may include 4H-SiC. The epitaxial layer 131 may include SiC with a 4H hexagonal crystal structure. The channel material layer 300P may include a material with a band gap different from that of the epitaxial layer 131. For example, the band gap of the material constituting the channel material layer 300P may be smaller than the band gap of the material constituting the epitaxial layer 131. The channel material layer 300P may include a material with a lower defect rate than the epitaxial layer 131.

[0124] The channel material layer 300P can have the same conductivity type as the epitaxial layer 131. The channel material layer 300P can have a first conductivity type. The channel material layer 300P can be doped with impurities of the first conductivity type. The channel material layer 300P can be lightly doped with impurities of the first conductivity type. Here, the first conductivity type can be n-type, but the example embodiment is not limited to this. The doping concentration of the channel material layer 300P can be lower than the doping concentration of the substrate 110. The doping concentration of the channel material layer 300P can be approximately 1*102 15 cm -3 Or higher, and approximately 1*10 17 cm -3 Or even lower. The material, doping type, doping concentration, etc. of the 300P channel material layer are not limited to this, and can be changed in various ways.

[0125] The channel material layer 300P can be formed using an epitaxial growth method, using a portion of the epitaxial layer 131 exposed by the gate trench 160 as a seed. Alternatively, the channel material layer 300P can also be formed using an epitaxial growth method, using a portion of the well region 133 exposed by the gate trench 160 and a portion of the first conductivity type doped layer 137 exposed by the gate trench 160 as seeds. For example, the channel material layer 300P can be formed on a portion of the epitaxial layer 131 defining the bottom surface 160_B of the gate trench 160 and a portion of the epitaxial layer 131 defining the inner sidewall 160_S of the gate trench 160.

[0126] In this case, defects may occur in the channel material layer 300P, depending on the crystal plane of the grown channel material layer 300P. For example, defects may occur in portions of the channel material layer 300P formed at point a1 where the bottom surface 160_B of the gate trench 160 intersects with the inner sidewall 160_S, portions of the channel material layer 300P formed at point a2 where the inner sidewall 160_S of the gate trench 160 intersects with the upper surface of the first conductivity type doped layer 137, portions of the channel material layer 300P formed on the gate trench 160, and portions of the channel material layer 300P formed on the bottom surface 160_B of the gate trench 160. However, the example embodiment is not limited to this, and the process for forming the channel material layer 300P can be performed using a deposition process.

[0127] refer to Figure 17 At least a portion of the channel material layer 300P located on the first conductivity type doped layer 137 and the second conductivity type doped layer 139 can be removed. For example, a planarization process can be performed, using chemical mechanical polishing (CMP) to remove at least a portion of the channel material layer 300P. Accordingly, the upper surfaces of the first conductivity type doped layer 137 and the second conductivity type doped layer 139 can be exposed. Since at least a portion of the channel material layer 300P has been removed, defects formed in the portion of the channel material layer 300P formed at the point where the inner sidewall 160_S of the gate trench 160 intersects with the upper surface of the first conductivity type doped layer 137 can be removed (see...). Figure 16 (a2), and defects formed in a portion of the channel material layer 300P formed on the gate trench 160.

[0128] refer to Figure 18 At least a portion of the channel material layer 300P can be etched to form the channel layer 300 that exposes the bottom surface 160_B of the gate trench 160.

[0129] For example, a second mask pattern MK2 having a second opening OP2 can be formed on the first conductivity type doped layer 137 and the second conductivity type doped layer 139. The second opening OP2 can expose at least a portion of the channel material layer 300P located within the gate trench 160. The second mask pattern MK2 can be used as a mask to etch at least a portion of the channel material layer 300P to form the channel layer 300. The process of etching at least a portion of the channel material layer 300P can be performed using a dry etching method, but the example embodiments are not limited thereto. The process of etching the channel material layer 300P can be performed using a material that has etch selectivity relative to the epitaxial layer 131. As another example, at least a portion of the channel material layer 300P can be etched using a wet etching method. As another example, after etching at least a portion of the channel material layer 300P using a dry etching method, the channel layer 300 can be formed by etching at least a portion of the channel material layer 300P using a wet etching method.

[0130] Accordingly, the bottom surface 160_B of the gate trench 160 can be exposed. The channel layer 300 can be located on the inner sidewall 160_S of the gate trench 160. Accordingly, defects formed in portions of the channel material layer 300P formed on the bottom surface 160_B of the gate trench 160 can be eliminated, thereby improving the reliability of the semiconductor device.

[0131] The channel layer 300 may protrude from the lower surface of the well region 133 toward the first surface 110a of the substrate 110. The lower surface 300_B of the channel layer 300 may be located at a lower height than the lower surface of the well region 133. The lower surface 300_B of the channel layer 300 may be located closer to the first surface 110a of the substrate 110 than the lower surface of the well region 133. The channel layer 300 may overlap with the well region 133 and the epitaxial layer 131 in a first direction (X direction).

[0132] The thickness of the channel layer 300 in the first direction (X direction) can remain substantially constant even as it increases away from the bottom surface 160_B of the gate trench 160, but the example embodiment is not limited thereto. For example, the thickness of the channel layer 300 in the first direction (X direction) can be about 1 / 10 to about 1 / 3 of the gate trench 160, but the example embodiment is not limited thereto. For example, the thickness of the channel layer 300 in the first direction (X direction) can be about 100 nm or greater, but the example embodiment is not limited thereto. As another example, such as Figure 2 As shown in the implementation, the channel layer 300 may include a portion whose thickness increases with distance from the bottom surface 160_B of the gate trench 160. The thickness of the channel layer 300 in the first direction (X direction) may increase with distance from the bottom surface 160_B of the gate trench 160. As another example, such as Figure 3As shown in the implementation, the thickness of the channel layer 300 in the first direction (X direction) can decrease as it moves away from the bottom surface 160_B of the gate trench 160.

[0133] The channel layer 300 may include a semiconductor material. The channel layer 300 may include the same material as the epitaxial layer 131. For example, the channel layer 300 may include a first material and a second material different from the first material. The first material may include silicon (Si), and the second material may include carbon (C). For example, the channel layer 300 may include SiC.

[0134] The channel layer 300 may have a different crystal structure than the epitaxial layer 131. For example, the channel layer 300 may include 3C-SiC. The channel layer 300 may include SiC having a 3C cubic crystal structure. Conversely, the epitaxial layer 131 may include 4H-SiC. The epitaxial layer 131 may include SiC having a 4H hexagonal crystal structure.

[0135] The content (atomic percentage) of the first material in the channel layer 300 can be substantially the same as the content (atomic percentage) of the first material in the epitaxial layer 131, but the example embodiment is not limited thereto. The first material may include silicon (Si), and the second material may include carbon (C). The lower surface of the channel layer 300 may be located at substantially the same height as the bottom surface 160_B of the gate trench 160. The lower surface of the channel layer 300 and the bottom surface 160_B of the gate trench 160 may be located at substantially the same distance from the first surface 110a of the substrate 110. However, the example embodiment is not limited thereto; as another example, such as... Figure 4 As shown in the embodiment, a portion of the channel layer 300 adjacent to the bottom surface 160_B of the gate trench 160 can be etched. In this case, the lower surface of the channel layer 300 can be located further away from the first surface 110a of the substrate 110 than the bottom surface 160_B of the gate trench 160. As another example, such as Figure 5 As shown in the embodiments, in the process of etching at least a portion of the channel material layer 300P, at least a portion of the epitaxial layer 131 can be etched together.

[0136] refer to Figure 19 The gate insulating layer 140 can be formed on the inner surface of the channel layer 300 and the bottom surface 160_B of the gate trench 160.

[0137] A gate insulating layer 140 may be located on the inner surface of the channel layer 300. The gate insulating layer 140 may contact the channel layer 300. Additionally, the gate insulating layer 140 may be located on the bottom surface 160_B of the gate trench 160. The lower surface of the gate insulating layer 140 may contact the epitaxial layer 131. The gate insulating layer 140 may have a substantially uniform thickness on the bottom surface 160_B of the gate trench 160 and the inner surface of the channel layer 300, but the exemplary embodiments are not limited thereto.

[0138] The lower surface of the gate insulating layer 140 may be located at substantially the same height as the lower surface 300_B of the channel layer 300. The lower surface of the gate insulating layer 140 and the lower surface 300_B of the channel layer 300 may be located at substantially the same distance from the first surface 110a of the substrate 110.

[0139] According to some embodiments, the gate insulating layer 140 of the semiconductor device may include a first portion 140_P1 located on the inner surface of the channel layer 300 and a second portion 140_P2 located on the bottom surface 160_B of the gate trench 160.

[0140] The first portion 140_P1 may extend in the third direction (Z direction). The first portion 140_P1 may extend parallel to the channel layer 300. The first portion 140_P1 may be located between the channel layer 300 and the gate electrode 150. The first portion 140_P1 may contact the inner surface of the channel layer 300. The upper surface of the first portion 140_P1 may be located at a height substantially the same as the upper surface of the channel layer 300. The upper surface of the first portion 140_P1 and the upper surface of the channel layer 300 may be located at a distance substantially the same from the first surface 110a of the substrate 110. Additionally, the upper surface of the first portion 140_P1 may be located at a height substantially the same as the upper surface of the first conductivity type doped layer 137. The upper surface of the first portion 140_P1 and the upper surface of the first conductivity type doped layer 137 may be located at a distance substantially the same from the first surface 110a of the substrate 110.

[0141] The second portion 140_P2 may be located on the bottom surface 160_B of the gate trench 160. The second portion 140_P2 may be conformally located on the bottom surface 160_B of the gate trench 160. The second portion 140_P2 may extend in a first direction (X direction). The second portion 140_P2 may be connected to the first portion 140_P1. The second portion 140_P2 may refer to the portion of the gate insulating layer 140 located on the bottom surface 160_B of the gate trench 160. The thickness of the second portion 140_P2 along the third direction (Z direction) may be substantially the same as the thickness of the first portion 140_P1 along the first direction (X direction), but the example embodiment is not limited thereto. As another example, such as Figure 8 As shown in the implementation, the thickness of the second part 140_P2 along the third direction (Z direction) can be greater than the thickness of the first part 140_P1 along the first direction (X direction).

[0142] The gate insulating layer 140 may include an insulating material. For example, the gate insulating layer 140 may include silicon oxide (SiO2). However, the example embodiments are not limited to this, and the material of the gate insulating layer 140 may be varied in various ways. As another example, the gate insulating layer 140 may include SiN, SiON, SiC, SiCN, or combinations thereof. In some embodiments, the gate insulating layer 140 may also include certain elements. For example, the gate insulating layer 140 may include carbon (C), nitrogen (N), or combinations thereof. For example, the gate insulating layer 140 may be composed of silicon oxide (SiO2) containing carbon (C) and nitrogen (N). The gate insulating layer 140 may be formed as a single layer or multiple layers.

[0143] refer to Figure 20 A gate electrode 150 can be formed within the gate trench 160. After forming the channel layer 300 and the gate insulating layer 140, the gate electrode 150 can fill the remaining portion of the gate trench 160. The gate electrode 150 can include a conductive material. For example, the gate electrode 150 can include polysilicon doped with impurities. As another example, the gate electrode 150 can include a metal, a metal alloy, a metal silicide, a doped semiconductor material, a conductive metal oxide, a conductive metal nitride, or a combination thereof. The gate electrode 150 can be formed from a single layer or multiple layers.

[0144] refer to Figure 21 A capping layer 142 is formed on the gate electrode 150, the gate insulating layer 140 and the channel layer 300, a source electrode 173 is formed on the first conductivity type doped layer 137 and the second conductivity type doped layer 139, and a drain electrode 175 is formed on the second surface 110b of the substrate 110, thereby forming a semiconductor device according to some embodiments.

[0145] The source electrode 173 may include a conductive material. For example, the source electrode 173 may include a metal, a metal alloy, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal nitride. In the process of forming the source electrode 173, a metal silicide layer 191 may be formed on the first conductivity type doped layer 137 and the second conductivity type doped layer 139, and then the source electrode 173 may be formed on the metal silicide layer 191, but the example embodiment is not limited to this.

[0146] Although this specification contains numerous details of specific embodiments, these details should not be construed as limiting the scope of claims or any invention, but rather as descriptions of features specific to particular embodiments that may be dedicated to a particular invention. In a single embodiment, certain features described in this specification within the context of separate embodiments may also be implemented in combination. Conversely, different features described in the context of a single embodiment may also be implemented individually in multiple embodiments, or in appropriate sub-combinations. Furthermore, although features may be described above as functioning in certain combinations, one or more features from a combination may be removed from the combination in some cases, and combinations may be for sub-combinations or variations of sub-combinations.

[0147] The above detailed description of embodiments of this disclosure is not intended to limit the scope of this disclosure. On the contrary, various modifications and improvements made by those skilled in the art using the basic concepts of this disclosure as defined in the appended claims also fall within the scope of this disclosure.

Claims

1. A semiconductor device, comprising: The substrate includes a first surface and a second surface opposite to the first surface; An epitaxial layer, on the first surface of the substrate, the epitaxial layer includes a gate trench, wherein the epitaxial layer has a first conductivity type; A channel layer on the inner sidewall of the gate trench, wherein the channel layer has the first conductivity type and has a lower defect rate than the epitaxial layer; The gate electrode is located in the gate trench. A gate insulating layer is located on the bottom surface of the gate trench and between the channel layer and the gate electrode. Source electrode, on the epitaxial layer; and The drain electrode is located on the second surface of the substrate.

2. The semiconductor device according to claim 1, in, The channel layer comprises the same material as the epitaxial layer.

3. The semiconductor device according to claim 2, in, The channel layer has a different crystal structure than the epitaxial layer.

4. The semiconductor device according to claim 3, in, The channel layer comprises a compound formed of a first material and a second material different from the first material, and The first material comprises Si, and the second material comprises C.

5. The semiconductor device according to claim 1, in, The lower surface of the gate insulating layer is in contact with the epitaxial layer, wherein the lower surface of the gate insulating layer faces the first surface of the substrate.

6. The semiconductor device according to claim 5, in, The lower surface of the channel layer is further away from the first surface of the substrate than the lower surface of the gate insulating layer, and wherein the lower surface of the channel layer faces the first surface of the substrate.

7. The semiconductor device according to claim 1, in, The gate insulating layer includes: The first part, on the inner surface of the channel layer, and The second part is on the bottom surface of the gate trench. The thickness of the second part is greater than or equal to the thickness of the first part.

8. The semiconductor device according to claim 1, in, The channel layer extends in the first direction, and The gate electrode does not overlap with the channel layer in the first direction.

9. The semiconductor device according to claim 1, in, The thickness of the channel layer is 1 / 10 to 1 / 3 of the width of the gate trench.

10. The semiconductor device according to claim 1, in, The channel layer includes a portion whose thickness increases with the distance from the bottom surface of the gate trench.

11. The semiconductor device according to claim 1, comprising: A shielding pattern, between the epitaxial layer and the gate insulating layer, has a second conductivity type different from the first conductivity type.

12. The semiconductor device according to claim 11, in, The shielding pattern is between the channel layer and the epitaxial layer.

13. The semiconductor device according to claim 1, The trench layer includes: The vertical portion extends along the inner sidewall of the gate trench in a first direction; as well as The horizontal portion extends along the bottom surface of the gate trench in a second direction intersecting the first direction.

14. The semiconductor device according to claim 13, in, The thickness of the vertical portion in the second direction is greater than or equal to the thickness of the horizontal portion in the first direction.

15. The semiconductor device according to claim 1, in, The gate insulating layer protrudes from the lower surface of the channel layer toward the first surface of the substrate.

16. A semiconductor device, comprising: The substrate includes a first surface and a second surface opposite to the first surface; An epitaxial layer, on the first surface of the substrate, the epitaxial layer includes a gate trench, wherein the epitaxial layer has a first conductivity type; A well region, on the epitaxial layer, having a second conductivity type different from the first conductivity type; A channel layer having the first conductivity type is located on the inner sidewall of the gate trench, wherein the channel layer has a lower defect rate than the epitaxial layer. A gate electrode, within the gate trench, wherein the gate electrode extends in a first direction; A gate insulating layer is located between the channel layer and the gate electrode; Source electrode, on the well region; and Drain electrode, on the second surface of the substrate. The channel layer extends in the first direction and protrudes from the lower surface of the well region toward the first surface of the substrate.

17. The semiconductor device according to claim 16, in, The channel layer overlaps with the well region and the epitaxial layer in a second direction intersecting the first direction, and wherein the channel layer does not overlap with the source electrode in the second direction.

18. The semiconductor device according to claim 16, in, The distance between the lower surface of the gate insulating layer and the first surface of the substrate is equal to the distance between the lower surface of the channel layer and the first surface of the substrate.

19. A semiconductor device, comprising: The substrate includes a first surface and a second surface opposite to the first surface; An epitaxial layer, on the first surface of the substrate, the epitaxial layer includes a gate trench, wherein the epitaxial layer comprises 4H-SiC; The channel layer comprises 3C-SiC, wherein the channel layer is on the inner sidewall of the gate trench, and wherein the channel layer has a lower defect rate than the epitaxial layer. The gate electrode is located in the gate trench. A gate insulating layer is located between the channel layer and the gate electrode; Source electrode, on the epitaxial layer; and The drain electrode is located on the second surface of the substrate.

20. The semiconductor device according to claim 19, in, The gate insulating layer is also located between the epitaxial layer and the gate electrode.

Images