Semiconductor devices with gate contacts and related methods

Abstract

This disclosure relates to semiconductor devices and related methods having gate contacts. One device includes: a substrate; an isolation structure located in the substrate; an active region laterally surrounded by the isolation structure; a first gate line located on the substrate and overlapping the active region and the isolation structure; a second gate line adjacent to the first gate line; a first contact located on the first gate line and overlapping the isolation structure; a second contact located on the first gate line and overlapping the active region; a third contact located on the second gate line and overlapping the isolation structure; a fourth contact located on the second gate line and overlapping the active region; and a metal layer including: a first portion; a second portion extending from the first portion and overlapping the first and third contacts; and a third portion extending from the first portion and overlapping the second and fourth contacts.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices having gate contacts and related methods. Background Technology

[0002] Semiconductor devices are formed on, in, and / or from semiconductor wafers and are used in a variety of electronic devices, such as mobile phones, laptops, desktops, tablets, watches, gaming systems, and various other industrial, commercial, and consumer electronics. One or more semiconductor manufacturing processes are performed to form semiconductor devices on, in, and / or from semiconductor wafers. Summary of the Invention

[0003] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a substrate; an isolation structure located in the substrate; an active region defined in the substrate, the active region being laterally surrounded by the isolation structure; a first gate line extending in a first direction, the first gate line being located on the substrate and overlapping the active region and the isolation structure; a second gate line adjacent to the first gate line along a second direction traversing the first direction, the second gate line extending in the first direction, the second gate line being located on the substrate and overlapping the active region and the isolation structure; a first contact located on the first gate line and overlapping the isolation structure; and a second contact located on the first gate line and overlapping the active region.

[0004] According to another aspect of this disclosure, a semiconductor device is provided, comprising: a first device including: a first gate line overlapping a first active region of a substrate and overlapping an isolation structure adjacent to the first active region; a first source / drain located in the substrate, immediately adjacent to the first gate line; and a first contact located on the first gate line and overlapping the isolation structure; and a second device including: a second gate line overlapping a second active region of the substrate, the second active region being separated from the first active region by the isolation structure; a second source / drain located in the substrate, immediately adjacent to the second gate line; a second contact located on the second gate line and overlapping the isolation structure; and a third contact located on the second gate line and overlapping the second active region.

[0005] According to another aspect of this disclosure, a method of forming a semiconductor device is provided, comprising: forming a first active region of a substrate, including forming an isolation structure in the substrate, the isolation structure being adjacent to the first active region; forming a first gate line extending along a first direction and overlapping the first active region and the isolation structure; forming a first source / drain adjacent to the first gate line in the first active region; forming a first opening, a second opening, and a third opening in a dielectric layer exposed by a mask layer, the first opening overlapping the first gate line and the isolation structure, the second opening overlapping the first gate line and the first active region, and the third opening overlapping the first source / drain; forming a first contact in the first opening and a third contact in the third opening; and forming a second contact in the second opening. Attached Figure Description

[0006] The various aspects of this disclosure are best understood when read in conjunction with the accompanying drawings in the following detailed description. Note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased arbitrarily for clarity of discussion.

[0007] Figure 1A , Figure 1B , Figure 1C and Figure 1D A side view of a device according to some embodiments is shown.

[0008] Figure 2A , Figure 2B and Figure 2C A schematic diagram of a method for forming a device in an intermediate stage of manufacturing, according to some embodiments, is shown.

[0009] Figure 3A , Figure 3B and Figure 3C A schematic diagram of a method for forming a device in an intermediate stage of manufacturing, according to some embodiments, is shown.

[0010] Figure 4A , Figure 4B and Figure 4C A schematic diagram of a method for forming a device in an intermediate stage of manufacturing, according to some embodiments, is shown.

[0011] Figure 5A , Figure 5B , Figure 5C and Figure 5D A schematic diagram of a method for forming a device in an intermediate stage of manufacturing, according to some embodiments, is shown.

[0012] Figure 6A and Figure 6BA schematic diagram of a method for forming a device in an intermediate stage of manufacturing, according to some embodiments, is shown.

[0013] Figure 7A , Figure 7B , Figure 7C and Figure 7D A schematic diagram of a method for forming a device in an intermediate stage of manufacturing, according to some embodiments, is shown.

[0014] Figure 8A , Figure 8B , Figure 8C and Figure 8D A schematic diagram of a method for forming a device in an intermediate stage of manufacturing, according to some embodiments, is shown.

[0015] Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E and Figure 9F A schematic diagram of a method for forming a device in an intermediate stage of manufacturing, according to some embodiments, is shown.

[0016] Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E and Figure 10F A schematic diagram of a method for forming a device in an intermediate stage of manufacturing, according to some embodiments, is shown.

[0017] Figure 11A , Figure 11B and Figure 11C A schematic diagram of a method for forming a device in an intermediate stage of manufacturing, according to some embodiments, is shown.

[0018] Figure 12 This is a flowchart illustrating a method according to some embodiments.

[0019] Figure 13 An example computer-readable medium according to some embodiments is shown, which may include processor-executable instructions configured to embody one or more configurations described herein. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, for ease of description, this document uses spatially relevant terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or feature shown in the figure and another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein will be interpreted accordingly.

[0022] The terms "above" and / or similar terms may be used to describe an element or feature that is vertically aligned with another element or feature and is at a higher height than the other element or feature. For example, if a first element is at a higher height than a second element, and at least a portion of the first element is vertically aligned with at least a portion of the second element, then the first element is above the second element.

[0023] The terms "below" and / or similar terms may be used to describe an element or feature that is vertically aligned with another element or feature and is at a lower height than the other element or feature. For example, if a first element is at a lower height than a second element, and at least a portion of the first element is vertically aligned with at least a portion of the second element, then the first element is below the second element.

[0024] The term "above" can be used to describe an element or feature that is at a higher height than another element or feature. For example, if the first element is at a higher height than the second element, then the first element is above the second element.

[0025] The term "located below" can be used to describe an element or feature that is at a lower height than another element or feature. For example, if the first element is at a lower height than the second element, then the first element is located below the second element.

[0026] In high-frequency field-effect transistor (FET) devices (e.g., radio frequency (RF) devices that include FETs), increasing the device width can increase the device speed. However, including FETs with a large width may reduce the maximum frequency (f) of the RF device. max The maximum frequency of an RF device can be defined as the unity-power gain cutoff frequency. The maximum frequency can be approximated using the following equation: ,

[0027] Embodiments of this disclosure reduce the AC gate resistance (R) by including the following. g_ac (1) a first gate contact that overlaps with an isolation structure that laterally surrounds the active region of the substrate on which the RF device FET is located, and (2) a second gate contact that overlaps with the active region. Including the second gate contact can reduce R... g_ac This allows the RF device's f max Increase.

[0028] Figure 1A , Figure 1B , Figure 1C and Figure 1D A schematic plan view and a cross-sectional side view of a portion of an IC device 10 manufactured according to embodiments of the present disclosure are shown, wherein the IC device 10 includes an RF device 20. For simplicity of illustration, in Figures 1A to 1D In a view, certain features may be intentionally removed. (See reference) Figures 1A to 1D Detailed description of IC device 10 is provided for reference in understanding. Figures 2A to 13 The described embodiments provide context.

[0029] Figure 1A A portion of the IC device 10, including the RF device 20, is shown. Figure 1AThe view shown depicts a planar field-effect transistor (FET) layout. It should be understood that embodiments of this disclosure may include fin-type FET devices, nanosheet or gate-all-around (GAA) FET devices, complementary FET devices, etc. In some embodiments, RF device 20 may include an N-type FET (NFET), a P-type FET (PFET), or both. IC device 10 may include transistors with different threshold voltages based on their function in the IC device. For example, input / output (IO) transistors may have a highest threshold voltage, core logic transistors may have a lowest threshold voltage, and a third threshold voltage between the highest threshold voltage of the IO transistors and the lowest threshold voltage of the core logic transistors may also be used for other functional transistors, such as static random access memory (SRAM) transistors. Some circuit blocks within IC device 10 may include two or more NFETs and / or PFETs having two or more different threshold voltages.

[0030] refer to Figure 1A The RF device 20 is formed on and / or within the substrate 110 and typically includes a gate structure 200C located over a corresponding semiconductor channel. The RF device 20 may be laterally surrounded by an isolation structure 36 (e.g., a shallow trench isolation or “STI” structure).

[0031] The channel is adjacent to a corresponding source / drain region 82. One or more source / drain regions may individually or collectively refer to the source or drain, depending on the context. Each gate structure 200C is operable to increase and / or decrease the current flow between two source / drain regions 82 through the corresponding channel therebetween.

[0032] Substrate 110 is at least one of the following materials or includes at least one of the following materials: silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimonide, SiGe, SiC, GaAs, GaN, GaP, InGaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or other suitable materials. Substrate 110 may include at least one of the following materials: single-crystal silicon, having <100> Crystalline silicon with crystal orientation <110> Crystalline silicon with crystal orientation, possessing <111> Crystalline silicon or other suitable materials with crystal orientation. Other structures and / or configurations of the substrate 110 are also within the scope of this disclosure. The channel may include a semiconductor material, which may be the same semiconductor material as the substrate 110, or another suitable semiconductor material, such as silicon or silicon compounds, such as silicon germanium, etc.

[0033] The gate structure 200C may be referred to as an active gate structure 200C and is operable to control current flow between the source / drain regions 82 via a channel in the substrate 110 beneath them. In some embodiments, the gate structure 200C is situated above and extends completely through the active region 52 of the substrate 110. The channel and the source / drain 82 are located within the active region 52.

[0034] like Figure 1A As shown, in some embodiments, one or more first dummy gate structures 200B are positioned adjacent to a gate structure 200C on the active region 52. The one or more first dummy gate structures 200B can improve process uniformity, reduce proximity effects, and reduce edge effects, which can improve the performance of the RF device 20 including the active gate structure 200C. The one or more first dummy gate structures 200B can be referred to as first non-active gate structures 200B. That is, the one or more first dummy gate structures 200B can be electrically floating and substantially do not carry electrical signals during operation. In some embodiments, one or more second dummy gate structures 200A are positioned adjacent to the one or more first dummy gate structures 200B and are entirely located on the isolation structure 36.

[0035] The source / drain region 82 may include SiB, SiGe, SiGeB, etc., and may include dopants such as Ge, Sb, B, etc. In some embodiments, the source / drain region 82 includes silicon-phosphorus (SiP; Si:P), silicon-arsenic (SiAs; Si:As), etc.

[0036] RF device 20 may include source / drain contacts 120 located above one or more of the source / drain terminals 82. The source / drain contacts 120 may include one or more liner layers and a core conductive layer. Figure 1A (Not shown separately). A silicide layer may be formed between the respective source / drain 82 and the source / drain contact 120 to reduce the source / drain contact resistance. A gate silicide layer may be formed on the respective gate line 45. In some embodiments, the silicide layer and the gate silicide layer are one or more of the following or include one or more of the following: nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals or alloys thereof. For example, the silicide layer and the gate silicide layer may be TiSi, TiNiSi, NiSi, WSi, CoSi, MoSi, RuSi, etc.

[0037] Figure 1B The following are shown according to some embodiments. Figure 1A A schematic cross-sectional view of line BB. Figure 1B In the middle, the gate structure 200C is disposed on the channel 22.

[0038] In some embodiments, each gate structure 200C includes a gate line 45 and a gate dielectric 43. The gate line 45 comprises polysilicon or another suitable material. In some embodiments, the gate line 45 comprises one or more metals or transition metal nitrides, such as W, TiN, TaN, etc.

[0039] In some embodiments, one or more gate dielectric layers 43 are located between the gate line 45 and the corresponding channel 22. The gate dielectric layer 43 may be one or more dielectric materials or include one or more dielectric materials, such as at least one high-k gate dielectric material. A high-k gate dielectric material can refer to a dielectric material having a high dielectric constant greater than that of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or combinations thereof. In some embodiments, the gate dielectric layer 43 has a thickness of about 5 Å to about 300 Å. In some embodiments, the gate dielectric layer 43 may include a non-high-k dielectric material, such as silicon oxide.

[0040] RF device 20 may include a gate or "sidewall" or "external" spacer 41 disposed on the sidewall of gate line 45. The sidewall spacer 41 may facilitate offsetting source / drain extension injection, reducing hot carrier effects, and guiding deep source / drain injection. The sidewall spacer 41 may include a dielectric material such as SiOCN, SiON, SiN, SiCN, or SiOC. In some embodiments, the sidewall spacer 41 may include one or more spacer layers. For example, such as... Figure 1B As shown, the sidewall spacer 41 includes a spacer layer.

[0041] Figure 1C The following are shown according to some embodiments. Figure 1A A cross-sectional side view of line CC. RF device 20 may include an interlayer dielectric (ILD) layer 130 on an optional etch stop layer, with source / drain contacts 120 extending through the ILD layer 130. The ILD layer 130 provides electrical isolation between various components of the RF device 20, for example, between the gate structure 200C and the source / drain contacts 120 therebetween. The etch stop layer may be formed prior to the formation of the ILD layer 130 and may be laterally positioned between the ILD layer 130 and the sidewall spacers 41, and vertically positioned between the ILD layer 130 and the source / drain region 82. In some embodiments, the etch stop layer is or includes the following materials: SiN, SiCN, SiC, SiOC, SiOCN, HfO2, ZrO2, ZrAlO x HfAlOx HfSiO x Al2O3 or other suitable materials. In some embodiments, the thickness of the etch stop layer is in the range of about 1 nm to about 5 nm.

[0042] IC device 10 may include a front-side interconnect structure 140 having additional interconnect conductive features 160 covering source / drain contacts 120 and ILD layer 130. In some embodiments, the interconnect conductive features 160 include conductive vias, conductive traces, etc. The interconnect conductive features 160 may be located in a stack of dielectric layers, which may include an intermediate ILD layer 132 on ILD layer 130 and a top ILD layer 134 covering the intermediate ILD layer 132. In some embodiments, a first passivation layer 136 may cover the top ILD layer 134 and may be an oxide dielectric layer. A second passivation layer 138 may cover the first passivation layer 136 and may be a nitride dielectric layer. In some embodiments, such as Figure 1A As shown, the first passivation layer 136 can smooth out non-uniformities in the underlying structure. Then, the second passivation layer 138 can further smooth out non-uniformities, while also helping to protect the underlying structure from moisture, contaminants, mechanical damage, etc.

[0043] Figure 1D The following are shown according to some embodiments. Figure 1A A cross-sectional side view of line DD. RF device 20 may include a first gate contact 124S, which may be referred to as isolation gate contact 124S. RF device 20 may include a second gate contact 124C, which may be referred to as active region (AA) gate contact 124C. The first gate contact 124S is located above and overlaps with the isolation structure 36, extends through the bottom layer of the intermediate ILD layer 132, and partially enters the gate structure 200C, for example, partially enters the gate line 45. The second gate contact 124C is located above and overlaps with the active region 52 (such as channel 22), extends through the bottom layer of the intermediate ILD layer 132, and partially enters the gate structure 200C, for example, partially enters the gate line 45.

[0044] Figure 12 and Figure 13Flowcharts of methods 1200 and 1300 for forming an IC device or a portion thereof from a workpiece according to one or more aspects of this disclosure are shown. Methods 1200 and 1300 are merely examples and are not intended to limit this disclosure to what is expressly shown in methods 1200 and 1300. Additional actions may be provided before, during, and after methods 1200 and 1300, and some described actions may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all actions are described in detail herein. The following is in conjunction with… Figures 2A to 11C Methods 1200 and 1300 are described by partial perspective and / or cross-sectional views of the workpiece during the manufacturing stage according to embodiments of methods 1200 and 1300. For the avoidance of ambiguity, throughout the figures, the X-axis direction is perpendicular to the Y-axis direction, and the Z-axis direction is perpendicular to both the X-axis and Y-axis directions. It is worth noting that since the workpiece can be manufactured into a semiconductor device, the workpiece can be referred to as a semiconductor device or simply "device," which is useful for the context. Methods 1200 and 1300 can be used to form... Figure 1A-1D The IC device 10 shown is shown.

[0045] In some embodiments, methods 1200 and 1300 are performed to form a FET device. Figures 2A to 11C In this context, FET devices can include planar FETs, FinFETs, and the like. In most figures, planar FETs are depicted as examples. The process for forming the AA gate contact 124C that overlaps with the active region of the RF device can be included in the process for forming a FinFET or another suitable field-effect transistor (FET).

[0046] Figures 2A to 11C These are perspective views, plan views, and cross-sectional views of intermediate stages in the fabrication of a FET device (e.g., a planar FET cascade device) according to some embodiments. Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 7C , Figure 8A and Figure 8C A perspective view is shown. Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B and Figure 9D It shows Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 7C , Figure 8A and Figure 8C The reference cross section B-B' shown is a gate cut or "Y cut". Figure 3C , Figure 4C , Figure 5C , Figure 8B , Figure 8D , Figure 9B , Figure 9C and Figure 9E It shows Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 7C , Figure 8A and Figure 8C The reference cross section C-C' shown is a groove cut or "X cut". Figure 10E and Figure 10F They are shown respectively Figure 10A and Figure 10B Reference cross sections EE and FF. Figure 2C , Figure 5D , Figure 9A , Figure 9F , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B and Figure 11C A floor plan is shown.

[0047] exist Figure 2A and Figure 2B In the above, a substrate 110 is provided. The substrate 110 can be a reference. Figure 1A and Figure 1B Any substrate 110 described may be or include a semiconductor substrate, such as a bulk semiconductor, which may be doped (e.g., with p-type or n-type dopant) or undoped. The semiconductor material of substrate 110 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide; or combinations thereof. Other substrates, such as single-layer, multilayer, or gradient substrates, may be used.

[0048] exist Figure 2C In some embodiments, the STI region 36 is formed in the substrate 110, corresponding to Figure 12Action 1202. In some embodiments, the formation of the STI region 36 may include performing wet chemical cleaning (e.g., RCA cleaning) to remove organic contaminants, native oxides, and metallic impurities. A thin thermal oxide layer (e.g., about 10 nm to about 20 nm) and a silicon nitride layer (e.g., about 100 nm to about 150 nm) may then be deposited, for example, by low-pressure chemical vapor deposition (LPCVD) to protect the active region or “OD region” 52. Photolithography may be performed to select the active region 52, marking the active regions as source, drain, and channel regions. One or more etch operations may expose the substrate 110 outside the active region mask by reactive ion etching (RIE) to form trench(s) of depth, which may be about 200 nm to 400 nm or another suitable depth. Silicon dioxide (SiO2) may be deposited in the trench(s) ... Planarization operations, such as chemical mechanical polishing (CMP), can be performed to remove excess oxide and stop on the silicon nitride layer. The nitride layer can then be stripped by thermal phosphoric acid or another suitable etchant, and the oxide layer can be removed by dilute HF or another suitable etchant, leaving the active region 52 laterally surrounded by one or more STI regions 36.

[0049] In some embodiments, a suitable well (not shown separately) may be formed in the active region 52. Using a mask, n-type impurity implantation may be performed in the p-type region of substrate 110, and n-type impurity implantation may be performed in the n-type region of substrate 110. Example n-type impurities may include phosphorus, arsenic, antimony, etc. Example p-type impurities may include boron, boron fluoride, indium, etc. Annealing may be performed after implantation to repair implantation damage and activate p-type and / or n-type impurities.

[0050] exist Figures 3A-3C In this configuration, gate line 45 is formed on substrate 110 on active region 52 and extends onto isolation structure 36, corresponding to... Figure 12Action 1204. Gate line 45 may be a semi-conductive, conductive, or non-conductive material, and may be one or more of the following, including one or more of the following: amorphous silicon, polysilicon, poly-SiGe, metal nitride, metal silicide, metal oxide, and metal. Gate line 45 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques suitable for depositing the selected material. In some embodiments, one or more mask layers are formed over gate line 45 and may include, for example, silicon nitride, silicon oxynitride, etc. In some embodiments, gate dielectric layer 43 is formed before gate line 45 and is located between gate line 45 and substrate 110. In some embodiments, gate line 45 is replaced in a subsequent process. In some embodiments, gate line 45 is not replaced.

[0051] exist Figures 4A-4C In this configuration, one or more spacer layers 41A', 41B' are formed above the gate line 45. According to some embodiments, the spacer layers 41A', 41B' may be or include insulating materials, such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, etc., and may have a single-layer structure or a multilayer structure including multiple dielectric layers. Figures 4A-4C A first spacer layer 41A' and a second spacer layer 41B' on the first spacer layer 41A' are depicted. In some embodiments, the first spacer layer 41A' and the second spacer layer 41B' are made of different materials or the same material. A mask layer 41C is formed on the spacer layer 41B'. ​​In some embodiments, before forming the spacer layers 41A' and 41B', the gate dielectric layer 43 is trimmed by removing the portion of the gate dielectric layer 43 exposed by the gate line 45.

[0052] exist Figures 5A-5D In this process, a sidewall spacer 41 is formed, which includes a first spacer 41A and a second spacer 41B located on the first spacer 41. (See reference) Figure 5A and Figure 5B According to some embodiments, forming the sidewall spacer 41 may include removing portions of the spacer layers 41A', 41B' located between the gate lines 45 by one or more anisotropic etching processes. In some embodiments, the sidewall spacer 41 has an upper surface recessed from the upper surface of the gate line 45. For example, the gate line 45 may protrude upward from the sidewall spacer.

[0053] exist Figure 5CIn some embodiments, the substrate 110 exposed by the sidewall spacer 41 is lightly etched, which may also be referred to as over-etching. As a result, a first portion of the substrate 110 directly below the sidewall spacer 41, the gate dielectric layer 43, and the gate line 45 has an upper surface at a first level LV1, which is above a second level LV2 of the upper surface of the substrate 110 exposed by the sidewall spacer 41.

[0054] Figure 5C and Figure 5D An opening 50 is depicted between the sidewalls of the sidewall spacers 41 between adjacent pairs of gate lines 45. The opening 50 exposes a first exposed region 74 of the substrate 110. Because the opening 50 is relatively narrow in the X-axis direction due to its location between adjacent pairs of gate lines 45 of the RF device 20, the source / drain regions and silicide layer formed in the first exposed region 74 during subsequent operations may have high resistance, which could lead to device failure and low yield.

[0055] Figure 6A and Figure 6B A view showing the formation of source / drain electrodes 82A, 82B, 82C and ILD layer 130 is shown, corresponding to... Figure 12 Action 1206.

[0056] Source / drain regions 82A, 82B, and 82C can be formed by appropriate implantation operations to implant N-type or P-type dopants into exposed regions of substrate 110. For example, after forming sidewall spacers 41, the exposed surfaces of substrate 110 can be cleaned to remove contaminants or native oxides; this can include wet chemical cleaning (e.g., dilute HF) or plasma-based cleaning. Shallow low-energy ion implantation can then be performed to form lightly doped drain (LDD) or source / drain extension regions. For N-type MOS (NMOS) devices, dopants including phosphorus or arsenic can be implanted. For P-type MOS (PMOS) devices, dopants including boron or BF2 can be implanted. Gate line 45 and sidewall spacers 41 can be used as masks to improve alignment of the extensions with the gate edge. In some embodiments, low-temperature annealing can be performed to activate the dopants and repair implantation damage. Higher-energy, higher-dose ion implantation can then be performed to form heavily doped source / drain regions 82A, 82B, and 82C. In some embodiments, for NMOS devices, a higher dose (e.g., 10¹) can be used. 5 cm⁻² to 10¹ 6Arsenic or phosphorus can be implanted at a concentration of cm⁻². In some embodiments, boron or BF₂ can be implanted at a similar dose for PMOS devices. Gate line 45 and sidewall spacer 41 can again be used as a self-alignment mask, with the width of sidewall spacer 41 improving the offset of source / drain regions 82A, 82B, 82C from the corresponding channels. Implantation parameters (e.g., energy, dose, angle) can be selected to achieve selected junction depth, doping distribution, and sheet resistance. Thermal annealing can be performed to activate the implanted dopant (e.g., doping the dopant into the silicon lattice) and repair crystal damage caused by implantation. For example, rapid thermal annealing (RTA) can be performed, which includes a short high-temperature process (e.g., 900°C to 1100°C for several seconds) to reduce dopant diffusion. In some embodiments, shorter high-temperature pulses or “spiking annealing” can be performed to reduce diffusion. Laser or flash annealing, including rapid heating, can be performed to activate the dopant using a reduced thermal budget. The final cleaning step can remove any residue or surface damage from the injection or annealing process, preparing the source / drain regions 82A, 82B, and 82C for subsequent operations, which may include RPO deposition, silicide (self-aligned silicide) formation, and contact formation.

[0057] After the formation of source / drain regions 82A, 82B, and 82C, and before the formation of source / drain contacts 120, an RPO operation to form a resist protective oxide (RPO) can be performed. The RPO is not shown separately in the figure. The formation of the RPO can protect one or more regions from silicide formation in subsequent self-aligned polysilicide processes. The RPO can also act as a barrier during contact etching to prevent over-etching into sensitive areas. Thin oxide layers (e.g., 10 nm to 50 nm) can be deposited using plasma-enhanced chemical vapor deposition (PECVD), low-pressure CVD (LPCVD), or similar methods. Photolithography can then be performed to pattern a photoresist mask over areas where silicide formation is not selected (e.g., for high-resistivity polysilicon resistors or some selected source / drain regions). In areas where silicide formation is to be performed, such as in source / drain regions 82A, 82B, 82C, gate line 45, or both, the RPO layer can be selectively etched (e.g., using dry etching, such as reactive ion etching). Strip the photoresist, leaving the RPO in the protected area.

[0058] After RPO formation, self-aligned silicide (salicide) formation can be performed. Forming silicide layers 118A, 118B, 118C and an optional gate silicide layer 128 (which may be a self-aligned silicide or "salicide") can reduce the sheet resistance of the source / drain regions 82A, 82B, 82C and the gate line 45 by forming a low-resistance metal silicide layer (e.g., NiSi, TiSi2, or CoSi2) on the exposed silicon or polysilicon surface. This improves contact performance and signal propagation. In some embodiments, silicide layers 118A, 118B, 118C and gate silicide layer 128 are one or more of the following or include one or more of the following: nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. For example, silicide layer 118 and gate silicide layer 128 may be TiSi, TiNiSi, NiSi, WSi, CoSi, MoSi, RuSi, etc. In some embodiments, silicide layers 118A, 118B, and 118C form source / drain contact openings 59 and gate contact openings in the ILD layer 130 (e.g., see...). Figures 8A-8D It is formed after and before the formation of the source / drain contact 120 and the gate contact 124C.

[0059] The formation of silicide layers 118A, 118B, 118C and gate silicide layer 128 may include surface treatments, such as cleaning the wafer on which device 10 is formed, for example, using dilute HF to remove native oxides from exposed source / drain regions 82A, 82B, 82C and gate line 45, improving the cleanliness of the silicon surface. A thin layer of metal (e.g., nickel, titanium, or cobalt) can then be deposited over the entire wafer containing IC device 10 by physical vapor deposition (PVD), sputtering, or another suitable operation. Low-temperature annealing (e.g., 400°C to 600°C for NiSi) can be performed to react the metal with the exposed silicon / polysilicon, forming silicide layers in the source / drain regions 82A, 82B, 82C and gate line 45. RPO can prevent silicide formation in the protected areas. Unreacted metal can then be removed (e.g., on RPO, spacers, or other dielectric surfaces) by wet etching, which includes, for example, a mixture of H2SO4 and H2O2 for nickel, or another suitable mixture for titanium, cobalt, etc. Annealing at a higher temperature (e.g., 700°C to 800°C for NiSi) can then be performed to stabilize the silicide phase and reduce its resistivity.

[0060] exist Figures 7A-7D In the process, after forming silicide layers 118A, 118B, and 118C, the gate line 45 can be optionally replaced to form a high-k metal gate (HKMG) structure 200, or simply "gate structure 200".

[0061] exist Figure 7A and Figure 7B In this process, gate line 45 is removed using an appropriate removal process. Removal of gate line 45 may follow the steps of: (1) forming gate line 45 and sidewall spacers 41, (2) implanting source / drain regions 82A, 82B, 82C and annealing them, (3) forming ILD layer 130, and (4) exposing the planarization of the top of gate line 45 (e.g., by chemical mechanical polishing, CMP). The removal process may include an etching process that forms trench 57 by removing gate line 45. The etching process may include highly selective wet or dry etching to remove the polysilicon of gate line 45. In some embodiments, the etching process includes wet etching, for example using a solution based on tetramethylammonium hydroxide (TMAH) or ammonium hydroxide (NH4OH), which selectively etches the polysilicon of gate line 45 relative to the materials of ILD layer 130 and sidewall spacers 41. In some embodiments, the etching process includes dry etching, such as reactive ion etching (RIE) using chlorine-based (Cl2) or fluorine-based (SF6) precursors selected for high selectivity of the polysilicon at gate line 45. The etching process can be stopped at gate dielectric 43. As a result, trench 57 is formed between the walls of sidewall spacers 41, and the channel region (e.g., substrate 110) is protected by gate dielectric 43 at the bottom. Post-etching cleaning (e.g., using dilute HF or piranha solution) removes residues and prepares trench 57 for subsequent deposition.

[0062] In some embodiments, the gate dielectric 43 may be removed prior to the formation of the HKMG. For example, the gate dielectric 43 may be a thin SiO2 layer at the bottom of the trench 57, which can be removed by etching with dilute HF (hydrofluoric acid) to expose the substrate 110. A thin interface layer (IL) (which may be SiO2, SiON, or another suitable material) is then grown or deposited to improve the interface quality between the channel 22 and the high-k dielectric layer 600 deposited in subsequent operations. The IL can be formed by controlled oxidation in an O2 environment to grow the thin SiO2 layer, for example, by using ozone or H2O2 to form a uniform IL. The IL can reduce interface traps and improve mobility.

[0063] After forming trench 57 and optionally removing gate dielectric 43, a high-k dielectric layer 600 is formed to reduce current leakage and increase capacitance. In some embodiments, dielectric layer 600 comprises one or more high-k materials, which may be or include hafnium-based dielectrics (e.g., HfO2, HfSiO4), zirconium-based dielectrics (e.g., ZrO2), or another suitable dielectric. High-k dielectric layer 600 can be formed by deposition processes including atomic layer deposition (ALD), CVD, etc. The thickness of high-k dielectric layer 600 may be in the range of about 1 nm to about 3 nm, or another suitable thickness. After depositing high-k dielectric layer 600, low-temperature annealing (e.g., 400-600°C in N2 or O2) may be performed to densify high-k dielectric layer 600 and reduce its defects. High-k dielectric layer 600 may be located on the optional gate dielectric layer 43 or the underlying substrate 110 and on the sidewalls of sidewall spacers 41.

[0064] After forming a high-k dielectric layer 600 in trench 57, a metal layer 290 is formed in trench 57 above the high-k dielectric layer 600. In some embodiments, different metals can be selected for NMOS and PMOS transistors to achieve appropriate work functions. For example, in an NMOS device, the metal layer 290 may be or comprise one or more metals having a work function close to that of the silicon conduction band (~4.1-4.3 eV), such as TiAl, TaN, or Al-doped TiN. In another example, in a PMOS device, the metal layer 290 may be or comprise one or more metals having a work function close to that of the silicon valence band (~5.0-5.2 eV), such as TiN, TaN, or Mo. In some embodiments, the metal layer 290 comprises a stack of multiple layers, which facilitates the selection of work functions and improves compatibility with the high-k dielectric layer 600. In some embodiments, the metal layer 290 is formed by one or more deposition processes, which may include ALD or PVD. In some embodiments, a work function metal is not formed.

[0065] After optionally forming one or more work function metal layers, the formation of metal layer 290 may include forming a low-resistivity filler metal, which may be or include one or more of tungsten (W), aluminum (Al), cobalt (Co), etc., which can benefit from low resistivity and good filling performance. The formation of metal layer 290 may include CVD, PVD, ALD, etc. In some embodiments, an optional barrier layer or liner layer (e.g., 1-2 nm TiN or TaN) may be deposited prior to the deposition of the filler metal to prevent diffusion and improve its adhesion. It should be understood that "filling" includes both partial filling and complete filling.

[0066] After the metal layer 290 is formed, planarization, such as CMP, can be performed to remove excess metal and high-k material from the metal layer 290 and the high-k dielectric layer 600, thereby isolating the gate structure 200 and planarizing its upper surface. Planarization can be stopped at the upper surface of the ILD layer 130, leaving the HKMG stack of the gate structure 200 within the trench 57 between the walls of the sidewall spacers 41.

[0067] exist Figures 8A-8D In the middle, source / drain contacts 120 are formed on the source / drain regions 82A, 82B, and 82C.

[0068] exist Figure 8A and Figure 8B In the ILD layer 130, source / drain openings 59 are formed to expose silicide regions 118A, 118B, and 118C on source / drain regions 82A, 82B, and 82C. Source / drain openings 59 are formed in the ILD layer 130 after the formation of the ILD layer 130 and the replacement gate structure 200. Source / drain openings 59 can be formed by an etching process, which can be or includes a reactive ion etching (RIE) process using fluorocarbon-based chemicals (e.g., CF4, CHF3, or C4F8) to etch through the ILD layer 130 to expose the silicide regions 118A, 118B, and 118C on the source / drain regions 82A, 82B, and 82C. The etching can be anisotropic, which allows the vertical sidewalls of the ILD layer 130 to be exposed by the source / drain openings 59. Following the RIE process, wet cleaning (e.g., dilute HF) or plasma stripping can be performed to remove polymer residues and native oxides from the surfaces of the silicide regions 118A, 118B, 118C, thereby improving (e.g., reducing) contact resistance. In some embodiments, the silicide layers 118A, 118B, 118C form source / drain contact openings 59 and gate contact openings in the ILD layer 130 (e.g., see...). Figures 8A-8D It is formed after and before the formation of the source / drain contact 120 and the gate contact 124C.

[0069] exist Figure 8C and Figure 8DIn the process, an optional barrier layer may be deposited in the source / drain opening 59. This barrier layer may include a thin Ti / TiN stack to improve adhesion, reduce contact resistance, and reduce diffusion of the fill metal of the source / drain contact 120. The Ti layer may be deposited by physical vapor deposition (PVD), ionized PVD, or chemical vapor deposition (CVD). A TiN layer may then be deposited by PVD, CVD, or ALD. A fill metal layer, including tungsten (W) or another suitable metal, may then be deposited by CVD (e.g., using a WF6 precursor) to fill the source / drain opening 59. In some embodiments, forming the fill metal layer may include a nucleation operation in which a thin W seed layer is deposited (e.g., by reduction with silane or B2H6) to initiate uniform growth. A WF6-based CVD may then be performed to fill the source / drain opening 59. Planarization, such as CMP, may be performed to remove excess W and barrier material and planarize the wafer surface to isolate the source / drain contact 120 and to prepare for the formation of a reference. Figure 1A-1D The interconnection structure 140 described is prepared for interconnection.

[0070] Figures 9A-9F Schematic plan view and cross-sectional view of IC device 10 according to some embodiments are shown. Figure 9A A plan view of IC device 10 is shown. Figure 9B IC device 10 is shown along Figure 9A A side view of the cross section of line BB. Figure 9C IC device 10 is shown along Figure 9A A side view of the cross section of line CC. Figure 9D IC device 10 is shown along Figure 9A A side view of the cross section of line DD. Figure 9E IC device 10 is shown along Figure 9A A side view of the cross section of line EE.

[0071] exist Figure 9A In this process, after forming source / drain contacts 120 on the source / drain 82, a first gate contact 124S and a second gate contact 124C are formed on the gate structure 200C. The first gate contact 124S is formed on the gate structure 200C and overlaps with the isolation structure 36. The second gate contact 124C is formed on the gate structure 200C and overlaps with the active region 52.

[0072] Figure 9BA second gate contact 124C is shown on two gate structures 200C according to various embodiments. In some embodiments, an etch stop layer (ESL) 133 is formed on the ILD layer 130, spacer 41, and metal layer 290 prior to the formation of the second gate contact 124C. A second ILD layer 132 is then formed on the ESL 133. The ESL 133 may be or includes a dielectric layer, such as a SiN layer or other suitable dielectric layer. The second ILD layer 132 may be or includes another dielectric layer, which may be or includes the following: low-k dielectric, silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), porous dielectric materials, etc. In some embodiments, the second ILD layer 132 may be formed by a high-density plasma (HDP) CVD process or another suitable process. For example, the second ILD layer 132 may be an HDP PSG.

[0073] Then, a gate contact opening can be formed, extending through the second ILD layer 132 and ESL 133, and partially entering the metal layer 290 of the gate structure 200C. A source / drain via opening can also be formed above the source / drain contact 120, corresponding to... Figure 12 Action 1208. The gate contact opening may include forming an opening located on the gate structure 200C and overlapping with the isolation structure 36, and an opening located on the gate architecture 200C and overlapping with the active region 52. The formation of the gate contact opening may include a suitable etching operation, such as anisotropic dry etching, which can remove material from the second ILD layer 132 and extend the gate contact opening into the metal layer 290 by removing material from the metal layer 290. After the etching operation, wet cleaning may be performed. As a result of performing wet cleaning, lateral etching may occur at the bottom of the gate contact opening, which will increase the width of the gate contact opening along the Y-axis direction. That is, performing wet cleaning after the dry etching that forms the contact opening may result in lateral etching at the bottom of the gate contact opening. For example, wet cleaning may be anisotropic etching that removes material from the metal layer 290 and the high-k dielectric layer 600 along the Y-axis direction, which is not limited by the sidewall spacer 41. Figure 9D As shown in the view, this can cause the width of the lower portion 1242 of the first gate contact 124S and the second gate contact 124C to exceed the width of the upper portion 1241 of the first gate contact 124S and the second gate contact 124C at the interface between the upper portion 1241 and the lower portion 1242. The etching of the gate contact opening can be limited along the X-axis direction by the sidewall spacer 41, which can act as a lateral etching stop when removing material from the metal layer 290.

[0074] After forming the gate contact opening, a second gate contact 124C (and a first gate contact 124S) are formed in the gate contact opening, and a source / drain via 122 is formed in the source / drain via opening (see [link]). Figure 9E ), corresponding to Figure 12 Actions 1210 and 1212. In some embodiments, actions 1210 and 1212 may be performed simultaneously. The formation of the first gate contact 124S and the second gate contact 124C may include forming a liner layer and a metal fill layer, which may be similar in many respects to the reference. Figures 8A-8D The formation of the source / drain contact 120 is described. In some embodiments, the first gate contact 124S and the second gate contact 124C may be or include one or more layers of Ti, TiN, tungsten, aluminum, copper, cobalt, etc. These layers can be formed by suitable deposition processes, such as PVD, CVD, or ALD. The first gate contact 124S and the second gate contact 124C may inherit the shape of the gate contact opening. Therefore, as Figure 9B As shown, the first gate contact 124S and the second gate contact 124C can contact the sidewall spacer 41 along the X-axis direction (e.g., direct contact).

[0075] Figure 9C A second gate contact 124C is shown on the gate structure 200C, while the first dummy gate structure 200B and the second dummy gate structure 200A do not have a second gate contact 124C. In some embodiments, the gate structure 200C includes a gate line 45 instead of a metal layer 290, as shown.

[0076] Figure 9D One of the second gate contact 124C and the first gate contact 124S is shown on and within a metal layer 290 of one of the gate structures 200C. (See reference...) Figure 9A The gate contact opening can extend into the metal layer 290, stop on the sidewall spacer 41 along the X-axis, and extend laterally along the Y-axis. The first gate contact 124S and the second gate contact 124C can inherit the shape of the gate contact opening. For example, the first gate contact 124S and the second gate contact 124C can each have an upper portion 1241 extending through the second ILD layer 132 and into the metal layer 290. The first gate contact 124S and the second gate contact 124C can each have a lower portion 1242 embedded in the metal layer 290 and extending laterally along the Y-axis.

[0077] Figure 9EA source / drain via 122 is shown formed on each corresponding source / drain contact 120. Each source / drain via 122 may extend through the second ILD layer 132 and be located on the corresponding source / drain contact 120. The formation of the source / drain via 122 may, in most respects, be similar to the formation of the source / drain contact 120 and / or the formation of the first gate contact 124S and the second gate contact 124C.

[0078] After forming the source / drain vias 122, the first gate contact 124S, and the second gate contact 124C, which can be formed in the same (one or more) operations, an interconnect structure 140 can be formed thereon.

[0079] Figure 9F A detailed plan view of a region of an IC device 10 according to some embodiments is shown.

[0080] exist Figure 9F In this configuration, each of the first gate contact 124S and the second gate contact 124C has a first dimension (e.g., width) F1 along the X-axis and a second dimension (e.g., length) F2 along the Y-axis. In some embodiments, the first dimension F1 is substantially equal to the length A1 of the gate structure 200C, and the first gate contact 124S and the second gate contact 124C are located on the gate structure 200C. In some embodiments, the first dimension F1 is different from (e.g., less than) the length A1. In some embodiments, the length A1 is in the range of about 20 nanometers to about 0.18 micrometers. In some embodiments, the first dimension F1 and the second dimension F2 are each in the range of about 20 nanometers to about 0.1 micrometers. In some embodiments, the first dimension F1 and the second dimension F2 are substantially equal to each other, such that the first gate contact 124S and the second gate contact 124C have a square outline in a plan view. In some embodiments, the first gate contact 124S and the second gate contact 124C have an outline of another shape other than a square in a plan view, such as a rectangle, a circle, an ellipse, etc. In some embodiments, the spacing E along the Y-axis between adjacent pairs of first gate contacts 124S and / or second gate contacts 124C is in the range of about 0.3 micrometers to about 30 micrometers, and typically exceeds about 0.3 micrometers.

[0081] Each source / drain contact 120 has a first dimension (e.g., width) G1 along the X-axis and a second dimension (e.g., length) G2 along the Y-axis. In some embodiments, the second dimension G2 exceeds the first dimension G1, such that the source / drain contact 120 has a rectangular profile in a planar view. In some embodiments, the first dimension G1 and the second dimension G2 are each in the range of about 20 nanometers to about 0.1 micrometers. Each source / drain contact 120 may be spaced apart by a dimension C along the X-axis from an adjacent gate structure 200C. In some embodiments, the dimension C exceeds about half of the first dimension G1. For example, the first dimension G1 (e.g., width) of the source / drain contact 120 may be about 20 nanometers, and the source / drain contact 120 may be spaced apart from the gate structure 200C by at least 10 nanometers. In another example, the source / drain contact 120 may have a first dimension G1 of about 100 nanometers and may be spaced apart from the gate structure 200C by at least 50 nanometers.

[0082] The spacing distance K between each of the source / drain contacts 120 and its nearest one or more second gate contacts 124C can be selected based on dimension C and dimension B3. In some embodiments, dimension B3 is the spacing between the source / drain contacts 120 and the second gate contacts 124C along the Y-axis. For example, the second gate contact 124C may have a dimension F (e.g., length) along the Y-axis between its first sidewall 124Ca and its second sidewall 124Cb. In some embodiments, dimension F may be the same as a second dimension F2. Dimension B3 may be the distance between the projections of the sidewall 120a and the first sidewall 124Ca of the first source / drain contact 1201 and / or the distance between the projections of the sidewall 120b and the second sidewall 124Cb of the second source / drain contact 1203. The spacing distance K can be calculated using the following equation: In some embodiments, the interval distance K exceeds the smallest of the first size F1, the second size F2, the first size G1, and the second size G2.

[0083] An example is provided to understand the spacing distance K. In this example, the first dimension G1 (e.g., width) of the source / drain contact 120 can be the smallest dimension and can be about 20 nanometers. Therefore, the dimension C that separates the source / drain contact 120 from the gate structure 200C can be about 10 nanometers. However, since the first dimension G1, as the smallest dimension, is about 20 nanometers, the spacing distance K also exceeds about 20 nanometers. That is, the spacing distance K exceeds the dimension C. As a result, there is a forbidden region 1250 depicted by dashed lines above the active region 52 immediately adjacent to the second gate contact 124C. That is, the dimension B3 of the source / drain contact 120 offset from the second gate contact 124C in the Y-axis direction exceeds zero to ensure that there is a sufficient distance (e.g., equal to or greater than the spacing distance K) between the source / drain contact 120 and the nearest second gate contact 124C. Therefore, when the smallest dimension among the first dimension F1, the second dimension F2, the first dimension G1 and the second dimension G2 exceeds dimension C, the source / drain contact 120 does not overlap with the second gate contact 124C and is offset from it along the Y-axis direction.

[0084] Figure 9F Dimension D3 is also depicted, which is the spacing between the source / drain contact 120 and the isolation structure 36. In some embodiments, dimension D3 is in the range of about 20 nanometers to about 0.1 micrometers.

[0085] Figure 9F Dimension A2 is also depicted, which is the width of the active region 52 along the Y-axis. In some embodiments, dimension A2 ranges from about 0.5 micrometers to about 12 micrometers.

[0086] Figure 10A-10F Plan view and cross-sectional side view of IC device 10 according to various embodiments are shown. Reference Figure 10A-10F The described embodiments can be compared with the references Figures 1A to 9F The described embodiments are combined.

[0087] exist Figure 10A In this embodiment, IC device 10 includes an active gate structure 200C and no first dummy gate structure 200B and / or second dummy gate structure 200A. Therefore, at least two active gate structures 200C can be adjacent to opposite sides of the isolation structure 36 without any additional gate structure (e.g., the first dummy gate structure 200B) in between. The isolation structure 36, which laterally surrounds the gate structure 200C and the active region 52, may have no gate structure (e.g., the second dummy gate structure 200A), except for an extension of the gate structure 200C that overlaps with the isolation structure 36.

[0088] exist Figure 10BIn the IC device 10, there are a first gate contact 124S, a second gate contact 124C, and a source / drain contact 120, which are elliptical or oval in plan view, rather than square or rectangular. Figure 10B The embodiments can be related to Figure 10A The embodiments are combined to include an elliptical first gate contact 124S, a second gate contact 124C, and a source / drain contact 120, omitting the first dummy gate structure 200B and the second dummy gate structure 200A. In some embodiments, the first gate contact 124S and the second gate contact 124C extend along the X-axis, and the source / drain contact 120 extends along the Y-axis. The width of the second gate contact 124C in the X-axis direction may exceed the length of the gate structure 200C in the X-axis direction, such that the second gate contact 124C may overlap with and extend beyond the opposite sidewall of the corresponding gate structure 200C on which the second gate contact 124C is located. Figure 10B As shown, the second gate contact 124C with an enlarged elliptical shape in the plan view can reduce the gate resistance, which can increase the f of the IC device 10. max The elliptical shape can also increase the area of ​​the first gate contact 124S, the second gate contact 124C, and the source / drain contact 120, while maintaining the reference area. Figure 9F The interval distance K is described.

[0089] exist Figure 10C In the IC device 10, there are a first gate contact 124S, a second gate contact 124C, and a source / drain contact 120, which are elliptical or oval in plan view, rather than square or rectangular. Figure 10C The embodiments can be related to Figure 10A The embodiments are combined to include an elliptical first gate contact 124S, a second gate contact 124C, and a source / drain contact 120, omitting the first dummy gate structure 200B and the second dummy gate structure 200A. In some embodiments, the first gate contact 124S, the second gate contact 124C, and the source / drain contact 120 extend along the Y-axis direction.

[0090] exist Figure 10D In the IC device 10, there are a first gate contact 124S, a second gate contact 124C, and a source / drain contact 120, which are elliptical or oval in plan view, rather than square or rectangular. Figure 10D The embodiments can be related to Figure 10AThe embodiments are combined to include an elliptical first gate contact 124S, a second gate contact 124C, and a source / drain contact 120, omitting the first dummy gate structure 200B and the second dummy gate structure 200A. In some embodiments, the first gate contact 124S extends along the Y-axis and partially overlaps with the corresponding gate structure 200C. For example, the first gate contact 124S may have increased dimensions in both the X-axis and Y-axis directions, and a portion of each first gate contact 124S may overlap with the active region 52. Increasing the contact area of ​​the first gate contact 124S can reduce the gate resistance, which can increase the f of the IC device 10. max .

[0091] Figure 10E The second gate contact 124C is shown along Figure 10A Detailed cross-sectional view of line EE. Figure 10F The second gate contact 124C is shown along Figure 10B Detailed cross-sectional view of line FF.

[0092] exist Figure 10E In this embodiment, the second gate contact 124C includes a first portion 1241 located above the sidewall spacer 41 and a second portion 1242 located below the first portion 1241. In some embodiments, the first portion 1241 does not extend laterally beyond the sidewall spacer 41 in the X-axis direction. The second portion 1242 may extend from one of the sidewall spacers 41 to the other of the sidewall spacers 41. Before forming the second gate contact 124C, a metal layer 290 replacing the gate structure 200C may extend from the dielectric layer 600 to the upper surface of the sidewall spacer 41, such as... Figure 10EThe first height H1 and the dashed line are shown in the figure. After the second gate contact 124C is formed, the metal layer 290 may have a second height H2 that is smaller than the first height H1 because some material of the metal layer 290 is removed during etching of the opening in which the second gate contact 124C is formed. In some embodiments, the ratio of the second height H2 to the first height H1 is in the range of about 5% to about 90%. That is, the amount of metal layer 290 removed may be in the range of about 10% to about 95% of the first height H1. In some embodiments, the amount of metal layer 290 removed when forming the first gate contact 124S located above the isolation region 36 is in the range of about 5% to 90% of the first height H1. In some embodiments, the remaining thickness of the metal layer 290 below the first gate contact 124S and the second gate contact 124C is in the range of about 0 nanometers to about 300 nanometers. In some embodiments, the metal layer 290 overlapping with the first gate contact 124S or the second gate contact 124C is completely removed, so that the first gate contact 124S or the third gate contact 124C is in direct contact with the dielectric layer 600.

[0093] Although reference Figure 10E The described embodiments include a metal layer 290, but in some embodiments, the dielectric layer 600 and the metal layer 290 are absent, and instead, gate lines 45 are present between the first gate contact 124S, the second gate contact 124C and the substrate 110 and / or the gate dielectric layer 43.

[0094] Figure 10F The second gate contact 124C is shown, which has the following configuration in the plan view as referenced. Figure 10B The described elliptical profile. In some embodiments, the second gate contact 124C has an elliptical shape in a plan view, and the sidewall spacer 41 has a second width W2 that exceeds the first width W1 of the sidewall spacer 41 associated with the second gate contact 124C, which has a square or rectangular shape in a plan view.

[0095] Figure 11A-11C A plan view of an IC device 10 according to some embodiments is shown.

[0096] exist Figure 11A In some embodiments, the IC device 10 includes a logic device 12 and an RF device 14. The IC device 10 may include a substrate 110 and an isolation structure 36 located in the substrate 110. Figure 11A(Not separately marked) and one or more active regions 52 defined in the substrate 110, the active regions 52 being laterally surrounded by one or more isolation structures 36. In some embodiments, the RF device 14 is operable to receive and / or transmit a first electrical signal at a first operating frequency, which may be in the range of about 30 GHz to about 200 GHz, for example, with the f of the RF device 14. max Relatedly, the f max Within the range of approximately 300 GHz to approximately 400 GHz. In some embodiments, the logic device 12 is operable to receive and / or transmit a second electrical signal at a second operating frequency, which may be in the range of approximately 1 GHz to approximately 10 GHz.

[0097] RF device 14 may include a first gate structure 200C1 (or a first gate line 45) extending along a first direction (e.g., the Y-axis direction), located on substrate 110, and overlapping with active region 52 and isolation structure 36. RF device 14 may include a second gate structure 200C2 (or a second gate line 45) adjacent to the first gate structure 200C1 or the first gate line 45 along a second direction traversing the first direction (e.g., the X-axis direction). The second gate structure 200C2 or the second gate line 45 extends along the first direction, located on substrate 110, and overlaps with active region 52 and isolation structure 36.

[0098] RF device 14 may include one or more first gate contacts 124S located on the first gate structure 200C1 or the first gate line 45 and overlapping with the isolation structure 36. RF device 14 may include one or more second gate contacts 124C located on the first gate structure 200C1 or the first gate line 45 and overlapping with the active region 52. RF device 14 may include one or more third gate contacts 124S located on the second gate structure 200C2 or the second gate line 45 and overlapping with the isolation structure 36. RF device 14 may include one or more fourth gate contacts 124C located on the second gate structure 200C2 or the second gate line 45 and overlapping with the active region 52. RF device 14 includes source / drain contacts 120 located on the active region 52.

[0099] RF device 14 includes portions of a metal layer 129, which may be a first metal (M1) layer immediately above a bottom metal layer (e.g., M0), with a first gate contact 124S, a second gate contact 124C, and a source / drain via 122 located within this bottom metal layer. In some embodiments, the metal layer 129 may be a second metal layer (M2), a third metal layer (M3), or other metal layers located above but not immediately adjacent to the bottom metal layer, and having other intermediate metal layers (e.g., M1, M2, M3, etc.) between them. RF device 14 includes a first portion 129Y of the metal layer 129 extending along a first direction (e.g., the Y-axis direction) and overlapping with the isolation structure 36. RF device 14 includes one or more second portions 129PU1, 129PU2 of the metal layer 129, which may be first pickup portions extending from the first portion 129Y along a second direction (e.g., the X-axis direction). The second portions 129PU1 and 129PU2 overlap with one or more first gate contacts 124S on the first gate structure 200C1 and one or more third gate contacts 124S on the second gate structure 200C2. The RF device 14 includes a third portion 129PU3 of the metal layer 129, which may be a second pickup portion extending from the first portion 129Y along a second direction and overlapping with one or more second gate contacts 124C on the first gate structure 200C1 and one or more fourth gate contacts 124C on the second gate structure 200C2. The third portion 129PU3 overlaps with the active region 52 and may have a region overlapping with the isolation structure 36.

[0100] Logic device 12 may be similar to RF device 14 in many respects. For example, logic device 12 may include a second active region 52L and a gate structure 200C extending across the second active region 52L. Logic device 12 may include one or more fifth gate contacts 124SL on the gate structure 200C that overlap with isolation structure 36 and one or more sixth gate contacts 124CL on the gate structure 200C that overlap with active region 52L. Logic device 12 includes a fourth portion 129YL of metal layer 129 extending in a first direction (e.g., the Y-axis direction). Logic device 12 includes one or more fifth portions 129PU4, 129PU5 of metal layer 129, which may be third pickup portions, extending from fourth portion 129YL in a second direction (e.g., the X-axis direction). The fifth portions 129PU4, 129PU5 overlap with one or more fifth gate contacts 124SL(on) on gate structure 200C and overlap with isolation structure 36. The logic device 12 includes a sixth portion 129PU6 of a metal layer 129 extending from the fourth portion 129YL along a second direction and overlapping with one or more sixth gate contacts 124CL on the gate structure 200C. The sixth portion 129PU6 overlaps with the active region 52 and may have a region overlapping with the isolation structure 36. The logic device 12 includes source / drain contacts 120 on the second active region 52L.

[0101] Figure 11B An IC device 10 is shown, in which the gate structure 200C of the logic device 12 has no gate contact (e.g., (one or more) sixth gate contact 124CL), and the sixth part 129PU6 is omitted.

[0102] Figure 11C An IC device 10 is shown in which the first gate structure 200C1 and / or the second gate structure 200C2 of the RF device 14 have no gate contacts (e.g., one or more second gate contacts 124C and / or one or more fourth gate contacts 124C), and the third part 129PU3 is omitted.

[0103] One or more embodiments relate to a computer-readable medium comprising processor-executable instructions configured to implement one or more technologies presented herein. Figure 13Exemplary computer-readable media are illustrated herein, wherein embodiment 90 includes a computer-readable medium 908 (e.g., a CD-R, DVD-R, flash drive, hard disk platter, etc.) encoded thereon with computer-readable data 906. This computer-readable data 906 further includes a set of processor-executable computer instructions 904 configured to implement one or more principles described herein when executed by a processor. In some embodiments 90, the processor-executable computer instructions 904 are configured to implement method 902, such as at least some of the methods(s) described above, when executed by a processor. In some embodiments, the processor-executable computer instructions 904 are configured to implement a system, such as at least some of the systems described above, when executed by a processor. Many such computer-readable media can be designed by those skilled in the art and configured to operate according to the techniques presented herein.

[0104] In some embodiments, a device is provided. The device includes: a substrate; an isolation structure located in the substrate; an active region defined in the substrate, the active region being laterally surrounded by the isolation structure; a first gate line extending in a first direction, the first gate line being located on the substrate and overlapping the active region and the isolation structure; a second gate line adjacent to the first gate line along a second direction traversing the first direction, the second gate line extending in the first direction, the second gate line being located on the substrate and overlapping the active region and the isolation structure; a first contact located on the first gate line and overlapping the isolation structure; a second contact located on the first gate line and overlapping the active region; a third contact located on the second gate line and overlapping the isolation structure; a fourth contact located on the second gate line and overlapping the active region; and a metal layer. The metal layer includes: a first portion extending along the first direction and overlapping the isolation structure; a second portion extending from the first portion along the second direction and overlapping the first and third contacts; and a third portion extending from the first portion along the second direction and overlapping the second and fourth contacts.

[0105] In some embodiments, a device is provided. The device includes a logic device and a radio frequency (RF) device. The logic device includes: a first gate line overlapping a first active region of a substrate and an isolation structure adjacent to the first active region; a first source / drain located in the substrate, immediately adjacent to the first gate line; and a first contact located on the first gate line and overlapping the isolation structure. The RF device includes: a second gate line overlapping a second active region of the substrate, the second active region being separated from the first active region by the isolation structure; a second source / drain located in the substrate, immediately adjacent to the second gate line; a second contact located on the second gate line and overlapping the isolation structure; and a third contact located on the second gate line and overlapping the second active region.

[0106] In some embodiments, a method is provided. The method includes: forming a first active region of a substrate, including forming an isolation structure in the substrate, the isolation structure being adjacent to the first active region; forming a first gate line extending along a first direction and overlapping the first active region and the isolation structure; forming a first source / drain adjacent to the first gate line in the first active region; forming a first opening, a second opening, and a third opening in a dielectric layer exposed by a mask layer, the first opening overlapping the first gate line and the isolation structure, the second opening overlapping the first gate line and the first active region, and the third opening overlapping the first source / drain; forming a first contact in the first opening and a third contact in the third opening; and reducing the alternating current (AC) resistance of the first gate line by forming a second contact in the second opening.

[0107] Although the subject matter has been described in language specific to structural features or methodological actions, it should be understood that the subject matter of the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms for implementing at least some of the claims.

[0108] This document provides various operations of the embodiments. The order in which some or all of the operations are described should not be construed as implying that these operations necessarily depend on the order. Alternative orderings will be understood with the help of this specification. Furthermore, it should be understood that not all operations must exist in every embodiment provided herein. Additionally, it should be understood that in some embodiments, not all operations are necessary.

[0109] It should be understood that, for simplicity and ease of understanding, the layers, features, elements, etc., described herein are shown in specific dimensions (e.g., structural dimensions or orientations) relative to each other, and in some embodiments, their actual dimensions differ significantly from those shown herein. Furthermore, various techniques exist for forming the layers, regions, features, elements, etc. mentioned herein, such as at least one of etching, planarization, implantation, doping, spin coating, sputtering, growth, or deposition techniques (e.g., chemical vapor deposition (CVD)).

[0110] Furthermore, terms such as “exemplary” are used herein to indicate that something is used as an example, instance, illustration, etc., and are not necessarily advantageous. As used in this application, “or” is intended to indicate an inclusive “or” rather than an exclusive “or.” Furthermore, “a” and “an” as used in this application and the appended claims are generally interpreted as meaning “one or more” unless otherwise stated or clearly pointed to from the context as a single form. Furthermore, at least one of A and B generally refers to A or B or both A and B. Furthermore, within the scope of the use of “comprising,” “having,” “containing,” “with,” or variations thereof, these terms are intended to be inclusive in a manner similar to the term “comprising.” Furthermore, unless otherwise specified, “first,” “second,” etc., are not intended to imply temporal, spatial, or sequential aspects. Rather, these terms are used only as identifiers, names, etc., of features, elements, items, etc. For example, a first element and a second element generally correspond to element A and element B, or two different or two identical elements, or the same element.

[0111] Furthermore, although this disclosure has been shown and described with respect to one or more implementations, equivalent changes and modifications will be made by those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This disclosure includes all such modifications and changes and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components (e.g., elements, resources, etc.), unless otherwise stated, the terminology used to describe such components is intended to correspond to any component that performs the specified function of said component (e.g., functional equivalence), even if it is not structurally equivalent to the disclosed structure. Moreover, while a particular feature of this disclosure may be disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of other implementations, which may be desirable and advantageous for any given or particular application.

[0112] Example 1. A semiconductor device comprising: a substrate; an isolation structure located in the substrate; an active region defined in the substrate, the active region being laterally surrounded by the isolation structure; a first gate line extending in a first direction, the first gate line being located on the substrate and overlapping the active region and the isolation structure; a second gate line adjacent to the first gate line along a second direction traversing the first direction, the second gate line extending in the first direction, the second gate line being located on the substrate and overlapping the active region and the isolation structure; a first contact located on the first gate line and overlapping the isolation structure; and a second contact located on the first gate line and overlapping the active region.

[0113] Example 2. The device according to Example 1 includes: a first source / drain located on a first side of the first gate line between the first gate line and the second gate line; a second source / drain located on a second side of the first gate line opposite to the first side; and a fifth contact located on the second source / drain, the fifth contact having a fifth width along the second direction and a fifth length along the first direction.

[0114] Example 3. The device according to Example 2, wherein: the fifth contact is spaced apart from the first gate line by a first distance (C) along the second direction; the fifth contact is offset from the second contact by a second distance (B3) along the first direction; the second contact has a second width along the second direction and a second length along the first direction; and the shortest distance (K) between the fifth contact and the second contact is And exceeds the minimum value among the second width, the second length, the fifth width, and the fifth length.

[0115] Example 4. The device according to Example 3, wherein the first distance between the fifth contact and the first gate line exceeds approximately 50% of the fifth width of the fifth contact located on the second source / drain.

[0116] Example 5. The device according to Example 1, comprising: a sixth contact located on the first gate line and overlapping the isolation structure and the active region.

[0117] Example 6. The device according to Example 1, wherein the first gate line includes: a gate dielectric layer; and a metal layer located on the gate dielectric layer; wherein the second contact extends into the metal layer to a depth below the upper surface of the metal layer.

[0118] Example 7. The device according to Example 6, wherein the second contact has a bottom portion that extends laterally into the metal layer along the first direction.

[0119] Example 8. The device according to Example 1 further includes: a third contact located on the second gate line and overlapping the isolation structure; a fourth contact located on the second gate line and overlapping the active region; and a metal layer comprising: a first portion extending along the first direction and overlapping the isolation structure; a second portion extending from the first portion along the second direction and overlapping the first contact and the third contact; and a third portion extending from the first portion along the second direction and overlapping the second contact and the fourth contact.

[0120] Example 9. The device according to Example 1, wherein the second contact has an elliptical shape that extends along the second direction, and the second contact extends along the second direction beyond the outer wall of the first gate line.

[0121] Example 10. The device according to Example 1 includes: an active gate line adjacent to the first gate line along the second direction, the first gate line being located between the active gate line and the second gate line.

[0122] Example 11. A semiconductor device comprising: a first device including: a first gate line overlapping a first active region of a substrate and an isolation structure adjacent to the first active region; a first source / drain located in the substrate, immediately adjacent to the first gate line; and a first contact located on the first gate line and overlapping the isolation structure; and a second device including: a second gate line overlapping a second active region of the substrate, the second active region being separated from the first active region by the isolation structure; a second source / drain located in the substrate, immediately adjacent to the second gate line; a second contact located on the second gate line and overlapping the isolation structure; and a third contact located on the second gate line and overlapping the second active region.

[0123] Example 12. The device according to Example 11, wherein the first device includes: a fourth contact located on the first gate line and overlapping the first active region.

[0124] Example 13. The device according to Example 11, wherein the second device includes: a plurality of source / drain contacts arranged in a row, the row extending parallel to the second gate line and spaced apart from the second gate line by a first distance, each of the plurality of source / drain contacts being spaced apart from the third contact by a distance exceeding: the width of the corresponding source / drain contact, the length of the corresponding source / drain contact, the width of the second contact, and the length of the second contact.

[0125] Example 14. The device according to Example 11 includes: a first metal layer electrically coupled to and overlapping the first contact, and defining an opening that completely overlaps with the first active region; and a second metal layer electrically coupled to the second contact and the third contact, and having an extension that partially overlaps with the second active region and completely overlaps with the third contact.

[0126] Example 15. The device according to Example 14, wherein the second device includes: a third gate line overlapping the second active region of the substrate; a third source / drain located in the substrate adjacent to the third gate line; a fourth contact located on the third gate line and overlapping the isolation structure; and a fifth contact located on the third gate line and overlapping the second active region; wherein the extension portion of the second metal layer completely overlaps the fifth contact.

[0127] Example 16. A method of forming a semiconductor device, comprising: forming a first active region of a substrate, including forming an isolation structure in the substrate, the isolation structure being adjacent to the first active region; forming a first gate line extending along a first direction and overlapping the first active region and the isolation structure; forming a first source / drain in the first active region adjacent to the first gate line; forming a first opening, a second opening, and a third opening in a dielectric layer exposed by a mask layer, the first opening overlapping the first gate line and the isolation structure, the second opening overlapping the first gate line and the first active region, and the third opening overlapping the first source / drain; forming a first contact in the first opening and forming a third contact in the third opening; and forming a second contact in the second opening.

[0128] Example 17. The method according to Example 16, wherein forming the isolation structure includes forming a second active region adjacent to the first active region and separated from the first active region by the isolation structure, the method comprising: forming a second gate line extending along the first direction and overlapping the second active region and the isolation structure; and forming a fourth contact on the second gate line overlapping the isolation structure, and forming a fifth contact on the second gate line overlapping the second active region.

[0129] Example 18. The method according to Example 17 includes: forming a first metal layer electrically coupled to the first contact and the second contact, the first metal layer overlapping the second contact; and forming a second metal layer electrically coupled to the fourth contact and the fifth contact, the second metal layer overlapping the fifth contact.

[0130] Example 19. The method according to Example 16, wherein forming the first gate line includes: forming a sacrificial gate line comprising polysilicon; forming a sidewall spacer adjacent to the sacrificial gate line; forming an opening between the sidewall spacers by removing the sacrificial gate line when the sidewall spacers are in place; forming a dielectric layer in the opening; and forming a metal layer on the dielectric layer in the opening, wherein forming the second opening includes: performing a dry etching process that removes material from the metal layer exposed by the mask layer.

[0131] Example 20. The method according to Example 19, wherein forming the second opening comprises: forming the second opening having an elliptical shape by removing material from the sidewall spacer.

Claims

1. A semiconductor device, comprising: Substrate; An isolation structure is located within the substrate; An active region is defined in the substrate and is laterally surrounded by the isolation structure; A first gate line extends in a first direction, the first gate line being located on the substrate and overlapping the active region and the isolation structure; The second gate line is adjacent to the first gate line along a second direction that traverses the first direction. The second gate line extends in the first direction and is located on the substrate and overlaps with the active region and the isolation structure. The first contact is located on the first gate line and overlaps with the isolation structure; as well as The second contact is located on the first gate line and overlaps with the active region.

2. The device according to claim 1, comprising: The first source / drain is located on a first side of the first gate line between the first gate line and the second gate line; The second source / drain is located on the second side of the first gate line opposite to the first side; as well as A fifth contact is located on the second source / drain electrode, the fifth contact having a fifth width along the second direction and a fifth length along the first direction.

3. The device according to claim 2, wherein: The fifth contact is spaced apart from the first gate line by a first distance (C) along the second direction. The fifth contact is offset from the second contact by a second distance (B3) along the first direction. The second contact member has a second width along the second direction and a second length along the first direction; as well as The shortest distance (K) between the fifth contact and the second contact is And exceeds the minimum value among the second width, the second length, the fifth width, and the fifth length.

4. The device according to claim 3, wherein, The first distance between the fifth contact and the first gate line exceeds approximately 50% of the fifth width of the fifth contact located on the second source / drain.

5. The device according to claim 1, comprising: The sixth contact is located on the first gate line and overlaps with the isolation structure and the active region.

6. The device according to claim 1, wherein, The first gate line includes: Gate dielectric layer; and A metal layer is located on the gate dielectric layer; The second contact extends into the metal layer to a depth below the upper surface of the metal layer.

7. The device according to claim 6, wherein, The second contact has a bottom portion that extends laterally into the metal layer along the first direction.

8. The device according to claim 1, further comprising: The third contact is located on the second gate line and overlaps with the isolation structure; The fourth contact is located on the second gate line and overlaps with the active region; as well as Metal layer, including: The first part extends along the first direction and overlaps with the isolation structure; The second portion extends from the first portion along the second direction, and the second portion overlaps with the first contact and the third contact; and The third portion extends from the first portion along the second direction, and the third portion overlaps with the second contact and the fourth contact.

9. A semiconductor device, comprising: The first device includes: The first gate line overlaps with the first active region of the substrate and with the isolation structure adjacent to the first active region; The first source / drain is located in the substrate, adjacent to the first gate line; and A first contact element is located on the first gate line and overlaps with the isolation structure; and The second device includes: The second gate line overlaps with the second active region of the substrate, and the second active region is separated from the first active region by the isolation structure; The second source / drain is located in the substrate, adjacent to the second gate line; A second contact is located on the second gate line and overlaps with the isolation structure; and The third contact is located on the second gate line and overlaps with the second active region.

10. A method of forming a semiconductor device, comprising: Forming a first active region of a substrate includes forming an isolation structure in the substrate, the isolation structure being adjacent to the first active region; A first gate line is formed, which extends along a first direction and overlaps with the first active region and the isolation structure; A first source / drain adjacent to the first gate line is formed in the first active region; A first opening, a second opening, and a third opening are formed in the dielectric layer exposed by the mask layer. The first opening overlaps with the first gate line and the isolation structure, the second opening overlaps with the first gate line and the first active region, and the third opening overlaps with the first source / drain. A first contact is formed in the first opening, and a third contact is formed in the third opening; as well as A second contact is formed in the second opening.

Images