A MOSFET device structure

Abstract

This invention relates to the field of semiconductor manufacturing technology and provides a MOSFET device structure. The MOSFET device structure of this invention includes a semiconductor substrate with an active region defined by an isolation structure within the substrate. The active region has a first length in a first direction. A gate structure includes a polysilicon gate disposed on the surface of the semiconductor substrate and corresponding to the active region. The orthographic projection of the polysilicon gate onto the surface of the semiconductor substrate completely falls within the active region. The polysilicon gate has a second length in the first direction, the second length being less than the first length. This invention enables the implanted well doping to be located away from the isolation structure, effectively reducing or eliminating the "boron-attracting and phosphorus-removing" effect of the isolation structure on the well region. It also enables the effective channel to be located away from the isolation structure region, so that the corner morphology of the active region will not affect the device. This invention can eliminate or reduce the bimodal effect.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a MOSFET device structure that can improve the bimodal effect. Background Technology

[0002] A MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) is a transistor suitable for high-voltage, high-power circuit applications. It has two states, on and off, and is commonly used as a switching transistor in circuits. Current MOSFET devices generally use shallow trench isolation (STI) technology to define the active region, and the threshold voltage of the device is adjusted by well injection into the active region.

[0003] Please refer to the following: Figures 1-2 ,in, Figure 1 This is a top view of an existing MOSFET device structure. Figure 2 For along Figure 1 A cross-sectional view of line AA. Taking NMOS as an example, in a MOSFET device using STI technology, the portion of the gate (Poly) 131 extending beyond the active region (AA) 12 in the substrate 10 rests on the shallow trench isolation (STI) structure 11 in the substrate 10; the effective channel Lg0 within the active region 12 is relatively long. A parasitic MOSFET is formed at the corner region 101 (shown as a dashed box in the figure) between the shallow trench isolation structure 11 and the active region 12, while the main MOSFET is formed in the central channel region 102 (shown as a dashed box in the figure). The double-hump effect is the phenomenon where two peaks appear in the current-voltage (Id-Vg) characteristic curve when measuring the threshold voltage of the device.

[0004] The bimodal effect is mainly due to: (1) the non-uniformity in the MOSFET device structure, since the gate oxide layer 132 of the corner region 101 is thinner than that of the central region, the threshold voltage of the parasitic MOSFET is reduced; (2) the parasitic effect: the dopant (such as boron (B)) of the P-type well 109 in the substrate 10 diffuses into the shallow trench isolation structure 11, which reduces the doping concentration of the corner region 101, further widening the threshold voltage difference between the parasitic MOSFET and the main MOSFET. The non-uniformity and parasitic effect in the MOSFET device structure cause the parasitic MOSFET to turn on and saturate earlier due to the lower threshold voltage, forming the first peak (hump) on the current-voltage (Id-Vg) characteristic curve; the main MOSFET turns on at a higher gate voltage, forming the second peak.

[0005] The bimodal effect increases the swing of the subthreshold turn-on voltage and the static leakage current, which is highly detrimental to low-power applications. Existing improvement processes mainly focus on rounding the corner regions at the edge of the active region and compensating for boron diffusion direction by reverse doping. However, the former is technically challenging and its effectiveness is not ideal, while the latter, due to the compensating doping, has a significant impact on the electrical properties of short-channel devices.

[0006] Therefore, designing a new MOSFET device structure that can eliminate or reduce the bipeak effect is of great practical significance and is a technical problem that urgently needs to be solved. Summary of the Invention

[0007] The purpose of this invention is to provide a MOSFET device structure that can eliminate or reduce the bimodal effect.

[0008] To achieve the above objectives, the present invention provides a MOSFET device structure, comprising: a semiconductor substrate having an active region defined by an isolation structure therein, the active region having a first length in a first direction, wherein the first direction is parallel to the surface of the semiconductor substrate; and a gate structure including a polysilicon gate disposed on the surface of the semiconductor substrate and corresponding to the active region, wherein the orthogonal projection of the polysilicon gate on the surface of the semiconductor substrate completely falls within the active region, and the polysilicon gate having a second length in the first direction, the second length being less than the first length.

[0009] In some embodiments, the gate structure further includes a sidewall covering the sidewall of the polysilicon gate, wherein the orthogonal projection of the sidewall onto the surface of the semiconductor substrate in a first direction has a portion overlapping the isolation structure; wherein the first direction is parallel to the surface of the semiconductor substrate.

[0010] In some embodiments, in the first direction, there is a gap between the orthographic projection of the polysilicon gate onto the surface of the semiconductor substrate and the isolation structure, and the width of the sidewall is greater than the gap.

[0011] The above technical solution, by ensuring that the orthogonal projection of the polysilicon gate onto the semiconductor substrate surface completely falls within the active region, enables the implanted well doping to be kept away from the isolation structure, effectively reducing or eliminating the "boron absorption and phosphorus repulsion" effect of the isolation structure on the well region formed by the implanted well doping; it also ensures that the effective channel is kept away from the isolation structure region, so that the corner morphology of the active region will not affect the device. This invention can eliminate or reduce the bimodal effect. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a top view of an existing MOSFET device structure; Figure 2 For along Figure 1 Sectional view of line AA in the middle; Figure 3 This is a top view schematic diagram of the MOSFET device structure according to an embodiment of the present invention; Figure 4 For along Figure 3 Sectional view of line AA in the middle; Figure 5 For along Figure 3 A cross-sectional view along the BB line.

[0014] Explanation of reference numerals in the attached figures: 10. Substrate; 101. Corner area; 102. Central Region; 109. P-type trap; 11. Shallow trench isolation structure; 12. Active region; 131. Gate; 132. Gate oxide layer; 30. Semiconductor substrate; 309. Trap Zone; 31. Isolation structure; 32. Active region; 321. Source / Drain; 33. Gate structure; 331. Polysilicon gate; 332. Gate oxide layer; 333. Side walls; 3331, First sub-side wall; 3332, Second sub-side wall; 3333, Third sub-side wall; 35. Metal silicide layer; 36. Introduction structure. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] Please refer to the following: Figures 3-5 ,in, Figure 3 This is a top view schematic diagram of the MOSFET device structure according to an embodiment of the present invention; Figure 4 For along Figure 3 Sectional view of line AA in the middle; Figure 5 For along Figure 3 A cross-sectional view along the BB line.

[0017] like Figures 3-5 As shown, the MOSFET device structure described in this embodiment includes a semiconductor substrate 30, an isolation structure 31, an active region 32, and a gate structure 33.

[0018] Specifically, the semiconductor substrate 30 has an active region 32 defined by an isolation structure 31, and the active region 32 has a first length L1 in a first direction D1. The gate structure 33 includes a polysilicon gate 331, which is disposed on the surface of the semiconductor substrate 30 and corresponds to the active region 32. The orthographic projection of the polysilicon gate 331 on the surface of the semiconductor substrate 30 completely falls within the active region 32. The polysilicon gate 331 has a second length L2 in the first direction D1; the second length L2 is smaller than the first length L1. The first direction D1 is parallel to the surface of the semiconductor substrate 30. That is, in the first direction D1, there is a gap between the orthographic projection of the polysilicon gate 331 on the surface of the semiconductor substrate 30 and the isolation structure 31.

[0019] Since the orthographic projection of the polysilicon gate 331 onto the surface of the semiconductor substrate 30 falls entirely within the active region 32, and there is a gap between the orthographic projection of the polysilicon gate 331 onto the surface of the semiconductor substrate 30 and the isolation structure 31, the implanted well doping can be kept away from the isolation structure 31, effectively weakening or eliminating the "boron absorption and phosphorus repulsion" effect of the isolation structure 31 on the well region formed by the implanted well doping. Simultaneously, the length of the orthographic projection of the polysilicon gate 331 onto the surface of the semiconductor substrate 30 is defined as the length of the effective channel Lg1. That is, this embodiment enables the effective channel to be kept away from the isolation structure 31 region, so the corner morphology of the active region will not affect the device.

[0020] In some embodiments, the semiconductor substrate 30 may be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.; it may also be a stacked structure, such as a silicon / germanium silicon stack, etc.

[0021] In some embodiments, the active region 32 can be defined in the semiconductor substrate 30 by means of an isolation structure 31, and the active region 32 can be formed by an ion implantation process. In this embodiment, the isolation structure 31 includes a shallow trench isolation structure (STI).

[0022] In some embodiments, a gate oxide layer 332 is further disposed on the surface of the active region 32; the polysilicon gate 331 is disposed on the surface of the gate oxide layer 332. For illustrative purposes, Figure 3 The gate oxide layer 332 is not shown in the figure.

[0023] like Figure 4 As shown, in this embodiment, the gate structure 33 further includes a sidewall 333 covering the sidewall of the polysilicon gate 331. In the first direction D1, the orthogonal projection of the sidewall 333 onto the surface of the semiconductor substrate 30 has a portion overlapping with the isolation structure 31. (For illustrative purposes only.) Figure 3 The sidewall 333 is not shown in the diagram. That is, the orthographic projection of the polysilicon gate 331 onto the surface of the semiconductor substrate 30 falls entirely within the active region 32, and the orthographic projection of the sidewall 333, which covers the sidewall of the polysilicon gate 331, onto the surface of the semiconductor substrate 30 can cover the region where the isolation structure 31 is located in the first direction D1. The sidewall 333, covering the sidewall of the polysilicon gate 331 and extending to cover the region where the isolation structure 31 is located, can block surface leakage current at the junction of the polysilicon gate, active region, and isolation structure, preventing the formation of parasitic channels and parasitic MOS transistors at corners and reducing off-state leakage current. Simultaneously, the sidewall, as an ion implantation barrier layer, extends to cover the region where the isolation structure is located, enabling precise control of the source and drain positions and contours, reducing short-channel effects, and improving the uniformity of the device threshold voltage. The sidewall extending to cover the region where the isolation structure is located can also alleviate corner rounding and pattern distortion caused by photolithography and etching, ensuring gate size (CD) stability.

[0024] In this embodiment, in the first direction D1, there is a gap W0 between the orthographic projection of the polysilicon gate 331 on the surface of the semiconductor substrate 30 and the isolation structure 31, and the width W3 of the sidewall 333 is greater than the gap W0. By setting the width W3 of the sidewall 333 to be greater than the gap W0, the sidewall 333 can fully extend to cover the area where the isolation structure 31 is located, thereby effectively blocking the surface leakage current at the junction of the polysilicon gate, the active region, and the isolation structure, avoiding the formation of parasitic channels and parasitic MOS transistors at corners, and reducing off-state leakage current; at the same time, it can precisely control the position and contour of the source and drain, weaken the short-channel effect, improve the uniformity of the device threshold voltage, and also alleviate the corner rounding and pattern distortion caused by photolithography and etching, ensuring the stability of the gate size.

[0025] In some embodiments, the width W3 of the sidewall is 40-100 nm, and the gap W0 is 20-80 nm. That is, the dimensions of the sidewall and the gap are designed with a 20 nm process fluctuation window.

[0026] In this embodiment, the sidewall 333 includes a first sub-sidewall 3331, a second sub-sidewall 3332, and a third sub-sidewall 3333, which are sequentially stacked and cover the sidewall of the polysilicon gate 331. The sidewall with the stacked structure provides better insulation, lower leakage current, stronger high-voltage / breakdown resistance, more controllable stress and interface, and more robust processing. The stacked structure also makes it easier to ensure the stability of the sidewall's width. In other embodiments, the sidewall 333 may also be a single-layer sidewall.

[0027] In some embodiments, the first sub-sidewall 3331 and the third sub-sidewall 3333 are made of silicon oxide, and the second sub-sidewall is made of silicon nitride, i.e., the sidewall 24 has an ONO (Oxide-Nitride-Oxide) structure. The inner silicon oxide layer has good interface matching with the substrate / gate oxide, low interface states, and few traps; the middle silicon nitride layer has a higher dielectric constant, high insulation strength, and strong carrier blocking ability; the outer silicon oxide layer can isolate metal silicides and suppress edge leakage current.

[0028] like Figure 5As shown, in this embodiment, the active region 32 has a first width W1 in the second direction D2; the gate structure 33 has a second width W2 in the second direction D2, and the second width W2 is smaller than the first width W1. The second direction D2 is parallel to the surface of the semiconductor substrate 30 and perpendicular to the first direction D1. Specifically, the second width W2 of the gate structure 33 in the second direction D2 is the sum of the width of the polysilicon gate 331 and the width of the sidewall 24. That is, in the second direction D2, the orthogonal projection of the sidewall 333 onto the surface of the semiconductor substrate 30 does not overlap with the isolation structure 31; the sidewall 333 only covers the sidewall of the polysilicon gate 331 and does not extend to cover the area where the isolation structure 31 is located. In the second direction D2, since the width of the gate structure 33 is smaller than the width of the active region 32, the gate structure 33 can be used as a shield to form a source / drain electrode within the active region 32 through ion implantation.

[0029] In this embodiment, the semiconductor substrate 30 has a well region 309, and the active region 32 is disposed within the well region 309; in the second direction D2, the active region 32 is provided with an active / drain electrode 321 near the isolation structure 31; in the second direction D2, the gate structure 33 exposes the source / drain electrode 321 through its orthogonal projection onto the surface of the semiconductor substrate 30. The second direction D2 is parallel to the surface of the semiconductor substrate 30 and perpendicular to the first direction D1. (For illustrative purposes,...) Figure 3 The source / drain 321 is not shown in the diagram.

[0030] In this embodiment, the well region 309 and the source / drain 321 are formed using ion implantation of different conductivity types. Specifically, the well region 309 is formed using ion implantation of a first conductivity type, and the source / drain 321 is formed using ion implantation of a second conductivity type. The first conductivity type and the second conductivity type are different. For example, the first conductivity type is P-type, and the second conductivity type is N-type, thereby forming an NMOS transistor. The ion implantation parameters can be adjusted according to the MOSFET device parameters and process conditions, and are not specifically limited here.

[0031] In this embodiment, the MOSFET device structure further includes a metal silicide layer 35 and multiple lead-out structures 36. For illustrative purposes, Figure 3The metal silicide layer 35 is not shown in the diagram. The metal silicide layer 35 covers the top surfaces of the source / drain 321 and the polysilicon gate 331, respectively; multiple lead-out structures 36 are in contact with the metal silicide layer 35. In this embodiment, multiple lead-out structures 36 are provided on the metal silicide layer 35 covering the top surface of the source / drain 321, and multiple lead-out structures 36 are also provided on the metal silicide layer 35 covering the top surface of the polysilicon gate 331; multiple lead-outs provide redundant connections, so that the failure of a single lead-out structure does not affect the overall function, thus improving the failure resistance.

[0032] The MOSFET device structure described in the above embodiments, by ensuring that the orthogonal projection of the polysilicon gate onto the semiconductor substrate surface completely falls within the active region, allows the implanted well doping to be kept away from the isolation structure, effectively reducing or eliminating the "boron absorption and phosphorus repulsion" effect of the isolation structure on the well region formed by the implanted well doping; it also allows the effective channel to be kept away from the isolation structure region, so that the corner morphology of the active region will not affect the device. This embodiment can eliminate or reduce the bimodal effect.

[0033] In the above description, descriptions of well-known components and technologies have been omitted to avoid unnecessarily obscuring the concept of the present invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar or identical parts between embodiments can be referred to mutually.

[0034] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising a…" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element. Additionally, embodiments and features thereof in this invention can be combined with each other without conflict.

[0035] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A MOSFET device structure, characterized in that, include: A semiconductor substrate having an active region defined by an isolation structure, the active region having a first length in a first direction, wherein the first direction is parallel to the surface of the semiconductor substrate; A gate structure includes a polysilicon gate disposed on the surface of the semiconductor substrate and corresponding to the active region. The orthogonal projection of the polysilicon gate on the surface of the semiconductor substrate falls entirely within the active region. The polysilicon gate has a second length in the first direction, and the second length is less than the first length.

2. The MOSFET device structure according to claim 1, characterized in that, The gate structure further includes a sidewall covering the sidewall of the polysilicon gate, wherein the orthogonal projection of the sidewall onto the surface of the semiconductor substrate in the first direction has a portion that overlaps with the isolation structure.

3. The MOSFET device structure according to claim 2, characterized in that, In the first direction, there is a gap between the orthogonal projection of the polysilicon gate onto the surface of the semiconductor substrate and the isolation structure, and the width of the sidewall is greater than the gap.

4. The MOSFET device structure according to claim 3, characterized in that, The width of the sidewall is 40~100nm, and the gap is 20-80nm.

5. The MOSFET device structure according to claim 2, characterized in that, The sidewall includes a first sub-sidewall, a second sub-sidewall, and a third sub-sidewall that are sequentially stacked and cover the sidewall of the polysilicon gate, wherein the first sub-sidewall and the third sub-sidewall are made of silicon oxide, and the second sub-sidewall is made of silicon nitride.

6. The MOSFET device structure according to claim 1, characterized in that, The active region has a first width in a second direction; the gate structure has a second width in the second direction, the second width being smaller than the first width; wherein the second direction is parallel to the surface of the semiconductor substrate and perpendicular to the first direction.

7. The MOSFET device structure according to claim 1, characterized in that, The semiconductor substrate has a well region, and the active region is disposed within the well region. In a second direction, the active region has an active / drain electrode disposed near the isolation structure. In the second direction, the orthogonal projection of the gate structure onto the surface of the semiconductor substrate exposes the source / drain electrode. The second direction is parallel to the surface of the semiconductor substrate and perpendicular to the first direction.

8. The MOSFET device structure according to claim 7, characterized in that, The well region and the source / drain are implanted with ions of different conductivity types.

9. The MOSFET device structure according to claim 7, characterized in that, Also includes: Metal silicide layers cover the top surfaces of the source / drain electrodes and the polysilicon gate, respectively; Multiple lead-out structures are respectively in contact with the metal silicide layer.

10. The MOSFET device structure according to claim 1, characterized in that, The isolation structure includes a shallow trench isolation structure.

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